1 /* 2 * PXA2xx SPI DMA engine support. 3 * 4 * Copyright (C) 2013, Intel Corporation 5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/dmaengine.h> 15 #include <linux/pxa2xx_ssp.h> 16 #include <linux/scatterlist.h> 17 #include <linux/sizes.h> 18 #include <linux/spi/spi.h> 19 #include <linux/spi/pxa2xx_spi.h> 20 21 #include "spi-pxa2xx.h" 22 23 static int pxa2xx_spi_map_dma_buffer(struct driver_data *drv_data, 24 enum dma_data_direction dir) 25 { 26 int i, nents, len = drv_data->len; 27 struct scatterlist *sg; 28 struct device *dmadev; 29 struct sg_table *sgt; 30 void *buf, *pbuf; 31 32 if (dir == DMA_TO_DEVICE) { 33 dmadev = drv_data->tx_chan->device->dev; 34 sgt = &drv_data->tx_sgt; 35 buf = drv_data->tx; 36 drv_data->tx_map_len = len; 37 } else { 38 dmadev = drv_data->rx_chan->device->dev; 39 sgt = &drv_data->rx_sgt; 40 buf = drv_data->rx; 41 drv_data->rx_map_len = len; 42 } 43 44 nents = DIV_ROUND_UP(len, SZ_2K); 45 if (nents != sgt->nents) { 46 int ret; 47 48 sg_free_table(sgt); 49 ret = sg_alloc_table(sgt, nents, GFP_ATOMIC); 50 if (ret) 51 return ret; 52 } 53 54 pbuf = buf; 55 for_each_sg(sgt->sgl, sg, sgt->nents, i) { 56 size_t bytes = min_t(size_t, len, SZ_2K); 57 58 if (buf) 59 sg_set_buf(sg, pbuf, bytes); 60 else 61 sg_set_buf(sg, drv_data->dummy, bytes); 62 63 pbuf += bytes; 64 len -= bytes; 65 } 66 67 nents = dma_map_sg(dmadev, sgt->sgl, sgt->nents, dir); 68 if (!nents) 69 return -ENOMEM; 70 71 return nents; 72 } 73 74 static void pxa2xx_spi_unmap_dma_buffer(struct driver_data *drv_data, 75 enum dma_data_direction dir) 76 { 77 struct device *dmadev; 78 struct sg_table *sgt; 79 80 if (dir == DMA_TO_DEVICE) { 81 dmadev = drv_data->tx_chan->device->dev; 82 sgt = &drv_data->tx_sgt; 83 } else { 84 dmadev = drv_data->rx_chan->device->dev; 85 sgt = &drv_data->rx_sgt; 86 } 87 88 dma_unmap_sg(dmadev, sgt->sgl, sgt->nents, dir); 89 } 90 91 static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data) 92 { 93 if (!drv_data->dma_mapped) 94 return; 95 96 pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_FROM_DEVICE); 97 pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE); 98 99 drv_data->dma_mapped = 0; 100 } 101 102 static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data, 103 bool error) 104 { 105 struct spi_message *msg = drv_data->cur_msg; 106 107 /* 108 * It is possible that one CPU is handling ROR interrupt and other 109 * just gets DMA completion. Calling pump_transfers() twice for the 110 * same transfer leads to problems thus we prevent concurrent calls 111 * by using ->dma_running. 112 */ 113 if (atomic_dec_and_test(&drv_data->dma_running)) { 114 void __iomem *reg = drv_data->ioaddr; 115 116 /* 117 * If the other CPU is still handling the ROR interrupt we 118 * might not know about the error yet. So we re-check the 119 * ROR bit here before we clear the status register. 120 */ 121 if (!error) { 122 u32 status = read_SSSR(reg) & drv_data->mask_sr; 123 error = status & SSSR_ROR; 124 } 125 126 /* Clear status & disable interrupts */ 127 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg); 128 write_SSSR_CS(drv_data, drv_data->clear_sr); 129 if (!pxa25x_ssp_comp(drv_data)) 130 write_SSTO(0, reg); 131 132 if (!error) { 133 pxa2xx_spi_unmap_dma_buffers(drv_data); 134 135 drv_data->tx += drv_data->tx_map_len; 136 drv_data->rx += drv_data->rx_map_len; 137 138 msg->actual_length += drv_data->len; 139 msg->state = pxa2xx_spi_next_transfer(drv_data); 140 } else { 141 /* In case we got an error we disable the SSP now */ 142 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg); 143 144 msg->state = ERROR_STATE; 145 } 146 147 tasklet_schedule(&drv_data->pump_transfers); 148 } 149 } 150 151 static void pxa2xx_spi_dma_callback(void *data) 152 { 153 pxa2xx_spi_dma_transfer_complete(data, false); 154 } 155 156 static struct dma_async_tx_descriptor * 157 pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data, 158 enum dma_transfer_direction dir) 159 { 160 struct pxa2xx_spi_master *pdata = drv_data->master_info; 161 struct chip_data *chip = drv_data->cur_chip; 162 enum dma_slave_buswidth width; 163 struct dma_slave_config cfg; 164 struct dma_chan *chan; 165 struct sg_table *sgt; 166 int nents, ret; 167 168 switch (drv_data->n_bytes) { 169 case 1: 170 width = DMA_SLAVE_BUSWIDTH_1_BYTE; 171 break; 172 case 2: 173 width = DMA_SLAVE_BUSWIDTH_2_BYTES; 174 break; 175 default: 176 width = DMA_SLAVE_BUSWIDTH_4_BYTES; 177 break; 178 } 179 180 memset(&cfg, 0, sizeof(cfg)); 181 cfg.direction = dir; 182 183 if (dir == DMA_MEM_TO_DEV) { 184 cfg.dst_addr = drv_data->ssdr_physical; 185 cfg.dst_addr_width = width; 186 cfg.dst_maxburst = chip->dma_burst_size; 187 cfg.slave_id = pdata->tx_slave_id; 188 189 sgt = &drv_data->tx_sgt; 190 nents = drv_data->tx_nents; 191 chan = drv_data->tx_chan; 192 } else { 193 cfg.src_addr = drv_data->ssdr_physical; 194 cfg.src_addr_width = width; 195 cfg.src_maxburst = chip->dma_burst_size; 196 cfg.slave_id = pdata->rx_slave_id; 197 198 sgt = &drv_data->rx_sgt; 199 nents = drv_data->rx_nents; 200 chan = drv_data->rx_chan; 201 } 202 203 ret = dmaengine_slave_config(chan, &cfg); 204 if (ret) { 205 dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n"); 206 return NULL; 207 } 208 209 return dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, 210 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 211 } 212 213 static bool pxa2xx_spi_dma_filter(struct dma_chan *chan, void *param) 214 { 215 const struct pxa2xx_spi_master *pdata = param; 216 217 return chan->chan_id == pdata->tx_chan_id || 218 chan->chan_id == pdata->rx_chan_id; 219 } 220 221 bool pxa2xx_spi_dma_is_possible(size_t len) 222 { 223 return len <= MAX_DMA_LEN; 224 } 225 226 int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data) 227 { 228 const struct chip_data *chip = drv_data->cur_chip; 229 int ret; 230 231 if (!chip->enable_dma) 232 return 0; 233 234 /* Don't bother with DMA if we can't do even a single burst */ 235 if (drv_data->len < chip->dma_burst_size) 236 return 0; 237 238 ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_TO_DEVICE); 239 if (ret <= 0) { 240 dev_warn(&drv_data->pdev->dev, "failed to DMA map TX\n"); 241 return 0; 242 } 243 244 drv_data->tx_nents = ret; 245 246 ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_FROM_DEVICE); 247 if (ret <= 0) { 248 pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE); 249 dev_warn(&drv_data->pdev->dev, "failed to DMA map RX\n"); 250 return 0; 251 } 252 253 drv_data->rx_nents = ret; 254 return 1; 255 } 256 257 irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data) 258 { 259 u32 status; 260 261 status = read_SSSR(drv_data->ioaddr) & drv_data->mask_sr; 262 if (status & SSSR_ROR) { 263 dev_err(&drv_data->pdev->dev, "FIFO overrun\n"); 264 265 dmaengine_terminate_all(drv_data->rx_chan); 266 dmaengine_terminate_all(drv_data->tx_chan); 267 268 pxa2xx_spi_dma_transfer_complete(drv_data, true); 269 return IRQ_HANDLED; 270 } 271 272 return IRQ_NONE; 273 } 274 275 int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst) 276 { 277 struct dma_async_tx_descriptor *tx_desc, *rx_desc; 278 279 tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV); 280 if (!tx_desc) { 281 dev_err(&drv_data->pdev->dev, 282 "failed to get DMA TX descriptor\n"); 283 return -EBUSY; 284 } 285 286 rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM); 287 if (!rx_desc) { 288 dev_err(&drv_data->pdev->dev, 289 "failed to get DMA RX descriptor\n"); 290 return -EBUSY; 291 } 292 293 /* We are ready when RX completes */ 294 rx_desc->callback = pxa2xx_spi_dma_callback; 295 rx_desc->callback_param = drv_data; 296 297 dmaengine_submit(rx_desc); 298 dmaengine_submit(tx_desc); 299 return 0; 300 } 301 302 void pxa2xx_spi_dma_start(struct driver_data *drv_data) 303 { 304 dma_async_issue_pending(drv_data->rx_chan); 305 dma_async_issue_pending(drv_data->tx_chan); 306 307 atomic_set(&drv_data->dma_running, 1); 308 } 309 310 int pxa2xx_spi_dma_setup(struct driver_data *drv_data) 311 { 312 struct pxa2xx_spi_master *pdata = drv_data->master_info; 313 struct device *dev = &drv_data->pdev->dev; 314 dma_cap_mask_t mask; 315 316 dma_cap_zero(mask); 317 dma_cap_set(DMA_SLAVE, mask); 318 319 drv_data->dummy = devm_kzalloc(dev, SZ_2K, GFP_KERNEL); 320 if (!drv_data->dummy) 321 return -ENOMEM; 322 323 drv_data->tx_chan = dma_request_slave_channel_compat(mask, 324 pxa2xx_spi_dma_filter, pdata, dev, "tx"); 325 if (!drv_data->tx_chan) 326 return -ENODEV; 327 328 drv_data->rx_chan = dma_request_slave_channel_compat(mask, 329 pxa2xx_spi_dma_filter, pdata, dev, "rx"); 330 if (!drv_data->rx_chan) { 331 dma_release_channel(drv_data->tx_chan); 332 drv_data->tx_chan = NULL; 333 return -ENODEV; 334 } 335 336 return 0; 337 } 338 339 void pxa2xx_spi_dma_release(struct driver_data *drv_data) 340 { 341 if (drv_data->rx_chan) { 342 dmaengine_terminate_all(drv_data->rx_chan); 343 dma_release_channel(drv_data->rx_chan); 344 sg_free_table(&drv_data->rx_sgt); 345 drv_data->rx_chan = NULL; 346 } 347 if (drv_data->tx_chan) { 348 dmaengine_terminate_all(drv_data->tx_chan); 349 dma_release_channel(drv_data->tx_chan); 350 sg_free_table(&drv_data->tx_sgt); 351 drv_data->tx_chan = NULL; 352 } 353 } 354 355 void pxa2xx_spi_dma_resume(struct driver_data *drv_data) 356 { 357 } 358 359 int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, 360 struct spi_device *spi, 361 u8 bits_per_word, u32 *burst_code, 362 u32 *threshold) 363 { 364 struct pxa2xx_spi_chip *chip_info = spi->controller_data; 365 366 /* 367 * If the DMA burst size is given in chip_info we use that, 368 * otherwise we use the default. Also we use the default FIFO 369 * thresholds for now. 370 */ 371 *burst_code = chip_info ? chip_info->dma_burst_size : 1; 372 *threshold = SSCR1_RxTresh(RX_THRESH_DFLT) 373 | SSCR1_TxTresh(TX_THRESH_DFLT); 374 375 return 0; 376 } 377