1 /* 2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. 3 * 4 * Copyright (C) 2008-2012 ST-Ericsson AB 5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6 * 7 * Author: Linus Walleij <linus.walleij@stericsson.com> 8 * 9 * Initial version inspired by: 10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11 * Initial adoption to PL022 by: 12 * Sachin Verma <sachin.verma@st.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/device.h> 28 #include <linux/ioport.h> 29 #include <linux/errno.h> 30 #include <linux/interrupt.h> 31 #include <linux/spi/spi.h> 32 #include <linux/delay.h> 33 #include <linux/clk.h> 34 #include <linux/err.h> 35 #include <linux/amba/bus.h> 36 #include <linux/amba/pl022.h> 37 #include <linux/io.h> 38 #include <linux/slab.h> 39 #include <linux/dmaengine.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/scatterlist.h> 42 #include <linux/pm_runtime.h> 43 #include <linux/gpio.h> 44 #include <linux/of_gpio.h> 45 #include <linux/pinctrl/consumer.h> 46 47 /* 48 * This macro is used to define some register default values. 49 * reg is masked with mask, the OR:ed with an (again masked) 50 * val shifted sb steps to the left. 51 */ 52 #define SSP_WRITE_BITS(reg, val, mask, sb) \ 53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) 54 55 /* 56 * This macro is also used to define some default values. 57 * It will just shift val by sb steps to the left and mask 58 * the result with mask. 59 */ 60 #define GEN_MASK_BITS(val, mask, sb) \ 61 (((val)<<(sb)) & (mask)) 62 63 #define DRIVE_TX 0 64 #define DO_NOT_DRIVE_TX 1 65 66 #define DO_NOT_QUEUE_DMA 0 67 #define QUEUE_DMA 1 68 69 #define RX_TRANSFER 1 70 #define TX_TRANSFER 2 71 72 /* 73 * Macros to access SSP Registers with their offsets 74 */ 75 #define SSP_CR0(r) (r + 0x000) 76 #define SSP_CR1(r) (r + 0x004) 77 #define SSP_DR(r) (r + 0x008) 78 #define SSP_SR(r) (r + 0x00C) 79 #define SSP_CPSR(r) (r + 0x010) 80 #define SSP_IMSC(r) (r + 0x014) 81 #define SSP_RIS(r) (r + 0x018) 82 #define SSP_MIS(r) (r + 0x01C) 83 #define SSP_ICR(r) (r + 0x020) 84 #define SSP_DMACR(r) (r + 0x024) 85 #define SSP_CSR(r) (r + 0x030) /* vendor extension */ 86 #define SSP_ITCR(r) (r + 0x080) 87 #define SSP_ITIP(r) (r + 0x084) 88 #define SSP_ITOP(r) (r + 0x088) 89 #define SSP_TDR(r) (r + 0x08C) 90 91 #define SSP_PID0(r) (r + 0xFE0) 92 #define SSP_PID1(r) (r + 0xFE4) 93 #define SSP_PID2(r) (r + 0xFE8) 94 #define SSP_PID3(r) (r + 0xFEC) 95 96 #define SSP_CID0(r) (r + 0xFF0) 97 #define SSP_CID1(r) (r + 0xFF4) 98 #define SSP_CID2(r) (r + 0xFF8) 99 #define SSP_CID3(r) (r + 0xFFC) 100 101 /* 102 * SSP Control Register 0 - SSP_CR0 103 */ 104 #define SSP_CR0_MASK_DSS (0x0FUL << 0) 105 #define SSP_CR0_MASK_FRF (0x3UL << 4) 106 #define SSP_CR0_MASK_SPO (0x1UL << 6) 107 #define SSP_CR0_MASK_SPH (0x1UL << 7) 108 #define SSP_CR0_MASK_SCR (0xFFUL << 8) 109 110 /* 111 * The ST version of this block moves som bits 112 * in SSP_CR0 and extends it to 32 bits 113 */ 114 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) 115 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) 116 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) 117 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) 118 119 /* 120 * SSP Control Register 0 - SSP_CR1 121 */ 122 #define SSP_CR1_MASK_LBM (0x1UL << 0) 123 #define SSP_CR1_MASK_SSE (0x1UL << 1) 124 #define SSP_CR1_MASK_MS (0x1UL << 2) 125 #define SSP_CR1_MASK_SOD (0x1UL << 3) 126 127 /* 128 * The ST version of this block adds some bits 129 * in SSP_CR1 130 */ 131 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) 132 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) 133 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) 134 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) 135 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) 136 /* This one is only in the PL023 variant */ 137 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) 138 139 /* 140 * SSP Status Register - SSP_SR 141 */ 142 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ 143 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ 144 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ 145 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ 146 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ 147 148 /* 149 * SSP Clock Prescale Register - SSP_CPSR 150 */ 151 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) 152 153 /* 154 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC 155 */ 156 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ 157 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ 158 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ 159 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ 160 161 /* 162 * SSP Raw Interrupt Status Register - SSP_RIS 163 */ 164 /* Receive Overrun Raw Interrupt status */ 165 #define SSP_RIS_MASK_RORRIS (0x1UL << 0) 166 /* Receive Timeout Raw Interrupt status */ 167 #define SSP_RIS_MASK_RTRIS (0x1UL << 1) 168 /* Receive FIFO Raw Interrupt status */ 169 #define SSP_RIS_MASK_RXRIS (0x1UL << 2) 170 /* Transmit FIFO Raw Interrupt status */ 171 #define SSP_RIS_MASK_TXRIS (0x1UL << 3) 172 173 /* 174 * SSP Masked Interrupt Status Register - SSP_MIS 175 */ 176 /* Receive Overrun Masked Interrupt status */ 177 #define SSP_MIS_MASK_RORMIS (0x1UL << 0) 178 /* Receive Timeout Masked Interrupt status */ 179 #define SSP_MIS_MASK_RTMIS (0x1UL << 1) 180 /* Receive FIFO Masked Interrupt status */ 181 #define SSP_MIS_MASK_RXMIS (0x1UL << 2) 182 /* Transmit FIFO Masked Interrupt status */ 183 #define SSP_MIS_MASK_TXMIS (0x1UL << 3) 184 185 /* 186 * SSP Interrupt Clear Register - SSP_ICR 187 */ 188 /* Receive Overrun Raw Clear Interrupt bit */ 189 #define SSP_ICR_MASK_RORIC (0x1UL << 0) 190 /* Receive Timeout Clear Interrupt bit */ 191 #define SSP_ICR_MASK_RTIC (0x1UL << 1) 192 193 /* 194 * SSP DMA Control Register - SSP_DMACR 195 */ 196 /* Receive DMA Enable bit */ 197 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) 198 /* Transmit DMA Enable bit */ 199 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) 200 201 /* 202 * SSP Chip Select Control Register - SSP_CSR 203 * (vendor extension) 204 */ 205 #define SSP_CSR_CSVALUE_MASK (0x1FUL << 0) 206 207 /* 208 * SSP Integration Test control Register - SSP_ITCR 209 */ 210 #define SSP_ITCR_MASK_ITEN (0x1UL << 0) 211 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) 212 213 /* 214 * SSP Integration Test Input Register - SSP_ITIP 215 */ 216 #define ITIP_MASK_SSPRXD (0x1UL << 0) 217 #define ITIP_MASK_SSPFSSIN (0x1UL << 1) 218 #define ITIP_MASK_SSPCLKIN (0x1UL << 2) 219 #define ITIP_MASK_RXDMAC (0x1UL << 3) 220 #define ITIP_MASK_TXDMAC (0x1UL << 4) 221 #define ITIP_MASK_SSPTXDIN (0x1UL << 5) 222 223 /* 224 * SSP Integration Test output Register - SSP_ITOP 225 */ 226 #define ITOP_MASK_SSPTXD (0x1UL << 0) 227 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) 228 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) 229 #define ITOP_MASK_SSPOEn (0x1UL << 3) 230 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) 231 #define ITOP_MASK_RORINTR (0x1UL << 5) 232 #define ITOP_MASK_RTINTR (0x1UL << 6) 233 #define ITOP_MASK_RXINTR (0x1UL << 7) 234 #define ITOP_MASK_TXINTR (0x1UL << 8) 235 #define ITOP_MASK_INTR (0x1UL << 9) 236 #define ITOP_MASK_RXDMABREQ (0x1UL << 10) 237 #define ITOP_MASK_RXDMASREQ (0x1UL << 11) 238 #define ITOP_MASK_TXDMABREQ (0x1UL << 12) 239 #define ITOP_MASK_TXDMASREQ (0x1UL << 13) 240 241 /* 242 * SSP Test Data Register - SSP_TDR 243 */ 244 #define TDR_MASK_TESTDATA (0xFFFFFFFF) 245 246 /* 247 * Message State 248 * we use the spi_message.state (void *) pointer to 249 * hold a single state value, that's why all this 250 * (void *) casting is done here. 251 */ 252 #define STATE_START ((void *) 0) 253 #define STATE_RUNNING ((void *) 1) 254 #define STATE_DONE ((void *) 2) 255 #define STATE_ERROR ((void *) -1) 256 257 /* 258 * SSP State - Whether Enabled or Disabled 259 */ 260 #define SSP_DISABLED (0) 261 #define SSP_ENABLED (1) 262 263 /* 264 * SSP DMA State - Whether DMA Enabled or Disabled 265 */ 266 #define SSP_DMA_DISABLED (0) 267 #define SSP_DMA_ENABLED (1) 268 269 /* 270 * SSP Clock Defaults 271 */ 272 #define SSP_DEFAULT_CLKRATE 0x2 273 #define SSP_DEFAULT_PRESCALE 0x40 274 275 /* 276 * SSP Clock Parameter ranges 277 */ 278 #define CPSDVR_MIN 0x02 279 #define CPSDVR_MAX 0xFE 280 #define SCR_MIN 0x00 281 #define SCR_MAX 0xFF 282 283 /* 284 * SSP Interrupt related Macros 285 */ 286 #define DEFAULT_SSP_REG_IMSC 0x0UL 287 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC 288 #define ENABLE_ALL_INTERRUPTS ( \ 289 SSP_IMSC_MASK_RORIM | \ 290 SSP_IMSC_MASK_RTIM | \ 291 SSP_IMSC_MASK_RXIM | \ 292 SSP_IMSC_MASK_TXIM \ 293 ) 294 295 #define CLEAR_ALL_INTERRUPTS 0x3 296 297 #define SPI_POLLING_TIMEOUT 1000 298 299 /* 300 * The type of reading going on on this chip 301 */ 302 enum ssp_reading { 303 READING_NULL, 304 READING_U8, 305 READING_U16, 306 READING_U32 307 }; 308 309 /** 310 * The type of writing going on on this chip 311 */ 312 enum ssp_writing { 313 WRITING_NULL, 314 WRITING_U8, 315 WRITING_U16, 316 WRITING_U32 317 }; 318 319 /** 320 * struct vendor_data - vendor-specific config parameters 321 * for PL022 derivates 322 * @fifodepth: depth of FIFOs (both) 323 * @max_bpw: maximum number of bits per word 324 * @unidir: supports unidirection transfers 325 * @extended_cr: 32 bit wide control register 0 with extra 326 * features and extra features in CR1 as found in the ST variants 327 * @pl023: supports a subset of the ST extensions called "PL023" 328 * @internal_cs_ctrl: supports chip select control register 329 */ 330 struct vendor_data { 331 int fifodepth; 332 int max_bpw; 333 bool unidir; 334 bool extended_cr; 335 bool pl023; 336 bool loopback; 337 bool internal_cs_ctrl; 338 }; 339 340 /** 341 * struct pl022 - This is the private SSP driver data structure 342 * @adev: AMBA device model hookup 343 * @vendor: vendor data for the IP block 344 * @phybase: the physical memory where the SSP device resides 345 * @virtbase: the virtual memory where the SSP is mapped 346 * @clk: outgoing clock "SPICLK" for the SPI bus 347 * @master: SPI framework hookup 348 * @master_info: controller-specific data from machine setup 349 * @pump_transfers: Tasklet used in Interrupt Transfer mode 350 * @cur_msg: Pointer to current spi_message being processed 351 * @cur_transfer: Pointer to current spi_transfer 352 * @cur_chip: pointer to current clients chip(assigned from controller_state) 353 * @next_msg_cs_active: the next message in the queue has been examined 354 * and it was found that it uses the same chip select as the previous 355 * message, so we left it active after the previous transfer, and it's 356 * active already. 357 * @tx: current position in TX buffer to be read 358 * @tx_end: end position in TX buffer to be read 359 * @rx: current position in RX buffer to be written 360 * @rx_end: end position in RX buffer to be written 361 * @read: the type of read currently going on 362 * @write: the type of write currently going on 363 * @exp_fifo_level: expected FIFO level 364 * @dma_rx_channel: optional channel for RX DMA 365 * @dma_tx_channel: optional channel for TX DMA 366 * @sgt_rx: scattertable for the RX transfer 367 * @sgt_tx: scattertable for the TX transfer 368 * @dummypage: a dummy page used for driving data on the bus with DMA 369 * @cur_cs: current chip select (gpio) 370 * @chipselects: list of chipselects (gpios) 371 */ 372 struct pl022 { 373 struct amba_device *adev; 374 struct vendor_data *vendor; 375 resource_size_t phybase; 376 void __iomem *virtbase; 377 struct clk *clk; 378 struct spi_master *master; 379 struct pl022_ssp_controller *master_info; 380 /* Message per-transfer pump */ 381 struct tasklet_struct pump_transfers; 382 struct spi_message *cur_msg; 383 struct spi_transfer *cur_transfer; 384 struct chip_data *cur_chip; 385 bool next_msg_cs_active; 386 void *tx; 387 void *tx_end; 388 void *rx; 389 void *rx_end; 390 enum ssp_reading read; 391 enum ssp_writing write; 392 u32 exp_fifo_level; 393 enum ssp_rx_level_trig rx_lev_trig; 394 enum ssp_tx_level_trig tx_lev_trig; 395 /* DMA settings */ 396 #ifdef CONFIG_DMA_ENGINE 397 struct dma_chan *dma_rx_channel; 398 struct dma_chan *dma_tx_channel; 399 struct sg_table sgt_rx; 400 struct sg_table sgt_tx; 401 char *dummypage; 402 bool dma_running; 403 #endif 404 int cur_cs; 405 int *chipselects; 406 }; 407 408 /** 409 * struct chip_data - To maintain runtime state of SSP for each client chip 410 * @cr0: Value of control register CR0 of SSP - on later ST variants this 411 * register is 32 bits wide rather than just 16 412 * @cr1: Value of control register CR1 of SSP 413 * @dmacr: Value of DMA control Register of SSP 414 * @cpsr: Value of Clock prescale register 415 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client 416 * @enable_dma: Whether to enable DMA or not 417 * @read: function ptr to be used to read when doing xfer for this chip 418 * @write: function ptr to be used to write when doing xfer for this chip 419 * @cs_control: chip select callback provided by chip 420 * @xfer_type: polling/interrupt/DMA 421 * 422 * Runtime state of the SSP controller, maintained per chip, 423 * This would be set according to the current message that would be served 424 */ 425 struct chip_data { 426 u32 cr0; 427 u16 cr1; 428 u16 dmacr; 429 u16 cpsr; 430 u8 n_bytes; 431 bool enable_dma; 432 enum ssp_reading read; 433 enum ssp_writing write; 434 void (*cs_control) (u32 command); 435 int xfer_type; 436 }; 437 438 /** 439 * null_cs_control - Dummy chip select function 440 * @command: select/delect the chip 441 * 442 * If no chip select function is provided by client this is used as dummy 443 * chip select 444 */ 445 static void null_cs_control(u32 command) 446 { 447 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); 448 } 449 450 /** 451 * internal_cs_control - Control chip select signals via SSP_CSR. 452 * @pl022: SSP driver private data structure 453 * @command: select/delect the chip 454 * 455 * Used on controller with internal chip select control via SSP_CSR register 456 * (vendor extension). Each of the 5 LSB in the register controls one chip 457 * select signal. 458 */ 459 static void internal_cs_control(struct pl022 *pl022, u32 command) 460 { 461 u32 tmp; 462 463 tmp = readw(SSP_CSR(pl022->virtbase)); 464 if (command == SSP_CHIP_SELECT) 465 tmp &= ~BIT(pl022->cur_cs); 466 else 467 tmp |= BIT(pl022->cur_cs); 468 writew(tmp, SSP_CSR(pl022->virtbase)); 469 } 470 471 static void pl022_cs_control(struct pl022 *pl022, u32 command) 472 { 473 if (pl022->vendor->internal_cs_ctrl) 474 internal_cs_control(pl022, command); 475 else if (gpio_is_valid(pl022->cur_cs)) 476 gpio_set_value(pl022->cur_cs, command); 477 else 478 pl022->cur_chip->cs_control(command); 479 } 480 481 /** 482 * giveback - current spi_message is over, schedule next message and call 483 * callback of this message. Assumes that caller already 484 * set message->status; dma and pio irqs are blocked 485 * @pl022: SSP driver private data structure 486 */ 487 static void giveback(struct pl022 *pl022) 488 { 489 struct spi_transfer *last_transfer; 490 pl022->next_msg_cs_active = false; 491 492 last_transfer = list_last_entry(&pl022->cur_msg->transfers, 493 struct spi_transfer, transfer_list); 494 495 /* Delay if requested before any change in chip select */ 496 if (last_transfer->delay_usecs) 497 /* 498 * FIXME: This runs in interrupt context. 499 * Is this really smart? 500 */ 501 udelay(last_transfer->delay_usecs); 502 503 if (!last_transfer->cs_change) { 504 struct spi_message *next_msg; 505 506 /* 507 * cs_change was not set. We can keep the chip select 508 * enabled if there is message in the queue and it is 509 * for the same spi device. 510 * 511 * We cannot postpone this until pump_messages, because 512 * after calling msg->complete (below) the driver that 513 * sent the current message could be unloaded, which 514 * could invalidate the cs_control() callback... 515 */ 516 /* get a pointer to the next message, if any */ 517 next_msg = spi_get_next_queued_message(pl022->master); 518 519 /* 520 * see if the next and current messages point 521 * to the same spi device. 522 */ 523 if (next_msg && next_msg->spi != pl022->cur_msg->spi) 524 next_msg = NULL; 525 if (!next_msg || pl022->cur_msg->state == STATE_ERROR) 526 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 527 else 528 pl022->next_msg_cs_active = true; 529 530 } 531 532 pl022->cur_msg = NULL; 533 pl022->cur_transfer = NULL; 534 pl022->cur_chip = NULL; 535 536 /* disable the SPI/SSP operation */ 537 writew((readw(SSP_CR1(pl022->virtbase)) & 538 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 539 540 spi_finalize_current_message(pl022->master); 541 } 542 543 /** 544 * flush - flush the FIFO to reach a clean state 545 * @pl022: SSP driver private data structure 546 */ 547 static int flush(struct pl022 *pl022) 548 { 549 unsigned long limit = loops_per_jiffy << 1; 550 551 dev_dbg(&pl022->adev->dev, "flush\n"); 552 do { 553 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 554 readw(SSP_DR(pl022->virtbase)); 555 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); 556 557 pl022->exp_fifo_level = 0; 558 559 return limit; 560 } 561 562 /** 563 * restore_state - Load configuration of current chip 564 * @pl022: SSP driver private data structure 565 */ 566 static void restore_state(struct pl022 *pl022) 567 { 568 struct chip_data *chip = pl022->cur_chip; 569 570 if (pl022->vendor->extended_cr) 571 writel(chip->cr0, SSP_CR0(pl022->virtbase)); 572 else 573 writew(chip->cr0, SSP_CR0(pl022->virtbase)); 574 writew(chip->cr1, SSP_CR1(pl022->virtbase)); 575 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); 576 writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); 577 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 578 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 579 } 580 581 /* 582 * Default SSP Register Values 583 */ 584 #define DEFAULT_SSP_REG_CR0 ( \ 585 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ 586 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ 587 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 588 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 589 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 590 ) 591 592 /* ST versions have slightly different bit layout */ 593 #define DEFAULT_SSP_REG_CR0_ST ( \ 594 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 595 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ 596 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 597 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 598 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ 599 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ 600 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ 601 ) 602 603 /* The PL023 version is slightly different again */ 604 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ 605 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ 606 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ 607 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ 608 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ 609 ) 610 611 #define DEFAULT_SSP_REG_CR1 ( \ 612 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ 613 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 614 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 615 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ 616 ) 617 618 /* ST versions extend this register to use all 16 bits */ 619 #define DEFAULT_SSP_REG_CR1_ST ( \ 620 DEFAULT_SSP_REG_CR1 | \ 621 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 622 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 623 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ 624 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 625 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ 626 ) 627 628 /* 629 * The PL023 variant has further differences: no loopback mode, no microwire 630 * support, and a new clock feedback delay setting. 631 */ 632 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ 633 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ 634 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ 635 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ 636 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ 637 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ 638 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ 639 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ 640 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ 641 ) 642 643 #define DEFAULT_SSP_REG_CPSR ( \ 644 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ 645 ) 646 647 #define DEFAULT_SSP_REG_DMACR (\ 648 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ 649 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ 650 ) 651 652 /** 653 * load_ssp_default_config - Load default configuration for SSP 654 * @pl022: SSP driver private data structure 655 */ 656 static void load_ssp_default_config(struct pl022 *pl022) 657 { 658 if (pl022->vendor->pl023) { 659 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); 660 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); 661 } else if (pl022->vendor->extended_cr) { 662 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); 663 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); 664 } else { 665 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); 666 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); 667 } 668 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); 669 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); 670 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); 671 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 672 } 673 674 /** 675 * This will write to TX and read from RX according to the parameters 676 * set in pl022. 677 */ 678 static void readwriter(struct pl022 *pl022) 679 { 680 681 /* 682 * The FIFO depth is different between primecell variants. 683 * I believe filling in too much in the FIFO might cause 684 * errons in 8bit wide transfers on ARM variants (just 8 words 685 * FIFO, means only 8x8 = 64 bits in FIFO) at least. 686 * 687 * To prevent this issue, the TX FIFO is only filled to the 688 * unused RX FIFO fill length, regardless of what the TX 689 * FIFO status flag indicates. 690 */ 691 dev_dbg(&pl022->adev->dev, 692 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", 693 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); 694 695 /* Read as much as you can */ 696 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 697 && (pl022->rx < pl022->rx_end)) { 698 switch (pl022->read) { 699 case READING_NULL: 700 readw(SSP_DR(pl022->virtbase)); 701 break; 702 case READING_U8: 703 *(u8 *) (pl022->rx) = 704 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 705 break; 706 case READING_U16: 707 *(u16 *) (pl022->rx) = 708 (u16) readw(SSP_DR(pl022->virtbase)); 709 break; 710 case READING_U32: 711 *(u32 *) (pl022->rx) = 712 readl(SSP_DR(pl022->virtbase)); 713 break; 714 } 715 pl022->rx += (pl022->cur_chip->n_bytes); 716 pl022->exp_fifo_level--; 717 } 718 /* 719 * Write as much as possible up to the RX FIFO size 720 */ 721 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) 722 && (pl022->tx < pl022->tx_end)) { 723 switch (pl022->write) { 724 case WRITING_NULL: 725 writew(0x0, SSP_DR(pl022->virtbase)); 726 break; 727 case WRITING_U8: 728 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); 729 break; 730 case WRITING_U16: 731 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); 732 break; 733 case WRITING_U32: 734 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); 735 break; 736 } 737 pl022->tx += (pl022->cur_chip->n_bytes); 738 pl022->exp_fifo_level++; 739 /* 740 * This inner reader takes care of things appearing in the RX 741 * FIFO as we're transmitting. This will happen a lot since the 742 * clock starts running when you put things into the TX FIFO, 743 * and then things are continuously clocked into the RX FIFO. 744 */ 745 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) 746 && (pl022->rx < pl022->rx_end)) { 747 switch (pl022->read) { 748 case READING_NULL: 749 readw(SSP_DR(pl022->virtbase)); 750 break; 751 case READING_U8: 752 *(u8 *) (pl022->rx) = 753 readw(SSP_DR(pl022->virtbase)) & 0xFFU; 754 break; 755 case READING_U16: 756 *(u16 *) (pl022->rx) = 757 (u16) readw(SSP_DR(pl022->virtbase)); 758 break; 759 case READING_U32: 760 *(u32 *) (pl022->rx) = 761 readl(SSP_DR(pl022->virtbase)); 762 break; 763 } 764 pl022->rx += (pl022->cur_chip->n_bytes); 765 pl022->exp_fifo_level--; 766 } 767 } 768 /* 769 * When we exit here the TX FIFO should be full and the RX FIFO 770 * should be empty 771 */ 772 } 773 774 /** 775 * next_transfer - Move to the Next transfer in the current spi message 776 * @pl022: SSP driver private data structure 777 * 778 * This function moves though the linked list of spi transfers in the 779 * current spi message and returns with the state of current spi 780 * message i.e whether its last transfer is done(STATE_DONE) or 781 * Next transfer is ready(STATE_RUNNING) 782 */ 783 static void *next_transfer(struct pl022 *pl022) 784 { 785 struct spi_message *msg = pl022->cur_msg; 786 struct spi_transfer *trans = pl022->cur_transfer; 787 788 /* Move to next transfer */ 789 if (trans->transfer_list.next != &msg->transfers) { 790 pl022->cur_transfer = 791 list_entry(trans->transfer_list.next, 792 struct spi_transfer, transfer_list); 793 return STATE_RUNNING; 794 } 795 return STATE_DONE; 796 } 797 798 /* 799 * This DMA functionality is only compiled in if we have 800 * access to the generic DMA devices/DMA engine. 801 */ 802 #ifdef CONFIG_DMA_ENGINE 803 static void unmap_free_dma_scatter(struct pl022 *pl022) 804 { 805 /* Unmap and free the SG tables */ 806 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, 807 pl022->sgt_tx.nents, DMA_TO_DEVICE); 808 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, 809 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 810 sg_free_table(&pl022->sgt_rx); 811 sg_free_table(&pl022->sgt_tx); 812 } 813 814 static void dma_callback(void *data) 815 { 816 struct pl022 *pl022 = data; 817 struct spi_message *msg = pl022->cur_msg; 818 819 BUG_ON(!pl022->sgt_rx.sgl); 820 821 #ifdef VERBOSE_DEBUG 822 /* 823 * Optionally dump out buffers to inspect contents, this is 824 * good if you want to convince yourself that the loopback 825 * read/write contents are the same, when adopting to a new 826 * DMA engine. 827 */ 828 { 829 struct scatterlist *sg; 830 unsigned int i; 831 832 dma_sync_sg_for_cpu(&pl022->adev->dev, 833 pl022->sgt_rx.sgl, 834 pl022->sgt_rx.nents, 835 DMA_FROM_DEVICE); 836 837 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { 838 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); 839 print_hex_dump(KERN_ERR, "SPI RX: ", 840 DUMP_PREFIX_OFFSET, 841 16, 842 1, 843 sg_virt(sg), 844 sg_dma_len(sg), 845 1); 846 } 847 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { 848 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); 849 print_hex_dump(KERN_ERR, "SPI TX: ", 850 DUMP_PREFIX_OFFSET, 851 16, 852 1, 853 sg_virt(sg), 854 sg_dma_len(sg), 855 1); 856 } 857 } 858 #endif 859 860 unmap_free_dma_scatter(pl022); 861 862 /* Update total bytes transferred */ 863 msg->actual_length += pl022->cur_transfer->len; 864 if (pl022->cur_transfer->cs_change) 865 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 866 867 /* Move to next transfer */ 868 msg->state = next_transfer(pl022); 869 tasklet_schedule(&pl022->pump_transfers); 870 } 871 872 static void setup_dma_scatter(struct pl022 *pl022, 873 void *buffer, 874 unsigned int length, 875 struct sg_table *sgtab) 876 { 877 struct scatterlist *sg; 878 int bytesleft = length; 879 void *bufp = buffer; 880 int mapbytes; 881 int i; 882 883 if (buffer) { 884 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 885 /* 886 * If there are less bytes left than what fits 887 * in the current page (plus page alignment offset) 888 * we just feed in this, else we stuff in as much 889 * as we can. 890 */ 891 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) 892 mapbytes = bytesleft; 893 else 894 mapbytes = PAGE_SIZE - offset_in_page(bufp); 895 sg_set_page(sg, virt_to_page(bufp), 896 mapbytes, offset_in_page(bufp)); 897 bufp += mapbytes; 898 bytesleft -= mapbytes; 899 dev_dbg(&pl022->adev->dev, 900 "set RX/TX target page @ %p, %d bytes, %d left\n", 901 bufp, mapbytes, bytesleft); 902 } 903 } else { 904 /* Map the dummy buffer on every page */ 905 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { 906 if (bytesleft < PAGE_SIZE) 907 mapbytes = bytesleft; 908 else 909 mapbytes = PAGE_SIZE; 910 sg_set_page(sg, virt_to_page(pl022->dummypage), 911 mapbytes, 0); 912 bytesleft -= mapbytes; 913 dev_dbg(&pl022->adev->dev, 914 "set RX/TX to dummy page %d bytes, %d left\n", 915 mapbytes, bytesleft); 916 917 } 918 } 919 BUG_ON(bytesleft); 920 } 921 922 /** 923 * configure_dma - configures the channels for the next transfer 924 * @pl022: SSP driver's private data structure 925 */ 926 static int configure_dma(struct pl022 *pl022) 927 { 928 struct dma_slave_config rx_conf = { 929 .src_addr = SSP_DR(pl022->phybase), 930 .direction = DMA_DEV_TO_MEM, 931 .device_fc = false, 932 }; 933 struct dma_slave_config tx_conf = { 934 .dst_addr = SSP_DR(pl022->phybase), 935 .direction = DMA_MEM_TO_DEV, 936 .device_fc = false, 937 }; 938 unsigned int pages; 939 int ret; 940 int rx_sglen, tx_sglen; 941 struct dma_chan *rxchan = pl022->dma_rx_channel; 942 struct dma_chan *txchan = pl022->dma_tx_channel; 943 struct dma_async_tx_descriptor *rxdesc; 944 struct dma_async_tx_descriptor *txdesc; 945 946 /* Check that the channels are available */ 947 if (!rxchan || !txchan) 948 return -ENODEV; 949 950 /* 951 * If supplied, the DMA burstsize should equal the FIFO trigger level. 952 * Notice that the DMA engine uses one-to-one mapping. Since we can 953 * not trigger on 2 elements this needs explicit mapping rather than 954 * calculation. 955 */ 956 switch (pl022->rx_lev_trig) { 957 case SSP_RX_1_OR_MORE_ELEM: 958 rx_conf.src_maxburst = 1; 959 break; 960 case SSP_RX_4_OR_MORE_ELEM: 961 rx_conf.src_maxburst = 4; 962 break; 963 case SSP_RX_8_OR_MORE_ELEM: 964 rx_conf.src_maxburst = 8; 965 break; 966 case SSP_RX_16_OR_MORE_ELEM: 967 rx_conf.src_maxburst = 16; 968 break; 969 case SSP_RX_32_OR_MORE_ELEM: 970 rx_conf.src_maxburst = 32; 971 break; 972 default: 973 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; 974 break; 975 } 976 977 switch (pl022->tx_lev_trig) { 978 case SSP_TX_1_OR_MORE_EMPTY_LOC: 979 tx_conf.dst_maxburst = 1; 980 break; 981 case SSP_TX_4_OR_MORE_EMPTY_LOC: 982 tx_conf.dst_maxburst = 4; 983 break; 984 case SSP_TX_8_OR_MORE_EMPTY_LOC: 985 tx_conf.dst_maxburst = 8; 986 break; 987 case SSP_TX_16_OR_MORE_EMPTY_LOC: 988 tx_conf.dst_maxburst = 16; 989 break; 990 case SSP_TX_32_OR_MORE_EMPTY_LOC: 991 tx_conf.dst_maxburst = 32; 992 break; 993 default: 994 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; 995 break; 996 } 997 998 switch (pl022->read) { 999 case READING_NULL: 1000 /* Use the same as for writing */ 1001 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1002 break; 1003 case READING_U8: 1004 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1005 break; 1006 case READING_U16: 1007 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1008 break; 1009 case READING_U32: 1010 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1011 break; 1012 } 1013 1014 switch (pl022->write) { 1015 case WRITING_NULL: 1016 /* Use the same as for reading */ 1017 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1018 break; 1019 case WRITING_U8: 1020 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1021 break; 1022 case WRITING_U16: 1023 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1024 break; 1025 case WRITING_U32: 1026 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1027 break; 1028 } 1029 1030 /* SPI pecularity: we need to read and write the same width */ 1031 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1032 rx_conf.src_addr_width = tx_conf.dst_addr_width; 1033 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 1034 tx_conf.dst_addr_width = rx_conf.src_addr_width; 1035 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); 1036 1037 dmaengine_slave_config(rxchan, &rx_conf); 1038 dmaengine_slave_config(txchan, &tx_conf); 1039 1040 /* Create sglists for the transfers */ 1041 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); 1042 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); 1043 1044 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); 1045 if (ret) 1046 goto err_alloc_rx_sg; 1047 1048 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); 1049 if (ret) 1050 goto err_alloc_tx_sg; 1051 1052 /* Fill in the scatterlists for the RX+TX buffers */ 1053 setup_dma_scatter(pl022, pl022->rx, 1054 pl022->cur_transfer->len, &pl022->sgt_rx); 1055 setup_dma_scatter(pl022, pl022->tx, 1056 pl022->cur_transfer->len, &pl022->sgt_tx); 1057 1058 /* Map DMA buffers */ 1059 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1060 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1061 if (!rx_sglen) 1062 goto err_rx_sgmap; 1063 1064 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1065 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1066 if (!tx_sglen) 1067 goto err_tx_sgmap; 1068 1069 /* Send both scatterlists */ 1070 rxdesc = dmaengine_prep_slave_sg(rxchan, 1071 pl022->sgt_rx.sgl, 1072 rx_sglen, 1073 DMA_DEV_TO_MEM, 1074 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1075 if (!rxdesc) 1076 goto err_rxdesc; 1077 1078 txdesc = dmaengine_prep_slave_sg(txchan, 1079 pl022->sgt_tx.sgl, 1080 tx_sglen, 1081 DMA_MEM_TO_DEV, 1082 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1083 if (!txdesc) 1084 goto err_txdesc; 1085 1086 /* Put the callback on the RX transfer only, that should finish last */ 1087 rxdesc->callback = dma_callback; 1088 rxdesc->callback_param = pl022; 1089 1090 /* Submit and fire RX and TX with TX last so we're ready to read! */ 1091 dmaengine_submit(rxdesc); 1092 dmaengine_submit(txdesc); 1093 dma_async_issue_pending(rxchan); 1094 dma_async_issue_pending(txchan); 1095 pl022->dma_running = true; 1096 1097 return 0; 1098 1099 err_txdesc: 1100 dmaengine_terminate_all(txchan); 1101 err_rxdesc: 1102 dmaengine_terminate_all(rxchan); 1103 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, 1104 pl022->sgt_tx.nents, DMA_TO_DEVICE); 1105 err_tx_sgmap: 1106 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, 1107 pl022->sgt_rx.nents, DMA_FROM_DEVICE); 1108 err_rx_sgmap: 1109 sg_free_table(&pl022->sgt_tx); 1110 err_alloc_tx_sg: 1111 sg_free_table(&pl022->sgt_rx); 1112 err_alloc_rx_sg: 1113 return -ENOMEM; 1114 } 1115 1116 static int pl022_dma_probe(struct pl022 *pl022) 1117 { 1118 dma_cap_mask_t mask; 1119 1120 /* Try to acquire a generic DMA engine slave channel */ 1121 dma_cap_zero(mask); 1122 dma_cap_set(DMA_SLAVE, mask); 1123 /* 1124 * We need both RX and TX channels to do DMA, else do none 1125 * of them. 1126 */ 1127 pl022->dma_rx_channel = dma_request_channel(mask, 1128 pl022->master_info->dma_filter, 1129 pl022->master_info->dma_rx_param); 1130 if (!pl022->dma_rx_channel) { 1131 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); 1132 goto err_no_rxchan; 1133 } 1134 1135 pl022->dma_tx_channel = dma_request_channel(mask, 1136 pl022->master_info->dma_filter, 1137 pl022->master_info->dma_tx_param); 1138 if (!pl022->dma_tx_channel) { 1139 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); 1140 goto err_no_txchan; 1141 } 1142 1143 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1144 if (!pl022->dummypage) 1145 goto err_no_dummypage; 1146 1147 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", 1148 dma_chan_name(pl022->dma_rx_channel), 1149 dma_chan_name(pl022->dma_tx_channel)); 1150 1151 return 0; 1152 1153 err_no_dummypage: 1154 dma_release_channel(pl022->dma_tx_channel); 1155 err_no_txchan: 1156 dma_release_channel(pl022->dma_rx_channel); 1157 pl022->dma_rx_channel = NULL; 1158 err_no_rxchan: 1159 dev_err(&pl022->adev->dev, 1160 "Failed to work in dma mode, work without dma!\n"); 1161 return -ENODEV; 1162 } 1163 1164 static int pl022_dma_autoprobe(struct pl022 *pl022) 1165 { 1166 struct device *dev = &pl022->adev->dev; 1167 struct dma_chan *chan; 1168 int err; 1169 1170 /* automatically configure DMA channels from platform, normally using DT */ 1171 chan = dma_request_slave_channel_reason(dev, "rx"); 1172 if (IS_ERR(chan)) { 1173 err = PTR_ERR(chan); 1174 goto err_no_rxchan; 1175 } 1176 1177 pl022->dma_rx_channel = chan; 1178 1179 chan = dma_request_slave_channel_reason(dev, "tx"); 1180 if (IS_ERR(chan)) { 1181 err = PTR_ERR(chan); 1182 goto err_no_txchan; 1183 } 1184 1185 pl022->dma_tx_channel = chan; 1186 1187 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); 1188 if (!pl022->dummypage) { 1189 err = -ENOMEM; 1190 goto err_no_dummypage; 1191 } 1192 1193 return 0; 1194 1195 err_no_dummypage: 1196 dma_release_channel(pl022->dma_tx_channel); 1197 pl022->dma_tx_channel = NULL; 1198 err_no_txchan: 1199 dma_release_channel(pl022->dma_rx_channel); 1200 pl022->dma_rx_channel = NULL; 1201 err_no_rxchan: 1202 return err; 1203 } 1204 1205 static void terminate_dma(struct pl022 *pl022) 1206 { 1207 struct dma_chan *rxchan = pl022->dma_rx_channel; 1208 struct dma_chan *txchan = pl022->dma_tx_channel; 1209 1210 dmaengine_terminate_all(rxchan); 1211 dmaengine_terminate_all(txchan); 1212 unmap_free_dma_scatter(pl022); 1213 pl022->dma_running = false; 1214 } 1215 1216 static void pl022_dma_remove(struct pl022 *pl022) 1217 { 1218 if (pl022->dma_running) 1219 terminate_dma(pl022); 1220 if (pl022->dma_tx_channel) 1221 dma_release_channel(pl022->dma_tx_channel); 1222 if (pl022->dma_rx_channel) 1223 dma_release_channel(pl022->dma_rx_channel); 1224 kfree(pl022->dummypage); 1225 } 1226 1227 #else 1228 static inline int configure_dma(struct pl022 *pl022) 1229 { 1230 return -ENODEV; 1231 } 1232 1233 static inline int pl022_dma_autoprobe(struct pl022 *pl022) 1234 { 1235 return 0; 1236 } 1237 1238 static inline int pl022_dma_probe(struct pl022 *pl022) 1239 { 1240 return 0; 1241 } 1242 1243 static inline void pl022_dma_remove(struct pl022 *pl022) 1244 { 1245 } 1246 #endif 1247 1248 /** 1249 * pl022_interrupt_handler - Interrupt handler for SSP controller 1250 * 1251 * This function handles interrupts generated for an interrupt based transfer. 1252 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the 1253 * current message's state as STATE_ERROR and schedule the tasklet 1254 * pump_transfers which will do the postprocessing of the current message by 1255 * calling giveback(). Otherwise it reads data from RX FIFO till there is no 1256 * more data, and writes data in TX FIFO till it is not full. If we complete 1257 * the transfer we move to the next transfer and schedule the tasklet. 1258 */ 1259 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) 1260 { 1261 struct pl022 *pl022 = dev_id; 1262 struct spi_message *msg = pl022->cur_msg; 1263 u16 irq_status = 0; 1264 1265 if (unlikely(!msg)) { 1266 dev_err(&pl022->adev->dev, 1267 "bad message state in interrupt handler"); 1268 /* Never fail */ 1269 return IRQ_HANDLED; 1270 } 1271 1272 /* Read the Interrupt Status Register */ 1273 irq_status = readw(SSP_MIS(pl022->virtbase)); 1274 1275 if (unlikely(!irq_status)) 1276 return IRQ_NONE; 1277 1278 /* 1279 * This handles the FIFO interrupts, the timeout 1280 * interrupts are flatly ignored, they cannot be 1281 * trusted. 1282 */ 1283 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { 1284 /* 1285 * Overrun interrupt - bail out since our Data has been 1286 * corrupted 1287 */ 1288 dev_err(&pl022->adev->dev, "FIFO overrun\n"); 1289 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) 1290 dev_err(&pl022->adev->dev, 1291 "RXFIFO is full\n"); 1292 1293 /* 1294 * Disable and clear interrupts, disable SSP, 1295 * mark message with bad status so it can be 1296 * retried. 1297 */ 1298 writew(DISABLE_ALL_INTERRUPTS, 1299 SSP_IMSC(pl022->virtbase)); 1300 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1301 writew((readw(SSP_CR1(pl022->virtbase)) & 1302 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1303 msg->state = STATE_ERROR; 1304 1305 /* Schedule message queue handler */ 1306 tasklet_schedule(&pl022->pump_transfers); 1307 return IRQ_HANDLED; 1308 } 1309 1310 readwriter(pl022); 1311 1312 if (pl022->tx == pl022->tx_end) { 1313 /* Disable Transmit interrupt, enable receive interrupt */ 1314 writew((readw(SSP_IMSC(pl022->virtbase)) & 1315 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, 1316 SSP_IMSC(pl022->virtbase)); 1317 } 1318 1319 /* 1320 * Since all transactions must write as much as shall be read, 1321 * we can conclude the entire transaction once RX is complete. 1322 * At this point, all TX will always be finished. 1323 */ 1324 if (pl022->rx >= pl022->rx_end) { 1325 writew(DISABLE_ALL_INTERRUPTS, 1326 SSP_IMSC(pl022->virtbase)); 1327 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); 1328 if (unlikely(pl022->rx > pl022->rx_end)) { 1329 dev_warn(&pl022->adev->dev, "read %u surplus " 1330 "bytes (did you request an odd " 1331 "number of bytes on a 16bit bus?)\n", 1332 (u32) (pl022->rx - pl022->rx_end)); 1333 } 1334 /* Update total bytes transferred */ 1335 msg->actual_length += pl022->cur_transfer->len; 1336 if (pl022->cur_transfer->cs_change) 1337 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1338 /* Move to next transfer */ 1339 msg->state = next_transfer(pl022); 1340 tasklet_schedule(&pl022->pump_transfers); 1341 return IRQ_HANDLED; 1342 } 1343 1344 return IRQ_HANDLED; 1345 } 1346 1347 /** 1348 * This sets up the pointers to memory for the next message to 1349 * send out on the SPI bus. 1350 */ 1351 static int set_up_next_transfer(struct pl022 *pl022, 1352 struct spi_transfer *transfer) 1353 { 1354 int residue; 1355 1356 /* Sanity check the message for this bus width */ 1357 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; 1358 if (unlikely(residue != 0)) { 1359 dev_err(&pl022->adev->dev, 1360 "message of %u bytes to transmit but the current " 1361 "chip bus has a data width of %u bytes!\n", 1362 pl022->cur_transfer->len, 1363 pl022->cur_chip->n_bytes); 1364 dev_err(&pl022->adev->dev, "skipping this message\n"); 1365 return -EIO; 1366 } 1367 pl022->tx = (void *)transfer->tx_buf; 1368 pl022->tx_end = pl022->tx + pl022->cur_transfer->len; 1369 pl022->rx = (void *)transfer->rx_buf; 1370 pl022->rx_end = pl022->rx + pl022->cur_transfer->len; 1371 pl022->write = 1372 pl022->tx ? pl022->cur_chip->write : WRITING_NULL; 1373 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; 1374 return 0; 1375 } 1376 1377 /** 1378 * pump_transfers - Tasklet function which schedules next transfer 1379 * when running in interrupt or DMA transfer mode. 1380 * @data: SSP driver private data structure 1381 * 1382 */ 1383 static void pump_transfers(unsigned long data) 1384 { 1385 struct pl022 *pl022 = (struct pl022 *) data; 1386 struct spi_message *message = NULL; 1387 struct spi_transfer *transfer = NULL; 1388 struct spi_transfer *previous = NULL; 1389 1390 /* Get current state information */ 1391 message = pl022->cur_msg; 1392 transfer = pl022->cur_transfer; 1393 1394 /* Handle for abort */ 1395 if (message->state == STATE_ERROR) { 1396 message->status = -EIO; 1397 giveback(pl022); 1398 return; 1399 } 1400 1401 /* Handle end of message */ 1402 if (message->state == STATE_DONE) { 1403 message->status = 0; 1404 giveback(pl022); 1405 return; 1406 } 1407 1408 /* Delay if requested at end of transfer before CS change */ 1409 if (message->state == STATE_RUNNING) { 1410 previous = list_entry(transfer->transfer_list.prev, 1411 struct spi_transfer, 1412 transfer_list); 1413 if (previous->delay_usecs) 1414 /* 1415 * FIXME: This runs in interrupt context. 1416 * Is this really smart? 1417 */ 1418 udelay(previous->delay_usecs); 1419 1420 /* Reselect chip select only if cs_change was requested */ 1421 if (previous->cs_change) 1422 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1423 } else { 1424 /* STATE_START */ 1425 message->state = STATE_RUNNING; 1426 } 1427 1428 if (set_up_next_transfer(pl022, transfer)) { 1429 message->state = STATE_ERROR; 1430 message->status = -EIO; 1431 giveback(pl022); 1432 return; 1433 } 1434 /* Flush the FIFOs and let's go! */ 1435 flush(pl022); 1436 1437 if (pl022->cur_chip->enable_dma) { 1438 if (configure_dma(pl022)) { 1439 dev_dbg(&pl022->adev->dev, 1440 "configuration of DMA failed, fall back to interrupt mode\n"); 1441 goto err_config_dma; 1442 } 1443 return; 1444 } 1445 1446 err_config_dma: 1447 /* enable all interrupts except RX */ 1448 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); 1449 } 1450 1451 static void do_interrupt_dma_transfer(struct pl022 *pl022) 1452 { 1453 /* 1454 * Default is to enable all interrupts except RX - 1455 * this will be enabled once TX is complete 1456 */ 1457 u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM); 1458 1459 /* Enable target chip, if not already active */ 1460 if (!pl022->next_msg_cs_active) 1461 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1462 1463 if (set_up_next_transfer(pl022, pl022->cur_transfer)) { 1464 /* Error path */ 1465 pl022->cur_msg->state = STATE_ERROR; 1466 pl022->cur_msg->status = -EIO; 1467 giveback(pl022); 1468 return; 1469 } 1470 /* If we're using DMA, set up DMA here */ 1471 if (pl022->cur_chip->enable_dma) { 1472 /* Configure DMA transfer */ 1473 if (configure_dma(pl022)) { 1474 dev_dbg(&pl022->adev->dev, 1475 "configuration of DMA failed, fall back to interrupt mode\n"); 1476 goto err_config_dma; 1477 } 1478 /* Disable interrupts in DMA mode, IRQ from DMA controller */ 1479 irqflags = DISABLE_ALL_INTERRUPTS; 1480 } 1481 err_config_dma: 1482 /* Enable SSP, turn on interrupts */ 1483 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1484 SSP_CR1(pl022->virtbase)); 1485 writew(irqflags, SSP_IMSC(pl022->virtbase)); 1486 } 1487 1488 static void do_polling_transfer(struct pl022 *pl022) 1489 { 1490 struct spi_message *message = NULL; 1491 struct spi_transfer *transfer = NULL; 1492 struct spi_transfer *previous = NULL; 1493 struct chip_data *chip; 1494 unsigned long time, timeout; 1495 1496 chip = pl022->cur_chip; 1497 message = pl022->cur_msg; 1498 1499 while (message->state != STATE_DONE) { 1500 /* Handle for abort */ 1501 if (message->state == STATE_ERROR) 1502 break; 1503 transfer = pl022->cur_transfer; 1504 1505 /* Delay if requested at end of transfer */ 1506 if (message->state == STATE_RUNNING) { 1507 previous = 1508 list_entry(transfer->transfer_list.prev, 1509 struct spi_transfer, transfer_list); 1510 if (previous->delay_usecs) 1511 udelay(previous->delay_usecs); 1512 if (previous->cs_change) 1513 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1514 } else { 1515 /* STATE_START */ 1516 message->state = STATE_RUNNING; 1517 if (!pl022->next_msg_cs_active) 1518 pl022_cs_control(pl022, SSP_CHIP_SELECT); 1519 } 1520 1521 /* Configuration Changing Per Transfer */ 1522 if (set_up_next_transfer(pl022, transfer)) { 1523 /* Error path */ 1524 message->state = STATE_ERROR; 1525 break; 1526 } 1527 /* Flush FIFOs and enable SSP */ 1528 flush(pl022); 1529 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), 1530 SSP_CR1(pl022->virtbase)); 1531 1532 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); 1533 1534 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); 1535 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { 1536 time = jiffies; 1537 readwriter(pl022); 1538 if (time_after(time, timeout)) { 1539 dev_warn(&pl022->adev->dev, 1540 "%s: timeout!\n", __func__); 1541 message->state = STATE_ERROR; 1542 goto out; 1543 } 1544 cpu_relax(); 1545 } 1546 1547 /* Update total byte transferred */ 1548 message->actual_length += pl022->cur_transfer->len; 1549 if (pl022->cur_transfer->cs_change) 1550 pl022_cs_control(pl022, SSP_CHIP_DESELECT); 1551 /* Move to next transfer */ 1552 message->state = next_transfer(pl022); 1553 } 1554 out: 1555 /* Handle end of message */ 1556 if (message->state == STATE_DONE) 1557 message->status = 0; 1558 else 1559 message->status = -EIO; 1560 1561 giveback(pl022); 1562 return; 1563 } 1564 1565 static int pl022_transfer_one_message(struct spi_master *master, 1566 struct spi_message *msg) 1567 { 1568 struct pl022 *pl022 = spi_master_get_devdata(master); 1569 1570 /* Initial message state */ 1571 pl022->cur_msg = msg; 1572 msg->state = STATE_START; 1573 1574 pl022->cur_transfer = list_entry(msg->transfers.next, 1575 struct spi_transfer, transfer_list); 1576 1577 /* Setup the SPI using the per chip configuration */ 1578 pl022->cur_chip = spi_get_ctldata(msg->spi); 1579 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; 1580 1581 restore_state(pl022); 1582 flush(pl022); 1583 1584 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) 1585 do_polling_transfer(pl022); 1586 else 1587 do_interrupt_dma_transfer(pl022); 1588 1589 return 0; 1590 } 1591 1592 static int pl022_unprepare_transfer_hardware(struct spi_master *master) 1593 { 1594 struct pl022 *pl022 = spi_master_get_devdata(master); 1595 1596 /* nothing more to do - disable spi/ssp and power off */ 1597 writew((readw(SSP_CR1(pl022->virtbase)) & 1598 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); 1599 1600 return 0; 1601 } 1602 1603 static int verify_controller_parameters(struct pl022 *pl022, 1604 struct pl022_config_chip const *chip_info) 1605 { 1606 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) 1607 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { 1608 dev_err(&pl022->adev->dev, 1609 "interface is configured incorrectly\n"); 1610 return -EINVAL; 1611 } 1612 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && 1613 (!pl022->vendor->unidir)) { 1614 dev_err(&pl022->adev->dev, 1615 "unidirectional mode not supported in this " 1616 "hardware version\n"); 1617 return -EINVAL; 1618 } 1619 if ((chip_info->hierarchy != SSP_MASTER) 1620 && (chip_info->hierarchy != SSP_SLAVE)) { 1621 dev_err(&pl022->adev->dev, 1622 "hierarchy is configured incorrectly\n"); 1623 return -EINVAL; 1624 } 1625 if ((chip_info->com_mode != INTERRUPT_TRANSFER) 1626 && (chip_info->com_mode != DMA_TRANSFER) 1627 && (chip_info->com_mode != POLLING_TRANSFER)) { 1628 dev_err(&pl022->adev->dev, 1629 "Communication mode is configured incorrectly\n"); 1630 return -EINVAL; 1631 } 1632 switch (chip_info->rx_lev_trig) { 1633 case SSP_RX_1_OR_MORE_ELEM: 1634 case SSP_RX_4_OR_MORE_ELEM: 1635 case SSP_RX_8_OR_MORE_ELEM: 1636 /* These are always OK, all variants can handle this */ 1637 break; 1638 case SSP_RX_16_OR_MORE_ELEM: 1639 if (pl022->vendor->fifodepth < 16) { 1640 dev_err(&pl022->adev->dev, 1641 "RX FIFO Trigger Level is configured incorrectly\n"); 1642 return -EINVAL; 1643 } 1644 break; 1645 case SSP_RX_32_OR_MORE_ELEM: 1646 if (pl022->vendor->fifodepth < 32) { 1647 dev_err(&pl022->adev->dev, 1648 "RX FIFO Trigger Level is configured incorrectly\n"); 1649 return -EINVAL; 1650 } 1651 break; 1652 default: 1653 dev_err(&pl022->adev->dev, 1654 "RX FIFO Trigger Level is configured incorrectly\n"); 1655 return -EINVAL; 1656 } 1657 switch (chip_info->tx_lev_trig) { 1658 case SSP_TX_1_OR_MORE_EMPTY_LOC: 1659 case SSP_TX_4_OR_MORE_EMPTY_LOC: 1660 case SSP_TX_8_OR_MORE_EMPTY_LOC: 1661 /* These are always OK, all variants can handle this */ 1662 break; 1663 case SSP_TX_16_OR_MORE_EMPTY_LOC: 1664 if (pl022->vendor->fifodepth < 16) { 1665 dev_err(&pl022->adev->dev, 1666 "TX FIFO Trigger Level is configured incorrectly\n"); 1667 return -EINVAL; 1668 } 1669 break; 1670 case SSP_TX_32_OR_MORE_EMPTY_LOC: 1671 if (pl022->vendor->fifodepth < 32) { 1672 dev_err(&pl022->adev->dev, 1673 "TX FIFO Trigger Level is configured incorrectly\n"); 1674 return -EINVAL; 1675 } 1676 break; 1677 default: 1678 dev_err(&pl022->adev->dev, 1679 "TX FIFO Trigger Level is configured incorrectly\n"); 1680 return -EINVAL; 1681 } 1682 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { 1683 if ((chip_info->ctrl_len < SSP_BITS_4) 1684 || (chip_info->ctrl_len > SSP_BITS_32)) { 1685 dev_err(&pl022->adev->dev, 1686 "CTRL LEN is configured incorrectly\n"); 1687 return -EINVAL; 1688 } 1689 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) 1690 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { 1691 dev_err(&pl022->adev->dev, 1692 "Wait State is configured incorrectly\n"); 1693 return -EINVAL; 1694 } 1695 /* Half duplex is only available in the ST Micro version */ 1696 if (pl022->vendor->extended_cr) { 1697 if ((chip_info->duplex != 1698 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1699 && (chip_info->duplex != 1700 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { 1701 dev_err(&pl022->adev->dev, 1702 "Microwire duplex mode is configured incorrectly\n"); 1703 return -EINVAL; 1704 } 1705 } else { 1706 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) 1707 dev_err(&pl022->adev->dev, 1708 "Microwire half duplex mode requested," 1709 " but this is only available in the" 1710 " ST version of PL022\n"); 1711 return -EINVAL; 1712 } 1713 } 1714 return 0; 1715 } 1716 1717 static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) 1718 { 1719 return rate / (cpsdvsr * (1 + scr)); 1720 } 1721 1722 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct 1723 ssp_clock_params * clk_freq) 1724 { 1725 /* Lets calculate the frequency parameters */ 1726 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; 1727 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, 1728 best_scr = 0, tmp, found = 0; 1729 1730 rate = clk_get_rate(pl022->clk); 1731 /* cpsdvscr = 2 & scr 0 */ 1732 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); 1733 /* cpsdvsr = 254 & scr = 255 */ 1734 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); 1735 1736 if (freq > max_tclk) 1737 dev_warn(&pl022->adev->dev, 1738 "Max speed that can be programmed is %d Hz, you requested %d\n", 1739 max_tclk, freq); 1740 1741 if (freq < min_tclk) { 1742 dev_err(&pl022->adev->dev, 1743 "Requested frequency: %d Hz is less than minimum possible %d Hz\n", 1744 freq, min_tclk); 1745 return -EINVAL; 1746 } 1747 1748 /* 1749 * best_freq will give closest possible available rate (<= requested 1750 * freq) for all values of scr & cpsdvsr. 1751 */ 1752 while ((cpsdvsr <= CPSDVR_MAX) && !found) { 1753 while (scr <= SCR_MAX) { 1754 tmp = spi_rate(rate, cpsdvsr, scr); 1755 1756 if (tmp > freq) { 1757 /* we need lower freq */ 1758 scr++; 1759 continue; 1760 } 1761 1762 /* 1763 * If found exact value, mark found and break. 1764 * If found more closer value, update and break. 1765 */ 1766 if (tmp > best_freq) { 1767 best_freq = tmp; 1768 best_cpsdvsr = cpsdvsr; 1769 best_scr = scr; 1770 1771 if (tmp == freq) 1772 found = 1; 1773 } 1774 /* 1775 * increased scr will give lower rates, which are not 1776 * required 1777 */ 1778 break; 1779 } 1780 cpsdvsr += 2; 1781 scr = SCR_MIN; 1782 } 1783 1784 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", 1785 freq); 1786 1787 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); 1788 clk_freq->scr = (u8) (best_scr & 0xFF); 1789 dev_dbg(&pl022->adev->dev, 1790 "SSP Target Frequency is: %u, Effective Frequency is %u\n", 1791 freq, best_freq); 1792 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", 1793 clk_freq->cpsdvsr, clk_freq->scr); 1794 1795 return 0; 1796 } 1797 1798 /* 1799 * A piece of default chip info unless the platform 1800 * supplies it. 1801 */ 1802 static const struct pl022_config_chip pl022_default_chip_info = { 1803 .com_mode = POLLING_TRANSFER, 1804 .iface = SSP_INTERFACE_MOTOROLA_SPI, 1805 .hierarchy = SSP_SLAVE, 1806 .slave_tx_disable = DO_NOT_DRIVE_TX, 1807 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, 1808 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, 1809 .ctrl_len = SSP_BITS_8, 1810 .wait_state = SSP_MWIRE_WAIT_ZERO, 1811 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 1812 .cs_control = null_cs_control, 1813 }; 1814 1815 /** 1816 * pl022_setup - setup function registered to SPI master framework 1817 * @spi: spi device which is requesting setup 1818 * 1819 * This function is registered to the SPI framework for this SPI master 1820 * controller. If it is the first time when setup is called by this device, 1821 * this function will initialize the runtime state for this chip and save 1822 * the same in the device structure. Else it will update the runtime info 1823 * with the updated chip info. Nothing is really being written to the 1824 * controller hardware here, that is not done until the actual transfer 1825 * commence. 1826 */ 1827 static int pl022_setup(struct spi_device *spi) 1828 { 1829 struct pl022_config_chip const *chip_info; 1830 struct pl022_config_chip chip_info_dt; 1831 struct chip_data *chip; 1832 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; 1833 int status = 0; 1834 struct pl022 *pl022 = spi_master_get_devdata(spi->master); 1835 unsigned int bits = spi->bits_per_word; 1836 u32 tmp; 1837 struct device_node *np = spi->dev.of_node; 1838 1839 if (!spi->max_speed_hz) 1840 return -EINVAL; 1841 1842 /* Get controller_state if one is supplied */ 1843 chip = spi_get_ctldata(spi); 1844 1845 if (chip == NULL) { 1846 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1847 if (!chip) 1848 return -ENOMEM; 1849 dev_dbg(&spi->dev, 1850 "allocated memory for controller's runtime state\n"); 1851 } 1852 1853 /* Get controller data if one is supplied */ 1854 chip_info = spi->controller_data; 1855 1856 if (chip_info == NULL) { 1857 if (np) { 1858 chip_info_dt = pl022_default_chip_info; 1859 1860 chip_info_dt.hierarchy = SSP_MASTER; 1861 of_property_read_u32(np, "pl022,interface", 1862 &chip_info_dt.iface); 1863 of_property_read_u32(np, "pl022,com-mode", 1864 &chip_info_dt.com_mode); 1865 of_property_read_u32(np, "pl022,rx-level-trig", 1866 &chip_info_dt.rx_lev_trig); 1867 of_property_read_u32(np, "pl022,tx-level-trig", 1868 &chip_info_dt.tx_lev_trig); 1869 of_property_read_u32(np, "pl022,ctrl-len", 1870 &chip_info_dt.ctrl_len); 1871 of_property_read_u32(np, "pl022,wait-state", 1872 &chip_info_dt.wait_state); 1873 of_property_read_u32(np, "pl022,duplex", 1874 &chip_info_dt.duplex); 1875 1876 chip_info = &chip_info_dt; 1877 } else { 1878 chip_info = &pl022_default_chip_info; 1879 /* spi_board_info.controller_data not is supplied */ 1880 dev_dbg(&spi->dev, 1881 "using default controller_data settings\n"); 1882 } 1883 } else 1884 dev_dbg(&spi->dev, 1885 "using user supplied controller_data settings\n"); 1886 1887 /* 1888 * We can override with custom divisors, else we use the board 1889 * frequency setting 1890 */ 1891 if ((0 == chip_info->clk_freq.cpsdvsr) 1892 && (0 == chip_info->clk_freq.scr)) { 1893 status = calculate_effective_freq(pl022, 1894 spi->max_speed_hz, 1895 &clk_freq); 1896 if (status < 0) 1897 goto err_config_params; 1898 } else { 1899 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); 1900 if ((clk_freq.cpsdvsr % 2) != 0) 1901 clk_freq.cpsdvsr = 1902 clk_freq.cpsdvsr - 1; 1903 } 1904 if ((clk_freq.cpsdvsr < CPSDVR_MIN) 1905 || (clk_freq.cpsdvsr > CPSDVR_MAX)) { 1906 status = -EINVAL; 1907 dev_err(&spi->dev, 1908 "cpsdvsr is configured incorrectly\n"); 1909 goto err_config_params; 1910 } 1911 1912 status = verify_controller_parameters(pl022, chip_info); 1913 if (status) { 1914 dev_err(&spi->dev, "controller data is incorrect"); 1915 goto err_config_params; 1916 } 1917 1918 pl022->rx_lev_trig = chip_info->rx_lev_trig; 1919 pl022->tx_lev_trig = chip_info->tx_lev_trig; 1920 1921 /* Now set controller state based on controller data */ 1922 chip->xfer_type = chip_info->com_mode; 1923 if (!chip_info->cs_control) { 1924 chip->cs_control = null_cs_control; 1925 if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) 1926 dev_warn(&spi->dev, 1927 "invalid chip select\n"); 1928 } else 1929 chip->cs_control = chip_info->cs_control; 1930 1931 /* Check bits per word with vendor specific range */ 1932 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { 1933 status = -ENOTSUPP; 1934 dev_err(&spi->dev, "illegal data size for this controller!\n"); 1935 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", 1936 pl022->vendor->max_bpw); 1937 goto err_config_params; 1938 } else if (bits <= 8) { 1939 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); 1940 chip->n_bytes = 1; 1941 chip->read = READING_U8; 1942 chip->write = WRITING_U8; 1943 } else if (bits <= 16) { 1944 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); 1945 chip->n_bytes = 2; 1946 chip->read = READING_U16; 1947 chip->write = WRITING_U16; 1948 } else { 1949 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); 1950 chip->n_bytes = 4; 1951 chip->read = READING_U32; 1952 chip->write = WRITING_U32; 1953 } 1954 1955 /* Now Initialize all register settings required for this chip */ 1956 chip->cr0 = 0; 1957 chip->cr1 = 0; 1958 chip->dmacr = 0; 1959 chip->cpsr = 0; 1960 if ((chip_info->com_mode == DMA_TRANSFER) 1961 && ((pl022->master_info)->enable_dma)) { 1962 chip->enable_dma = true; 1963 dev_dbg(&spi->dev, "DMA mode set in controller state\n"); 1964 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1965 SSP_DMACR_MASK_RXDMAE, 0); 1966 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, 1967 SSP_DMACR_MASK_TXDMAE, 1); 1968 } else { 1969 chip->enable_dma = false; 1970 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); 1971 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1972 SSP_DMACR_MASK_RXDMAE, 0); 1973 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, 1974 SSP_DMACR_MASK_TXDMAE, 1); 1975 } 1976 1977 chip->cpsr = clk_freq.cpsdvsr; 1978 1979 /* Special setup for the ST micro extended control registers */ 1980 if (pl022->vendor->extended_cr) { 1981 u32 etx; 1982 1983 if (pl022->vendor->pl023) { 1984 /* These bits are only in the PL023 */ 1985 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, 1986 SSP_CR1_MASK_FBCLKDEL_ST, 13); 1987 } else { 1988 /* These bits are in the PL022 but not PL023 */ 1989 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, 1990 SSP_CR0_MASK_HALFDUP_ST, 5); 1991 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, 1992 SSP_CR0_MASK_CSS_ST, 16); 1993 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 1994 SSP_CR0_MASK_FRF_ST, 21); 1995 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, 1996 SSP_CR1_MASK_MWAIT_ST, 6); 1997 } 1998 SSP_WRITE_BITS(chip->cr0, bits - 1, 1999 SSP_CR0_MASK_DSS_ST, 0); 2000 2001 if (spi->mode & SPI_LSB_FIRST) { 2002 tmp = SSP_RX_LSB; 2003 etx = SSP_TX_LSB; 2004 } else { 2005 tmp = SSP_RX_MSB; 2006 etx = SSP_TX_MSB; 2007 } 2008 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); 2009 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); 2010 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, 2011 SSP_CR1_MASK_RXIFLSEL_ST, 7); 2012 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, 2013 SSP_CR1_MASK_TXIFLSEL_ST, 10); 2014 } else { 2015 SSP_WRITE_BITS(chip->cr0, bits - 1, 2016 SSP_CR0_MASK_DSS, 0); 2017 SSP_WRITE_BITS(chip->cr0, chip_info->iface, 2018 SSP_CR0_MASK_FRF, 4); 2019 } 2020 2021 /* Stuff that is common for all versions */ 2022 if (spi->mode & SPI_CPOL) 2023 tmp = SSP_CLK_POL_IDLE_HIGH; 2024 else 2025 tmp = SSP_CLK_POL_IDLE_LOW; 2026 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); 2027 2028 if (spi->mode & SPI_CPHA) 2029 tmp = SSP_CLK_SECOND_EDGE; 2030 else 2031 tmp = SSP_CLK_FIRST_EDGE; 2032 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); 2033 2034 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); 2035 /* Loopback is available on all versions except PL023 */ 2036 if (pl022->vendor->loopback) { 2037 if (spi->mode & SPI_LOOP) 2038 tmp = LOOPBACK_ENABLED; 2039 else 2040 tmp = LOOPBACK_DISABLED; 2041 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); 2042 } 2043 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); 2044 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); 2045 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 2046 3); 2047 2048 /* Save controller_state */ 2049 spi_set_ctldata(spi, chip); 2050 return status; 2051 err_config_params: 2052 spi_set_ctldata(spi, NULL); 2053 kfree(chip); 2054 return status; 2055 } 2056 2057 /** 2058 * pl022_cleanup - cleanup function registered to SPI master framework 2059 * @spi: spi device which is requesting cleanup 2060 * 2061 * This function is registered to the SPI framework for this SPI master 2062 * controller. It will free the runtime state of chip. 2063 */ 2064 static void pl022_cleanup(struct spi_device *spi) 2065 { 2066 struct chip_data *chip = spi_get_ctldata(spi); 2067 2068 spi_set_ctldata(spi, NULL); 2069 kfree(chip); 2070 } 2071 2072 static struct pl022_ssp_controller * 2073 pl022_platform_data_dt_get(struct device *dev) 2074 { 2075 struct device_node *np = dev->of_node; 2076 struct pl022_ssp_controller *pd; 2077 u32 tmp = 0; 2078 2079 if (!np) { 2080 dev_err(dev, "no dt node defined\n"); 2081 return NULL; 2082 } 2083 2084 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL); 2085 if (!pd) 2086 return NULL; 2087 2088 pd->bus_id = -1; 2089 pd->enable_dma = 1; 2090 of_property_read_u32(np, "num-cs", &tmp); 2091 pd->num_chipselect = tmp; 2092 of_property_read_u32(np, "pl022,autosuspend-delay", 2093 &pd->autosuspend_delay); 2094 pd->rt = of_property_read_bool(np, "pl022,rt"); 2095 2096 return pd; 2097 } 2098 2099 static int pl022_probe(struct amba_device *adev, const struct amba_id *id) 2100 { 2101 struct device *dev = &adev->dev; 2102 struct pl022_ssp_controller *platform_info = 2103 dev_get_platdata(&adev->dev); 2104 struct spi_master *master; 2105 struct pl022 *pl022 = NULL; /*Data for this driver */ 2106 struct device_node *np = adev->dev.of_node; 2107 int status = 0, i, num_cs; 2108 2109 dev_info(&adev->dev, 2110 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); 2111 if (!platform_info && IS_ENABLED(CONFIG_OF)) 2112 platform_info = pl022_platform_data_dt_get(dev); 2113 2114 if (!platform_info) { 2115 dev_err(dev, "probe: no platform data defined\n"); 2116 return -ENODEV; 2117 } 2118 2119 if (platform_info->num_chipselect) { 2120 num_cs = platform_info->num_chipselect; 2121 } else { 2122 dev_err(dev, "probe: no chip select defined\n"); 2123 return -ENODEV; 2124 } 2125 2126 /* Allocate master with space for data */ 2127 master = spi_alloc_master(dev, sizeof(struct pl022)); 2128 if (master == NULL) { 2129 dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); 2130 return -ENOMEM; 2131 } 2132 2133 pl022 = spi_master_get_devdata(master); 2134 pl022->master = master; 2135 pl022->master_info = platform_info; 2136 pl022->adev = adev; 2137 pl022->vendor = id->data; 2138 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), 2139 GFP_KERNEL); 2140 if (!pl022->chipselects) { 2141 status = -ENOMEM; 2142 goto err_no_mem; 2143 } 2144 2145 /* 2146 * Bus Number Which has been Assigned to this SSP controller 2147 * on this board 2148 */ 2149 master->bus_num = platform_info->bus_id; 2150 master->num_chipselect = num_cs; 2151 master->cleanup = pl022_cleanup; 2152 master->setup = pl022_setup; 2153 master->auto_runtime_pm = true; 2154 master->transfer_one_message = pl022_transfer_one_message; 2155 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; 2156 master->rt = platform_info->rt; 2157 master->dev.of_node = dev->of_node; 2158 2159 if (platform_info->num_chipselect && platform_info->chipselects) { 2160 for (i = 0; i < num_cs; i++) 2161 pl022->chipselects[i] = platform_info->chipselects[i]; 2162 } else if (pl022->vendor->internal_cs_ctrl) { 2163 for (i = 0; i < num_cs; i++) 2164 pl022->chipselects[i] = i; 2165 } else if (IS_ENABLED(CONFIG_OF)) { 2166 for (i = 0; i < num_cs; i++) { 2167 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 2168 2169 if (cs_gpio == -EPROBE_DEFER) { 2170 status = -EPROBE_DEFER; 2171 goto err_no_gpio; 2172 } 2173 2174 pl022->chipselects[i] = cs_gpio; 2175 2176 if (gpio_is_valid(cs_gpio)) { 2177 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) 2178 dev_err(&adev->dev, 2179 "could not request %d gpio\n", 2180 cs_gpio); 2181 else if (gpio_direction_output(cs_gpio, 1)) 2182 dev_err(&adev->dev, 2183 "could not set gpio %d as output\n", 2184 cs_gpio); 2185 } 2186 } 2187 } 2188 2189 /* 2190 * Supports mode 0-3, loopback, and active low CS. Transfers are 2191 * always MS bit first on the original pl022. 2192 */ 2193 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 2194 if (pl022->vendor->extended_cr) 2195 master->mode_bits |= SPI_LSB_FIRST; 2196 2197 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); 2198 2199 status = amba_request_regions(adev, NULL); 2200 if (status) 2201 goto err_no_ioregion; 2202 2203 pl022->phybase = adev->res.start; 2204 pl022->virtbase = devm_ioremap(dev, adev->res.start, 2205 resource_size(&adev->res)); 2206 if (pl022->virtbase == NULL) { 2207 status = -ENOMEM; 2208 goto err_no_ioremap; 2209 } 2210 dev_info(&adev->dev, "mapped registers from %pa to %p\n", 2211 &adev->res.start, pl022->virtbase); 2212 2213 pl022->clk = devm_clk_get(&adev->dev, NULL); 2214 if (IS_ERR(pl022->clk)) { 2215 status = PTR_ERR(pl022->clk); 2216 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); 2217 goto err_no_clk; 2218 } 2219 2220 status = clk_prepare_enable(pl022->clk); 2221 if (status) { 2222 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); 2223 goto err_no_clk_en; 2224 } 2225 2226 /* Initialize transfer pump */ 2227 tasklet_init(&pl022->pump_transfers, pump_transfers, 2228 (unsigned long)pl022); 2229 2230 /* Disable SSP */ 2231 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), 2232 SSP_CR1(pl022->virtbase)); 2233 load_ssp_default_config(pl022); 2234 2235 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, 2236 0, "pl022", pl022); 2237 if (status < 0) { 2238 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); 2239 goto err_no_irq; 2240 } 2241 2242 /* Get DMA channels, try autoconfiguration first */ 2243 status = pl022_dma_autoprobe(pl022); 2244 if (status == -EPROBE_DEFER) { 2245 dev_dbg(dev, "deferring probe to get DMA channel\n"); 2246 goto err_no_irq; 2247 } 2248 2249 /* If that failed, use channels from platform_info */ 2250 if (status == 0) 2251 platform_info->enable_dma = 1; 2252 else if (platform_info->enable_dma) { 2253 status = pl022_dma_probe(pl022); 2254 if (status != 0) 2255 platform_info->enable_dma = 0; 2256 } 2257 2258 /* Register with the SPI framework */ 2259 amba_set_drvdata(adev, pl022); 2260 status = devm_spi_register_master(&adev->dev, master); 2261 if (status != 0) { 2262 dev_err(&adev->dev, 2263 "probe - problem registering spi master\n"); 2264 goto err_spi_register; 2265 } 2266 dev_dbg(dev, "probe succeeded\n"); 2267 2268 /* let runtime pm put suspend */ 2269 if (platform_info->autosuspend_delay > 0) { 2270 dev_info(&adev->dev, 2271 "will use autosuspend for runtime pm, delay %dms\n", 2272 platform_info->autosuspend_delay); 2273 pm_runtime_set_autosuspend_delay(dev, 2274 platform_info->autosuspend_delay); 2275 pm_runtime_use_autosuspend(dev); 2276 } 2277 pm_runtime_put(dev); 2278 2279 return 0; 2280 2281 err_spi_register: 2282 if (platform_info->enable_dma) 2283 pl022_dma_remove(pl022); 2284 err_no_irq: 2285 clk_disable_unprepare(pl022->clk); 2286 err_no_clk_en: 2287 err_no_clk: 2288 err_no_ioremap: 2289 amba_release_regions(adev); 2290 err_no_ioregion: 2291 err_no_gpio: 2292 err_no_mem: 2293 spi_master_put(master); 2294 return status; 2295 } 2296 2297 static int 2298 pl022_remove(struct amba_device *adev) 2299 { 2300 struct pl022 *pl022 = amba_get_drvdata(adev); 2301 2302 if (!pl022) 2303 return 0; 2304 2305 /* 2306 * undo pm_runtime_put() in probe. I assume that we're not 2307 * accessing the primecell here. 2308 */ 2309 pm_runtime_get_noresume(&adev->dev); 2310 2311 load_ssp_default_config(pl022); 2312 if (pl022->master_info->enable_dma) 2313 pl022_dma_remove(pl022); 2314 2315 clk_disable_unprepare(pl022->clk); 2316 amba_release_regions(adev); 2317 tasklet_disable(&pl022->pump_transfers); 2318 return 0; 2319 } 2320 2321 #ifdef CONFIG_PM_SLEEP 2322 static int pl022_suspend(struct device *dev) 2323 { 2324 struct pl022 *pl022 = dev_get_drvdata(dev); 2325 int ret; 2326 2327 ret = spi_master_suspend(pl022->master); 2328 if (ret) { 2329 dev_warn(dev, "cannot suspend master\n"); 2330 return ret; 2331 } 2332 2333 ret = pm_runtime_force_suspend(dev); 2334 if (ret) { 2335 spi_master_resume(pl022->master); 2336 return ret; 2337 } 2338 2339 pinctrl_pm_select_sleep_state(dev); 2340 2341 dev_dbg(dev, "suspended\n"); 2342 return 0; 2343 } 2344 2345 static int pl022_resume(struct device *dev) 2346 { 2347 struct pl022 *pl022 = dev_get_drvdata(dev); 2348 int ret; 2349 2350 ret = pm_runtime_force_resume(dev); 2351 if (ret) 2352 dev_err(dev, "problem resuming\n"); 2353 2354 /* Start the queue running */ 2355 ret = spi_master_resume(pl022->master); 2356 if (ret) 2357 dev_err(dev, "problem starting queue (%d)\n", ret); 2358 else 2359 dev_dbg(dev, "resumed\n"); 2360 2361 return ret; 2362 } 2363 #endif 2364 2365 #ifdef CONFIG_PM 2366 static int pl022_runtime_suspend(struct device *dev) 2367 { 2368 struct pl022 *pl022 = dev_get_drvdata(dev); 2369 2370 clk_disable_unprepare(pl022->clk); 2371 pinctrl_pm_select_idle_state(dev); 2372 2373 return 0; 2374 } 2375 2376 static int pl022_runtime_resume(struct device *dev) 2377 { 2378 struct pl022 *pl022 = dev_get_drvdata(dev); 2379 2380 pinctrl_pm_select_default_state(dev); 2381 clk_prepare_enable(pl022->clk); 2382 2383 return 0; 2384 } 2385 #endif 2386 2387 static const struct dev_pm_ops pl022_dev_pm_ops = { 2388 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) 2389 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) 2390 }; 2391 2392 static struct vendor_data vendor_arm = { 2393 .fifodepth = 8, 2394 .max_bpw = 16, 2395 .unidir = false, 2396 .extended_cr = false, 2397 .pl023 = false, 2398 .loopback = true, 2399 .internal_cs_ctrl = false, 2400 }; 2401 2402 static struct vendor_data vendor_st = { 2403 .fifodepth = 32, 2404 .max_bpw = 32, 2405 .unidir = false, 2406 .extended_cr = true, 2407 .pl023 = false, 2408 .loopback = true, 2409 .internal_cs_ctrl = false, 2410 }; 2411 2412 static struct vendor_data vendor_st_pl023 = { 2413 .fifodepth = 32, 2414 .max_bpw = 32, 2415 .unidir = false, 2416 .extended_cr = true, 2417 .pl023 = true, 2418 .loopback = false, 2419 .internal_cs_ctrl = false, 2420 }; 2421 2422 static struct vendor_data vendor_lsi = { 2423 .fifodepth = 8, 2424 .max_bpw = 16, 2425 .unidir = false, 2426 .extended_cr = false, 2427 .pl023 = false, 2428 .loopback = true, 2429 .internal_cs_ctrl = true, 2430 }; 2431 2432 static const struct amba_id pl022_ids[] = { 2433 { 2434 /* 2435 * ARM PL022 variant, this has a 16bit wide 2436 * and 8 locations deep TX/RX FIFO 2437 */ 2438 .id = 0x00041022, 2439 .mask = 0x000fffff, 2440 .data = &vendor_arm, 2441 }, 2442 { 2443 /* 2444 * ST Micro derivative, this has 32bit wide 2445 * and 32 locations deep TX/RX FIFO 2446 */ 2447 .id = 0x01080022, 2448 .mask = 0xffffffff, 2449 .data = &vendor_st, 2450 }, 2451 { 2452 /* 2453 * ST-Ericsson derivative "PL023" (this is not 2454 * an official ARM number), this is a PL022 SSP block 2455 * stripped to SPI mode only, it has 32bit wide 2456 * and 32 locations deep TX/RX FIFO but no extended 2457 * CR0/CR1 register 2458 */ 2459 .id = 0x00080023, 2460 .mask = 0xffffffff, 2461 .data = &vendor_st_pl023, 2462 }, 2463 { 2464 /* 2465 * PL022 variant that has a chip select control register whih 2466 * allows control of 5 output signals nCS[0:4]. 2467 */ 2468 .id = 0x000b6022, 2469 .mask = 0x000fffff, 2470 .data = &vendor_lsi, 2471 }, 2472 { 0, 0 }, 2473 }; 2474 2475 MODULE_DEVICE_TABLE(amba, pl022_ids); 2476 2477 static struct amba_driver pl022_driver = { 2478 .drv = { 2479 .name = "ssp-pl022", 2480 .pm = &pl022_dev_pm_ops, 2481 }, 2482 .id_table = pl022_ids, 2483 .probe = pl022_probe, 2484 .remove = pl022_remove, 2485 }; 2486 2487 static int __init pl022_init(void) 2488 { 2489 return amba_driver_register(&pl022_driver); 2490 } 2491 subsys_initcall(pl022_init); 2492 2493 static void __exit pl022_exit(void) 2494 { 2495 amba_driver_unregister(&pl022_driver); 2496 } 2497 module_exit(pl022_exit); 2498 2499 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 2500 MODULE_DESCRIPTION("PL022 SSP Controller Driver"); 2501 MODULE_LICENSE("GPL"); 2502