1 /* 2 * Marvell Orion SPI controller driver 3 * 4 * Author: Shadi Ammouri <shadi@marvell.com> 5 * Copyright (C) 2007-2008 Marvell Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/platform_device.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/spi/spi.h> 18 #include <linux/module.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/clk.h> 24 #include <linux/sizes.h> 25 #include <asm/unaligned.h> 26 27 #define DRIVER_NAME "orion_spi" 28 29 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */ 30 #define SPI_AUTOSUSPEND_TIMEOUT 200 31 32 /* Some SoCs using this driver support up to 8 chip selects. 33 * It is up to the implementer to only use the chip selects 34 * that are available. 35 */ 36 #define ORION_NUM_CHIPSELECTS 8 37 38 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ 39 40 #define ORION_SPI_IF_CTRL_REG 0x00 41 #define ORION_SPI_IF_CONFIG_REG 0x04 42 #define ORION_SPI_DATA_OUT_REG 0x08 43 #define ORION_SPI_DATA_IN_REG 0x0c 44 #define ORION_SPI_INT_CAUSE_REG 0x10 45 #define ORION_SPI_TIMING_PARAMS_REG 0x18 46 47 /* Register for the "Direct Mode" */ 48 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20 49 50 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6) 51 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6) 52 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6) 53 54 #define ORION_SPI_MODE_CPOL (1 << 11) 55 #define ORION_SPI_MODE_CPHA (1 << 12) 56 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) 57 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F 58 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF 59 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ 60 ORION_SPI_MODE_CPHA) 61 #define ORION_SPI_CS_MASK 0x1C 62 #define ORION_SPI_CS_SHIFT 2 63 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ 64 ORION_SPI_CS_MASK) 65 66 enum orion_spi_type { 67 ORION_SPI, 68 ARMADA_SPI, 69 }; 70 71 struct orion_spi_dev { 72 enum orion_spi_type typ; 73 /* 74 * min_divisor and max_hz should be exclusive, the only we can 75 * have both is for managing the armada-370-spi case with old 76 * device tree 77 */ 78 unsigned long max_hz; 79 unsigned int min_divisor; 80 unsigned int max_divisor; 81 u32 prescale_mask; 82 bool is_errata_50mhz_ac; 83 }; 84 85 struct orion_direct_acc { 86 void __iomem *vaddr; 87 u32 size; 88 }; 89 90 struct orion_spi { 91 struct spi_master *master; 92 void __iomem *base; 93 struct clk *clk; 94 const struct orion_spi_dev *devdata; 95 96 struct orion_direct_acc direct_access[ORION_NUM_CHIPSELECTS]; 97 }; 98 99 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) 100 { 101 return orion_spi->base + reg; 102 } 103 104 static inline void 105 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 106 { 107 void __iomem *reg_addr = spi_reg(orion_spi, reg); 108 u32 val; 109 110 val = readl(reg_addr); 111 val |= mask; 112 writel(val, reg_addr); 113 } 114 115 static inline void 116 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 117 { 118 void __iomem *reg_addr = spi_reg(orion_spi, reg); 119 u32 val; 120 121 val = readl(reg_addr); 122 val &= ~mask; 123 writel(val, reg_addr); 124 } 125 126 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 127 { 128 u32 tclk_hz; 129 u32 rate; 130 u32 prescale; 131 u32 reg; 132 struct orion_spi *orion_spi; 133 const struct orion_spi_dev *devdata; 134 135 orion_spi = spi_master_get_devdata(spi->master); 136 devdata = orion_spi->devdata; 137 138 tclk_hz = clk_get_rate(orion_spi->clk); 139 140 if (devdata->typ == ARMADA_SPI) { 141 unsigned int clk, spr, sppr, sppr2, err; 142 unsigned int best_spr, best_sppr, best_err; 143 144 best_err = speed; 145 best_spr = 0; 146 best_sppr = 0; 147 148 /* Iterate over the valid range looking for best fit */ 149 for (sppr = 0; sppr < 8; sppr++) { 150 sppr2 = 0x1 << sppr; 151 152 spr = tclk_hz / sppr2; 153 spr = DIV_ROUND_UP(spr, speed); 154 if ((spr == 0) || (spr > 15)) 155 continue; 156 157 clk = tclk_hz / (spr * sppr2); 158 err = speed - clk; 159 160 if (err < best_err) { 161 best_spr = spr; 162 best_sppr = sppr; 163 best_err = err; 164 } 165 } 166 167 if ((best_sppr == 0) && (best_spr == 0)) 168 return -EINVAL; 169 170 prescale = ((best_sppr & 0x6) << 5) | 171 ((best_sppr & 0x1) << 4) | best_spr; 172 } else { 173 /* 174 * the supported rates are: 4,6,8...30 175 * round up as we look for equal or less speed 176 */ 177 rate = DIV_ROUND_UP(tclk_hz, speed); 178 rate = roundup(rate, 2); 179 180 /* check if requested speed is too small */ 181 if (rate > 30) 182 return -EINVAL; 183 184 if (rate < 4) 185 rate = 4; 186 187 /* Convert the rate to SPI clock divisor value. */ 188 prescale = 0x10 + rate/2; 189 } 190 191 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 192 reg = ((reg & ~devdata->prescale_mask) | prescale); 193 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 194 195 return 0; 196 } 197 198 static void 199 orion_spi_mode_set(struct spi_device *spi) 200 { 201 u32 reg; 202 struct orion_spi *orion_spi; 203 204 orion_spi = spi_master_get_devdata(spi->master); 205 206 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 207 reg &= ~ORION_SPI_MODE_MASK; 208 if (spi->mode & SPI_CPOL) 209 reg |= ORION_SPI_MODE_CPOL; 210 if (spi->mode & SPI_CPHA) 211 reg |= ORION_SPI_MODE_CPHA; 212 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 213 } 214 215 static void 216 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed) 217 { 218 u32 reg; 219 struct orion_spi *orion_spi; 220 221 orion_spi = spi_master_get_devdata(spi->master); 222 223 /* 224 * Erratum description: (Erratum NO. FE-9144572) The device 225 * SPI interface supports frequencies of up to 50 MHz. 226 * However, due to this erratum, when the device core clock is 227 * 250 MHz and the SPI interfaces is configured for 50MHz SPI 228 * clock and CPOL=CPHA=1 there might occur data corruption on 229 * reads from the SPI device. 230 * Erratum Workaround: 231 * Work in one of the following configurations: 232 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration 233 * Register". 234 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1 235 * Register" before setting the interface. 236 */ 237 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); 238 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK; 239 240 if (clk_get_rate(orion_spi->clk) == 250000000 && 241 speed == 50000000 && spi->mode & SPI_CPOL && 242 spi->mode & SPI_CPHA) 243 reg |= ORION_SPI_TMISO_SAMPLE_2; 244 else 245 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */ 246 247 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); 248 } 249 250 /* 251 * called only when no transfer is active on the bus 252 */ 253 static int 254 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 255 { 256 struct orion_spi *orion_spi; 257 unsigned int speed = spi->max_speed_hz; 258 unsigned int bits_per_word = spi->bits_per_word; 259 int rc; 260 261 orion_spi = spi_master_get_devdata(spi->master); 262 263 if ((t != NULL) && t->speed_hz) 264 speed = t->speed_hz; 265 266 if ((t != NULL) && t->bits_per_word) 267 bits_per_word = t->bits_per_word; 268 269 orion_spi_mode_set(spi); 270 271 if (orion_spi->devdata->is_errata_50mhz_ac) 272 orion_spi_50mhz_ac_timing_erratum(spi, speed); 273 274 rc = orion_spi_baudrate_set(spi, speed); 275 if (rc) 276 return rc; 277 278 if (bits_per_word == 16) 279 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 280 ORION_SPI_IF_8_16_BIT_MODE); 281 else 282 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 283 ORION_SPI_IF_8_16_BIT_MODE); 284 285 return 0; 286 } 287 288 static void orion_spi_set_cs(struct spi_device *spi, bool enable) 289 { 290 struct orion_spi *orion_spi; 291 292 orion_spi = spi_master_get_devdata(spi->master); 293 294 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); 295 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 296 ORION_SPI_CS(spi->chip_select)); 297 298 /* Chip select logic is inverted from spi_set_cs */ 299 if (!enable) 300 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 301 else 302 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 303 } 304 305 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) 306 { 307 int i; 308 309 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { 310 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) 311 return 1; 312 313 udelay(1); 314 } 315 316 return -1; 317 } 318 319 static inline int 320 orion_spi_write_read_8bit(struct spi_device *spi, 321 const u8 **tx_buf, u8 **rx_buf) 322 { 323 void __iomem *tx_reg, *rx_reg, *int_reg; 324 struct orion_spi *orion_spi; 325 326 orion_spi = spi_master_get_devdata(spi->master); 327 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 328 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 329 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 330 331 /* clear the interrupt cause register */ 332 writel(0x0, int_reg); 333 334 if (tx_buf && *tx_buf) 335 writel(*(*tx_buf)++, tx_reg); 336 else 337 writel(0, tx_reg); 338 339 if (orion_spi_wait_till_ready(orion_spi) < 0) { 340 dev_err(&spi->dev, "TXS timed out\n"); 341 return -1; 342 } 343 344 if (rx_buf && *rx_buf) 345 *(*rx_buf)++ = readl(rx_reg); 346 347 return 1; 348 } 349 350 static inline int 351 orion_spi_write_read_16bit(struct spi_device *spi, 352 const u16 **tx_buf, u16 **rx_buf) 353 { 354 void __iomem *tx_reg, *rx_reg, *int_reg; 355 struct orion_spi *orion_spi; 356 357 orion_spi = spi_master_get_devdata(spi->master); 358 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 359 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 360 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 361 362 /* clear the interrupt cause register */ 363 writel(0x0, int_reg); 364 365 if (tx_buf && *tx_buf) 366 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); 367 else 368 writel(0, tx_reg); 369 370 if (orion_spi_wait_till_ready(orion_spi) < 0) { 371 dev_err(&spi->dev, "TXS timed out\n"); 372 return -1; 373 } 374 375 if (rx_buf && *rx_buf) 376 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); 377 378 return 1; 379 } 380 381 static unsigned int 382 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 383 { 384 unsigned int count; 385 int word_len; 386 struct orion_spi *orion_spi; 387 int cs = spi->chip_select; 388 389 word_len = spi->bits_per_word; 390 count = xfer->len; 391 392 orion_spi = spi_master_get_devdata(spi->master); 393 394 /* 395 * Use SPI direct write mode if base address is available. Otherwise 396 * fall back to PIO mode for this transfer. 397 */ 398 if ((orion_spi->direct_access[cs].vaddr) && (xfer->tx_buf) && 399 (word_len == 8)) { 400 unsigned int cnt = count / 4; 401 unsigned int rem = count % 4; 402 403 /* 404 * Send the TX-data to the SPI device via the direct 405 * mapped address window 406 */ 407 iowrite32_rep(orion_spi->direct_access[cs].vaddr, 408 xfer->tx_buf, cnt); 409 if (rem) { 410 u32 *buf = (u32 *)xfer->tx_buf; 411 412 iowrite8_rep(orion_spi->direct_access[cs].vaddr, 413 &buf[cnt], rem); 414 } 415 416 return count; 417 } 418 419 if (word_len == 8) { 420 const u8 *tx = xfer->tx_buf; 421 u8 *rx = xfer->rx_buf; 422 423 do { 424 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) 425 goto out; 426 count--; 427 } while (count); 428 } else if (word_len == 16) { 429 const u16 *tx = xfer->tx_buf; 430 u16 *rx = xfer->rx_buf; 431 432 do { 433 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) 434 goto out; 435 count -= 2; 436 } while (count); 437 } 438 439 out: 440 return xfer->len - count; 441 } 442 443 static int orion_spi_transfer_one(struct spi_master *master, 444 struct spi_device *spi, 445 struct spi_transfer *t) 446 { 447 int status = 0; 448 449 status = orion_spi_setup_transfer(spi, t); 450 if (status < 0) 451 return status; 452 453 if (t->len) 454 orion_spi_write_read(spi, t); 455 456 return status; 457 } 458 459 static int orion_spi_setup(struct spi_device *spi) 460 { 461 return orion_spi_setup_transfer(spi, NULL); 462 } 463 464 static int orion_spi_reset(struct orion_spi *orion_spi) 465 { 466 /* Verify that the CS is deasserted */ 467 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 468 469 /* Don't deassert CS between the direct mapped SPI transfers */ 470 writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG)); 471 472 return 0; 473 } 474 475 static const struct orion_spi_dev orion_spi_dev_data = { 476 .typ = ORION_SPI, 477 .min_divisor = 4, 478 .max_divisor = 30, 479 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, 480 }; 481 482 static const struct orion_spi_dev armada_370_spi_dev_data = { 483 .typ = ARMADA_SPI, 484 .min_divisor = 4, 485 .max_divisor = 1920, 486 .max_hz = 50000000, 487 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 488 }; 489 490 static const struct orion_spi_dev armada_xp_spi_dev_data = { 491 .typ = ARMADA_SPI, 492 .max_hz = 50000000, 493 .max_divisor = 1920, 494 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 495 }; 496 497 static const struct orion_spi_dev armada_375_spi_dev_data = { 498 .typ = ARMADA_SPI, 499 .min_divisor = 15, 500 .max_divisor = 1920, 501 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 502 }; 503 504 static const struct orion_spi_dev armada_380_spi_dev_data = { 505 .typ = ARMADA_SPI, 506 .max_hz = 50000000, 507 .max_divisor = 1920, 508 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 509 .is_errata_50mhz_ac = true, 510 }; 511 512 static const struct of_device_id orion_spi_of_match_table[] = { 513 { 514 .compatible = "marvell,orion-spi", 515 .data = &orion_spi_dev_data, 516 }, 517 { 518 .compatible = "marvell,armada-370-spi", 519 .data = &armada_370_spi_dev_data, 520 }, 521 { 522 .compatible = "marvell,armada-375-spi", 523 .data = &armada_375_spi_dev_data, 524 }, 525 { 526 .compatible = "marvell,armada-380-spi", 527 .data = &armada_380_spi_dev_data, 528 }, 529 { 530 .compatible = "marvell,armada-390-spi", 531 .data = &armada_xp_spi_dev_data, 532 }, 533 { 534 .compatible = "marvell,armada-xp-spi", 535 .data = &armada_xp_spi_dev_data, 536 }, 537 538 {} 539 }; 540 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); 541 542 static int orion_spi_probe(struct platform_device *pdev) 543 { 544 const struct of_device_id *of_id; 545 const struct orion_spi_dev *devdata; 546 struct spi_master *master; 547 struct orion_spi *spi; 548 struct resource *r; 549 unsigned long tclk_hz; 550 int status = 0; 551 struct device_node *np; 552 553 master = spi_alloc_master(&pdev->dev, sizeof(*spi)); 554 if (master == NULL) { 555 dev_dbg(&pdev->dev, "master allocation failed\n"); 556 return -ENOMEM; 557 } 558 559 if (pdev->id != -1) 560 master->bus_num = pdev->id; 561 if (pdev->dev.of_node) { 562 u32 cell_index; 563 564 if (!of_property_read_u32(pdev->dev.of_node, "cell-index", 565 &cell_index)) 566 master->bus_num = cell_index; 567 } 568 569 /* we support only mode 0, and no options */ 570 master->mode_bits = SPI_CPHA | SPI_CPOL; 571 master->set_cs = orion_spi_set_cs; 572 master->transfer_one = orion_spi_transfer_one; 573 master->num_chipselect = ORION_NUM_CHIPSELECTS; 574 master->setup = orion_spi_setup; 575 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 576 master->auto_runtime_pm = true; 577 578 platform_set_drvdata(pdev, master); 579 580 spi = spi_master_get_devdata(master); 581 spi->master = master; 582 583 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); 584 devdata = (of_id) ? of_id->data : &orion_spi_dev_data; 585 spi->devdata = devdata; 586 587 spi->clk = devm_clk_get(&pdev->dev, NULL); 588 if (IS_ERR(spi->clk)) { 589 status = PTR_ERR(spi->clk); 590 goto out; 591 } 592 593 status = clk_prepare_enable(spi->clk); 594 if (status) 595 goto out; 596 597 tclk_hz = clk_get_rate(spi->clk); 598 599 /* 600 * With old device tree, armada-370-spi could be used with 601 * Armada XP, however for this SoC the maximum frequency is 602 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be 603 * higher than 200MHz. So, in order to be able to handle both 604 * SoCs, we can take the minimum of 50MHz and tclk/4. 605 */ 606 if (of_device_is_compatible(pdev->dev.of_node, 607 "marvell,armada-370-spi")) 608 master->max_speed_hz = min(devdata->max_hz, 609 DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); 610 else if (devdata->min_divisor) 611 master->max_speed_hz = 612 DIV_ROUND_UP(tclk_hz, devdata->min_divisor); 613 else 614 master->max_speed_hz = devdata->max_hz; 615 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); 616 617 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 618 spi->base = devm_ioremap_resource(&pdev->dev, r); 619 if (IS_ERR(spi->base)) { 620 status = PTR_ERR(spi->base); 621 goto out_rel_clk; 622 } 623 624 /* Scan all SPI devices of this controller for direct mapped devices */ 625 for_each_available_child_of_node(pdev->dev.of_node, np) { 626 u32 cs; 627 628 /* Get chip-select number from the "reg" property */ 629 status = of_property_read_u32(np, "reg", &cs); 630 if (status) { 631 dev_err(&pdev->dev, 632 "%s has no valid 'reg' property (%d)\n", 633 np->full_name, status); 634 status = 0; 635 continue; 636 } 637 638 /* 639 * Check if an address is configured for this SPI device. If 640 * not, the MBus mapping via the 'ranges' property in the 'soc' 641 * node is not configured and this device should not use the 642 * direct mode. In this case, just continue with the next 643 * device. 644 */ 645 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r); 646 if (status) 647 continue; 648 649 /* 650 * Only map one page for direct access. This is enough for the 651 * simple TX transfer which only writes to the first word. 652 * This needs to get extended for the direct SPI-NOR / SPI-NAND 653 * support, once this gets implemented. 654 */ 655 spi->direct_access[cs].vaddr = devm_ioremap(&pdev->dev, 656 r->start, 657 PAGE_SIZE); 658 if (!spi->direct_access[cs].vaddr) { 659 status = -ENOMEM; 660 goto out_rel_clk; 661 } 662 spi->direct_access[cs].size = PAGE_SIZE; 663 664 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs); 665 } 666 667 pm_runtime_set_active(&pdev->dev); 668 pm_runtime_use_autosuspend(&pdev->dev); 669 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 670 pm_runtime_enable(&pdev->dev); 671 672 status = orion_spi_reset(spi); 673 if (status < 0) 674 goto out_rel_pm; 675 676 pm_runtime_mark_last_busy(&pdev->dev); 677 pm_runtime_put_autosuspend(&pdev->dev); 678 679 master->dev.of_node = pdev->dev.of_node; 680 status = spi_register_master(master); 681 if (status < 0) 682 goto out_rel_pm; 683 684 return status; 685 686 out_rel_pm: 687 pm_runtime_disable(&pdev->dev); 688 out_rel_clk: 689 clk_disable_unprepare(spi->clk); 690 out: 691 spi_master_put(master); 692 return status; 693 } 694 695 696 static int orion_spi_remove(struct platform_device *pdev) 697 { 698 struct spi_master *master = platform_get_drvdata(pdev); 699 struct orion_spi *spi = spi_master_get_devdata(master); 700 701 pm_runtime_get_sync(&pdev->dev); 702 clk_disable_unprepare(spi->clk); 703 704 spi_unregister_master(master); 705 pm_runtime_disable(&pdev->dev); 706 707 return 0; 708 } 709 710 MODULE_ALIAS("platform:" DRIVER_NAME); 711 712 #ifdef CONFIG_PM 713 static int orion_spi_runtime_suspend(struct device *dev) 714 { 715 struct spi_master *master = dev_get_drvdata(dev); 716 struct orion_spi *spi = spi_master_get_devdata(master); 717 718 clk_disable_unprepare(spi->clk); 719 return 0; 720 } 721 722 static int orion_spi_runtime_resume(struct device *dev) 723 { 724 struct spi_master *master = dev_get_drvdata(dev); 725 struct orion_spi *spi = spi_master_get_devdata(master); 726 727 return clk_prepare_enable(spi->clk); 728 } 729 #endif 730 731 static const struct dev_pm_ops orion_spi_pm_ops = { 732 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, 733 orion_spi_runtime_resume, 734 NULL) 735 }; 736 737 static struct platform_driver orion_spi_driver = { 738 .driver = { 739 .name = DRIVER_NAME, 740 .pm = &orion_spi_pm_ops, 741 .of_match_table = of_match_ptr(orion_spi_of_match_table), 742 }, 743 .probe = orion_spi_probe, 744 .remove = orion_spi_remove, 745 }; 746 747 module_platform_driver(orion_spi_driver); 748 749 MODULE_DESCRIPTION("Orion SPI driver"); 750 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); 751 MODULE_LICENSE("GPL"); 752