1 /* 2 * Marvell Orion SPI controller driver 3 * 4 * Author: Shadi Ammouri <shadi@marvell.com> 5 * Copyright (C) 2007-2008 Marvell Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/platform_device.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/spi/spi.h> 18 #include <linux/module.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/clk.h> 24 #include <linux/sizes.h> 25 #include <linux/gpio.h> 26 #include <asm/unaligned.h> 27 28 #define DRIVER_NAME "orion_spi" 29 30 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */ 31 #define SPI_AUTOSUSPEND_TIMEOUT 200 32 33 /* Some SoCs using this driver support up to 8 chip selects. 34 * It is up to the implementer to only use the chip selects 35 * that are available. 36 */ 37 #define ORION_NUM_CHIPSELECTS 8 38 39 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */ 40 41 #define ORION_SPI_IF_CTRL_REG 0x00 42 #define ORION_SPI_IF_CONFIG_REG 0x04 43 #define ORION_SPI_IF_RXLSBF BIT(14) 44 #define ORION_SPI_IF_TXLSBF BIT(13) 45 #define ORION_SPI_DATA_OUT_REG 0x08 46 #define ORION_SPI_DATA_IN_REG 0x0c 47 #define ORION_SPI_INT_CAUSE_REG 0x10 48 #define ORION_SPI_TIMING_PARAMS_REG 0x18 49 50 /* Register for the "Direct Mode" */ 51 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20 52 53 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6) 54 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6) 55 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6) 56 57 #define ORION_SPI_MODE_CPOL (1 << 11) 58 #define ORION_SPI_MODE_CPHA (1 << 12) 59 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5) 60 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F 61 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF 62 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \ 63 ORION_SPI_MODE_CPHA) 64 #define ORION_SPI_CS_MASK 0x1C 65 #define ORION_SPI_CS_SHIFT 2 66 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \ 67 ORION_SPI_CS_MASK) 68 69 enum orion_spi_type { 70 ORION_SPI, 71 ARMADA_SPI, 72 }; 73 74 struct orion_spi_dev { 75 enum orion_spi_type typ; 76 /* 77 * min_divisor and max_hz should be exclusive, the only we can 78 * have both is for managing the armada-370-spi case with old 79 * device tree 80 */ 81 unsigned long max_hz; 82 unsigned int min_divisor; 83 unsigned int max_divisor; 84 u32 prescale_mask; 85 bool is_errata_50mhz_ac; 86 }; 87 88 struct orion_direct_acc { 89 void __iomem *vaddr; 90 u32 size; 91 }; 92 93 struct orion_spi { 94 struct spi_master *master; 95 void __iomem *base; 96 struct clk *clk; 97 struct clk *axi_clk; 98 const struct orion_spi_dev *devdata; 99 100 struct orion_direct_acc direct_access[ORION_NUM_CHIPSELECTS]; 101 }; 102 103 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg) 104 { 105 return orion_spi->base + reg; 106 } 107 108 static inline void 109 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 110 { 111 void __iomem *reg_addr = spi_reg(orion_spi, reg); 112 u32 val; 113 114 val = readl(reg_addr); 115 val |= mask; 116 writel(val, reg_addr); 117 } 118 119 static inline void 120 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) 121 { 122 void __iomem *reg_addr = spi_reg(orion_spi, reg); 123 u32 val; 124 125 val = readl(reg_addr); 126 val &= ~mask; 127 writel(val, reg_addr); 128 } 129 130 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) 131 { 132 u32 tclk_hz; 133 u32 rate; 134 u32 prescale; 135 u32 reg; 136 struct orion_spi *orion_spi; 137 const struct orion_spi_dev *devdata; 138 139 orion_spi = spi_master_get_devdata(spi->master); 140 devdata = orion_spi->devdata; 141 142 tclk_hz = clk_get_rate(orion_spi->clk); 143 144 if (devdata->typ == ARMADA_SPI) { 145 /* 146 * Given the core_clk (tclk_hz) and the target rate (speed) we 147 * determine the best values for SPR (in [0 .. 15]) and SPPR (in 148 * [0..7]) such that 149 * 150 * core_clk / (SPR * 2 ** SPPR) 151 * 152 * is as big as possible but not bigger than speed. 153 */ 154 155 /* best integer divider: */ 156 unsigned divider = DIV_ROUND_UP(tclk_hz, speed); 157 unsigned spr, sppr; 158 159 if (divider < 16) { 160 /* This is the easy case, divider is less than 16 */ 161 spr = divider; 162 sppr = 0; 163 164 } else { 165 unsigned two_pow_sppr; 166 /* 167 * Find the highest bit set in divider. This and the 168 * three next bits define SPR (apart from rounding). 169 * SPPR is then the number of zero bits that must be 170 * appended: 171 */ 172 sppr = fls(divider) - 4; 173 174 /* 175 * As SPR only has 4 bits, we have to round divider up 176 * to the next multiple of 2 ** sppr. 177 */ 178 two_pow_sppr = 1 << sppr; 179 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr; 180 181 /* 182 * recalculate sppr as rounding up divider might have 183 * increased it enough to change the position of the 184 * highest set bit. In this case the bit that now 185 * doesn't make it into SPR is 0, so there is no need to 186 * round again. 187 */ 188 sppr = fls(divider) - 4; 189 spr = divider >> sppr; 190 191 /* 192 * Now do range checking. SPR is constructed to have a 193 * width of 4 bits, so this is fine for sure. So we 194 * still need to check for sppr to fit into 3 bits: 195 */ 196 if (sppr > 7) 197 return -EINVAL; 198 } 199 200 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr; 201 } else { 202 /* 203 * the supported rates are: 4,6,8...30 204 * round up as we look for equal or less speed 205 */ 206 rate = DIV_ROUND_UP(tclk_hz, speed); 207 rate = roundup(rate, 2); 208 209 /* check if requested speed is too small */ 210 if (rate > 30) 211 return -EINVAL; 212 213 if (rate < 4) 214 rate = 4; 215 216 /* Convert the rate to SPI clock divisor value. */ 217 prescale = 0x10 + rate/2; 218 } 219 220 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 221 reg = ((reg & ~devdata->prescale_mask) | prescale); 222 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 223 224 return 0; 225 } 226 227 static void 228 orion_spi_mode_set(struct spi_device *spi) 229 { 230 u32 reg; 231 struct orion_spi *orion_spi; 232 233 orion_spi = spi_master_get_devdata(spi->master); 234 235 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 236 reg &= ~ORION_SPI_MODE_MASK; 237 if (spi->mode & SPI_CPOL) 238 reg |= ORION_SPI_MODE_CPOL; 239 if (spi->mode & SPI_CPHA) 240 reg |= ORION_SPI_MODE_CPHA; 241 if (spi->mode & SPI_LSB_FIRST) 242 reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF; 243 else 244 reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF); 245 246 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG)); 247 } 248 249 static void 250 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed) 251 { 252 u32 reg; 253 struct orion_spi *orion_spi; 254 255 orion_spi = spi_master_get_devdata(spi->master); 256 257 /* 258 * Erratum description: (Erratum NO. FE-9144572) The device 259 * SPI interface supports frequencies of up to 50 MHz. 260 * However, due to this erratum, when the device core clock is 261 * 250 MHz and the SPI interfaces is configured for 50MHz SPI 262 * clock and CPOL=CPHA=1 there might occur data corruption on 263 * reads from the SPI device. 264 * Erratum Workaround: 265 * Work in one of the following configurations: 266 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration 267 * Register". 268 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1 269 * Register" before setting the interface. 270 */ 271 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); 272 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK; 273 274 if (clk_get_rate(orion_spi->clk) == 250000000 && 275 speed == 50000000 && spi->mode & SPI_CPOL && 276 spi->mode & SPI_CPHA) 277 reg |= ORION_SPI_TMISO_SAMPLE_2; 278 else 279 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */ 280 281 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG)); 282 } 283 284 /* 285 * called only when no transfer is active on the bus 286 */ 287 static int 288 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) 289 { 290 struct orion_spi *orion_spi; 291 unsigned int speed = spi->max_speed_hz; 292 unsigned int bits_per_word = spi->bits_per_word; 293 int rc; 294 295 orion_spi = spi_master_get_devdata(spi->master); 296 297 if ((t != NULL) && t->speed_hz) 298 speed = t->speed_hz; 299 300 if ((t != NULL) && t->bits_per_word) 301 bits_per_word = t->bits_per_word; 302 303 orion_spi_mode_set(spi); 304 305 if (orion_spi->devdata->is_errata_50mhz_ac) 306 orion_spi_50mhz_ac_timing_erratum(spi, speed); 307 308 rc = orion_spi_baudrate_set(spi, speed); 309 if (rc) 310 return rc; 311 312 if (bits_per_word == 16) 313 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 314 ORION_SPI_IF_8_16_BIT_MODE); 315 else 316 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG, 317 ORION_SPI_IF_8_16_BIT_MODE); 318 319 return 0; 320 } 321 322 static void orion_spi_set_cs(struct spi_device *spi, bool enable) 323 { 324 struct orion_spi *orion_spi; 325 int cs; 326 327 if (gpio_is_valid(spi->cs_gpio)) 328 cs = 0; 329 else 330 cs = spi->chip_select; 331 332 orion_spi = spi_master_get_devdata(spi->master); 333 334 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK); 335 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 336 ORION_SPI_CS(cs)); 337 338 /* Chip select logic is inverted from spi_set_cs */ 339 if (!enable) 340 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 341 else 342 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 343 } 344 345 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi) 346 { 347 int i; 348 349 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) { 350 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG))) 351 return 1; 352 353 udelay(1); 354 } 355 356 return -1; 357 } 358 359 static inline int 360 orion_spi_write_read_8bit(struct spi_device *spi, 361 const u8 **tx_buf, u8 **rx_buf) 362 { 363 void __iomem *tx_reg, *rx_reg, *int_reg; 364 struct orion_spi *orion_spi; 365 366 orion_spi = spi_master_get_devdata(spi->master); 367 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 368 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 369 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 370 371 /* clear the interrupt cause register */ 372 writel(0x0, int_reg); 373 374 if (tx_buf && *tx_buf) 375 writel(*(*tx_buf)++, tx_reg); 376 else 377 writel(0, tx_reg); 378 379 if (orion_spi_wait_till_ready(orion_spi) < 0) { 380 dev_err(&spi->dev, "TXS timed out\n"); 381 return -1; 382 } 383 384 if (rx_buf && *rx_buf) 385 *(*rx_buf)++ = readl(rx_reg); 386 387 return 1; 388 } 389 390 static inline int 391 orion_spi_write_read_16bit(struct spi_device *spi, 392 const u16 **tx_buf, u16 **rx_buf) 393 { 394 void __iomem *tx_reg, *rx_reg, *int_reg; 395 struct orion_spi *orion_spi; 396 397 orion_spi = spi_master_get_devdata(spi->master); 398 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG); 399 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG); 400 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG); 401 402 /* clear the interrupt cause register */ 403 writel(0x0, int_reg); 404 405 if (tx_buf && *tx_buf) 406 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg); 407 else 408 writel(0, tx_reg); 409 410 if (orion_spi_wait_till_ready(orion_spi) < 0) { 411 dev_err(&spi->dev, "TXS timed out\n"); 412 return -1; 413 } 414 415 if (rx_buf && *rx_buf) 416 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++); 417 418 return 1; 419 } 420 421 static unsigned int 422 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer) 423 { 424 unsigned int count; 425 int word_len; 426 struct orion_spi *orion_spi; 427 int cs = spi->chip_select; 428 429 word_len = spi->bits_per_word; 430 count = xfer->len; 431 432 orion_spi = spi_master_get_devdata(spi->master); 433 434 /* 435 * Use SPI direct write mode if base address is available. Otherwise 436 * fall back to PIO mode for this transfer. 437 */ 438 if ((orion_spi->direct_access[cs].vaddr) && (xfer->tx_buf) && 439 (word_len == 8)) { 440 unsigned int cnt = count / 4; 441 unsigned int rem = count % 4; 442 443 /* 444 * Send the TX-data to the SPI device via the direct 445 * mapped address window 446 */ 447 iowrite32_rep(orion_spi->direct_access[cs].vaddr, 448 xfer->tx_buf, cnt); 449 if (rem) { 450 u32 *buf = (u32 *)xfer->tx_buf; 451 452 iowrite8_rep(orion_spi->direct_access[cs].vaddr, 453 &buf[cnt], rem); 454 } 455 456 return count; 457 } 458 459 if (word_len == 8) { 460 const u8 *tx = xfer->tx_buf; 461 u8 *rx = xfer->rx_buf; 462 463 do { 464 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0) 465 goto out; 466 count--; 467 } while (count); 468 } else if (word_len == 16) { 469 const u16 *tx = xfer->tx_buf; 470 u16 *rx = xfer->rx_buf; 471 472 do { 473 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0) 474 goto out; 475 count -= 2; 476 } while (count); 477 } 478 479 out: 480 return xfer->len - count; 481 } 482 483 static int orion_spi_transfer_one(struct spi_master *master, 484 struct spi_device *spi, 485 struct spi_transfer *t) 486 { 487 int status = 0; 488 489 status = orion_spi_setup_transfer(spi, t); 490 if (status < 0) 491 return status; 492 493 if (t->len) 494 orion_spi_write_read(spi, t); 495 496 return status; 497 } 498 499 static int orion_spi_setup(struct spi_device *spi) 500 { 501 return orion_spi_setup_transfer(spi, NULL); 502 } 503 504 static int orion_spi_reset(struct orion_spi *orion_spi) 505 { 506 /* Verify that the CS is deasserted */ 507 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1); 508 509 /* Don't deassert CS between the direct mapped SPI transfers */ 510 writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG)); 511 512 return 0; 513 } 514 515 static const struct orion_spi_dev orion_spi_dev_data = { 516 .typ = ORION_SPI, 517 .min_divisor = 4, 518 .max_divisor = 30, 519 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK, 520 }; 521 522 static const struct orion_spi_dev armada_370_spi_dev_data = { 523 .typ = ARMADA_SPI, 524 .min_divisor = 4, 525 .max_divisor = 1920, 526 .max_hz = 50000000, 527 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 528 }; 529 530 static const struct orion_spi_dev armada_xp_spi_dev_data = { 531 .typ = ARMADA_SPI, 532 .max_hz = 50000000, 533 .max_divisor = 1920, 534 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 535 }; 536 537 static const struct orion_spi_dev armada_375_spi_dev_data = { 538 .typ = ARMADA_SPI, 539 .min_divisor = 15, 540 .max_divisor = 1920, 541 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 542 }; 543 544 static const struct orion_spi_dev armada_380_spi_dev_data = { 545 .typ = ARMADA_SPI, 546 .max_hz = 50000000, 547 .max_divisor = 1920, 548 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK, 549 .is_errata_50mhz_ac = true, 550 }; 551 552 static const struct of_device_id orion_spi_of_match_table[] = { 553 { 554 .compatible = "marvell,orion-spi", 555 .data = &orion_spi_dev_data, 556 }, 557 { 558 .compatible = "marvell,armada-370-spi", 559 .data = &armada_370_spi_dev_data, 560 }, 561 { 562 .compatible = "marvell,armada-375-spi", 563 .data = &armada_375_spi_dev_data, 564 }, 565 { 566 .compatible = "marvell,armada-380-spi", 567 .data = &armada_380_spi_dev_data, 568 }, 569 { 570 .compatible = "marvell,armada-390-spi", 571 .data = &armada_xp_spi_dev_data, 572 }, 573 { 574 .compatible = "marvell,armada-xp-spi", 575 .data = &armada_xp_spi_dev_data, 576 }, 577 578 {} 579 }; 580 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table); 581 582 static int orion_spi_probe(struct platform_device *pdev) 583 { 584 const struct of_device_id *of_id; 585 const struct orion_spi_dev *devdata; 586 struct spi_master *master; 587 struct orion_spi *spi; 588 struct resource *r; 589 unsigned long tclk_hz; 590 int status = 0; 591 struct device_node *np; 592 593 master = spi_alloc_master(&pdev->dev, sizeof(*spi)); 594 if (master == NULL) { 595 dev_dbg(&pdev->dev, "master allocation failed\n"); 596 return -ENOMEM; 597 } 598 599 if (pdev->id != -1) 600 master->bus_num = pdev->id; 601 if (pdev->dev.of_node) { 602 u32 cell_index; 603 604 if (!of_property_read_u32(pdev->dev.of_node, "cell-index", 605 &cell_index)) 606 master->bus_num = cell_index; 607 } 608 609 /* we support all 4 SPI modes and LSB first option */ 610 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; 611 master->set_cs = orion_spi_set_cs; 612 master->transfer_one = orion_spi_transfer_one; 613 master->num_chipselect = ORION_NUM_CHIPSELECTS; 614 master->setup = orion_spi_setup; 615 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 616 master->auto_runtime_pm = true; 617 master->flags = SPI_MASTER_GPIO_SS; 618 619 platform_set_drvdata(pdev, master); 620 621 spi = spi_master_get_devdata(master); 622 spi->master = master; 623 624 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev); 625 devdata = (of_id) ? of_id->data : &orion_spi_dev_data; 626 spi->devdata = devdata; 627 628 spi->clk = devm_clk_get(&pdev->dev, NULL); 629 if (IS_ERR(spi->clk)) { 630 status = PTR_ERR(spi->clk); 631 goto out; 632 } 633 634 status = clk_prepare_enable(spi->clk); 635 if (status) 636 goto out; 637 638 /* The following clock is only used by some SoCs */ 639 spi->axi_clk = devm_clk_get(&pdev->dev, "axi"); 640 if (IS_ERR(spi->axi_clk) && 641 PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) { 642 status = -EPROBE_DEFER; 643 goto out_rel_clk; 644 } 645 if (!IS_ERR(spi->axi_clk)) 646 clk_prepare_enable(spi->axi_clk); 647 648 tclk_hz = clk_get_rate(spi->clk); 649 650 /* 651 * With old device tree, armada-370-spi could be used with 652 * Armada XP, however for this SoC the maximum frequency is 653 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be 654 * higher than 200MHz. So, in order to be able to handle both 655 * SoCs, we can take the minimum of 50MHz and tclk/4. 656 */ 657 if (of_device_is_compatible(pdev->dev.of_node, 658 "marvell,armada-370-spi")) 659 master->max_speed_hz = min(devdata->max_hz, 660 DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); 661 else if (devdata->min_divisor) 662 master->max_speed_hz = 663 DIV_ROUND_UP(tclk_hz, devdata->min_divisor); 664 else 665 master->max_speed_hz = devdata->max_hz; 666 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); 667 668 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 669 spi->base = devm_ioremap_resource(&pdev->dev, r); 670 if (IS_ERR(spi->base)) { 671 status = PTR_ERR(spi->base); 672 goto out_rel_axi_clk; 673 } 674 675 /* Scan all SPI devices of this controller for direct mapped devices */ 676 for_each_available_child_of_node(pdev->dev.of_node, np) { 677 u32 cs; 678 679 /* Get chip-select number from the "reg" property */ 680 status = of_property_read_u32(np, "reg", &cs); 681 if (status) { 682 dev_err(&pdev->dev, 683 "%pOF has no valid 'reg' property (%d)\n", 684 np, status); 685 continue; 686 } 687 688 /* 689 * Check if an address is configured for this SPI device. If 690 * not, the MBus mapping via the 'ranges' property in the 'soc' 691 * node is not configured and this device should not use the 692 * direct mode. In this case, just continue with the next 693 * device. 694 */ 695 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r); 696 if (status) 697 continue; 698 699 /* 700 * Only map one page for direct access. This is enough for the 701 * simple TX transfer which only writes to the first word. 702 * This needs to get extended for the direct SPI-NOR / SPI-NAND 703 * support, once this gets implemented. 704 */ 705 spi->direct_access[cs].vaddr = devm_ioremap(&pdev->dev, 706 r->start, 707 PAGE_SIZE); 708 if (!spi->direct_access[cs].vaddr) { 709 status = -ENOMEM; 710 goto out_rel_axi_clk; 711 } 712 spi->direct_access[cs].size = PAGE_SIZE; 713 714 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs); 715 } 716 717 pm_runtime_set_active(&pdev->dev); 718 pm_runtime_use_autosuspend(&pdev->dev); 719 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 720 pm_runtime_enable(&pdev->dev); 721 722 status = orion_spi_reset(spi); 723 if (status < 0) 724 goto out_rel_pm; 725 726 pm_runtime_mark_last_busy(&pdev->dev); 727 pm_runtime_put_autosuspend(&pdev->dev); 728 729 master->dev.of_node = pdev->dev.of_node; 730 status = spi_register_master(master); 731 if (status < 0) 732 goto out_rel_pm; 733 734 return status; 735 736 out_rel_pm: 737 pm_runtime_disable(&pdev->dev); 738 out_rel_axi_clk: 739 clk_disable_unprepare(spi->axi_clk); 740 out_rel_clk: 741 clk_disable_unprepare(spi->clk); 742 out: 743 spi_master_put(master); 744 return status; 745 } 746 747 748 static int orion_spi_remove(struct platform_device *pdev) 749 { 750 struct spi_master *master = platform_get_drvdata(pdev); 751 struct orion_spi *spi = spi_master_get_devdata(master); 752 753 pm_runtime_get_sync(&pdev->dev); 754 clk_disable_unprepare(spi->axi_clk); 755 clk_disable_unprepare(spi->clk); 756 757 spi_unregister_master(master); 758 pm_runtime_disable(&pdev->dev); 759 760 return 0; 761 } 762 763 MODULE_ALIAS("platform:" DRIVER_NAME); 764 765 #ifdef CONFIG_PM 766 static int orion_spi_runtime_suspend(struct device *dev) 767 { 768 struct spi_master *master = dev_get_drvdata(dev); 769 struct orion_spi *spi = spi_master_get_devdata(master); 770 771 clk_disable_unprepare(spi->axi_clk); 772 clk_disable_unprepare(spi->clk); 773 return 0; 774 } 775 776 static int orion_spi_runtime_resume(struct device *dev) 777 { 778 struct spi_master *master = dev_get_drvdata(dev); 779 struct orion_spi *spi = spi_master_get_devdata(master); 780 781 if (!IS_ERR(spi->axi_clk)) 782 clk_prepare_enable(spi->axi_clk); 783 return clk_prepare_enable(spi->clk); 784 } 785 #endif 786 787 static const struct dev_pm_ops orion_spi_pm_ops = { 788 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend, 789 orion_spi_runtime_resume, 790 NULL) 791 }; 792 793 static struct platform_driver orion_spi_driver = { 794 .driver = { 795 .name = DRIVER_NAME, 796 .pm = &orion_spi_pm_ops, 797 .of_match_table = of_match_ptr(orion_spi_of_match_table), 798 }, 799 .probe = orion_spi_probe, 800 .remove = orion_spi_remove, 801 }; 802 803 module_platform_driver(orion_spi_driver); 804 805 MODULE_DESCRIPTION("Orion SPI driver"); 806 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>"); 807 MODULE_LICENSE("GPL"); 808