1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * OMAP2 McSPI controller driver 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * Copyright (C) 2005, 2006 Nokia Corporation 5ca632f55SGrant Likely * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and 6ca632f55SGrant Likely * Juha Yrj�l� <juha.yrjola@nokia.com> 7ca632f55SGrant Likely * 8ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 9ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 10ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 11ca632f55SGrant Likely * (at your option) any later version. 12ca632f55SGrant Likely * 13ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 14ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 15ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16ca632f55SGrant Likely * GNU General Public License for more details. 17ca632f55SGrant Likely */ 18ca632f55SGrant Likely 19ca632f55SGrant Likely #include <linux/kernel.h> 20ca632f55SGrant Likely #include <linux/interrupt.h> 21ca632f55SGrant Likely #include <linux/module.h> 22ca632f55SGrant Likely #include <linux/device.h> 23ca632f55SGrant Likely #include <linux/delay.h> 24ca632f55SGrant Likely #include <linux/dma-mapping.h> 2553741ed8SRussell King #include <linux/dmaengine.h> 2653741ed8SRussell King #include <linux/omap-dma.h> 27beca3655SPascal Huerst #include <linux/pinctrl/consumer.h> 28ca632f55SGrant Likely #include <linux/platform_device.h> 29ca632f55SGrant Likely #include <linux/err.h> 30ca632f55SGrant Likely #include <linux/clk.h> 31ca632f55SGrant Likely #include <linux/io.h> 32ca632f55SGrant Likely #include <linux/slab.h> 33ca632f55SGrant Likely #include <linux/pm_runtime.h> 34d5a80031SBenoit Cousson #include <linux/of.h> 35d5a80031SBenoit Cousson #include <linux/of_device.h> 36d33f473dSIllia Smyrnov #include <linux/gcd.h> 37ca632f55SGrant Likely 38ca632f55SGrant Likely #include <linux/spi/spi.h> 39bc7f9bbcSMichael Welling #include <linux/gpio.h> 40ca632f55SGrant Likely 412203747cSArnd Bergmann #include <linux/platform_data/spi-omap2-mcspi.h> 42ca632f55SGrant Likely 43ca632f55SGrant Likely #define OMAP2_MCSPI_MAX_FREQ 48000000 44faee9b05SStefan Sørensen #define OMAP2_MCSPI_MAX_DIVIDER 4096 45d33f473dSIllia Smyrnov #define OMAP2_MCSPI_MAX_FIFODEPTH 64 46d33f473dSIllia Smyrnov #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF 4727b5284cSShubhrajyoti D #define SPI_AUTOSUSPEND_TIMEOUT 2000 48ca632f55SGrant Likely 49ca632f55SGrant Likely #define OMAP2_MCSPI_REVISION 0x00 50ca632f55SGrant Likely #define OMAP2_MCSPI_SYSSTATUS 0x14 51ca632f55SGrant Likely #define OMAP2_MCSPI_IRQSTATUS 0x18 52ca632f55SGrant Likely #define OMAP2_MCSPI_IRQENABLE 0x1c 53ca632f55SGrant Likely #define OMAP2_MCSPI_WAKEUPENABLE 0x20 54ca632f55SGrant Likely #define OMAP2_MCSPI_SYST 0x24 55ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL 0x28 56d33f473dSIllia Smyrnov #define OMAP2_MCSPI_XFERLEVEL 0x7c 57ca632f55SGrant Likely 58ca632f55SGrant Likely /* per-channel banks, 0x14 bytes each, first is: */ 59ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF0 0x2c 60ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT0 0x30 61ca632f55SGrant Likely #define OMAP2_MCSPI_CHCTRL0 0x34 62ca632f55SGrant Likely #define OMAP2_MCSPI_TX0 0x38 63ca632f55SGrant Likely #define OMAP2_MCSPI_RX0 0x3c 64ca632f55SGrant Likely 65ca632f55SGrant Likely /* per-register bitmasks: */ 66d33f473dSIllia Smyrnov #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) 67ca632f55SGrant Likely 68ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) 69ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) 70ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) 71ca632f55SGrant Likely 72ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_PHA BIT(0) 73ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_POL BIT(1) 74ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) 75ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) 76ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) 77ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) 78ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) 79ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) 80ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) 81ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) 82ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) 83ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) 84ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_IS BIT(18) 85ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) 86ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) 87d33f473dSIllia Smyrnov #define OMAP2_MCSPI_CHCONF_FFET BIT(27) 88d33f473dSIllia Smyrnov #define OMAP2_MCSPI_CHCONF_FFER BIT(28) 89faee9b05SStefan Sørensen #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) 90ca632f55SGrant Likely 91ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) 92ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) 93ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) 94d33f473dSIllia Smyrnov #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) 95ca632f55SGrant Likely 96ca632f55SGrant Likely #define OMAP2_MCSPI_CHCTRL_EN BIT(0) 97faee9b05SStefan Sørensen #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) 98ca632f55SGrant Likely 99ca632f55SGrant Likely #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) 100ca632f55SGrant Likely 101ca632f55SGrant Likely /* We have 2 DMA channels per CS, one for RX and one for TX */ 102ca632f55SGrant Likely struct omap2_mcspi_dma { 10353741ed8SRussell King struct dma_chan *dma_tx; 10453741ed8SRussell King struct dma_chan *dma_rx; 105ca632f55SGrant Likely 106ca632f55SGrant Likely int dma_tx_sync_dev; 107ca632f55SGrant Likely int dma_rx_sync_dev; 108ca632f55SGrant Likely 109ca632f55SGrant Likely struct completion dma_tx_completion; 110ca632f55SGrant Likely struct completion dma_rx_completion; 11174f3aaadSMatt Porter 11274f3aaadSMatt Porter char dma_rx_ch_name[14]; 11374f3aaadSMatt Porter char dma_tx_ch_name[14]; 114ca632f55SGrant Likely }; 115ca632f55SGrant Likely 116ca632f55SGrant Likely /* use PIO for small transfers, avoiding DMA setup/teardown overhead and 117ca632f55SGrant Likely * cache operations; better heuristics consider wordsize and bitrate. 118ca632f55SGrant Likely */ 119ca632f55SGrant Likely #define DMA_MIN_BYTES 160 120ca632f55SGrant Likely 121ca632f55SGrant Likely 1221bd897f8SBenoit Cousson /* 1231bd897f8SBenoit Cousson * Used for context save and restore, structure members to be updated whenever 1241bd897f8SBenoit Cousson * corresponding registers are modified. 1251bd897f8SBenoit Cousson */ 1261bd897f8SBenoit Cousson struct omap2_mcspi_regs { 1271bd897f8SBenoit Cousson u32 modulctrl; 1281bd897f8SBenoit Cousson u32 wakeupenable; 1291bd897f8SBenoit Cousson struct list_head cs; 1301bd897f8SBenoit Cousson }; 1311bd897f8SBenoit Cousson 132ca632f55SGrant Likely struct omap2_mcspi { 133ca632f55SGrant Likely struct spi_master *master; 134ca632f55SGrant Likely /* Virtual base address of the controller */ 135ca632f55SGrant Likely void __iomem *base; 136ca632f55SGrant Likely unsigned long phys; 137ca632f55SGrant Likely /* SPI1 has 4 channels, while SPI2 has 2 */ 138ca632f55SGrant Likely struct omap2_mcspi_dma *dma_channels; 139ca632f55SGrant Likely struct device *dev; 1401bd897f8SBenoit Cousson struct omap2_mcspi_regs ctx; 141d33f473dSIllia Smyrnov int fifo_depth; 1420384e90bSDaniel Mack unsigned int pin_dir:1; 143ca632f55SGrant Likely }; 144ca632f55SGrant Likely 145ca632f55SGrant Likely struct omap2_mcspi_cs { 146ca632f55SGrant Likely void __iomem *base; 147ca632f55SGrant Likely unsigned long phys; 148ca632f55SGrant Likely int word_len; 14997ca0d6cSMark A. Greer u16 mode; 150ca632f55SGrant Likely struct list_head node; 151ca632f55SGrant Likely /* Context save and restore shadow register */ 152faee9b05SStefan Sørensen u32 chconf0, chctrl0; 153ca632f55SGrant Likely }; 154ca632f55SGrant Likely 155ca632f55SGrant Likely static inline void mcspi_write_reg(struct spi_master *master, 156ca632f55SGrant Likely int idx, u32 val) 157ca632f55SGrant Likely { 158ca632f55SGrant Likely struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 159ca632f55SGrant Likely 16021b2ce5eSVictor Kamensky writel_relaxed(val, mcspi->base + idx); 161ca632f55SGrant Likely } 162ca632f55SGrant Likely 163ca632f55SGrant Likely static inline u32 mcspi_read_reg(struct spi_master *master, int idx) 164ca632f55SGrant Likely { 165ca632f55SGrant Likely struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 166ca632f55SGrant Likely 16721b2ce5eSVictor Kamensky return readl_relaxed(mcspi->base + idx); 168ca632f55SGrant Likely } 169ca632f55SGrant Likely 170ca632f55SGrant Likely static inline void mcspi_write_cs_reg(const struct spi_device *spi, 171ca632f55SGrant Likely int idx, u32 val) 172ca632f55SGrant Likely { 173ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 174ca632f55SGrant Likely 17521b2ce5eSVictor Kamensky writel_relaxed(val, cs->base + idx); 176ca632f55SGrant Likely } 177ca632f55SGrant Likely 178ca632f55SGrant Likely static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) 179ca632f55SGrant Likely { 180ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 181ca632f55SGrant Likely 18221b2ce5eSVictor Kamensky return readl_relaxed(cs->base + idx); 183ca632f55SGrant Likely } 184ca632f55SGrant Likely 185ca632f55SGrant Likely static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) 186ca632f55SGrant Likely { 187ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 188ca632f55SGrant Likely 189ca632f55SGrant Likely return cs->chconf0; 190ca632f55SGrant Likely } 191ca632f55SGrant Likely 192ca632f55SGrant Likely static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) 193ca632f55SGrant Likely { 194ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 195ca632f55SGrant Likely 196ca632f55SGrant Likely cs->chconf0 = val; 197ca632f55SGrant Likely mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); 198ca632f55SGrant Likely mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 199ca632f55SGrant Likely } 200ca632f55SGrant Likely 20156cd5c15SIllia Smyrnov static inline int mcspi_bytes_per_word(int word_len) 20256cd5c15SIllia Smyrnov { 20356cd5c15SIllia Smyrnov if (word_len <= 8) 20456cd5c15SIllia Smyrnov return 1; 20556cd5c15SIllia Smyrnov else if (word_len <= 16) 20656cd5c15SIllia Smyrnov return 2; 20756cd5c15SIllia Smyrnov else /* word_len <= 32 */ 20856cd5c15SIllia Smyrnov return 4; 20956cd5c15SIllia Smyrnov } 21056cd5c15SIllia Smyrnov 211ca632f55SGrant Likely static void omap2_mcspi_set_dma_req(const struct spi_device *spi, 212ca632f55SGrant Likely int is_read, int enable) 213ca632f55SGrant Likely { 214ca632f55SGrant Likely u32 l, rw; 215ca632f55SGrant Likely 216ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 217ca632f55SGrant Likely 218ca632f55SGrant Likely if (is_read) /* 1 is read, 0 write */ 219ca632f55SGrant Likely rw = OMAP2_MCSPI_CHCONF_DMAR; 220ca632f55SGrant Likely else 221ca632f55SGrant Likely rw = OMAP2_MCSPI_CHCONF_DMAW; 222ca632f55SGrant Likely 223af4e944dSShubhrajyoti D if (enable) 224af4e944dSShubhrajyoti D l |= rw; 225af4e944dSShubhrajyoti D else 226af4e944dSShubhrajyoti D l &= ~rw; 227af4e944dSShubhrajyoti D 228ca632f55SGrant Likely mcspi_write_chconf0(spi, l); 229ca632f55SGrant Likely } 230ca632f55SGrant Likely 231ca632f55SGrant Likely static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 232ca632f55SGrant Likely { 233faee9b05SStefan Sørensen struct omap2_mcspi_cs *cs = spi->controller_state; 234ca632f55SGrant Likely u32 l; 235ca632f55SGrant Likely 236faee9b05SStefan Sørensen l = cs->chctrl0; 237faee9b05SStefan Sørensen if (enable) 238faee9b05SStefan Sørensen l |= OMAP2_MCSPI_CHCTRL_EN; 239faee9b05SStefan Sørensen else 240faee9b05SStefan Sørensen l &= ~OMAP2_MCSPI_CHCTRL_EN; 241faee9b05SStefan Sørensen cs->chctrl0 = l; 242faee9b05SStefan Sørensen mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); 243ca632f55SGrant Likely /* Flash post-writes */ 244ca632f55SGrant Likely mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); 245ca632f55SGrant Likely } 246ca632f55SGrant Likely 247ddcad7e9SMichael Welling static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) 248ca632f55SGrant Likely { 2495f74db10SSebastian Reichel struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 250ca632f55SGrant Likely u32 l; 251ca632f55SGrant Likely 2524373f8b6SMichael Welling /* The controller handles the inverted chip selects 2534373f8b6SMichael Welling * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert 2544373f8b6SMichael Welling * the inversion from the core spi_set_cs function. 2554373f8b6SMichael Welling */ 2564373f8b6SMichael Welling if (spi->mode & SPI_CS_HIGH) 2574373f8b6SMichael Welling enable = !enable; 2584373f8b6SMichael Welling 259ddcad7e9SMichael Welling if (spi->controller_state) { 2605f74db10SSebastian Reichel int err = pm_runtime_get_sync(mcspi->dev); 2615f74db10SSebastian Reichel if (err < 0) { 2625f74db10SSebastian Reichel dev_err(mcspi->dev, "failed to get sync: %d\n", err); 2635f74db10SSebastian Reichel return; 2645f74db10SSebastian Reichel } 2655f74db10SSebastian Reichel 266ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 267ddcad7e9SMichael Welling 268ddcad7e9SMichael Welling if (enable) 269af4e944dSShubhrajyoti D l &= ~OMAP2_MCSPI_CHCONF_FORCE; 270ddcad7e9SMichael Welling else 271ddcad7e9SMichael Welling l |= OMAP2_MCSPI_CHCONF_FORCE; 272af4e944dSShubhrajyoti D 273ca632f55SGrant Likely mcspi_write_chconf0(spi, l); 2745f74db10SSebastian Reichel 2755f74db10SSebastian Reichel pm_runtime_mark_last_busy(mcspi->dev); 2765f74db10SSebastian Reichel pm_runtime_put_autosuspend(mcspi->dev); 277ca632f55SGrant Likely } 278ddcad7e9SMichael Welling } 279ca632f55SGrant Likely 280ca632f55SGrant Likely static void omap2_mcspi_set_master_mode(struct spi_master *master) 281ca632f55SGrant Likely { 2821bd897f8SBenoit Cousson struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 2831bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 284ca632f55SGrant Likely u32 l; 285ca632f55SGrant Likely 2861bd897f8SBenoit Cousson /* 2871bd897f8SBenoit Cousson * Setup when switching from (reset default) slave mode 288ca632f55SGrant Likely * to single-channel master mode 289ca632f55SGrant Likely */ 290ca632f55SGrant Likely l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); 291af4e944dSShubhrajyoti D l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); 292af4e944dSShubhrajyoti D l |= OMAP2_MCSPI_MODULCTRL_SINGLE; 293ca632f55SGrant Likely mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); 294ca632f55SGrant Likely 2951bd897f8SBenoit Cousson ctx->modulctrl = l; 296ca632f55SGrant Likely } 297ca632f55SGrant Likely 298d33f473dSIllia Smyrnov static void omap2_mcspi_set_fifo(const struct spi_device *spi, 299d33f473dSIllia Smyrnov struct spi_transfer *t, int enable) 300d33f473dSIllia Smyrnov { 301d33f473dSIllia Smyrnov struct spi_master *master = spi->master; 302d33f473dSIllia Smyrnov struct omap2_mcspi_cs *cs = spi->controller_state; 303d33f473dSIllia Smyrnov struct omap2_mcspi *mcspi; 304d33f473dSIllia Smyrnov unsigned int wcnt; 3055db542edSIllia Smyrnov int max_fifo_depth, fifo_depth, bytes_per_word; 306d33f473dSIllia Smyrnov u32 chconf, xferlevel; 307d33f473dSIllia Smyrnov 308d33f473dSIllia Smyrnov mcspi = spi_master_get_devdata(master); 309d33f473dSIllia Smyrnov 310d33f473dSIllia Smyrnov chconf = mcspi_cached_chconf0(spi); 311d33f473dSIllia Smyrnov if (enable) { 312d33f473dSIllia Smyrnov bytes_per_word = mcspi_bytes_per_word(cs->word_len); 313d33f473dSIllia Smyrnov if (t->len % bytes_per_word != 0) 314d33f473dSIllia Smyrnov goto disable_fifo; 315d33f473dSIllia Smyrnov 3165db542edSIllia Smyrnov if (t->rx_buf != NULL && t->tx_buf != NULL) 3175db542edSIllia Smyrnov max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; 3185db542edSIllia Smyrnov else 3195db542edSIllia Smyrnov max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; 3205db542edSIllia Smyrnov 3215db542edSIllia Smyrnov fifo_depth = gcd(t->len, max_fifo_depth); 322d33f473dSIllia Smyrnov if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) 323d33f473dSIllia Smyrnov goto disable_fifo; 324d33f473dSIllia Smyrnov 325d33f473dSIllia Smyrnov wcnt = t->len / bytes_per_word; 326d33f473dSIllia Smyrnov if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) 327d33f473dSIllia Smyrnov goto disable_fifo; 328d33f473dSIllia Smyrnov 329d33f473dSIllia Smyrnov xferlevel = wcnt << 16; 330d33f473dSIllia Smyrnov if (t->rx_buf != NULL) { 331d33f473dSIllia Smyrnov chconf |= OMAP2_MCSPI_CHCONF_FFER; 332d33f473dSIllia Smyrnov xferlevel |= (fifo_depth - 1) << 8; 3335db542edSIllia Smyrnov } 3345db542edSIllia Smyrnov if (t->tx_buf != NULL) { 335d33f473dSIllia Smyrnov chconf |= OMAP2_MCSPI_CHCONF_FFET; 336d33f473dSIllia Smyrnov xferlevel |= fifo_depth - 1; 337d33f473dSIllia Smyrnov } 338d33f473dSIllia Smyrnov 339d33f473dSIllia Smyrnov mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); 340d33f473dSIllia Smyrnov mcspi_write_chconf0(spi, chconf); 341d33f473dSIllia Smyrnov mcspi->fifo_depth = fifo_depth; 342d33f473dSIllia Smyrnov 343d33f473dSIllia Smyrnov return; 344d33f473dSIllia Smyrnov } 345d33f473dSIllia Smyrnov 346d33f473dSIllia Smyrnov disable_fifo: 347d33f473dSIllia Smyrnov if (t->rx_buf != NULL) 348d33f473dSIllia Smyrnov chconf &= ~OMAP2_MCSPI_CHCONF_FFER; 3493d0763c0SJorge A. Ventura 3503d0763c0SJorge A. Ventura if (t->tx_buf != NULL) 351d33f473dSIllia Smyrnov chconf &= ~OMAP2_MCSPI_CHCONF_FFET; 352d33f473dSIllia Smyrnov 353d33f473dSIllia Smyrnov mcspi_write_chconf0(spi, chconf); 354d33f473dSIllia Smyrnov mcspi->fifo_depth = 0; 355d33f473dSIllia Smyrnov } 356d33f473dSIllia Smyrnov 357ca632f55SGrant Likely static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) 358ca632f55SGrant Likely { 3591bd897f8SBenoit Cousson struct spi_master *spi_cntrl = mcspi->master; 3601bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 361ca632f55SGrant Likely struct omap2_mcspi_cs *cs; 362ca632f55SGrant Likely 363ca632f55SGrant Likely /* McSPI: context restore */ 3641bd897f8SBenoit Cousson mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); 3651bd897f8SBenoit Cousson mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); 366ca632f55SGrant Likely 3671bd897f8SBenoit Cousson list_for_each_entry(cs, &ctx->cs, node) 36821b2ce5eSVictor Kamensky writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 369ca632f55SGrant Likely } 370ca632f55SGrant Likely 371ca632f55SGrant Likely static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) 372ca632f55SGrant Likely { 373ca632f55SGrant Likely unsigned long timeout; 374ca632f55SGrant Likely 375ca632f55SGrant Likely timeout = jiffies + msecs_to_jiffies(1000); 37621b2ce5eSVictor Kamensky while (!(readl_relaxed(reg) & bit)) { 377ff23fa3bSSebastian Andrzej Siewior if (time_after(jiffies, timeout)) { 37821b2ce5eSVictor Kamensky if (!(readl_relaxed(reg) & bit)) 379ff23fa3bSSebastian Andrzej Siewior return -ETIMEDOUT; 380ff23fa3bSSebastian Andrzej Siewior else 381ff23fa3bSSebastian Andrzej Siewior return 0; 382ff23fa3bSSebastian Andrzej Siewior } 383ca632f55SGrant Likely cpu_relax(); 384ca632f55SGrant Likely } 385ca632f55SGrant Likely return 0; 386ca632f55SGrant Likely } 387ca632f55SGrant Likely 38853741ed8SRussell King static void omap2_mcspi_rx_callback(void *data) 38953741ed8SRussell King { 39053741ed8SRussell King struct spi_device *spi = data; 39153741ed8SRussell King struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 39253741ed8SRussell King struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 39353741ed8SRussell King 39453741ed8SRussell King /* We must disable the DMA RX request */ 39553741ed8SRussell King omap2_mcspi_set_dma_req(spi, 1, 0); 396830379e0SFelipe Balbi 397830379e0SFelipe Balbi complete(&mcspi_dma->dma_rx_completion); 39853741ed8SRussell King } 39953741ed8SRussell King 40053741ed8SRussell King static void omap2_mcspi_tx_callback(void *data) 40153741ed8SRussell King { 40253741ed8SRussell King struct spi_device *spi = data; 40353741ed8SRussell King struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 40453741ed8SRussell King struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 40553741ed8SRussell King 40653741ed8SRussell King /* We must disable the DMA TX request */ 40753741ed8SRussell King omap2_mcspi_set_dma_req(spi, 0, 0); 408830379e0SFelipe Balbi 409830379e0SFelipe Balbi complete(&mcspi_dma->dma_tx_completion); 41053741ed8SRussell King } 41153741ed8SRussell King 412d7b4394eSShubhrajyoti D static void omap2_mcspi_tx_dma(struct spi_device *spi, 413d7b4394eSShubhrajyoti D struct spi_transfer *xfer, 414d7b4394eSShubhrajyoti D struct dma_slave_config cfg) 415ca632f55SGrant Likely { 416ca632f55SGrant Likely struct omap2_mcspi *mcspi; 417ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 4188c7494a5SRussell King unsigned int count; 419ca632f55SGrant Likely 420ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 421ca632f55SGrant Likely mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 422d7b4394eSShubhrajyoti D count = xfer->len; 423ca632f55SGrant Likely 424d7b4394eSShubhrajyoti D if (mcspi_dma->dma_tx) { 42553741ed8SRussell King struct dma_async_tx_descriptor *tx; 42653741ed8SRussell King struct scatterlist sg; 42753741ed8SRussell King 42853741ed8SRussell King dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); 42953741ed8SRussell King 43053741ed8SRussell King sg_init_table(&sg, 1); 43153741ed8SRussell King sg_dma_address(&sg) = xfer->tx_dma; 43253741ed8SRussell King sg_dma_len(&sg) = xfer->len; 43353741ed8SRussell King 43453741ed8SRussell King tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, 43553741ed8SRussell King DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 43653741ed8SRussell King if (tx) { 43753741ed8SRussell King tx->callback = omap2_mcspi_tx_callback; 43853741ed8SRussell King tx->callback_param = spi; 43953741ed8SRussell King dmaengine_submit(tx); 44053741ed8SRussell King } else { 44153741ed8SRussell King /* FIXME: fall back to PIO? */ 44253741ed8SRussell King } 44353741ed8SRussell King } 44453741ed8SRussell King dma_async_issue_pending(mcspi_dma->dma_tx); 445ca632f55SGrant Likely omap2_mcspi_set_dma_req(spi, 0, 1); 446ca632f55SGrant Likely 447ca632f55SGrant Likely } 448ca632f55SGrant Likely 449d7b4394eSShubhrajyoti D static unsigned 450d7b4394eSShubhrajyoti D omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, 451d7b4394eSShubhrajyoti D struct dma_slave_config cfg, 452d7b4394eSShubhrajyoti D unsigned es) 453d7b4394eSShubhrajyoti D { 454d7b4394eSShubhrajyoti D struct omap2_mcspi *mcspi; 455d7b4394eSShubhrajyoti D struct omap2_mcspi_dma *mcspi_dma; 456d33f473dSIllia Smyrnov unsigned int count, dma_count; 457d7b4394eSShubhrajyoti D u32 l; 458d7b4394eSShubhrajyoti D int elements = 0; 459d7b4394eSShubhrajyoti D int word_len, element_count; 460d7b4394eSShubhrajyoti D struct omap2_mcspi_cs *cs = spi->controller_state; 461d7b4394eSShubhrajyoti D mcspi = spi_master_get_devdata(spi->master); 462d7b4394eSShubhrajyoti D mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 463d7b4394eSShubhrajyoti D count = xfer->len; 464d33f473dSIllia Smyrnov dma_count = xfer->len; 465d33f473dSIllia Smyrnov 466d33f473dSIllia Smyrnov if (mcspi->fifo_depth == 0) 467d33f473dSIllia Smyrnov dma_count -= es; 468d33f473dSIllia Smyrnov 469d7b4394eSShubhrajyoti D word_len = cs->word_len; 470d7b4394eSShubhrajyoti D l = mcspi_cached_chconf0(spi); 471d7b4394eSShubhrajyoti D 472d7b4394eSShubhrajyoti D if (word_len <= 8) 473d7b4394eSShubhrajyoti D element_count = count; 474d7b4394eSShubhrajyoti D else if (word_len <= 16) 475d7b4394eSShubhrajyoti D element_count = count >> 1; 476d7b4394eSShubhrajyoti D else /* word_len <= 32 */ 477d7b4394eSShubhrajyoti D element_count = count >> 2; 478d7b4394eSShubhrajyoti D 479d7b4394eSShubhrajyoti D if (mcspi_dma->dma_rx) { 480d7b4394eSShubhrajyoti D struct dma_async_tx_descriptor *tx; 481d7b4394eSShubhrajyoti D struct scatterlist sg; 482d7b4394eSShubhrajyoti D 483d7b4394eSShubhrajyoti D dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); 484d7b4394eSShubhrajyoti D 485d33f473dSIllia Smyrnov if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) 486d33f473dSIllia Smyrnov dma_count -= es; 487d7b4394eSShubhrajyoti D 488d7b4394eSShubhrajyoti D sg_init_table(&sg, 1); 489d7b4394eSShubhrajyoti D sg_dma_address(&sg) = xfer->rx_dma; 490d33f473dSIllia Smyrnov sg_dma_len(&sg) = dma_count; 491d7b4394eSShubhrajyoti D 492d7b4394eSShubhrajyoti D tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, 493d7b4394eSShubhrajyoti D DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | 494d7b4394eSShubhrajyoti D DMA_CTRL_ACK); 495d7b4394eSShubhrajyoti D if (tx) { 496d7b4394eSShubhrajyoti D tx->callback = omap2_mcspi_rx_callback; 497d7b4394eSShubhrajyoti D tx->callback_param = spi; 498d7b4394eSShubhrajyoti D dmaengine_submit(tx); 499d7b4394eSShubhrajyoti D } else { 500d7b4394eSShubhrajyoti D /* FIXME: fall back to PIO? */ 501d7b4394eSShubhrajyoti D } 502d7b4394eSShubhrajyoti D } 503d7b4394eSShubhrajyoti D 504d7b4394eSShubhrajyoti D dma_async_issue_pending(mcspi_dma->dma_rx); 505d7b4394eSShubhrajyoti D omap2_mcspi_set_dma_req(spi, 1, 1); 506d7b4394eSShubhrajyoti D 507ca632f55SGrant Likely wait_for_completion(&mcspi_dma->dma_rx_completion); 508a3ce9a80SShubhrajyoti D dma_unmap_single(mcspi->dev, xfer->rx_dma, count, 509a3ce9a80SShubhrajyoti D DMA_FROM_DEVICE); 510d33f473dSIllia Smyrnov 511d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0) 512d33f473dSIllia Smyrnov return count; 513d33f473dSIllia Smyrnov 514ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 515ca632f55SGrant Likely 51653741ed8SRussell King elements = element_count - 1; 51753741ed8SRussell King 518ca632f55SGrant Likely if (l & OMAP2_MCSPI_CHCONF_TURBO) { 51953741ed8SRussell King elements--; 520ca632f55SGrant Likely 521ca632f55SGrant Likely if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 522ca632f55SGrant Likely & OMAP2_MCSPI_CHSTAT_RXS)) { 523ca632f55SGrant Likely u32 w; 524ca632f55SGrant Likely 525ca632f55SGrant Likely w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 526ca632f55SGrant Likely if (word_len <= 8) 527ca632f55SGrant Likely ((u8 *)xfer->rx_buf)[elements++] = w; 528ca632f55SGrant Likely else if (word_len <= 16) 529ca632f55SGrant Likely ((u16 *)xfer->rx_buf)[elements++] = w; 530ca632f55SGrant Likely else /* word_len <= 32 */ 531ca632f55SGrant Likely ((u32 *)xfer->rx_buf)[elements++] = w; 532ca632f55SGrant Likely } else { 53356cd5c15SIllia Smyrnov int bytes_per_word = mcspi_bytes_per_word(word_len); 534a1829d2bSJarkko Nikula dev_err(&spi->dev, "DMA RX penultimate word empty\n"); 53556cd5c15SIllia Smyrnov count -= (bytes_per_word << 1); 536ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 1); 537ca632f55SGrant Likely return count; 538ca632f55SGrant Likely } 539ca632f55SGrant Likely } 540ca632f55SGrant Likely if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 541ca632f55SGrant Likely & OMAP2_MCSPI_CHSTAT_RXS)) { 542ca632f55SGrant Likely u32 w; 543ca632f55SGrant Likely 544ca632f55SGrant Likely w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 545ca632f55SGrant Likely if (word_len <= 8) 546ca632f55SGrant Likely ((u8 *)xfer->rx_buf)[elements] = w; 547ca632f55SGrant Likely else if (word_len <= 16) 548ca632f55SGrant Likely ((u16 *)xfer->rx_buf)[elements] = w; 549ca632f55SGrant Likely else /* word_len <= 32 */ 550ca632f55SGrant Likely ((u32 *)xfer->rx_buf)[elements] = w; 551ca632f55SGrant Likely } else { 552a1829d2bSJarkko Nikula dev_err(&spi->dev, "DMA RX last word empty\n"); 55356cd5c15SIllia Smyrnov count -= mcspi_bytes_per_word(word_len); 554ca632f55SGrant Likely } 555ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 1); 556d7b4394eSShubhrajyoti D return count; 557ca632f55SGrant Likely } 558d7b4394eSShubhrajyoti D 559d7b4394eSShubhrajyoti D static unsigned 560d7b4394eSShubhrajyoti D omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 561d7b4394eSShubhrajyoti D { 562d7b4394eSShubhrajyoti D struct omap2_mcspi *mcspi; 563d7b4394eSShubhrajyoti D struct omap2_mcspi_cs *cs = spi->controller_state; 564d7b4394eSShubhrajyoti D struct omap2_mcspi_dma *mcspi_dma; 565d7b4394eSShubhrajyoti D unsigned int count; 566d7b4394eSShubhrajyoti D u32 l; 567d7b4394eSShubhrajyoti D u8 *rx; 568d7b4394eSShubhrajyoti D const u8 *tx; 569d7b4394eSShubhrajyoti D struct dma_slave_config cfg; 570d7b4394eSShubhrajyoti D enum dma_slave_buswidth width; 571d7b4394eSShubhrajyoti D unsigned es; 572d33f473dSIllia Smyrnov u32 burst; 573e47a682aSShubhrajyoti D void __iomem *chstat_reg; 574d33f473dSIllia Smyrnov void __iomem *irqstat_reg; 575d33f473dSIllia Smyrnov int wait_res; 576d7b4394eSShubhrajyoti D 577d7b4394eSShubhrajyoti D mcspi = spi_master_get_devdata(spi->master); 578d7b4394eSShubhrajyoti D mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 579d7b4394eSShubhrajyoti D l = mcspi_cached_chconf0(spi); 580d7b4394eSShubhrajyoti D 581d7b4394eSShubhrajyoti D 582d7b4394eSShubhrajyoti D if (cs->word_len <= 8) { 583d7b4394eSShubhrajyoti D width = DMA_SLAVE_BUSWIDTH_1_BYTE; 584d7b4394eSShubhrajyoti D es = 1; 585d7b4394eSShubhrajyoti D } else if (cs->word_len <= 16) { 586d7b4394eSShubhrajyoti D width = DMA_SLAVE_BUSWIDTH_2_BYTES; 587d7b4394eSShubhrajyoti D es = 2; 588d7b4394eSShubhrajyoti D } else { 589d7b4394eSShubhrajyoti D width = DMA_SLAVE_BUSWIDTH_4_BYTES; 590d7b4394eSShubhrajyoti D es = 4; 591d7b4394eSShubhrajyoti D } 592d7b4394eSShubhrajyoti D 593d33f473dSIllia Smyrnov count = xfer->len; 594d33f473dSIllia Smyrnov burst = 1; 595d33f473dSIllia Smyrnov 596d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0) { 597d33f473dSIllia Smyrnov if (count > mcspi->fifo_depth) 598d33f473dSIllia Smyrnov burst = mcspi->fifo_depth / es; 599d33f473dSIllia Smyrnov else 600d33f473dSIllia Smyrnov burst = count / es; 601d33f473dSIllia Smyrnov } 602d33f473dSIllia Smyrnov 603d7b4394eSShubhrajyoti D memset(&cfg, 0, sizeof(cfg)); 604d7b4394eSShubhrajyoti D cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; 605d7b4394eSShubhrajyoti D cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; 606d7b4394eSShubhrajyoti D cfg.src_addr_width = width; 607d7b4394eSShubhrajyoti D cfg.dst_addr_width = width; 608d33f473dSIllia Smyrnov cfg.src_maxburst = burst; 609d33f473dSIllia Smyrnov cfg.dst_maxburst = burst; 610d7b4394eSShubhrajyoti D 611d7b4394eSShubhrajyoti D rx = xfer->rx_buf; 612d7b4394eSShubhrajyoti D tx = xfer->tx_buf; 613d7b4394eSShubhrajyoti D 614d7b4394eSShubhrajyoti D if (tx != NULL) 615d7b4394eSShubhrajyoti D omap2_mcspi_tx_dma(spi, xfer, cfg); 616d7b4394eSShubhrajyoti D 617d7b4394eSShubhrajyoti D if (rx != NULL) 618e47a682aSShubhrajyoti D count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); 619d7b4394eSShubhrajyoti D 620e47a682aSShubhrajyoti D if (tx != NULL) { 621e47a682aSShubhrajyoti D wait_for_completion(&mcspi_dma->dma_tx_completion); 622e47a682aSShubhrajyoti D dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, 623e47a682aSShubhrajyoti D DMA_TO_DEVICE); 624e47a682aSShubhrajyoti D 625d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0) { 626d33f473dSIllia Smyrnov irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; 627d33f473dSIllia Smyrnov 628d33f473dSIllia Smyrnov if (mcspi_wait_for_reg_bit(irqstat_reg, 629d33f473dSIllia Smyrnov OMAP2_MCSPI_IRQSTATUS_EOW) < 0) 630d33f473dSIllia Smyrnov dev_err(&spi->dev, "EOW timed out\n"); 631d33f473dSIllia Smyrnov 632d33f473dSIllia Smyrnov mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, 633d33f473dSIllia Smyrnov OMAP2_MCSPI_IRQSTATUS_EOW); 634d33f473dSIllia Smyrnov } 635d33f473dSIllia Smyrnov 636e47a682aSShubhrajyoti D /* for TX_ONLY mode, be sure all words have shifted out */ 637e47a682aSShubhrajyoti D if (rx == NULL) { 638d33f473dSIllia Smyrnov chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; 639d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0) { 640d33f473dSIllia Smyrnov wait_res = mcspi_wait_for_reg_bit(chstat_reg, 641d33f473dSIllia Smyrnov OMAP2_MCSPI_CHSTAT_TXFFE); 642d33f473dSIllia Smyrnov if (wait_res < 0) 643d33f473dSIllia Smyrnov dev_err(&spi->dev, "TXFFE timed out\n"); 644d33f473dSIllia Smyrnov } else { 645d33f473dSIllia Smyrnov wait_res = mcspi_wait_for_reg_bit(chstat_reg, 646d33f473dSIllia Smyrnov OMAP2_MCSPI_CHSTAT_TXS); 647d33f473dSIllia Smyrnov if (wait_res < 0) 648e47a682aSShubhrajyoti D dev_err(&spi->dev, "TXS timed out\n"); 649d33f473dSIllia Smyrnov } 650d33f473dSIllia Smyrnov if (wait_res >= 0 && 651d33f473dSIllia Smyrnov (mcspi_wait_for_reg_bit(chstat_reg, 652d33f473dSIllia Smyrnov OMAP2_MCSPI_CHSTAT_EOT) < 0)) 653e47a682aSShubhrajyoti D dev_err(&spi->dev, "EOT timed out\n"); 654e47a682aSShubhrajyoti D } 655e47a682aSShubhrajyoti D } 656ca632f55SGrant Likely return count; 657ca632f55SGrant Likely } 658ca632f55SGrant Likely 659ca632f55SGrant Likely static unsigned 660ca632f55SGrant Likely omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) 661ca632f55SGrant Likely { 662ca632f55SGrant Likely struct omap2_mcspi *mcspi; 663ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 664ca632f55SGrant Likely unsigned int count, c; 665ca632f55SGrant Likely u32 l; 666ca632f55SGrant Likely void __iomem *base = cs->base; 667ca632f55SGrant Likely void __iomem *tx_reg; 668ca632f55SGrant Likely void __iomem *rx_reg; 669ca632f55SGrant Likely void __iomem *chstat_reg; 670ca632f55SGrant Likely int word_len; 671ca632f55SGrant Likely 672ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 673ca632f55SGrant Likely count = xfer->len; 674ca632f55SGrant Likely c = count; 675ca632f55SGrant Likely word_len = cs->word_len; 676ca632f55SGrant Likely 677ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 678ca632f55SGrant Likely 679ca632f55SGrant Likely /* We store the pre-calculated register addresses on stack to speed 680ca632f55SGrant Likely * up the transfer loop. */ 681ca632f55SGrant Likely tx_reg = base + OMAP2_MCSPI_TX0; 682ca632f55SGrant Likely rx_reg = base + OMAP2_MCSPI_RX0; 683ca632f55SGrant Likely chstat_reg = base + OMAP2_MCSPI_CHSTAT0; 684ca632f55SGrant Likely 685ca632f55SGrant Likely if (c < (word_len>>3)) 686ca632f55SGrant Likely return 0; 687ca632f55SGrant Likely 688ca632f55SGrant Likely if (word_len <= 8) { 689ca632f55SGrant Likely u8 *rx; 690ca632f55SGrant Likely const u8 *tx; 691ca632f55SGrant Likely 692ca632f55SGrant Likely rx = xfer->rx_buf; 693ca632f55SGrant Likely tx = xfer->tx_buf; 694ca632f55SGrant Likely 695ca632f55SGrant Likely do { 696ca632f55SGrant Likely c -= 1; 697ca632f55SGrant Likely if (tx != NULL) { 698ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 699ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 700ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 701ca632f55SGrant Likely goto out; 702ca632f55SGrant Likely } 703ca632f55SGrant Likely dev_vdbg(&spi->dev, "write-%d %02x\n", 704ca632f55SGrant Likely word_len, *tx); 70521b2ce5eSVictor Kamensky writel_relaxed(*tx++, tx_reg); 706ca632f55SGrant Likely } 707ca632f55SGrant Likely if (rx != NULL) { 708ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 709ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 710ca632f55SGrant Likely dev_err(&spi->dev, "RXS timed out\n"); 711ca632f55SGrant Likely goto out; 712ca632f55SGrant Likely } 713ca632f55SGrant Likely 714ca632f55SGrant Likely if (c == 1 && tx == NULL && 715ca632f55SGrant Likely (l & OMAP2_MCSPI_CHCONF_TURBO)) { 716ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 71721b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 718ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %02x\n", 719ca632f55SGrant Likely word_len, *(rx - 1)); 720ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 721ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 722ca632f55SGrant Likely dev_err(&spi->dev, 723ca632f55SGrant Likely "RXS timed out\n"); 724ca632f55SGrant Likely goto out; 725ca632f55SGrant Likely } 726ca632f55SGrant Likely c = 0; 727ca632f55SGrant Likely } else if (c == 0 && tx == NULL) { 728ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 729ca632f55SGrant Likely } 730ca632f55SGrant Likely 73121b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 732ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %02x\n", 733ca632f55SGrant Likely word_len, *(rx - 1)); 734ca632f55SGrant Likely } 735ca632f55SGrant Likely } while (c); 736ca632f55SGrant Likely } else if (word_len <= 16) { 737ca632f55SGrant Likely u16 *rx; 738ca632f55SGrant Likely const u16 *tx; 739ca632f55SGrant Likely 740ca632f55SGrant Likely rx = xfer->rx_buf; 741ca632f55SGrant Likely tx = xfer->tx_buf; 742ca632f55SGrant Likely do { 743ca632f55SGrant Likely c -= 2; 744ca632f55SGrant Likely if (tx != NULL) { 745ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 746ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 747ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 748ca632f55SGrant Likely goto out; 749ca632f55SGrant Likely } 750ca632f55SGrant Likely dev_vdbg(&spi->dev, "write-%d %04x\n", 751ca632f55SGrant Likely word_len, *tx); 75221b2ce5eSVictor Kamensky writel_relaxed(*tx++, tx_reg); 753ca632f55SGrant Likely } 754ca632f55SGrant Likely if (rx != NULL) { 755ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 756ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 757ca632f55SGrant Likely dev_err(&spi->dev, "RXS timed out\n"); 758ca632f55SGrant Likely goto out; 759ca632f55SGrant Likely } 760ca632f55SGrant Likely 761ca632f55SGrant Likely if (c == 2 && tx == NULL && 762ca632f55SGrant Likely (l & OMAP2_MCSPI_CHCONF_TURBO)) { 763ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 76421b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 765ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %04x\n", 766ca632f55SGrant Likely word_len, *(rx - 1)); 767ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 768ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 769ca632f55SGrant Likely dev_err(&spi->dev, 770ca632f55SGrant Likely "RXS timed out\n"); 771ca632f55SGrant Likely goto out; 772ca632f55SGrant Likely } 773ca632f55SGrant Likely c = 0; 774ca632f55SGrant Likely } else if (c == 0 && tx == NULL) { 775ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 776ca632f55SGrant Likely } 777ca632f55SGrant Likely 77821b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 779ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %04x\n", 780ca632f55SGrant Likely word_len, *(rx - 1)); 781ca632f55SGrant Likely } 782ca632f55SGrant Likely } while (c >= 2); 783ca632f55SGrant Likely } else if (word_len <= 32) { 784ca632f55SGrant Likely u32 *rx; 785ca632f55SGrant Likely const u32 *tx; 786ca632f55SGrant Likely 787ca632f55SGrant Likely rx = xfer->rx_buf; 788ca632f55SGrant Likely tx = xfer->tx_buf; 789ca632f55SGrant Likely do { 790ca632f55SGrant Likely c -= 4; 791ca632f55SGrant Likely if (tx != NULL) { 792ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 793ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 794ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 795ca632f55SGrant Likely goto out; 796ca632f55SGrant Likely } 797ca632f55SGrant Likely dev_vdbg(&spi->dev, "write-%d %08x\n", 798ca632f55SGrant Likely word_len, *tx); 79921b2ce5eSVictor Kamensky writel_relaxed(*tx++, tx_reg); 800ca632f55SGrant Likely } 801ca632f55SGrant Likely if (rx != NULL) { 802ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 803ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 804ca632f55SGrant Likely dev_err(&spi->dev, "RXS timed out\n"); 805ca632f55SGrant Likely goto out; 806ca632f55SGrant Likely } 807ca632f55SGrant Likely 808ca632f55SGrant Likely if (c == 4 && tx == NULL && 809ca632f55SGrant Likely (l & OMAP2_MCSPI_CHCONF_TURBO)) { 810ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 81121b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 812ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %08x\n", 813ca632f55SGrant Likely word_len, *(rx - 1)); 814ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 815ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 816ca632f55SGrant Likely dev_err(&spi->dev, 817ca632f55SGrant Likely "RXS timed out\n"); 818ca632f55SGrant Likely goto out; 819ca632f55SGrant Likely } 820ca632f55SGrant Likely c = 0; 821ca632f55SGrant Likely } else if (c == 0 && tx == NULL) { 822ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 823ca632f55SGrant Likely } 824ca632f55SGrant Likely 82521b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 826ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %08x\n", 827ca632f55SGrant Likely word_len, *(rx - 1)); 828ca632f55SGrant Likely } 829ca632f55SGrant Likely } while (c >= 4); 830ca632f55SGrant Likely } 831ca632f55SGrant Likely 832ca632f55SGrant Likely /* for TX_ONLY mode, be sure all words have shifted out */ 833ca632f55SGrant Likely if (xfer->rx_buf == NULL) { 834ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 835ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 836ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 837ca632f55SGrant Likely } else if (mcspi_wait_for_reg_bit(chstat_reg, 838ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_EOT) < 0) 839ca632f55SGrant Likely dev_err(&spi->dev, "EOT timed out\n"); 840ca632f55SGrant Likely 841ca632f55SGrant Likely /* disable chan to purge rx datas received in TX_ONLY transfer, 842ca632f55SGrant Likely * otherwise these rx datas will affect the direct following 843ca632f55SGrant Likely * RX_ONLY transfer. 844ca632f55SGrant Likely */ 845ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 846ca632f55SGrant Likely } 847ca632f55SGrant Likely out: 848ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 1); 849ca632f55SGrant Likely return count - c; 850ca632f55SGrant Likely } 851ca632f55SGrant Likely 852ca632f55SGrant Likely static u32 omap2_mcspi_calc_divisor(u32 speed_hz) 853ca632f55SGrant Likely { 854ca632f55SGrant Likely u32 div; 855ca632f55SGrant Likely 856ca632f55SGrant Likely for (div = 0; div < 15; div++) 857ca632f55SGrant Likely if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) 858ca632f55SGrant Likely return div; 859ca632f55SGrant Likely 860ca632f55SGrant Likely return 15; 861ca632f55SGrant Likely } 862ca632f55SGrant Likely 863ca632f55SGrant Likely /* called only when no transfer is active to this device */ 864ca632f55SGrant Likely static int omap2_mcspi_setup_transfer(struct spi_device *spi, 865ca632f55SGrant Likely struct spi_transfer *t) 866ca632f55SGrant Likely { 867ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 868ca632f55SGrant Likely struct omap2_mcspi *mcspi; 869ca632f55SGrant Likely struct spi_master *spi_cntrl; 870faee9b05SStefan Sørensen u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; 871ca632f55SGrant Likely u8 word_len = spi->bits_per_word; 872ca632f55SGrant Likely u32 speed_hz = spi->max_speed_hz; 873ca632f55SGrant Likely 874ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 875ca632f55SGrant Likely spi_cntrl = mcspi->master; 876ca632f55SGrant Likely 877ca632f55SGrant Likely if (t != NULL && t->bits_per_word) 878ca632f55SGrant Likely word_len = t->bits_per_word; 879ca632f55SGrant Likely 880ca632f55SGrant Likely cs->word_len = word_len; 881ca632f55SGrant Likely 882ca632f55SGrant Likely if (t && t->speed_hz) 883ca632f55SGrant Likely speed_hz = t->speed_hz; 884ca632f55SGrant Likely 885ca632f55SGrant Likely speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); 886faee9b05SStefan Sørensen if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { 887faee9b05SStefan Sørensen clkd = omap2_mcspi_calc_divisor(speed_hz); 888faee9b05SStefan Sørensen speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; 889faee9b05SStefan Sørensen clkg = 0; 890faee9b05SStefan Sørensen } else { 891faee9b05SStefan Sørensen div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; 892faee9b05SStefan Sørensen speed_hz = OMAP2_MCSPI_MAX_FREQ / div; 893faee9b05SStefan Sørensen clkd = (div - 1) & 0xf; 894faee9b05SStefan Sørensen extclk = (div - 1) >> 4; 895faee9b05SStefan Sørensen clkg = OMAP2_MCSPI_CHCONF_CLKG; 896faee9b05SStefan Sørensen } 897ca632f55SGrant Likely 898ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 899ca632f55SGrant Likely 900ca632f55SGrant Likely /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 901ca632f55SGrant Likely * REVISIT: this controller could support SPI_3WIRE mode. 902ca632f55SGrant Likely */ 9032cd45179SDaniel Mack if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { 9040384e90bSDaniel Mack l &= ~OMAP2_MCSPI_CHCONF_IS; 9050384e90bSDaniel Mack l &= ~OMAP2_MCSPI_CHCONF_DPE1; 906ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_DPE0; 9070384e90bSDaniel Mack } else { 9080384e90bSDaniel Mack l |= OMAP2_MCSPI_CHCONF_IS; 9090384e90bSDaniel Mack l |= OMAP2_MCSPI_CHCONF_DPE1; 9100384e90bSDaniel Mack l &= ~OMAP2_MCSPI_CHCONF_DPE0; 9110384e90bSDaniel Mack } 912ca632f55SGrant Likely 913ca632f55SGrant Likely /* wordlength */ 914ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; 915ca632f55SGrant Likely l |= (word_len - 1) << 7; 916ca632f55SGrant Likely 917ca632f55SGrant Likely /* set chipselect polarity; manage with FORCE */ 918ca632f55SGrant Likely if (!(spi->mode & SPI_CS_HIGH)) 919ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ 920ca632f55SGrant Likely else 921ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_EPOL; 922ca632f55SGrant Likely 923ca632f55SGrant Likely /* set clock divisor */ 924ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; 925faee9b05SStefan Sørensen l |= clkd << 2; 926faee9b05SStefan Sørensen 927faee9b05SStefan Sørensen /* set clock granularity */ 928faee9b05SStefan Sørensen l &= ~OMAP2_MCSPI_CHCONF_CLKG; 929faee9b05SStefan Sørensen l |= clkg; 930faee9b05SStefan Sørensen if (clkg) { 931faee9b05SStefan Sørensen cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; 932faee9b05SStefan Sørensen cs->chctrl0 |= extclk << 8; 933faee9b05SStefan Sørensen mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); 934faee9b05SStefan Sørensen } 935ca632f55SGrant Likely 936ca632f55SGrant Likely /* set SPI mode 0..3 */ 937ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 938ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_POL; 939ca632f55SGrant Likely else 940ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_POL; 941ca632f55SGrant Likely if (spi->mode & SPI_CPHA) 942ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_PHA; 943ca632f55SGrant Likely else 944ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_PHA; 945ca632f55SGrant Likely 946ca632f55SGrant Likely mcspi_write_chconf0(spi, l); 947ca632f55SGrant Likely 94897ca0d6cSMark A. Greer cs->mode = spi->mode; 94997ca0d6cSMark A. Greer 950ca632f55SGrant Likely dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 951faee9b05SStefan Sørensen speed_hz, 952ca632f55SGrant Likely (spi->mode & SPI_CPHA) ? "trailing" : "leading", 953ca632f55SGrant Likely (spi->mode & SPI_CPOL) ? "inverted" : "normal"); 954ca632f55SGrant Likely 955ca632f55SGrant Likely return 0; 956ca632f55SGrant Likely } 957ca632f55SGrant Likely 958ddc5cdf1STony Lindgren /* 959ddc5cdf1STony Lindgren * Note that we currently allow DMA only if we get a channel 960ddc5cdf1STony Lindgren * for both rx and tx. Otherwise we'll do PIO for both rx and tx. 961ddc5cdf1STony Lindgren */ 962ca632f55SGrant Likely static int omap2_mcspi_request_dma(struct spi_device *spi) 963ca632f55SGrant Likely { 964ca632f55SGrant Likely struct spi_master *master = spi->master; 965ca632f55SGrant Likely struct omap2_mcspi *mcspi; 966ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 96753741ed8SRussell King dma_cap_mask_t mask; 96853741ed8SRussell King unsigned sig; 969ca632f55SGrant Likely 970ca632f55SGrant Likely mcspi = spi_master_get_devdata(master); 971ca632f55SGrant Likely mcspi_dma = mcspi->dma_channels + spi->chip_select; 972ca632f55SGrant Likely 973ca632f55SGrant Likely init_completion(&mcspi_dma->dma_rx_completion); 974ca632f55SGrant Likely init_completion(&mcspi_dma->dma_tx_completion); 975ca632f55SGrant Likely 97653741ed8SRussell King dma_cap_zero(mask); 97753741ed8SRussell King dma_cap_set(DMA_SLAVE, mask); 97853741ed8SRussell King sig = mcspi_dma->dma_rx_sync_dev; 97974f3aaadSMatt Porter 98074f3aaadSMatt Porter mcspi_dma->dma_rx = 98174f3aaadSMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 98274f3aaadSMatt Porter &sig, &master->dev, 98374f3aaadSMatt Porter mcspi_dma->dma_rx_ch_name); 984ddc5cdf1STony Lindgren if (!mcspi_dma->dma_rx) 985ddc5cdf1STony Lindgren goto no_dma; 986ca632f55SGrant Likely 98753741ed8SRussell King sig = mcspi_dma->dma_tx_sync_dev; 98874f3aaadSMatt Porter mcspi_dma->dma_tx = 98974f3aaadSMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 99074f3aaadSMatt Porter &sig, &master->dev, 99174f3aaadSMatt Porter mcspi_dma->dma_tx_ch_name); 99274f3aaadSMatt Porter 99353741ed8SRussell King if (!mcspi_dma->dma_tx) { 99453741ed8SRussell King dma_release_channel(mcspi_dma->dma_rx); 99553741ed8SRussell King mcspi_dma->dma_rx = NULL; 996ddc5cdf1STony Lindgren goto no_dma; 99753741ed8SRussell King } 998ca632f55SGrant Likely 999ca632f55SGrant Likely return 0; 1000ddc5cdf1STony Lindgren 1001ddc5cdf1STony Lindgren no_dma: 1002ddc5cdf1STony Lindgren dev_warn(&spi->dev, "not using DMA for McSPI\n"); 1003ddc5cdf1STony Lindgren return -EAGAIN; 1004ca632f55SGrant Likely } 1005ca632f55SGrant Likely 1006ca632f55SGrant Likely static int omap2_mcspi_setup(struct spi_device *spi) 1007ca632f55SGrant Likely { 1008ca632f55SGrant Likely int ret; 10091bd897f8SBenoit Cousson struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 10101bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1011ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 1012ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 1013ca632f55SGrant Likely 1014ca632f55SGrant Likely mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1015ca632f55SGrant Likely 1016ca632f55SGrant Likely if (!cs) { 101710aa5a35SRussell King cs = kzalloc(sizeof *cs, GFP_KERNEL); 1018ca632f55SGrant Likely if (!cs) 1019ca632f55SGrant Likely return -ENOMEM; 1020ca632f55SGrant Likely cs->base = mcspi->base + spi->chip_select * 0x14; 1021ca632f55SGrant Likely cs->phys = mcspi->phys + spi->chip_select * 0x14; 102297ca0d6cSMark A. Greer cs->mode = 0; 1023ca632f55SGrant Likely cs->chconf0 = 0; 1024faee9b05SStefan Sørensen cs->chctrl0 = 0; 1025ca632f55SGrant Likely spi->controller_state = cs; 1026ca632f55SGrant Likely /* Link this to context save list */ 10271bd897f8SBenoit Cousson list_add_tail(&cs->node, &ctx->cs); 1028ca632f55SGrant Likely 1029bc7f9bbcSMichael Welling if (gpio_is_valid(spi->cs_gpio)) { 1030c4339ac7SMichael Welling ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); 1031c4339ac7SMichael Welling if (ret) { 1032c4339ac7SMichael Welling dev_err(&spi->dev, "failed to request gpio\n"); 1033c4339ac7SMichael Welling return ret; 1034c4339ac7SMichael Welling } 1035*2f538c01SMichael Welling gpio_direction_output(spi->cs_gpio, 1036*2f538c01SMichael Welling !(spi->mode & SPI_CS_HIGH)); 1037*2f538c01SMichael Welling } 1038*2f538c01SMichael Welling } 1039*2f538c01SMichael Welling 1040*2f538c01SMichael Welling if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { 1041*2f538c01SMichael Welling ret = omap2_mcspi_request_dma(spi); 1042*2f538c01SMichael Welling if (ret < 0 && ret != -EAGAIN) 1043*2f538c01SMichael Welling return ret; 1044bc7f9bbcSMichael Welling } 1045bc7f9bbcSMichael Welling 1046034d3dc9SShubhrajyoti D ret = pm_runtime_get_sync(mcspi->dev); 1047ca632f55SGrant Likely if (ret < 0) 1048ca632f55SGrant Likely return ret; 1049ca632f55SGrant Likely 1050ca632f55SGrant Likely ret = omap2_mcspi_setup_transfer(spi, NULL); 1051034d3dc9SShubhrajyoti D pm_runtime_mark_last_busy(mcspi->dev); 1052034d3dc9SShubhrajyoti D pm_runtime_put_autosuspend(mcspi->dev); 1053ca632f55SGrant Likely 1054ca632f55SGrant Likely return ret; 1055ca632f55SGrant Likely } 1056ca632f55SGrant Likely 1057ca632f55SGrant Likely static void omap2_mcspi_cleanup(struct spi_device *spi) 1058ca632f55SGrant Likely { 1059ca632f55SGrant Likely struct omap2_mcspi *mcspi; 1060ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 1061ca632f55SGrant Likely struct omap2_mcspi_cs *cs; 1062ca632f55SGrant Likely 1063ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 1064ca632f55SGrant Likely 1065ca632f55SGrant Likely if (spi->controller_state) { 1066ca632f55SGrant Likely /* Unlink controller state from context save list */ 1067ca632f55SGrant Likely cs = spi->controller_state; 1068ca632f55SGrant Likely list_del(&cs->node); 1069ca632f55SGrant Likely 107010aa5a35SRussell King kfree(cs); 1071ca632f55SGrant Likely } 1072ca632f55SGrant Likely 1073ca632f55SGrant Likely if (spi->chip_select < spi->master->num_chipselect) { 1074ca632f55SGrant Likely mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1075ca632f55SGrant Likely 107653741ed8SRussell King if (mcspi_dma->dma_rx) { 107753741ed8SRussell King dma_release_channel(mcspi_dma->dma_rx); 107853741ed8SRussell King mcspi_dma->dma_rx = NULL; 1079ca632f55SGrant Likely } 108053741ed8SRussell King if (mcspi_dma->dma_tx) { 108153741ed8SRussell King dma_release_channel(mcspi_dma->dma_tx); 108253741ed8SRussell King mcspi_dma->dma_tx = NULL; 1083ca632f55SGrant Likely } 1084ca632f55SGrant Likely } 1085bc7f9bbcSMichael Welling 1086bc7f9bbcSMichael Welling if (gpio_is_valid(spi->cs_gpio)) 1087bc7f9bbcSMichael Welling gpio_free(spi->cs_gpio); 1088ca632f55SGrant Likely } 1089ca632f55SGrant Likely 1090b28cb941SMichael Welling static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi, 1091b28cb941SMichael Welling struct spi_device *spi, struct spi_transfer *t) 1092ca632f55SGrant Likely { 1093ca632f55SGrant Likely 1094ca632f55SGrant Likely /* We only enable one channel at a time -- the one whose message is 10955fda88f5SShubhrajyoti D * -- although this controller would gladly 1096ca632f55SGrant Likely * arbitrate among multiple channels. This corresponds to "single 1097ca632f55SGrant Likely * channel" master mode. As a side effect, we need to manage the 1098ca632f55SGrant Likely * chipselect with the FORCE bit ... CS != channel enable. 1099ca632f55SGrant Likely */ 11005fda88f5SShubhrajyoti D 11015cbc7ca9SMatthias Brugger struct spi_master *master; 1102ddc5cdf1STony Lindgren struct omap2_mcspi_dma *mcspi_dma; 1103ca632f55SGrant Likely struct omap2_mcspi_cs *cs; 1104ca632f55SGrant Likely struct omap2_mcspi_device_config *cd; 1105ca632f55SGrant Likely int par_override = 0; 1106ca632f55SGrant Likely int status = 0; 1107ca632f55SGrant Likely u32 chconf; 1108ca632f55SGrant Likely 11095cbc7ca9SMatthias Brugger master = spi->master; 1110ddc5cdf1STony Lindgren mcspi_dma = mcspi->dma_channels + spi->chip_select; 1111ca632f55SGrant Likely cs = spi->controller_state; 1112ca632f55SGrant Likely cd = spi->controller_data; 1113ca632f55SGrant Likely 111497ca0d6cSMark A. Greer /* 111597ca0d6cSMark A. Greer * The slave driver could have changed spi->mode in which case 111697ca0d6cSMark A. Greer * it will be different from cs->mode (the current hardware setup). 111797ca0d6cSMark A. Greer * If so, set par_override (even though its not a parity issue) so 111897ca0d6cSMark A. Greer * omap2_mcspi_setup_transfer will be called to configure the hardware 111997ca0d6cSMark A. Greer * with the correct mode on the first iteration of the loop below. 112097ca0d6cSMark A. Greer */ 112197ca0d6cSMark A. Greer if (spi->mode != cs->mode) 112297ca0d6cSMark A. Greer par_override = 1; 112397ca0d6cSMark A. Greer 1124d33f473dSIllia Smyrnov omap2_mcspi_set_enable(spi, 0); 1125b28cb941SMichael Welling 1126a06b430fSMichael Welling if (gpio_is_valid(spi->cs_gpio)) 1127a06b430fSMichael Welling omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); 1128a06b430fSMichael Welling 11292bd16e3eSStefan Sørensen if (par_override || 11302bd16e3eSStefan Sørensen (t->speed_hz != spi->max_speed_hz) || 11312bd16e3eSStefan Sørensen (t->bits_per_word != spi->bits_per_word)) { 1132ca632f55SGrant Likely par_override = 1; 1133ca632f55SGrant Likely status = omap2_mcspi_setup_transfer(spi, t); 1134ca632f55SGrant Likely if (status < 0) 1135b28cb941SMichael Welling goto out; 11362bd16e3eSStefan Sørensen if (t->speed_hz == spi->max_speed_hz && 11372bd16e3eSStefan Sørensen t->bits_per_word == spi->bits_per_word) 1138ca632f55SGrant Likely par_override = 0; 1139ca632f55SGrant Likely } 11405cbc7ca9SMatthias Brugger if (cd && cd->cs_per_word) { 11415cbc7ca9SMatthias Brugger chconf = mcspi->ctx.modulctrl; 11425cbc7ca9SMatthias Brugger chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; 11435cbc7ca9SMatthias Brugger mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 11445cbc7ca9SMatthias Brugger mcspi->ctx.modulctrl = 11455cbc7ca9SMatthias Brugger mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 11465cbc7ca9SMatthias Brugger } 11475cbc7ca9SMatthias Brugger 1148ca632f55SGrant Likely chconf = mcspi_cached_chconf0(spi); 1149ca632f55SGrant Likely chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; 1150ca632f55SGrant Likely chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; 1151ca632f55SGrant Likely 1152ca632f55SGrant Likely if (t->tx_buf == NULL) 1153ca632f55SGrant Likely chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; 1154ca632f55SGrant Likely else if (t->rx_buf == NULL) 1155ca632f55SGrant Likely chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; 1156ca632f55SGrant Likely 1157ca632f55SGrant Likely if (cd && cd->turbo_mode && t->tx_buf == NULL) { 1158ca632f55SGrant Likely /* Turbo mode is for more than one word */ 1159ca632f55SGrant Likely if (t->len > ((cs->word_len + 7) >> 3)) 1160ca632f55SGrant Likely chconf |= OMAP2_MCSPI_CHCONF_TURBO; 1161ca632f55SGrant Likely } 1162ca632f55SGrant Likely 1163ca632f55SGrant Likely mcspi_write_chconf0(spi, chconf); 1164ca632f55SGrant Likely 1165ca632f55SGrant Likely if (t->len) { 1166ca632f55SGrant Likely unsigned count; 1167ca632f55SGrant Likely 1168d33f473dSIllia Smyrnov if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1169b28cb941SMichael Welling (t->len >= DMA_MIN_BYTES)) 1170d33f473dSIllia Smyrnov omap2_mcspi_set_fifo(spi, t, 1); 1171d33f473dSIllia Smyrnov 1172d33f473dSIllia Smyrnov omap2_mcspi_set_enable(spi, 1); 1173d33f473dSIllia Smyrnov 1174ca632f55SGrant Likely /* RX_ONLY mode needs dummy data in TX reg */ 1175ca632f55SGrant Likely if (t->tx_buf == NULL) 117621b2ce5eSVictor Kamensky writel_relaxed(0, cs->base 1177ca632f55SGrant Likely + OMAP2_MCSPI_TX0); 1178ca632f55SGrant Likely 1179ddc5cdf1STony Lindgren if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 1180b28cb941SMichael Welling (t->len >= DMA_MIN_BYTES)) 1181ca632f55SGrant Likely count = omap2_mcspi_txrx_dma(spi, t); 1182ca632f55SGrant Likely else 1183ca632f55SGrant Likely count = omap2_mcspi_txrx_pio(spi, t); 1184ca632f55SGrant Likely 1185ca632f55SGrant Likely if (count != t->len) { 1186ca632f55SGrant Likely status = -EIO; 1187b28cb941SMichael Welling goto out; 1188ca632f55SGrant Likely } 1189ca632f55SGrant Likely } 1190ca632f55SGrant Likely 1191d33f473dSIllia Smyrnov omap2_mcspi_set_enable(spi, 0); 1192d33f473dSIllia Smyrnov 1193d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0) 1194d33f473dSIllia Smyrnov omap2_mcspi_set_fifo(spi, t, 0); 1195b28cb941SMichael Welling 1196b28cb941SMichael Welling out: 1197ca632f55SGrant Likely /* Restore defaults if they were overriden */ 1198ca632f55SGrant Likely if (par_override) { 1199ca632f55SGrant Likely par_override = 0; 1200ca632f55SGrant Likely status = omap2_mcspi_setup_transfer(spi, NULL); 1201ca632f55SGrant Likely } 1202ca632f55SGrant Likely 12035cbc7ca9SMatthias Brugger if (cd && cd->cs_per_word) { 12045cbc7ca9SMatthias Brugger chconf = mcspi->ctx.modulctrl; 12055cbc7ca9SMatthias Brugger chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; 12065cbc7ca9SMatthias Brugger mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 12075cbc7ca9SMatthias Brugger mcspi->ctx.modulctrl = 12085cbc7ca9SMatthias Brugger mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 12095cbc7ca9SMatthias Brugger } 12105cbc7ca9SMatthias Brugger 1211ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 1212ca632f55SGrant Likely 1213a06b430fSMichael Welling if (gpio_is_valid(spi->cs_gpio)) 1214a06b430fSMichael Welling omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); 1215a06b430fSMichael Welling 1216d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0 && t) 1217d33f473dSIllia Smyrnov omap2_mcspi_set_fifo(spi, t, 0); 1218ca632f55SGrant Likely 1219b28cb941SMichael Welling return status; 1220ca632f55SGrant Likely } 1221ca632f55SGrant Likely 1222468a3208SNeil Armstrong static int omap2_mcspi_prepare_message(struct spi_master *master, 1223468a3208SNeil Armstrong struct spi_message *msg) 1224468a3208SNeil Armstrong { 1225468a3208SNeil Armstrong struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1226468a3208SNeil Armstrong struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1227468a3208SNeil Armstrong struct omap2_mcspi_cs *cs; 1228468a3208SNeil Armstrong 1229468a3208SNeil Armstrong /* Only a single channel can have the FORCE bit enabled 1230468a3208SNeil Armstrong * in its chconf0 register. 1231468a3208SNeil Armstrong * Scan all channels and disable them except the current one. 1232468a3208SNeil Armstrong * A FORCE can remain from a last transfer having cs_change enabled 1233468a3208SNeil Armstrong */ 1234468a3208SNeil Armstrong list_for_each_entry(cs, &ctx->cs, node) { 1235468a3208SNeil Armstrong if (msg->spi->controller_state == cs) 1236468a3208SNeil Armstrong continue; 1237468a3208SNeil Armstrong 1238468a3208SNeil Armstrong if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { 1239468a3208SNeil Armstrong cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 1240468a3208SNeil Armstrong writel_relaxed(cs->chconf0, 1241468a3208SNeil Armstrong cs->base + OMAP2_MCSPI_CHCONF0); 1242468a3208SNeil Armstrong readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); 1243468a3208SNeil Armstrong } 1244468a3208SNeil Armstrong } 1245468a3208SNeil Armstrong 1246468a3208SNeil Armstrong return 0; 1247468a3208SNeil Armstrong } 1248468a3208SNeil Armstrong 1249b28cb941SMichael Welling static int omap2_mcspi_transfer_one(struct spi_master *master, 1250b28cb941SMichael Welling struct spi_device *spi, struct spi_transfer *t) 1251ca632f55SGrant Likely { 1252ca632f55SGrant Likely struct omap2_mcspi *mcspi; 1253ddc5cdf1STony Lindgren struct omap2_mcspi_dma *mcspi_dma; 1254ca632f55SGrant Likely const void *tx_buf = t->tx_buf; 1255ca632f55SGrant Likely void *rx_buf = t->rx_buf; 1256ca632f55SGrant Likely unsigned len = t->len; 1257ca632f55SGrant Likely 1258b28cb941SMichael Welling mcspi = spi_master_get_devdata(master); 1259b28cb941SMichael Welling mcspi_dma = mcspi->dma_channels + spi->chip_select; 1260b28cb941SMichael Welling 1261aca0924bSAxel Lin if ((len && !(rx_buf || tx_buf))) { 12625fda88f5SShubhrajyoti D dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", 1263ca632f55SGrant Likely t->speed_hz, 1264ca632f55SGrant Likely len, 1265ca632f55SGrant Likely tx_buf ? "tx" : "", 1266ca632f55SGrant Likely rx_buf ? "rx" : "", 1267ca632f55SGrant Likely t->bits_per_word); 1268b28cb941SMichael Welling return -EINVAL; 1269ca632f55SGrant Likely } 1270ca632f55SGrant Likely 1271b28cb941SMichael Welling if (len < DMA_MIN_BYTES) 1272b28cb941SMichael Welling goto skip_dma_map; 1273ca632f55SGrant Likely 1274ddc5cdf1STony Lindgren if (mcspi_dma->dma_tx && tx_buf != NULL) { 12755fda88f5SShubhrajyoti D t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, 1276ca632f55SGrant Likely len, DMA_TO_DEVICE); 12775fda88f5SShubhrajyoti D if (dma_mapping_error(mcspi->dev, t->tx_dma)) { 12785fda88f5SShubhrajyoti D dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 1279ca632f55SGrant Likely 'T', len); 1280b28cb941SMichael Welling return -EINVAL; 1281ca632f55SGrant Likely } 1282ca632f55SGrant Likely } 1283ddc5cdf1STony Lindgren if (mcspi_dma->dma_rx && rx_buf != NULL) { 12845fda88f5SShubhrajyoti D t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, 1285ca632f55SGrant Likely DMA_FROM_DEVICE); 12865fda88f5SShubhrajyoti D if (dma_mapping_error(mcspi->dev, t->rx_dma)) { 12875fda88f5SShubhrajyoti D dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 1288ca632f55SGrant Likely 'R', len); 1289ca632f55SGrant Likely if (tx_buf != NULL) 12905fda88f5SShubhrajyoti D dma_unmap_single(mcspi->dev, t->tx_dma, 1291ca632f55SGrant Likely len, DMA_TO_DEVICE); 1292b28cb941SMichael Welling return -EINVAL; 1293ca632f55SGrant Likely } 1294ca632f55SGrant Likely } 1295ca632f55SGrant Likely 1296b28cb941SMichael Welling skip_dma_map: 1297b28cb941SMichael Welling return omap2_mcspi_work_one(mcspi, spi, t); 1298ca632f55SGrant Likely } 1299ca632f55SGrant Likely 1300fd4a319bSGrant Likely static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) 1301ca632f55SGrant Likely { 1302ca632f55SGrant Likely struct spi_master *master = mcspi->master; 13031bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1304ca632f55SGrant Likely int ret = 0; 1305ca632f55SGrant Likely 1306034d3dc9SShubhrajyoti D ret = pm_runtime_get_sync(mcspi->dev); 1307ca632f55SGrant Likely if (ret < 0) 1308ca632f55SGrant Likely return ret; 1309ca632f55SGrant Likely 131039f8052dSShubhrajyoti D mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, 131139f8052dSShubhrajyoti D OMAP2_MCSPI_WAKEUPENABLE_WKEN); 131239f8052dSShubhrajyoti D ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; 1313ca632f55SGrant Likely 1314ca632f55SGrant Likely omap2_mcspi_set_master_mode(master); 1315034d3dc9SShubhrajyoti D pm_runtime_mark_last_busy(mcspi->dev); 1316034d3dc9SShubhrajyoti D pm_runtime_put_autosuspend(mcspi->dev); 1317ca632f55SGrant Likely return 0; 1318ca632f55SGrant Likely } 1319ca632f55SGrant Likely 1320ca632f55SGrant Likely static int omap_mcspi_runtime_resume(struct device *dev) 1321ca632f55SGrant Likely { 1322ca632f55SGrant Likely struct omap2_mcspi *mcspi; 1323ca632f55SGrant Likely struct spi_master *master; 1324ca632f55SGrant Likely 1325ca632f55SGrant Likely master = dev_get_drvdata(dev); 1326ca632f55SGrant Likely mcspi = spi_master_get_devdata(master); 1327ca632f55SGrant Likely omap2_mcspi_restore_ctx(mcspi); 1328ca632f55SGrant Likely 1329ca632f55SGrant Likely return 0; 1330ca632f55SGrant Likely } 1331ca632f55SGrant Likely 1332d5a80031SBenoit Cousson static struct omap2_mcspi_platform_config omap2_pdata = { 1333d5a80031SBenoit Cousson .regs_offset = 0, 1334d5a80031SBenoit Cousson }; 1335d5a80031SBenoit Cousson 1336d5a80031SBenoit Cousson static struct omap2_mcspi_platform_config omap4_pdata = { 1337d5a80031SBenoit Cousson .regs_offset = OMAP4_MCSPI_REG_OFFSET, 1338d5a80031SBenoit Cousson }; 1339d5a80031SBenoit Cousson 1340d5a80031SBenoit Cousson static const struct of_device_id omap_mcspi_of_match[] = { 1341d5a80031SBenoit Cousson { 1342d5a80031SBenoit Cousson .compatible = "ti,omap2-mcspi", 1343d5a80031SBenoit Cousson .data = &omap2_pdata, 1344d5a80031SBenoit Cousson }, 1345d5a80031SBenoit Cousson { 1346d5a80031SBenoit Cousson .compatible = "ti,omap4-mcspi", 1347d5a80031SBenoit Cousson .data = &omap4_pdata, 1348d5a80031SBenoit Cousson }, 1349d5a80031SBenoit Cousson { }, 1350d5a80031SBenoit Cousson }; 1351d5a80031SBenoit Cousson MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); 1352ca632f55SGrant Likely 1353fd4a319bSGrant Likely static int omap2_mcspi_probe(struct platform_device *pdev) 1354ca632f55SGrant Likely { 1355ca632f55SGrant Likely struct spi_master *master; 135683a01e72SUwe Kleine-König const struct omap2_mcspi_platform_config *pdata; 1357ca632f55SGrant Likely struct omap2_mcspi *mcspi; 1358ca632f55SGrant Likely struct resource *r; 1359ca632f55SGrant Likely int status = 0, i; 1360d5a80031SBenoit Cousson u32 regs_offset = 0; 1361d5a80031SBenoit Cousson static int bus_num = 1; 1362d5a80031SBenoit Cousson struct device_node *node = pdev->dev.of_node; 1363d5a80031SBenoit Cousson const struct of_device_id *match; 1364ca632f55SGrant Likely 1365ca632f55SGrant Likely master = spi_alloc_master(&pdev->dev, sizeof *mcspi); 1366ca632f55SGrant Likely if (master == NULL) { 1367ca632f55SGrant Likely dev_dbg(&pdev->dev, "master allocation failed\n"); 1368ca632f55SGrant Likely return -ENOMEM; 1369ca632f55SGrant Likely } 1370ca632f55SGrant Likely 1371ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 1372ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 137324778be2SStephen Warren master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1374ca632f55SGrant Likely master->setup = omap2_mcspi_setup; 1375f0278a1aSMark Brown master->auto_runtime_pm = true; 1376468a3208SNeil Armstrong master->prepare_message = omap2_mcspi_prepare_message; 1377b28cb941SMichael Welling master->transfer_one = omap2_mcspi_transfer_one; 1378ddcad7e9SMichael Welling master->set_cs = omap2_mcspi_set_cs; 1379ca632f55SGrant Likely master->cleanup = omap2_mcspi_cleanup; 1380d5a80031SBenoit Cousson master->dev.of_node = node; 1381aca0924bSAxel Lin master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; 1382aca0924bSAxel Lin master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; 1383d5a80031SBenoit Cousson 138424b5a82cSJingoo Han platform_set_drvdata(pdev, master); 13850384e90bSDaniel Mack 13860384e90bSDaniel Mack mcspi = spi_master_get_devdata(master); 13870384e90bSDaniel Mack mcspi->master = master; 13880384e90bSDaniel Mack 1389d5a80031SBenoit Cousson match = of_match_device(omap_mcspi_of_match, &pdev->dev); 1390d5a80031SBenoit Cousson if (match) { 1391d5a80031SBenoit Cousson u32 num_cs = 1; /* default number of chipselect */ 1392d5a80031SBenoit Cousson pdata = match->data; 1393d5a80031SBenoit Cousson 1394d5a80031SBenoit Cousson of_property_read_u32(node, "ti,spi-num-cs", &num_cs); 1395d5a80031SBenoit Cousson master->num_chipselect = num_cs; 1396d5a80031SBenoit Cousson master->bus_num = bus_num++; 13972cd45179SDaniel Mack if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) 13982cd45179SDaniel Mack mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; 1399d5a80031SBenoit Cousson } else { 14008074cf06SJingoo Han pdata = dev_get_platdata(&pdev->dev); 1401ca632f55SGrant Likely master->num_chipselect = pdata->num_cs; 1402d5a80031SBenoit Cousson if (pdev->id != -1) 1403d5a80031SBenoit Cousson master->bus_num = pdev->id; 14040384e90bSDaniel Mack mcspi->pin_dir = pdata->pin_dir; 1405d5a80031SBenoit Cousson } 1406d5a80031SBenoit Cousson regs_offset = pdata->regs_offset; 1407ca632f55SGrant Likely 1408ca632f55SGrant Likely r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1409ca632f55SGrant Likely if (r == NULL) { 1410ca632f55SGrant Likely status = -ENODEV; 141139f1b565SShubhrajyoti D goto free_master; 1412ca632f55SGrant Likely } 14131458d160SShubhrajyoti D 1414d5a80031SBenoit Cousson r->start += regs_offset; 1415d5a80031SBenoit Cousson r->end += regs_offset; 14161458d160SShubhrajyoti D mcspi->phys = r->start; 1417ca632f55SGrant Likely 1418b0ee5605SThierry Reding mcspi->base = devm_ioremap_resource(&pdev->dev, r); 1419b0ee5605SThierry Reding if (IS_ERR(mcspi->base)) { 1420b0ee5605SThierry Reding status = PTR_ERR(mcspi->base); 14211a77b127SShubhrajyoti D goto free_master; 1422ca632f55SGrant Likely } 1423ca632f55SGrant Likely 1424ca632f55SGrant Likely mcspi->dev = &pdev->dev; 1425ca632f55SGrant Likely 14261bd897f8SBenoit Cousson INIT_LIST_HEAD(&mcspi->ctx.cs); 1427ca632f55SGrant Likely 1428a6f936dbSAxel Lin mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, 1429ca632f55SGrant Likely sizeof(struct omap2_mcspi_dma), 1430ca632f55SGrant Likely GFP_KERNEL); 1431a6f936dbSAxel Lin if (mcspi->dma_channels == NULL) { 1432a6f936dbSAxel Lin status = -ENOMEM; 14331a77b127SShubhrajyoti D goto free_master; 1434a6f936dbSAxel Lin } 1435ca632f55SGrant Likely 1436ca632f55SGrant Likely for (i = 0; i < master->num_chipselect; i++) { 143774f3aaadSMatt Porter char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; 143874f3aaadSMatt Porter char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; 1439ca632f55SGrant Likely struct resource *dma_res; 1440ca632f55SGrant Likely 144174f3aaadSMatt Porter sprintf(dma_rx_ch_name, "rx%d", i); 144274f3aaadSMatt Porter if (!pdev->dev.of_node) { 144374f3aaadSMatt Porter dma_res = 144474f3aaadSMatt Porter platform_get_resource_byname(pdev, 144574f3aaadSMatt Porter IORESOURCE_DMA, 144674f3aaadSMatt Porter dma_rx_ch_name); 1447ca632f55SGrant Likely if (!dma_res) { 144874f3aaadSMatt Porter dev_dbg(&pdev->dev, 144974f3aaadSMatt Porter "cannot get DMA RX channel\n"); 1450ca632f55SGrant Likely status = -ENODEV; 1451ca632f55SGrant Likely break; 1452ca632f55SGrant Likely } 1453ca632f55SGrant Likely 145474f3aaadSMatt Porter mcspi->dma_channels[i].dma_rx_sync_dev = 145574f3aaadSMatt Porter dma_res->start; 145674f3aaadSMatt Porter } 145774f3aaadSMatt Porter sprintf(dma_tx_ch_name, "tx%d", i); 145874f3aaadSMatt Porter if (!pdev->dev.of_node) { 145974f3aaadSMatt Porter dma_res = 146074f3aaadSMatt Porter platform_get_resource_byname(pdev, 146174f3aaadSMatt Porter IORESOURCE_DMA, 146274f3aaadSMatt Porter dma_tx_ch_name); 1463ca632f55SGrant Likely if (!dma_res) { 146474f3aaadSMatt Porter dev_dbg(&pdev->dev, 146574f3aaadSMatt Porter "cannot get DMA TX channel\n"); 1466ca632f55SGrant Likely status = -ENODEV; 1467ca632f55SGrant Likely break; 1468ca632f55SGrant Likely } 1469ca632f55SGrant Likely 147074f3aaadSMatt Porter mcspi->dma_channels[i].dma_tx_sync_dev = 147174f3aaadSMatt Porter dma_res->start; 147274f3aaadSMatt Porter } 1473ca632f55SGrant Likely } 1474ca632f55SGrant Likely 147539f1b565SShubhrajyoti D if (status < 0) 1476a6f936dbSAxel Lin goto free_master; 147739f1b565SShubhrajyoti D 147827b5284cSShubhrajyoti D pm_runtime_use_autosuspend(&pdev->dev); 147927b5284cSShubhrajyoti D pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1480ca632f55SGrant Likely pm_runtime_enable(&pdev->dev); 1481ca632f55SGrant Likely 1482142e07beSWei Yongjun status = omap2_mcspi_master_setup(mcspi); 1483142e07beSWei Yongjun if (status < 0) 148439f1b565SShubhrajyoti D goto disable_pm; 1485ca632f55SGrant Likely 1486b95e02b7SJingoo Han status = devm_spi_register_master(&pdev->dev, master); 1487ca632f55SGrant Likely if (status < 0) 148837a2d84aSShubhrajyoti D goto disable_pm; 1489ca632f55SGrant Likely 1490ca632f55SGrant Likely return status; 1491ca632f55SGrant Likely 149239f1b565SShubhrajyoti D disable_pm: 1493751c925cSShubhrajyoti D pm_runtime_disable(&pdev->dev); 149439f1b565SShubhrajyoti D free_master: 149537a2d84aSShubhrajyoti D spi_master_put(master); 1496ca632f55SGrant Likely return status; 1497ca632f55SGrant Likely } 1498ca632f55SGrant Likely 1499fd4a319bSGrant Likely static int omap2_mcspi_remove(struct platform_device *pdev) 1500ca632f55SGrant Likely { 1501a6f936dbSAxel Lin struct spi_master *master = platform_get_drvdata(pdev); 1502a6f936dbSAxel Lin struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1503ca632f55SGrant Likely 1504a93a2029SShubhrajyoti D pm_runtime_put_sync(mcspi->dev); 1505751c925cSShubhrajyoti D pm_runtime_disable(&pdev->dev); 1506ca632f55SGrant Likely 1507ca632f55SGrant Likely return 0; 1508ca632f55SGrant Likely } 1509ca632f55SGrant Likely 1510ca632f55SGrant Likely /* work with hotplug and coldplug */ 1511ca632f55SGrant Likely MODULE_ALIAS("platform:omap2_mcspi"); 1512ca632f55SGrant Likely 1513ca632f55SGrant Likely #ifdef CONFIG_SUSPEND 1514ca632f55SGrant Likely /* 1515ca632f55SGrant Likely * When SPI wake up from off-mode, CS is in activate state. If it was in 1516ca632f55SGrant Likely * unactive state when driver was suspend, then force it to unactive state at 1517ca632f55SGrant Likely * wake up. 1518ca632f55SGrant Likely */ 1519ca632f55SGrant Likely static int omap2_mcspi_resume(struct device *dev) 1520ca632f55SGrant Likely { 1521ca632f55SGrant Likely struct spi_master *master = dev_get_drvdata(dev); 1522ca632f55SGrant Likely struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 15231bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1524ca632f55SGrant Likely struct omap2_mcspi_cs *cs; 1525ca632f55SGrant Likely 1526034d3dc9SShubhrajyoti D pm_runtime_get_sync(mcspi->dev); 15271bd897f8SBenoit Cousson list_for_each_entry(cs, &ctx->cs, node) { 1528ca632f55SGrant Likely if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { 1529ca632f55SGrant Likely /* 1530ca632f55SGrant Likely * We need to toggle CS state for OMAP take this 1531ca632f55SGrant Likely * change in account. 1532ca632f55SGrant Likely */ 1533af4e944dSShubhrajyoti D cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; 153421b2ce5eSVictor Kamensky writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1535af4e944dSShubhrajyoti D cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 153621b2ce5eSVictor Kamensky writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1537ca632f55SGrant Likely } 1538ca632f55SGrant Likely } 1539034d3dc9SShubhrajyoti D pm_runtime_mark_last_busy(mcspi->dev); 1540034d3dc9SShubhrajyoti D pm_runtime_put_autosuspend(mcspi->dev); 1541beca3655SPascal Huerst 1542beca3655SPascal Huerst return pinctrl_pm_select_default_state(dev); 1543ca632f55SGrant Likely } 1544beca3655SPascal Huerst 1545beca3655SPascal Huerst static int omap2_mcspi_suspend(struct device *dev) 1546beca3655SPascal Huerst { 1547beca3655SPascal Huerst return pinctrl_pm_select_sleep_state(dev); 1548beca3655SPascal Huerst } 1549beca3655SPascal Huerst 1550ca632f55SGrant Likely #else 1551beca3655SPascal Huerst #define omap2_mcspi_suspend NULL 1552ca632f55SGrant Likely #define omap2_mcspi_resume NULL 1553ca632f55SGrant Likely #endif 1554ca632f55SGrant Likely 1555ca632f55SGrant Likely static const struct dev_pm_ops omap2_mcspi_pm_ops = { 1556ca632f55SGrant Likely .resume = omap2_mcspi_resume, 1557beca3655SPascal Huerst .suspend = omap2_mcspi_suspend, 1558ca632f55SGrant Likely .runtime_resume = omap_mcspi_runtime_resume, 1559ca632f55SGrant Likely }; 1560ca632f55SGrant Likely 1561ca632f55SGrant Likely static struct platform_driver omap2_mcspi_driver = { 1562ca632f55SGrant Likely .driver = { 1563ca632f55SGrant Likely .name = "omap2_mcspi", 1564d5a80031SBenoit Cousson .pm = &omap2_mcspi_pm_ops, 1565d5a80031SBenoit Cousson .of_match_table = omap_mcspi_of_match, 1566ca632f55SGrant Likely }, 15677d6b6d83SFelipe Balbi .probe = omap2_mcspi_probe, 1568fd4a319bSGrant Likely .remove = omap2_mcspi_remove, 1569ca632f55SGrant Likely }; 1570ca632f55SGrant Likely 15719fdca9dfSFelipe Balbi module_platform_driver(omap2_mcspi_driver); 1572ca632f55SGrant Likely MODULE_LICENSE("GPL"); 1573