1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * OMAP2 McSPI controller driver 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * Copyright (C) 2005, 2006 Nokia Corporation 5ca632f55SGrant Likely * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and 6ca632f55SGrant Likely * Juha Yrj�l� <juha.yrjola@nokia.com> 7ca632f55SGrant Likely * 8ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 9ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 10ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 11ca632f55SGrant Likely * (at your option) any later version. 12ca632f55SGrant Likely * 13ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 14ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 15ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16ca632f55SGrant Likely * GNU General Public License for more details. 17ca632f55SGrant Likely */ 18ca632f55SGrant Likely 19ca632f55SGrant Likely #include <linux/kernel.h> 20ca632f55SGrant Likely #include <linux/interrupt.h> 21ca632f55SGrant Likely #include <linux/module.h> 22ca632f55SGrant Likely #include <linux/device.h> 23ca632f55SGrant Likely #include <linux/delay.h> 24ca632f55SGrant Likely #include <linux/dma-mapping.h> 2553741ed8SRussell King #include <linux/dmaengine.h> 26beca3655SPascal Huerst #include <linux/pinctrl/consumer.h> 27ca632f55SGrant Likely #include <linux/platform_device.h> 28ca632f55SGrant Likely #include <linux/err.h> 29ca632f55SGrant Likely #include <linux/clk.h> 30ca632f55SGrant Likely #include <linux/io.h> 31ca632f55SGrant Likely #include <linux/slab.h> 32ca632f55SGrant Likely #include <linux/pm_runtime.h> 33d5a80031SBenoit Cousson #include <linux/of.h> 34d5a80031SBenoit Cousson #include <linux/of_device.h> 35d33f473dSIllia Smyrnov #include <linux/gcd.h> 36*13d515c7SVignesh R #include <linux/iopoll.h> 37ca632f55SGrant Likely 38ca632f55SGrant Likely #include <linux/spi/spi.h> 39bc7f9bbcSMichael Welling #include <linux/gpio.h> 40ca632f55SGrant Likely 412203747cSArnd Bergmann #include <linux/platform_data/spi-omap2-mcspi.h> 42ca632f55SGrant Likely 43ca632f55SGrant Likely #define OMAP2_MCSPI_MAX_FREQ 48000000 44faee9b05SStefan Sørensen #define OMAP2_MCSPI_MAX_DIVIDER 4096 45d33f473dSIllia Smyrnov #define OMAP2_MCSPI_MAX_FIFODEPTH 64 46d33f473dSIllia Smyrnov #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF 4727b5284cSShubhrajyoti D #define SPI_AUTOSUSPEND_TIMEOUT 2000 48ca632f55SGrant Likely 49ca632f55SGrant Likely #define OMAP2_MCSPI_REVISION 0x00 50ca632f55SGrant Likely #define OMAP2_MCSPI_SYSSTATUS 0x14 51ca632f55SGrant Likely #define OMAP2_MCSPI_IRQSTATUS 0x18 52ca632f55SGrant Likely #define OMAP2_MCSPI_IRQENABLE 0x1c 53ca632f55SGrant Likely #define OMAP2_MCSPI_WAKEUPENABLE 0x20 54ca632f55SGrant Likely #define OMAP2_MCSPI_SYST 0x24 55ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL 0x28 56d33f473dSIllia Smyrnov #define OMAP2_MCSPI_XFERLEVEL 0x7c 57ca632f55SGrant Likely 58ca632f55SGrant Likely /* per-channel banks, 0x14 bytes each, first is: */ 59ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF0 0x2c 60ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT0 0x30 61ca632f55SGrant Likely #define OMAP2_MCSPI_CHCTRL0 0x34 62ca632f55SGrant Likely #define OMAP2_MCSPI_TX0 0x38 63ca632f55SGrant Likely #define OMAP2_MCSPI_RX0 0x3c 64ca632f55SGrant Likely 65ca632f55SGrant Likely /* per-register bitmasks: */ 66d33f473dSIllia Smyrnov #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) 67ca632f55SGrant Likely 68ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) 69ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) 70ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) 71ca632f55SGrant Likely 72ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_PHA BIT(0) 73ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_POL BIT(1) 74ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) 75ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) 76ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) 77ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) 78ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) 79ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) 80ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) 81ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) 82ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) 83ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) 84ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_IS BIT(18) 85ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) 86ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) 87d33f473dSIllia Smyrnov #define OMAP2_MCSPI_CHCONF_FFET BIT(27) 88d33f473dSIllia Smyrnov #define OMAP2_MCSPI_CHCONF_FFER BIT(28) 89faee9b05SStefan Sørensen #define OMAP2_MCSPI_CHCONF_CLKG BIT(29) 90ca632f55SGrant Likely 91ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) 92ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) 93ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) 94d33f473dSIllia Smyrnov #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) 95ca632f55SGrant Likely 96ca632f55SGrant Likely #define OMAP2_MCSPI_CHCTRL_EN BIT(0) 97faee9b05SStefan Sørensen #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8) 98ca632f55SGrant Likely 99ca632f55SGrant Likely #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) 100ca632f55SGrant Likely 101ca632f55SGrant Likely /* We have 2 DMA channels per CS, one for RX and one for TX */ 102ca632f55SGrant Likely struct omap2_mcspi_dma { 10353741ed8SRussell King struct dma_chan *dma_tx; 10453741ed8SRussell King struct dma_chan *dma_rx; 105ca632f55SGrant Likely 106ca632f55SGrant Likely struct completion dma_tx_completion; 107ca632f55SGrant Likely struct completion dma_rx_completion; 10874f3aaadSMatt Porter 10974f3aaadSMatt Porter char dma_rx_ch_name[14]; 11074f3aaadSMatt Porter char dma_tx_ch_name[14]; 111ca632f55SGrant Likely }; 112ca632f55SGrant Likely 113ca632f55SGrant Likely /* use PIO for small transfers, avoiding DMA setup/teardown overhead and 114ca632f55SGrant Likely * cache operations; better heuristics consider wordsize and bitrate. 115ca632f55SGrant Likely */ 116ca632f55SGrant Likely #define DMA_MIN_BYTES 160 117ca632f55SGrant Likely 118ca632f55SGrant Likely 1191bd897f8SBenoit Cousson /* 1201bd897f8SBenoit Cousson * Used for context save and restore, structure members to be updated whenever 1211bd897f8SBenoit Cousson * corresponding registers are modified. 1221bd897f8SBenoit Cousson */ 1231bd897f8SBenoit Cousson struct omap2_mcspi_regs { 1241bd897f8SBenoit Cousson u32 modulctrl; 1251bd897f8SBenoit Cousson u32 wakeupenable; 1261bd897f8SBenoit Cousson struct list_head cs; 1271bd897f8SBenoit Cousson }; 1281bd897f8SBenoit Cousson 129ca632f55SGrant Likely struct omap2_mcspi { 130ca632f55SGrant Likely struct spi_master *master; 131ca632f55SGrant Likely /* Virtual base address of the controller */ 132ca632f55SGrant Likely void __iomem *base; 133ca632f55SGrant Likely unsigned long phys; 134ca632f55SGrant Likely /* SPI1 has 4 channels, while SPI2 has 2 */ 135ca632f55SGrant Likely struct omap2_mcspi_dma *dma_channels; 136ca632f55SGrant Likely struct device *dev; 1371bd897f8SBenoit Cousson struct omap2_mcspi_regs ctx; 138d33f473dSIllia Smyrnov int fifo_depth; 1390384e90bSDaniel Mack unsigned int pin_dir:1; 140ca632f55SGrant Likely }; 141ca632f55SGrant Likely 142ca632f55SGrant Likely struct omap2_mcspi_cs { 143ca632f55SGrant Likely void __iomem *base; 144ca632f55SGrant Likely unsigned long phys; 145ca632f55SGrant Likely int word_len; 14697ca0d6cSMark A. Greer u16 mode; 147ca632f55SGrant Likely struct list_head node; 148ca632f55SGrant Likely /* Context save and restore shadow register */ 149faee9b05SStefan Sørensen u32 chconf0, chctrl0; 150ca632f55SGrant Likely }; 151ca632f55SGrant Likely 152ca632f55SGrant Likely static inline void mcspi_write_reg(struct spi_master *master, 153ca632f55SGrant Likely int idx, u32 val) 154ca632f55SGrant Likely { 155ca632f55SGrant Likely struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 156ca632f55SGrant Likely 15721b2ce5eSVictor Kamensky writel_relaxed(val, mcspi->base + idx); 158ca632f55SGrant Likely } 159ca632f55SGrant Likely 160ca632f55SGrant Likely static inline u32 mcspi_read_reg(struct spi_master *master, int idx) 161ca632f55SGrant Likely { 162ca632f55SGrant Likely struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 163ca632f55SGrant Likely 16421b2ce5eSVictor Kamensky return readl_relaxed(mcspi->base + idx); 165ca632f55SGrant Likely } 166ca632f55SGrant Likely 167ca632f55SGrant Likely static inline void mcspi_write_cs_reg(const struct spi_device *spi, 168ca632f55SGrant Likely int idx, u32 val) 169ca632f55SGrant Likely { 170ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 171ca632f55SGrant Likely 17221b2ce5eSVictor Kamensky writel_relaxed(val, cs->base + idx); 173ca632f55SGrant Likely } 174ca632f55SGrant Likely 175ca632f55SGrant Likely static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) 176ca632f55SGrant Likely { 177ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 178ca632f55SGrant Likely 17921b2ce5eSVictor Kamensky return readl_relaxed(cs->base + idx); 180ca632f55SGrant Likely } 181ca632f55SGrant Likely 182ca632f55SGrant Likely static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) 183ca632f55SGrant Likely { 184ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 185ca632f55SGrant Likely 186ca632f55SGrant Likely return cs->chconf0; 187ca632f55SGrant Likely } 188ca632f55SGrant Likely 189ca632f55SGrant Likely static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) 190ca632f55SGrant Likely { 191ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 192ca632f55SGrant Likely 193ca632f55SGrant Likely cs->chconf0 = val; 194ca632f55SGrant Likely mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); 195ca632f55SGrant Likely mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 196ca632f55SGrant Likely } 197ca632f55SGrant Likely 19856cd5c15SIllia Smyrnov static inline int mcspi_bytes_per_word(int word_len) 19956cd5c15SIllia Smyrnov { 20056cd5c15SIllia Smyrnov if (word_len <= 8) 20156cd5c15SIllia Smyrnov return 1; 20256cd5c15SIllia Smyrnov else if (word_len <= 16) 20356cd5c15SIllia Smyrnov return 2; 20456cd5c15SIllia Smyrnov else /* word_len <= 32 */ 20556cd5c15SIllia Smyrnov return 4; 20656cd5c15SIllia Smyrnov } 20756cd5c15SIllia Smyrnov 208ca632f55SGrant Likely static void omap2_mcspi_set_dma_req(const struct spi_device *spi, 209ca632f55SGrant Likely int is_read, int enable) 210ca632f55SGrant Likely { 211ca632f55SGrant Likely u32 l, rw; 212ca632f55SGrant Likely 213ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 214ca632f55SGrant Likely 215ca632f55SGrant Likely if (is_read) /* 1 is read, 0 write */ 216ca632f55SGrant Likely rw = OMAP2_MCSPI_CHCONF_DMAR; 217ca632f55SGrant Likely else 218ca632f55SGrant Likely rw = OMAP2_MCSPI_CHCONF_DMAW; 219ca632f55SGrant Likely 220af4e944dSShubhrajyoti D if (enable) 221af4e944dSShubhrajyoti D l |= rw; 222af4e944dSShubhrajyoti D else 223af4e944dSShubhrajyoti D l &= ~rw; 224af4e944dSShubhrajyoti D 225ca632f55SGrant Likely mcspi_write_chconf0(spi, l); 226ca632f55SGrant Likely } 227ca632f55SGrant Likely 228ca632f55SGrant Likely static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 229ca632f55SGrant Likely { 230faee9b05SStefan Sørensen struct omap2_mcspi_cs *cs = spi->controller_state; 231ca632f55SGrant Likely u32 l; 232ca632f55SGrant Likely 233faee9b05SStefan Sørensen l = cs->chctrl0; 234faee9b05SStefan Sørensen if (enable) 235faee9b05SStefan Sørensen l |= OMAP2_MCSPI_CHCTRL_EN; 236faee9b05SStefan Sørensen else 237faee9b05SStefan Sørensen l &= ~OMAP2_MCSPI_CHCTRL_EN; 238faee9b05SStefan Sørensen cs->chctrl0 = l; 239faee9b05SStefan Sørensen mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); 240ca632f55SGrant Likely /* Flash post-writes */ 241ca632f55SGrant Likely mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); 242ca632f55SGrant Likely } 243ca632f55SGrant Likely 244ddcad7e9SMichael Welling static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) 245ca632f55SGrant Likely { 2465f74db10SSebastian Reichel struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 247ca632f55SGrant Likely u32 l; 248ca632f55SGrant Likely 2494373f8b6SMichael Welling /* The controller handles the inverted chip selects 2504373f8b6SMichael Welling * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert 2514373f8b6SMichael Welling * the inversion from the core spi_set_cs function. 2524373f8b6SMichael Welling */ 2534373f8b6SMichael Welling if (spi->mode & SPI_CS_HIGH) 2544373f8b6SMichael Welling enable = !enable; 2554373f8b6SMichael Welling 256ddcad7e9SMichael Welling if (spi->controller_state) { 2575f74db10SSebastian Reichel int err = pm_runtime_get_sync(mcspi->dev); 2585f74db10SSebastian Reichel if (err < 0) { 2595a686b2cSTony Lindgren pm_runtime_put_noidle(mcspi->dev); 2605f74db10SSebastian Reichel dev_err(mcspi->dev, "failed to get sync: %d\n", err); 2615f74db10SSebastian Reichel return; 2625f74db10SSebastian Reichel } 2635f74db10SSebastian Reichel 264ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 265ddcad7e9SMichael Welling 266ddcad7e9SMichael Welling if (enable) 267af4e944dSShubhrajyoti D l &= ~OMAP2_MCSPI_CHCONF_FORCE; 268ddcad7e9SMichael Welling else 269ddcad7e9SMichael Welling l |= OMAP2_MCSPI_CHCONF_FORCE; 270af4e944dSShubhrajyoti D 271ca632f55SGrant Likely mcspi_write_chconf0(spi, l); 2725f74db10SSebastian Reichel 2735f74db10SSebastian Reichel pm_runtime_mark_last_busy(mcspi->dev); 2745f74db10SSebastian Reichel pm_runtime_put_autosuspend(mcspi->dev); 275ca632f55SGrant Likely } 276ddcad7e9SMichael Welling } 277ca632f55SGrant Likely 278ca632f55SGrant Likely static void omap2_mcspi_set_master_mode(struct spi_master *master) 279ca632f55SGrant Likely { 2801bd897f8SBenoit Cousson struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 2811bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 282ca632f55SGrant Likely u32 l; 283ca632f55SGrant Likely 2841bd897f8SBenoit Cousson /* 2851bd897f8SBenoit Cousson * Setup when switching from (reset default) slave mode 286ca632f55SGrant Likely * to single-channel master mode 287ca632f55SGrant Likely */ 288ca632f55SGrant Likely l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); 289af4e944dSShubhrajyoti D l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); 290af4e944dSShubhrajyoti D l |= OMAP2_MCSPI_MODULCTRL_SINGLE; 291ca632f55SGrant Likely mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); 292ca632f55SGrant Likely 2931bd897f8SBenoit Cousson ctx->modulctrl = l; 294ca632f55SGrant Likely } 295ca632f55SGrant Likely 296d33f473dSIllia Smyrnov static void omap2_mcspi_set_fifo(const struct spi_device *spi, 297d33f473dSIllia Smyrnov struct spi_transfer *t, int enable) 298d33f473dSIllia Smyrnov { 299d33f473dSIllia Smyrnov struct spi_master *master = spi->master; 300d33f473dSIllia Smyrnov struct omap2_mcspi_cs *cs = spi->controller_state; 301d33f473dSIllia Smyrnov struct omap2_mcspi *mcspi; 302d33f473dSIllia Smyrnov unsigned int wcnt; 3035db542edSIllia Smyrnov int max_fifo_depth, fifo_depth, bytes_per_word; 304d33f473dSIllia Smyrnov u32 chconf, xferlevel; 305d33f473dSIllia Smyrnov 306d33f473dSIllia Smyrnov mcspi = spi_master_get_devdata(master); 307d33f473dSIllia Smyrnov 308d33f473dSIllia Smyrnov chconf = mcspi_cached_chconf0(spi); 309d33f473dSIllia Smyrnov if (enable) { 310d33f473dSIllia Smyrnov bytes_per_word = mcspi_bytes_per_word(cs->word_len); 311d33f473dSIllia Smyrnov if (t->len % bytes_per_word != 0) 312d33f473dSIllia Smyrnov goto disable_fifo; 313d33f473dSIllia Smyrnov 3145db542edSIllia Smyrnov if (t->rx_buf != NULL && t->tx_buf != NULL) 3155db542edSIllia Smyrnov max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; 3165db542edSIllia Smyrnov else 3175db542edSIllia Smyrnov max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; 3185db542edSIllia Smyrnov 3195db542edSIllia Smyrnov fifo_depth = gcd(t->len, max_fifo_depth); 320d33f473dSIllia Smyrnov if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) 321d33f473dSIllia Smyrnov goto disable_fifo; 322d33f473dSIllia Smyrnov 323d33f473dSIllia Smyrnov wcnt = t->len / bytes_per_word; 324d33f473dSIllia Smyrnov if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) 325d33f473dSIllia Smyrnov goto disable_fifo; 326d33f473dSIllia Smyrnov 327d33f473dSIllia Smyrnov xferlevel = wcnt << 16; 328d33f473dSIllia Smyrnov if (t->rx_buf != NULL) { 329d33f473dSIllia Smyrnov chconf |= OMAP2_MCSPI_CHCONF_FFER; 330d33f473dSIllia Smyrnov xferlevel |= (fifo_depth - 1) << 8; 3315db542edSIllia Smyrnov } 3325db542edSIllia Smyrnov if (t->tx_buf != NULL) { 333d33f473dSIllia Smyrnov chconf |= OMAP2_MCSPI_CHCONF_FFET; 334d33f473dSIllia Smyrnov xferlevel |= fifo_depth - 1; 335d33f473dSIllia Smyrnov } 336d33f473dSIllia Smyrnov 337d33f473dSIllia Smyrnov mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); 338d33f473dSIllia Smyrnov mcspi_write_chconf0(spi, chconf); 339d33f473dSIllia Smyrnov mcspi->fifo_depth = fifo_depth; 340d33f473dSIllia Smyrnov 341d33f473dSIllia Smyrnov return; 342d33f473dSIllia Smyrnov } 343d33f473dSIllia Smyrnov 344d33f473dSIllia Smyrnov disable_fifo: 345d33f473dSIllia Smyrnov if (t->rx_buf != NULL) 346d33f473dSIllia Smyrnov chconf &= ~OMAP2_MCSPI_CHCONF_FFER; 3473d0763c0SJorge A. Ventura 3483d0763c0SJorge A. Ventura if (t->tx_buf != NULL) 349d33f473dSIllia Smyrnov chconf &= ~OMAP2_MCSPI_CHCONF_FFET; 350d33f473dSIllia Smyrnov 351d33f473dSIllia Smyrnov mcspi_write_chconf0(spi, chconf); 352d33f473dSIllia Smyrnov mcspi->fifo_depth = 0; 353d33f473dSIllia Smyrnov } 354d33f473dSIllia Smyrnov 355ca632f55SGrant Likely static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) 356ca632f55SGrant Likely { 357*13d515c7SVignesh R u32 val; 358ca632f55SGrant Likely 359*13d515c7SVignesh R return readl_poll_timeout(reg, val, val & bit, 1, MSEC_PER_SEC); 360ca632f55SGrant Likely } 361ca632f55SGrant Likely 36253741ed8SRussell King static void omap2_mcspi_rx_callback(void *data) 36353741ed8SRussell King { 36453741ed8SRussell King struct spi_device *spi = data; 36553741ed8SRussell King struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 36653741ed8SRussell King struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 36753741ed8SRussell King 36853741ed8SRussell King /* We must disable the DMA RX request */ 36953741ed8SRussell King omap2_mcspi_set_dma_req(spi, 1, 0); 370830379e0SFelipe Balbi 371830379e0SFelipe Balbi complete(&mcspi_dma->dma_rx_completion); 37253741ed8SRussell King } 37353741ed8SRussell King 37453741ed8SRussell King static void omap2_mcspi_tx_callback(void *data) 37553741ed8SRussell King { 37653741ed8SRussell King struct spi_device *spi = data; 37753741ed8SRussell King struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 37853741ed8SRussell King struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 37953741ed8SRussell King 38053741ed8SRussell King /* We must disable the DMA TX request */ 38153741ed8SRussell King omap2_mcspi_set_dma_req(spi, 0, 0); 382830379e0SFelipe Balbi 383830379e0SFelipe Balbi complete(&mcspi_dma->dma_tx_completion); 38453741ed8SRussell King } 38553741ed8SRussell King 386d7b4394eSShubhrajyoti D static void omap2_mcspi_tx_dma(struct spi_device *spi, 387d7b4394eSShubhrajyoti D struct spi_transfer *xfer, 388d7b4394eSShubhrajyoti D struct dma_slave_config cfg) 389ca632f55SGrant Likely { 390ca632f55SGrant Likely struct omap2_mcspi *mcspi; 391ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 392ca632f55SGrant Likely 393ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 394ca632f55SGrant Likely mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 395ca632f55SGrant Likely 396d7b4394eSShubhrajyoti D if (mcspi_dma->dma_tx) { 39753741ed8SRussell King struct dma_async_tx_descriptor *tx; 39853741ed8SRussell King 39953741ed8SRussell King dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); 40053741ed8SRussell King 4010ba1870fSFranklin S Cooper Jr tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, 4020ba1870fSFranklin S Cooper Jr xfer->tx_sg.nents, 4030ba1870fSFranklin S Cooper Jr DMA_MEM_TO_DEV, 4040ba1870fSFranklin S Cooper Jr DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 40553741ed8SRussell King if (tx) { 40653741ed8SRussell King tx->callback = omap2_mcspi_tx_callback; 40753741ed8SRussell King tx->callback_param = spi; 40853741ed8SRussell King dmaengine_submit(tx); 40953741ed8SRussell King } else { 41053741ed8SRussell King /* FIXME: fall back to PIO? */ 41153741ed8SRussell King } 41253741ed8SRussell King } 41353741ed8SRussell King dma_async_issue_pending(mcspi_dma->dma_tx); 414ca632f55SGrant Likely omap2_mcspi_set_dma_req(spi, 0, 1); 415ca632f55SGrant Likely 416ca632f55SGrant Likely } 417ca632f55SGrant Likely 418d7b4394eSShubhrajyoti D static unsigned 419d7b4394eSShubhrajyoti D omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, 420d7b4394eSShubhrajyoti D struct dma_slave_config cfg, 421d7b4394eSShubhrajyoti D unsigned es) 422d7b4394eSShubhrajyoti D { 423d7b4394eSShubhrajyoti D struct omap2_mcspi *mcspi; 424d7b4394eSShubhrajyoti D struct omap2_mcspi_dma *mcspi_dma; 4250ba1870fSFranklin S Cooper Jr unsigned int count, transfer_reduction = 0; 4260ba1870fSFranklin S Cooper Jr struct scatterlist *sg_out[2]; 4270ba1870fSFranklin S Cooper Jr int nb_sizes = 0, out_mapped_nents[2], ret, x; 4280ba1870fSFranklin S Cooper Jr size_t sizes[2]; 429d7b4394eSShubhrajyoti D u32 l; 430d7b4394eSShubhrajyoti D int elements = 0; 431d7b4394eSShubhrajyoti D int word_len, element_count; 432d7b4394eSShubhrajyoti D struct omap2_mcspi_cs *cs = spi->controller_state; 43381261359SAkinobu Mita void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; 43481261359SAkinobu Mita 435d7b4394eSShubhrajyoti D mcspi = spi_master_get_devdata(spi->master); 436d7b4394eSShubhrajyoti D mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 437d7b4394eSShubhrajyoti D count = xfer->len; 438d33f473dSIllia Smyrnov 4394bd00413SFranklin S Cooper Jr /* 4404bd00413SFranklin S Cooper Jr * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM 4414bd00413SFranklin S Cooper Jr * it mentions reducing DMA transfer length by one element in master 4424bd00413SFranklin S Cooper Jr * normal mode. 4434bd00413SFranklin S Cooper Jr */ 444d33f473dSIllia Smyrnov if (mcspi->fifo_depth == 0) 4450ba1870fSFranklin S Cooper Jr transfer_reduction = es; 446d33f473dSIllia Smyrnov 447d7b4394eSShubhrajyoti D word_len = cs->word_len; 448d7b4394eSShubhrajyoti D l = mcspi_cached_chconf0(spi); 449d7b4394eSShubhrajyoti D 450d7b4394eSShubhrajyoti D if (word_len <= 8) 451d7b4394eSShubhrajyoti D element_count = count; 452d7b4394eSShubhrajyoti D else if (word_len <= 16) 453d7b4394eSShubhrajyoti D element_count = count >> 1; 454d7b4394eSShubhrajyoti D else /* word_len <= 32 */ 455d7b4394eSShubhrajyoti D element_count = count >> 2; 456d7b4394eSShubhrajyoti D 457d7b4394eSShubhrajyoti D if (mcspi_dma->dma_rx) { 458d7b4394eSShubhrajyoti D struct dma_async_tx_descriptor *tx; 459d7b4394eSShubhrajyoti D 460d7b4394eSShubhrajyoti D dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); 461d7b4394eSShubhrajyoti D 4624bd00413SFranklin S Cooper Jr /* 4634bd00413SFranklin S Cooper Jr * Reduce DMA transfer length by one more if McSPI is 4644bd00413SFranklin S Cooper Jr * configured in turbo mode. 4654bd00413SFranklin S Cooper Jr */ 466d33f473dSIllia Smyrnov if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) 4670ba1870fSFranklin S Cooper Jr transfer_reduction += es; 468d7b4394eSShubhrajyoti D 4690ba1870fSFranklin S Cooper Jr if (transfer_reduction) { 4700ba1870fSFranklin S Cooper Jr /* Split sgl into two. The second sgl won't be used. */ 4710ba1870fSFranklin S Cooper Jr sizes[0] = count - transfer_reduction; 4720ba1870fSFranklin S Cooper Jr sizes[1] = transfer_reduction; 4730ba1870fSFranklin S Cooper Jr nb_sizes = 2; 4740ba1870fSFranklin S Cooper Jr } else { 4750ba1870fSFranklin S Cooper Jr /* 4760ba1870fSFranklin S Cooper Jr * Don't bother splitting the sgl. This essentially 4770ba1870fSFranklin S Cooper Jr * clones the original sgl. 4780ba1870fSFranklin S Cooper Jr */ 4790ba1870fSFranklin S Cooper Jr sizes[0] = count; 4800ba1870fSFranklin S Cooper Jr nb_sizes = 1; 4810ba1870fSFranklin S Cooper Jr } 482d7b4394eSShubhrajyoti D 4830ba1870fSFranklin S Cooper Jr ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 4840ba1870fSFranklin S Cooper Jr 0, nb_sizes, 4850ba1870fSFranklin S Cooper Jr sizes, 4860ba1870fSFranklin S Cooper Jr sg_out, out_mapped_nents, 4870ba1870fSFranklin S Cooper Jr GFP_KERNEL); 4880ba1870fSFranklin S Cooper Jr 4890ba1870fSFranklin S Cooper Jr if (ret < 0) { 4900ba1870fSFranklin S Cooper Jr dev_err(&spi->dev, "sg_split failed\n"); 4910ba1870fSFranklin S Cooper Jr return 0; 4920ba1870fSFranklin S Cooper Jr } 4930ba1870fSFranklin S Cooper Jr 4940ba1870fSFranklin S Cooper Jr tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, 4950ba1870fSFranklin S Cooper Jr sg_out[0], 4960ba1870fSFranklin S Cooper Jr out_mapped_nents[0], 4970ba1870fSFranklin S Cooper Jr DMA_DEV_TO_MEM, 4980ba1870fSFranklin S Cooper Jr DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 499d7b4394eSShubhrajyoti D if (tx) { 500d7b4394eSShubhrajyoti D tx->callback = omap2_mcspi_rx_callback; 501d7b4394eSShubhrajyoti D tx->callback_param = spi; 502d7b4394eSShubhrajyoti D dmaengine_submit(tx); 503d7b4394eSShubhrajyoti D } else { 504d7b4394eSShubhrajyoti D /* FIXME: fall back to PIO? */ 505d7b4394eSShubhrajyoti D } 506d7b4394eSShubhrajyoti D } 507d7b4394eSShubhrajyoti D 508d7b4394eSShubhrajyoti D dma_async_issue_pending(mcspi_dma->dma_rx); 509d7b4394eSShubhrajyoti D omap2_mcspi_set_dma_req(spi, 1, 1); 510d7b4394eSShubhrajyoti D 511ca632f55SGrant Likely wait_for_completion(&mcspi_dma->dma_rx_completion); 5120ba1870fSFranklin S Cooper Jr 5130ba1870fSFranklin S Cooper Jr for (x = 0; x < nb_sizes; x++) 5140ba1870fSFranklin S Cooper Jr kfree(sg_out[x]); 515d33f473dSIllia Smyrnov 516d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0) 517d33f473dSIllia Smyrnov return count; 518d33f473dSIllia Smyrnov 5194bd00413SFranklin S Cooper Jr /* 5204bd00413SFranklin S Cooper Jr * Due to the DMA transfer length reduction the missing bytes must 5214bd00413SFranklin S Cooper Jr * be read manually to receive all of the expected data. 5224bd00413SFranklin S Cooper Jr */ 523ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 524ca632f55SGrant Likely 52553741ed8SRussell King elements = element_count - 1; 52653741ed8SRussell King 527ca632f55SGrant Likely if (l & OMAP2_MCSPI_CHCONF_TURBO) { 52853741ed8SRussell King elements--; 529ca632f55SGrant Likely 53081261359SAkinobu Mita if (!mcspi_wait_for_reg_bit(chstat_reg, 53181261359SAkinobu Mita OMAP2_MCSPI_CHSTAT_RXS)) { 532ca632f55SGrant Likely u32 w; 533ca632f55SGrant Likely 534ca632f55SGrant Likely w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 535ca632f55SGrant Likely if (word_len <= 8) 536ca632f55SGrant Likely ((u8 *)xfer->rx_buf)[elements++] = w; 537ca632f55SGrant Likely else if (word_len <= 16) 538ca632f55SGrant Likely ((u16 *)xfer->rx_buf)[elements++] = w; 539ca632f55SGrant Likely else /* word_len <= 32 */ 540ca632f55SGrant Likely ((u32 *)xfer->rx_buf)[elements++] = w; 541ca632f55SGrant Likely } else { 54256cd5c15SIllia Smyrnov int bytes_per_word = mcspi_bytes_per_word(word_len); 543a1829d2bSJarkko Nikula dev_err(&spi->dev, "DMA RX penultimate word empty\n"); 54456cd5c15SIllia Smyrnov count -= (bytes_per_word << 1); 545ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 1); 546ca632f55SGrant Likely return count; 547ca632f55SGrant Likely } 548ca632f55SGrant Likely } 54981261359SAkinobu Mita if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) { 550ca632f55SGrant Likely u32 w; 551ca632f55SGrant Likely 552ca632f55SGrant Likely w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 553ca632f55SGrant Likely if (word_len <= 8) 554ca632f55SGrant Likely ((u8 *)xfer->rx_buf)[elements] = w; 555ca632f55SGrant Likely else if (word_len <= 16) 556ca632f55SGrant Likely ((u16 *)xfer->rx_buf)[elements] = w; 557ca632f55SGrant Likely else /* word_len <= 32 */ 558ca632f55SGrant Likely ((u32 *)xfer->rx_buf)[elements] = w; 559ca632f55SGrant Likely } else { 560a1829d2bSJarkko Nikula dev_err(&spi->dev, "DMA RX last word empty\n"); 56156cd5c15SIllia Smyrnov count -= mcspi_bytes_per_word(word_len); 562ca632f55SGrant Likely } 563ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 1); 564d7b4394eSShubhrajyoti D return count; 565ca632f55SGrant Likely } 566d7b4394eSShubhrajyoti D 567d7b4394eSShubhrajyoti D static unsigned 568d7b4394eSShubhrajyoti D omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 569d7b4394eSShubhrajyoti D { 570d7b4394eSShubhrajyoti D struct omap2_mcspi *mcspi; 571d7b4394eSShubhrajyoti D struct omap2_mcspi_cs *cs = spi->controller_state; 572d7b4394eSShubhrajyoti D struct omap2_mcspi_dma *mcspi_dma; 573d7b4394eSShubhrajyoti D unsigned int count; 574d7b4394eSShubhrajyoti D u8 *rx; 575d7b4394eSShubhrajyoti D const u8 *tx; 576d7b4394eSShubhrajyoti D struct dma_slave_config cfg; 577d7b4394eSShubhrajyoti D enum dma_slave_buswidth width; 578d7b4394eSShubhrajyoti D unsigned es; 579d33f473dSIllia Smyrnov u32 burst; 580e47a682aSShubhrajyoti D void __iomem *chstat_reg; 581d33f473dSIllia Smyrnov void __iomem *irqstat_reg; 582d33f473dSIllia Smyrnov int wait_res; 583d7b4394eSShubhrajyoti D 584d7b4394eSShubhrajyoti D mcspi = spi_master_get_devdata(spi->master); 585d7b4394eSShubhrajyoti D mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 586d7b4394eSShubhrajyoti D 587d7b4394eSShubhrajyoti D if (cs->word_len <= 8) { 588d7b4394eSShubhrajyoti D width = DMA_SLAVE_BUSWIDTH_1_BYTE; 589d7b4394eSShubhrajyoti D es = 1; 590d7b4394eSShubhrajyoti D } else if (cs->word_len <= 16) { 591d7b4394eSShubhrajyoti D width = DMA_SLAVE_BUSWIDTH_2_BYTES; 592d7b4394eSShubhrajyoti D es = 2; 593d7b4394eSShubhrajyoti D } else { 594d7b4394eSShubhrajyoti D width = DMA_SLAVE_BUSWIDTH_4_BYTES; 595d7b4394eSShubhrajyoti D es = 4; 596d7b4394eSShubhrajyoti D } 597d7b4394eSShubhrajyoti D 598d33f473dSIllia Smyrnov count = xfer->len; 599d33f473dSIllia Smyrnov burst = 1; 600d33f473dSIllia Smyrnov 601d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0) { 602d33f473dSIllia Smyrnov if (count > mcspi->fifo_depth) 603d33f473dSIllia Smyrnov burst = mcspi->fifo_depth / es; 604d33f473dSIllia Smyrnov else 605d33f473dSIllia Smyrnov burst = count / es; 606d33f473dSIllia Smyrnov } 607d33f473dSIllia Smyrnov 608d7b4394eSShubhrajyoti D memset(&cfg, 0, sizeof(cfg)); 609d7b4394eSShubhrajyoti D cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; 610d7b4394eSShubhrajyoti D cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; 611d7b4394eSShubhrajyoti D cfg.src_addr_width = width; 612d7b4394eSShubhrajyoti D cfg.dst_addr_width = width; 613d33f473dSIllia Smyrnov cfg.src_maxburst = burst; 614d33f473dSIllia Smyrnov cfg.dst_maxburst = burst; 615d7b4394eSShubhrajyoti D 616d7b4394eSShubhrajyoti D rx = xfer->rx_buf; 617d7b4394eSShubhrajyoti D tx = xfer->tx_buf; 618d7b4394eSShubhrajyoti D 619d7b4394eSShubhrajyoti D if (tx != NULL) 620d7b4394eSShubhrajyoti D omap2_mcspi_tx_dma(spi, xfer, cfg); 621d7b4394eSShubhrajyoti D 622d7b4394eSShubhrajyoti D if (rx != NULL) 623e47a682aSShubhrajyoti D count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); 624d7b4394eSShubhrajyoti D 625e47a682aSShubhrajyoti D if (tx != NULL) { 626e47a682aSShubhrajyoti D wait_for_completion(&mcspi_dma->dma_tx_completion); 627e47a682aSShubhrajyoti D 628d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0) { 629d33f473dSIllia Smyrnov irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; 630d33f473dSIllia Smyrnov 631d33f473dSIllia Smyrnov if (mcspi_wait_for_reg_bit(irqstat_reg, 632d33f473dSIllia Smyrnov OMAP2_MCSPI_IRQSTATUS_EOW) < 0) 633d33f473dSIllia Smyrnov dev_err(&spi->dev, "EOW timed out\n"); 634d33f473dSIllia Smyrnov 635d33f473dSIllia Smyrnov mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, 636d33f473dSIllia Smyrnov OMAP2_MCSPI_IRQSTATUS_EOW); 637d33f473dSIllia Smyrnov } 638d33f473dSIllia Smyrnov 639e47a682aSShubhrajyoti D /* for TX_ONLY mode, be sure all words have shifted out */ 640e47a682aSShubhrajyoti D if (rx == NULL) { 641d33f473dSIllia Smyrnov chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; 642d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0) { 643d33f473dSIllia Smyrnov wait_res = mcspi_wait_for_reg_bit(chstat_reg, 644d33f473dSIllia Smyrnov OMAP2_MCSPI_CHSTAT_TXFFE); 645d33f473dSIllia Smyrnov if (wait_res < 0) 646d33f473dSIllia Smyrnov dev_err(&spi->dev, "TXFFE timed out\n"); 647d33f473dSIllia Smyrnov } else { 648d33f473dSIllia Smyrnov wait_res = mcspi_wait_for_reg_bit(chstat_reg, 649d33f473dSIllia Smyrnov OMAP2_MCSPI_CHSTAT_TXS); 650d33f473dSIllia Smyrnov if (wait_res < 0) 651e47a682aSShubhrajyoti D dev_err(&spi->dev, "TXS timed out\n"); 652d33f473dSIllia Smyrnov } 653d33f473dSIllia Smyrnov if (wait_res >= 0 && 654d33f473dSIllia Smyrnov (mcspi_wait_for_reg_bit(chstat_reg, 655d33f473dSIllia Smyrnov OMAP2_MCSPI_CHSTAT_EOT) < 0)) 656e47a682aSShubhrajyoti D dev_err(&spi->dev, "EOT timed out\n"); 657e47a682aSShubhrajyoti D } 658e47a682aSShubhrajyoti D } 659ca632f55SGrant Likely return count; 660ca632f55SGrant Likely } 661ca632f55SGrant Likely 662ca632f55SGrant Likely static unsigned 663ca632f55SGrant Likely omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) 664ca632f55SGrant Likely { 665ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 666ca632f55SGrant Likely unsigned int count, c; 667ca632f55SGrant Likely u32 l; 668ca632f55SGrant Likely void __iomem *base = cs->base; 669ca632f55SGrant Likely void __iomem *tx_reg; 670ca632f55SGrant Likely void __iomem *rx_reg; 671ca632f55SGrant Likely void __iomem *chstat_reg; 672ca632f55SGrant Likely int word_len; 673ca632f55SGrant Likely 674ca632f55SGrant Likely count = xfer->len; 675ca632f55SGrant Likely c = count; 676ca632f55SGrant Likely word_len = cs->word_len; 677ca632f55SGrant Likely 678ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 679ca632f55SGrant Likely 680ca632f55SGrant Likely /* We store the pre-calculated register addresses on stack to speed 681ca632f55SGrant Likely * up the transfer loop. */ 682ca632f55SGrant Likely tx_reg = base + OMAP2_MCSPI_TX0; 683ca632f55SGrant Likely rx_reg = base + OMAP2_MCSPI_RX0; 684ca632f55SGrant Likely chstat_reg = base + OMAP2_MCSPI_CHSTAT0; 685ca632f55SGrant Likely 686ca632f55SGrant Likely if (c < (word_len>>3)) 687ca632f55SGrant Likely return 0; 688ca632f55SGrant Likely 689ca632f55SGrant Likely if (word_len <= 8) { 690ca632f55SGrant Likely u8 *rx; 691ca632f55SGrant Likely const u8 *tx; 692ca632f55SGrant Likely 693ca632f55SGrant Likely rx = xfer->rx_buf; 694ca632f55SGrant Likely tx = xfer->tx_buf; 695ca632f55SGrant Likely 696ca632f55SGrant Likely do { 697ca632f55SGrant Likely c -= 1; 698ca632f55SGrant Likely if (tx != NULL) { 699ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 700ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 701ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 702ca632f55SGrant Likely goto out; 703ca632f55SGrant Likely } 704ca632f55SGrant Likely dev_vdbg(&spi->dev, "write-%d %02x\n", 705ca632f55SGrant Likely word_len, *tx); 70621b2ce5eSVictor Kamensky writel_relaxed(*tx++, tx_reg); 707ca632f55SGrant Likely } 708ca632f55SGrant Likely if (rx != NULL) { 709ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 710ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 711ca632f55SGrant Likely dev_err(&spi->dev, "RXS timed out\n"); 712ca632f55SGrant Likely goto out; 713ca632f55SGrant Likely } 714ca632f55SGrant Likely 715ca632f55SGrant Likely if (c == 1 && tx == NULL && 716ca632f55SGrant Likely (l & OMAP2_MCSPI_CHCONF_TURBO)) { 717ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 71821b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 719ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %02x\n", 720ca632f55SGrant Likely word_len, *(rx - 1)); 721ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 722ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 723ca632f55SGrant Likely dev_err(&spi->dev, 724ca632f55SGrant Likely "RXS timed out\n"); 725ca632f55SGrant Likely goto out; 726ca632f55SGrant Likely } 727ca632f55SGrant Likely c = 0; 728ca632f55SGrant Likely } else if (c == 0 && tx == NULL) { 729ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 730ca632f55SGrant Likely } 731ca632f55SGrant Likely 73221b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 733ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %02x\n", 734ca632f55SGrant Likely word_len, *(rx - 1)); 735ca632f55SGrant Likely } 736ca632f55SGrant Likely } while (c); 737ca632f55SGrant Likely } else if (word_len <= 16) { 738ca632f55SGrant Likely u16 *rx; 739ca632f55SGrant Likely const u16 *tx; 740ca632f55SGrant Likely 741ca632f55SGrant Likely rx = xfer->rx_buf; 742ca632f55SGrant Likely tx = xfer->tx_buf; 743ca632f55SGrant Likely do { 744ca632f55SGrant Likely c -= 2; 745ca632f55SGrant Likely if (tx != NULL) { 746ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 747ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 748ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 749ca632f55SGrant Likely goto out; 750ca632f55SGrant Likely } 751ca632f55SGrant Likely dev_vdbg(&spi->dev, "write-%d %04x\n", 752ca632f55SGrant Likely word_len, *tx); 75321b2ce5eSVictor Kamensky writel_relaxed(*tx++, tx_reg); 754ca632f55SGrant Likely } 755ca632f55SGrant Likely if (rx != NULL) { 756ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 757ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 758ca632f55SGrant Likely dev_err(&spi->dev, "RXS timed out\n"); 759ca632f55SGrant Likely goto out; 760ca632f55SGrant Likely } 761ca632f55SGrant Likely 762ca632f55SGrant Likely if (c == 2 && tx == NULL && 763ca632f55SGrant Likely (l & OMAP2_MCSPI_CHCONF_TURBO)) { 764ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 76521b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 766ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %04x\n", 767ca632f55SGrant Likely word_len, *(rx - 1)); 768ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 769ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 770ca632f55SGrant Likely dev_err(&spi->dev, 771ca632f55SGrant Likely "RXS timed out\n"); 772ca632f55SGrant Likely goto out; 773ca632f55SGrant Likely } 774ca632f55SGrant Likely c = 0; 775ca632f55SGrant Likely } else if (c == 0 && tx == NULL) { 776ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 777ca632f55SGrant Likely } 778ca632f55SGrant Likely 77921b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 780ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %04x\n", 781ca632f55SGrant Likely word_len, *(rx - 1)); 782ca632f55SGrant Likely } 783ca632f55SGrant Likely } while (c >= 2); 784ca632f55SGrant Likely } else if (word_len <= 32) { 785ca632f55SGrant Likely u32 *rx; 786ca632f55SGrant Likely const u32 *tx; 787ca632f55SGrant Likely 788ca632f55SGrant Likely rx = xfer->rx_buf; 789ca632f55SGrant Likely tx = xfer->tx_buf; 790ca632f55SGrant Likely do { 791ca632f55SGrant Likely c -= 4; 792ca632f55SGrant Likely if (tx != NULL) { 793ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 794ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 795ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 796ca632f55SGrant Likely goto out; 797ca632f55SGrant Likely } 798ca632f55SGrant Likely dev_vdbg(&spi->dev, "write-%d %08x\n", 799ca632f55SGrant Likely word_len, *tx); 80021b2ce5eSVictor Kamensky writel_relaxed(*tx++, tx_reg); 801ca632f55SGrant Likely } 802ca632f55SGrant Likely if (rx != NULL) { 803ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 804ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 805ca632f55SGrant Likely dev_err(&spi->dev, "RXS timed out\n"); 806ca632f55SGrant Likely goto out; 807ca632f55SGrant Likely } 808ca632f55SGrant Likely 809ca632f55SGrant Likely if (c == 4 && tx == NULL && 810ca632f55SGrant Likely (l & OMAP2_MCSPI_CHCONF_TURBO)) { 811ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 81221b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 813ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %08x\n", 814ca632f55SGrant Likely word_len, *(rx - 1)); 815ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 816ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 817ca632f55SGrant Likely dev_err(&spi->dev, 818ca632f55SGrant Likely "RXS timed out\n"); 819ca632f55SGrant Likely goto out; 820ca632f55SGrant Likely } 821ca632f55SGrant Likely c = 0; 822ca632f55SGrant Likely } else if (c == 0 && tx == NULL) { 823ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 824ca632f55SGrant Likely } 825ca632f55SGrant Likely 82621b2ce5eSVictor Kamensky *rx++ = readl_relaxed(rx_reg); 827ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %08x\n", 828ca632f55SGrant Likely word_len, *(rx - 1)); 829ca632f55SGrant Likely } 830ca632f55SGrant Likely } while (c >= 4); 831ca632f55SGrant Likely } 832ca632f55SGrant Likely 833ca632f55SGrant Likely /* for TX_ONLY mode, be sure all words have shifted out */ 834ca632f55SGrant Likely if (xfer->rx_buf == NULL) { 835ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 836ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 837ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 838ca632f55SGrant Likely } else if (mcspi_wait_for_reg_bit(chstat_reg, 839ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_EOT) < 0) 840ca632f55SGrant Likely dev_err(&spi->dev, "EOT timed out\n"); 841ca632f55SGrant Likely 842ca632f55SGrant Likely /* disable chan to purge rx datas received in TX_ONLY transfer, 843ca632f55SGrant Likely * otherwise these rx datas will affect the direct following 844ca632f55SGrant Likely * RX_ONLY transfer. 845ca632f55SGrant Likely */ 846ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 847ca632f55SGrant Likely } 848ca632f55SGrant Likely out: 849ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 1); 850ca632f55SGrant Likely return count - c; 851ca632f55SGrant Likely } 852ca632f55SGrant Likely 853ca632f55SGrant Likely static u32 omap2_mcspi_calc_divisor(u32 speed_hz) 854ca632f55SGrant Likely { 855ca632f55SGrant Likely u32 div; 856ca632f55SGrant Likely 857ca632f55SGrant Likely for (div = 0; div < 15; div++) 858ca632f55SGrant Likely if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) 859ca632f55SGrant Likely return div; 860ca632f55SGrant Likely 861ca632f55SGrant Likely return 15; 862ca632f55SGrant Likely } 863ca632f55SGrant Likely 864ca632f55SGrant Likely /* called only when no transfer is active to this device */ 865ca632f55SGrant Likely static int omap2_mcspi_setup_transfer(struct spi_device *spi, 866ca632f55SGrant Likely struct spi_transfer *t) 867ca632f55SGrant Likely { 868ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 869ca632f55SGrant Likely struct omap2_mcspi *mcspi; 870faee9b05SStefan Sørensen u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0; 871ca632f55SGrant Likely u8 word_len = spi->bits_per_word; 872ca632f55SGrant Likely u32 speed_hz = spi->max_speed_hz; 873ca632f55SGrant Likely 874ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 875ca632f55SGrant Likely 876ca632f55SGrant Likely if (t != NULL && t->bits_per_word) 877ca632f55SGrant Likely word_len = t->bits_per_word; 878ca632f55SGrant Likely 879ca632f55SGrant Likely cs->word_len = word_len; 880ca632f55SGrant Likely 881ca632f55SGrant Likely if (t && t->speed_hz) 882ca632f55SGrant Likely speed_hz = t->speed_hz; 883ca632f55SGrant Likely 884ca632f55SGrant Likely speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); 885faee9b05SStefan Sørensen if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) { 886faee9b05SStefan Sørensen clkd = omap2_mcspi_calc_divisor(speed_hz); 887faee9b05SStefan Sørensen speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd; 888faee9b05SStefan Sørensen clkg = 0; 889faee9b05SStefan Sørensen } else { 890faee9b05SStefan Sørensen div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; 891faee9b05SStefan Sørensen speed_hz = OMAP2_MCSPI_MAX_FREQ / div; 892faee9b05SStefan Sørensen clkd = (div - 1) & 0xf; 893faee9b05SStefan Sørensen extclk = (div - 1) >> 4; 894faee9b05SStefan Sørensen clkg = OMAP2_MCSPI_CHCONF_CLKG; 895faee9b05SStefan Sørensen } 896ca632f55SGrant Likely 897ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 898ca632f55SGrant Likely 899ca632f55SGrant Likely /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 900ca632f55SGrant Likely * REVISIT: this controller could support SPI_3WIRE mode. 901ca632f55SGrant Likely */ 9022cd45179SDaniel Mack if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { 9030384e90bSDaniel Mack l &= ~OMAP2_MCSPI_CHCONF_IS; 9040384e90bSDaniel Mack l &= ~OMAP2_MCSPI_CHCONF_DPE1; 905ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_DPE0; 9060384e90bSDaniel Mack } else { 9070384e90bSDaniel Mack l |= OMAP2_MCSPI_CHCONF_IS; 9080384e90bSDaniel Mack l |= OMAP2_MCSPI_CHCONF_DPE1; 9090384e90bSDaniel Mack l &= ~OMAP2_MCSPI_CHCONF_DPE0; 9100384e90bSDaniel Mack } 911ca632f55SGrant Likely 912ca632f55SGrant Likely /* wordlength */ 913ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; 914ca632f55SGrant Likely l |= (word_len - 1) << 7; 915ca632f55SGrant Likely 916ca632f55SGrant Likely /* set chipselect polarity; manage with FORCE */ 917ca632f55SGrant Likely if (!(spi->mode & SPI_CS_HIGH)) 918ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ 919ca632f55SGrant Likely else 920ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_EPOL; 921ca632f55SGrant Likely 922ca632f55SGrant Likely /* set clock divisor */ 923ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; 924faee9b05SStefan Sørensen l |= clkd << 2; 925faee9b05SStefan Sørensen 926faee9b05SStefan Sørensen /* set clock granularity */ 927faee9b05SStefan Sørensen l &= ~OMAP2_MCSPI_CHCONF_CLKG; 928faee9b05SStefan Sørensen l |= clkg; 929faee9b05SStefan Sørensen if (clkg) { 930faee9b05SStefan Sørensen cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; 931faee9b05SStefan Sørensen cs->chctrl0 |= extclk << 8; 932faee9b05SStefan Sørensen mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); 933faee9b05SStefan Sørensen } 934ca632f55SGrant Likely 935ca632f55SGrant Likely /* set SPI mode 0..3 */ 936ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 937ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_POL; 938ca632f55SGrant Likely else 939ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_POL; 940ca632f55SGrant Likely if (spi->mode & SPI_CPHA) 941ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_PHA; 942ca632f55SGrant Likely else 943ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_PHA; 944ca632f55SGrant Likely 945ca632f55SGrant Likely mcspi_write_chconf0(spi, l); 946ca632f55SGrant Likely 94797ca0d6cSMark A. Greer cs->mode = spi->mode; 94897ca0d6cSMark A. Greer 949ca632f55SGrant Likely dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 950faee9b05SStefan Sørensen speed_hz, 951ca632f55SGrant Likely (spi->mode & SPI_CPHA) ? "trailing" : "leading", 952ca632f55SGrant Likely (spi->mode & SPI_CPOL) ? "inverted" : "normal"); 953ca632f55SGrant Likely 954ca632f55SGrant Likely return 0; 955ca632f55SGrant Likely } 956ca632f55SGrant Likely 957ddc5cdf1STony Lindgren /* 958ddc5cdf1STony Lindgren * Note that we currently allow DMA only if we get a channel 959ddc5cdf1STony Lindgren * for both rx and tx. Otherwise we'll do PIO for both rx and tx. 960ddc5cdf1STony Lindgren */ 961ca632f55SGrant Likely static int omap2_mcspi_request_dma(struct spi_device *spi) 962ca632f55SGrant Likely { 963ca632f55SGrant Likely struct spi_master *master = spi->master; 964ca632f55SGrant Likely struct omap2_mcspi *mcspi; 965ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 966b085c612SPeter Ujfalusi int ret = 0; 967ca632f55SGrant Likely 968ca632f55SGrant Likely mcspi = spi_master_get_devdata(master); 969ca632f55SGrant Likely mcspi_dma = mcspi->dma_channels + spi->chip_select; 970ca632f55SGrant Likely 971ca632f55SGrant Likely init_completion(&mcspi_dma->dma_rx_completion); 972ca632f55SGrant Likely init_completion(&mcspi_dma->dma_tx_completion); 973ca632f55SGrant Likely 974b085c612SPeter Ujfalusi mcspi_dma->dma_rx = dma_request_chan(&master->dev, 97574f3aaadSMatt Porter mcspi_dma->dma_rx_ch_name); 976b085c612SPeter Ujfalusi if (IS_ERR(mcspi_dma->dma_rx)) { 977b085c612SPeter Ujfalusi ret = PTR_ERR(mcspi_dma->dma_rx); 97853741ed8SRussell King mcspi_dma->dma_rx = NULL; 979ddc5cdf1STony Lindgren goto no_dma; 98053741ed8SRussell King } 981ca632f55SGrant Likely 982b085c612SPeter Ujfalusi mcspi_dma->dma_tx = dma_request_chan(&master->dev, 983b085c612SPeter Ujfalusi mcspi_dma->dma_tx_ch_name); 984b085c612SPeter Ujfalusi if (IS_ERR(mcspi_dma->dma_tx)) { 985b085c612SPeter Ujfalusi ret = PTR_ERR(mcspi_dma->dma_tx); 986b085c612SPeter Ujfalusi mcspi_dma->dma_tx = NULL; 987b085c612SPeter Ujfalusi dma_release_channel(mcspi_dma->dma_rx); 988b085c612SPeter Ujfalusi mcspi_dma->dma_rx = NULL; 989b085c612SPeter Ujfalusi } 990ddc5cdf1STony Lindgren 991ddc5cdf1STony Lindgren no_dma: 992b085c612SPeter Ujfalusi return ret; 993ca632f55SGrant Likely } 994ca632f55SGrant Likely 995ca632f55SGrant Likely static int omap2_mcspi_setup(struct spi_device *spi) 996ca632f55SGrant Likely { 997ca632f55SGrant Likely int ret; 9981bd897f8SBenoit Cousson struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 9991bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1000ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 1001ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 1002ca632f55SGrant Likely 1003ca632f55SGrant Likely mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1004ca632f55SGrant Likely 1005ca632f55SGrant Likely if (!cs) { 100610aa5a35SRussell King cs = kzalloc(sizeof *cs, GFP_KERNEL); 1007ca632f55SGrant Likely if (!cs) 1008ca632f55SGrant Likely return -ENOMEM; 1009ca632f55SGrant Likely cs->base = mcspi->base + spi->chip_select * 0x14; 1010ca632f55SGrant Likely cs->phys = mcspi->phys + spi->chip_select * 0x14; 101197ca0d6cSMark A. Greer cs->mode = 0; 1012ca632f55SGrant Likely cs->chconf0 = 0; 1013faee9b05SStefan Sørensen cs->chctrl0 = 0; 1014ca632f55SGrant Likely spi->controller_state = cs; 1015ca632f55SGrant Likely /* Link this to context save list */ 10161bd897f8SBenoit Cousson list_add_tail(&cs->node, &ctx->cs); 1017ca632f55SGrant Likely 1018bc7f9bbcSMichael Welling if (gpio_is_valid(spi->cs_gpio)) { 1019c4339ac7SMichael Welling ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); 1020c4339ac7SMichael Welling if (ret) { 1021c4339ac7SMichael Welling dev_err(&spi->dev, "failed to request gpio\n"); 1022c4339ac7SMichael Welling return ret; 1023c4339ac7SMichael Welling } 10242f538c01SMichael Welling gpio_direction_output(spi->cs_gpio, 10252f538c01SMichael Welling !(spi->mode & SPI_CS_HIGH)); 10262f538c01SMichael Welling } 10272f538c01SMichael Welling } 10282f538c01SMichael Welling 10292f538c01SMichael Welling if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { 10302f538c01SMichael Welling ret = omap2_mcspi_request_dma(spi); 1031b085c612SPeter Ujfalusi if (ret) 1032b085c612SPeter Ujfalusi dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n", 1033b085c612SPeter Ujfalusi ret); 1034bc7f9bbcSMichael Welling } 1035bc7f9bbcSMichael Welling 1036034d3dc9SShubhrajyoti D ret = pm_runtime_get_sync(mcspi->dev); 10375a686b2cSTony Lindgren if (ret < 0) { 10385a686b2cSTony Lindgren pm_runtime_put_noidle(mcspi->dev); 10395a686b2cSTony Lindgren 1040ca632f55SGrant Likely return ret; 10415a686b2cSTony Lindgren } 1042ca632f55SGrant Likely 1043ca632f55SGrant Likely ret = omap2_mcspi_setup_transfer(spi, NULL); 1044034d3dc9SShubhrajyoti D pm_runtime_mark_last_busy(mcspi->dev); 1045034d3dc9SShubhrajyoti D pm_runtime_put_autosuspend(mcspi->dev); 1046ca632f55SGrant Likely 1047ca632f55SGrant Likely return ret; 1048ca632f55SGrant Likely } 1049ca632f55SGrant Likely 1050ca632f55SGrant Likely static void omap2_mcspi_cleanup(struct spi_device *spi) 1051ca632f55SGrant Likely { 1052ca632f55SGrant Likely struct omap2_mcspi *mcspi; 1053ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 1054ca632f55SGrant Likely struct omap2_mcspi_cs *cs; 1055ca632f55SGrant Likely 1056ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 1057ca632f55SGrant Likely 1058ca632f55SGrant Likely if (spi->controller_state) { 1059ca632f55SGrant Likely /* Unlink controller state from context save list */ 1060ca632f55SGrant Likely cs = spi->controller_state; 1061ca632f55SGrant Likely list_del(&cs->node); 1062ca632f55SGrant Likely 106310aa5a35SRussell King kfree(cs); 1064ca632f55SGrant Likely } 1065ca632f55SGrant Likely 1066ca632f55SGrant Likely if (spi->chip_select < spi->master->num_chipselect) { 1067ca632f55SGrant Likely mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 1068ca632f55SGrant Likely 106953741ed8SRussell King if (mcspi_dma->dma_rx) { 107053741ed8SRussell King dma_release_channel(mcspi_dma->dma_rx); 107153741ed8SRussell King mcspi_dma->dma_rx = NULL; 1072ca632f55SGrant Likely } 107353741ed8SRussell King if (mcspi_dma->dma_tx) { 107453741ed8SRussell King dma_release_channel(mcspi_dma->dma_tx); 107553741ed8SRussell King mcspi_dma->dma_tx = NULL; 1076ca632f55SGrant Likely } 1077ca632f55SGrant Likely } 1078bc7f9bbcSMichael Welling 1079bc7f9bbcSMichael Welling if (gpio_is_valid(spi->cs_gpio)) 1080bc7f9bbcSMichael Welling gpio_free(spi->cs_gpio); 1081ca632f55SGrant Likely } 1082ca632f55SGrant Likely 10830ba1870fSFranklin S Cooper Jr static int omap2_mcspi_transfer_one(struct spi_master *master, 10840ba1870fSFranklin S Cooper Jr struct spi_device *spi, 10850ba1870fSFranklin S Cooper Jr struct spi_transfer *t) 1086ca632f55SGrant Likely { 1087ca632f55SGrant Likely 1088ca632f55SGrant Likely /* We only enable one channel at a time -- the one whose message is 10895fda88f5SShubhrajyoti D * -- although this controller would gladly 1090ca632f55SGrant Likely * arbitrate among multiple channels. This corresponds to "single 1091ca632f55SGrant Likely * channel" master mode. As a side effect, we need to manage the 1092ca632f55SGrant Likely * chipselect with the FORCE bit ... CS != channel enable. 1093ca632f55SGrant Likely */ 10945fda88f5SShubhrajyoti D 10950ba1870fSFranklin S Cooper Jr struct omap2_mcspi *mcspi; 1096ddc5cdf1STony Lindgren struct omap2_mcspi_dma *mcspi_dma; 1097ca632f55SGrant Likely struct omap2_mcspi_cs *cs; 1098ca632f55SGrant Likely struct omap2_mcspi_device_config *cd; 1099ca632f55SGrant Likely int par_override = 0; 1100ca632f55SGrant Likely int status = 0; 1101ca632f55SGrant Likely u32 chconf; 1102ca632f55SGrant Likely 11030ba1870fSFranklin S Cooper Jr mcspi = spi_master_get_devdata(master); 1104ddc5cdf1STony Lindgren mcspi_dma = mcspi->dma_channels + spi->chip_select; 1105ca632f55SGrant Likely cs = spi->controller_state; 1106ca632f55SGrant Likely cd = spi->controller_data; 1107ca632f55SGrant Likely 110897ca0d6cSMark A. Greer /* 110997ca0d6cSMark A. Greer * The slave driver could have changed spi->mode in which case 111097ca0d6cSMark A. Greer * it will be different from cs->mode (the current hardware setup). 111197ca0d6cSMark A. Greer * If so, set par_override (even though its not a parity issue) so 111297ca0d6cSMark A. Greer * omap2_mcspi_setup_transfer will be called to configure the hardware 111397ca0d6cSMark A. Greer * with the correct mode on the first iteration of the loop below. 111497ca0d6cSMark A. Greer */ 111597ca0d6cSMark A. Greer if (spi->mode != cs->mode) 111697ca0d6cSMark A. Greer par_override = 1; 111797ca0d6cSMark A. Greer 1118d33f473dSIllia Smyrnov omap2_mcspi_set_enable(spi, 0); 1119b28cb941SMichael Welling 1120a06b430fSMichael Welling if (gpio_is_valid(spi->cs_gpio)) 1121a06b430fSMichael Welling omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); 1122a06b430fSMichael Welling 11232bd16e3eSStefan Sørensen if (par_override || 11242bd16e3eSStefan Sørensen (t->speed_hz != spi->max_speed_hz) || 11252bd16e3eSStefan Sørensen (t->bits_per_word != spi->bits_per_word)) { 1126ca632f55SGrant Likely par_override = 1; 1127ca632f55SGrant Likely status = omap2_mcspi_setup_transfer(spi, t); 1128ca632f55SGrant Likely if (status < 0) 1129b28cb941SMichael Welling goto out; 11302bd16e3eSStefan Sørensen if (t->speed_hz == spi->max_speed_hz && 11312bd16e3eSStefan Sørensen t->bits_per_word == spi->bits_per_word) 1132ca632f55SGrant Likely par_override = 0; 1133ca632f55SGrant Likely } 11345cbc7ca9SMatthias Brugger if (cd && cd->cs_per_word) { 11355cbc7ca9SMatthias Brugger chconf = mcspi->ctx.modulctrl; 11365cbc7ca9SMatthias Brugger chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; 11375cbc7ca9SMatthias Brugger mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 11385cbc7ca9SMatthias Brugger mcspi->ctx.modulctrl = 11395cbc7ca9SMatthias Brugger mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 11405cbc7ca9SMatthias Brugger } 11415cbc7ca9SMatthias Brugger 1142ca632f55SGrant Likely chconf = mcspi_cached_chconf0(spi); 1143ca632f55SGrant Likely chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; 1144ca632f55SGrant Likely chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; 1145ca632f55SGrant Likely 1146ca632f55SGrant Likely if (t->tx_buf == NULL) 1147ca632f55SGrant Likely chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; 1148ca632f55SGrant Likely else if (t->rx_buf == NULL) 1149ca632f55SGrant Likely chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; 1150ca632f55SGrant Likely 1151ca632f55SGrant Likely if (cd && cd->turbo_mode && t->tx_buf == NULL) { 1152ca632f55SGrant Likely /* Turbo mode is for more than one word */ 1153ca632f55SGrant Likely if (t->len > ((cs->word_len + 7) >> 3)) 1154ca632f55SGrant Likely chconf |= OMAP2_MCSPI_CHCONF_TURBO; 1155ca632f55SGrant Likely } 1156ca632f55SGrant Likely 1157ca632f55SGrant Likely mcspi_write_chconf0(spi, chconf); 1158ca632f55SGrant Likely 1159ca632f55SGrant Likely if (t->len) { 1160ca632f55SGrant Likely unsigned count; 1161ca632f55SGrant Likely 1162d33f473dSIllia Smyrnov if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 11630ba1870fSFranklin S Cooper Jr master->cur_msg_mapped && 11640ba1870fSFranklin S Cooper Jr master->can_dma(master, spi, t)) 1165d33f473dSIllia Smyrnov omap2_mcspi_set_fifo(spi, t, 1); 1166d33f473dSIllia Smyrnov 1167d33f473dSIllia Smyrnov omap2_mcspi_set_enable(spi, 1); 1168d33f473dSIllia Smyrnov 1169ca632f55SGrant Likely /* RX_ONLY mode needs dummy data in TX reg */ 1170ca632f55SGrant Likely if (t->tx_buf == NULL) 117121b2ce5eSVictor Kamensky writel_relaxed(0, cs->base 1172ca632f55SGrant Likely + OMAP2_MCSPI_TX0); 1173ca632f55SGrant Likely 1174ddc5cdf1STony Lindgren if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && 11750ba1870fSFranklin S Cooper Jr master->cur_msg_mapped && 11760ba1870fSFranklin S Cooper Jr master->can_dma(master, spi, t)) 1177ca632f55SGrant Likely count = omap2_mcspi_txrx_dma(spi, t); 1178ca632f55SGrant Likely else 1179ca632f55SGrant Likely count = omap2_mcspi_txrx_pio(spi, t); 1180ca632f55SGrant Likely 1181ca632f55SGrant Likely if (count != t->len) { 1182ca632f55SGrant Likely status = -EIO; 1183b28cb941SMichael Welling goto out; 1184ca632f55SGrant Likely } 1185ca632f55SGrant Likely } 1186ca632f55SGrant Likely 1187d33f473dSIllia Smyrnov omap2_mcspi_set_enable(spi, 0); 1188d33f473dSIllia Smyrnov 1189d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0) 1190d33f473dSIllia Smyrnov omap2_mcspi_set_fifo(spi, t, 0); 1191b28cb941SMichael Welling 1192b28cb941SMichael Welling out: 1193ca632f55SGrant Likely /* Restore defaults if they were overriden */ 1194ca632f55SGrant Likely if (par_override) { 1195ca632f55SGrant Likely par_override = 0; 1196ca632f55SGrant Likely status = omap2_mcspi_setup_transfer(spi, NULL); 1197ca632f55SGrant Likely } 1198ca632f55SGrant Likely 11995cbc7ca9SMatthias Brugger if (cd && cd->cs_per_word) { 12005cbc7ca9SMatthias Brugger chconf = mcspi->ctx.modulctrl; 12015cbc7ca9SMatthias Brugger chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; 12025cbc7ca9SMatthias Brugger mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); 12035cbc7ca9SMatthias Brugger mcspi->ctx.modulctrl = 12045cbc7ca9SMatthias Brugger mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); 12055cbc7ca9SMatthias Brugger } 12065cbc7ca9SMatthias Brugger 1207ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 1208ca632f55SGrant Likely 1209a06b430fSMichael Welling if (gpio_is_valid(spi->cs_gpio)) 1210a06b430fSMichael Welling omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); 1211a06b430fSMichael Welling 1212d33f473dSIllia Smyrnov if (mcspi->fifo_depth > 0 && t) 1213d33f473dSIllia Smyrnov omap2_mcspi_set_fifo(spi, t, 0); 1214ca632f55SGrant Likely 1215b28cb941SMichael Welling return status; 1216ca632f55SGrant Likely } 1217ca632f55SGrant Likely 1218468a3208SNeil Armstrong static int omap2_mcspi_prepare_message(struct spi_master *master, 1219468a3208SNeil Armstrong struct spi_message *msg) 1220468a3208SNeil Armstrong { 1221468a3208SNeil Armstrong struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1222468a3208SNeil Armstrong struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1223468a3208SNeil Armstrong struct omap2_mcspi_cs *cs; 1224468a3208SNeil Armstrong 1225468a3208SNeil Armstrong /* Only a single channel can have the FORCE bit enabled 1226468a3208SNeil Armstrong * in its chconf0 register. 1227468a3208SNeil Armstrong * Scan all channels and disable them except the current one. 1228468a3208SNeil Armstrong * A FORCE can remain from a last transfer having cs_change enabled 1229468a3208SNeil Armstrong */ 1230468a3208SNeil Armstrong list_for_each_entry(cs, &ctx->cs, node) { 1231468a3208SNeil Armstrong if (msg->spi->controller_state == cs) 1232468a3208SNeil Armstrong continue; 1233468a3208SNeil Armstrong 1234468a3208SNeil Armstrong if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { 1235468a3208SNeil Armstrong cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 1236468a3208SNeil Armstrong writel_relaxed(cs->chconf0, 1237468a3208SNeil Armstrong cs->base + OMAP2_MCSPI_CHCONF0); 1238468a3208SNeil Armstrong readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); 1239468a3208SNeil Armstrong } 1240468a3208SNeil Armstrong } 1241468a3208SNeil Armstrong 1242468a3208SNeil Armstrong return 0; 1243468a3208SNeil Armstrong } 1244468a3208SNeil Armstrong 12450ba1870fSFranklin S Cooper Jr static bool omap2_mcspi_can_dma(struct spi_master *master, 12460ba1870fSFranklin S Cooper Jr struct spi_device *spi, 12470ba1870fSFranklin S Cooper Jr struct spi_transfer *xfer) 1248ca632f55SGrant Likely { 12490ba1870fSFranklin S Cooper Jr return (xfer->len >= DMA_MIN_BYTES); 1250ca632f55SGrant Likely } 1251ca632f55SGrant Likely 1252fd4a319bSGrant Likely static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) 1253ca632f55SGrant Likely { 1254ca632f55SGrant Likely struct spi_master *master = mcspi->master; 12551bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1256ca632f55SGrant Likely int ret = 0; 1257ca632f55SGrant Likely 1258034d3dc9SShubhrajyoti D ret = pm_runtime_get_sync(mcspi->dev); 12595a686b2cSTony Lindgren if (ret < 0) { 12605a686b2cSTony Lindgren pm_runtime_put_noidle(mcspi->dev); 12615a686b2cSTony Lindgren 1262ca632f55SGrant Likely return ret; 12635a686b2cSTony Lindgren } 1264ca632f55SGrant Likely 126539f8052dSShubhrajyoti D mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, 126639f8052dSShubhrajyoti D OMAP2_MCSPI_WAKEUPENABLE_WKEN); 126739f8052dSShubhrajyoti D ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; 1268ca632f55SGrant Likely 1269ca632f55SGrant Likely omap2_mcspi_set_master_mode(master); 1270034d3dc9SShubhrajyoti D pm_runtime_mark_last_busy(mcspi->dev); 1271034d3dc9SShubhrajyoti D pm_runtime_put_autosuspend(mcspi->dev); 1272ca632f55SGrant Likely return 0; 1273ca632f55SGrant Likely } 1274ca632f55SGrant Likely 127552e9a5bbSTony Lindgren /* 127652e9a5bbSTony Lindgren * When SPI wake up from off-mode, CS is in activate state. If it was in 127752e9a5bbSTony Lindgren * inactive state when driver was suspend, then force it to inactive state at 127852e9a5bbSTony Lindgren * wake up. 127952e9a5bbSTony Lindgren */ 1280ca632f55SGrant Likely static int omap_mcspi_runtime_resume(struct device *dev) 1281ca632f55SGrant Likely { 128252e9a5bbSTony Lindgren struct spi_master *master = dev_get_drvdata(dev); 128352e9a5bbSTony Lindgren struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 128452e9a5bbSTony Lindgren struct omap2_mcspi_regs *ctx = &mcspi->ctx; 128552e9a5bbSTony Lindgren struct omap2_mcspi_cs *cs; 1286ca632f55SGrant Likely 128752e9a5bbSTony Lindgren /* McSPI: context restore */ 128852e9a5bbSTony Lindgren mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); 128952e9a5bbSTony Lindgren mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); 129052e9a5bbSTony Lindgren 129152e9a5bbSTony Lindgren list_for_each_entry(cs, &ctx->cs, node) { 129252e9a5bbSTony Lindgren /* 129352e9a5bbSTony Lindgren * We need to toggle CS state for OMAP take this 129452e9a5bbSTony Lindgren * change in account. 129552e9a5bbSTony Lindgren */ 129652e9a5bbSTony Lindgren if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { 129752e9a5bbSTony Lindgren cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; 129852e9a5bbSTony Lindgren writel_relaxed(cs->chconf0, 129952e9a5bbSTony Lindgren cs->base + OMAP2_MCSPI_CHCONF0); 130052e9a5bbSTony Lindgren cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 130152e9a5bbSTony Lindgren writel_relaxed(cs->chconf0, 130252e9a5bbSTony Lindgren cs->base + OMAP2_MCSPI_CHCONF0); 130352e9a5bbSTony Lindgren } else { 130452e9a5bbSTony Lindgren writel_relaxed(cs->chconf0, 130552e9a5bbSTony Lindgren cs->base + OMAP2_MCSPI_CHCONF0); 130652e9a5bbSTony Lindgren } 130752e9a5bbSTony Lindgren } 1308ca632f55SGrant Likely 1309ca632f55SGrant Likely return 0; 1310ca632f55SGrant Likely } 1311ca632f55SGrant Likely 1312d5a80031SBenoit Cousson static struct omap2_mcspi_platform_config omap2_pdata = { 1313d5a80031SBenoit Cousson .regs_offset = 0, 1314d5a80031SBenoit Cousson }; 1315d5a80031SBenoit Cousson 1316d5a80031SBenoit Cousson static struct omap2_mcspi_platform_config omap4_pdata = { 1317d5a80031SBenoit Cousson .regs_offset = OMAP4_MCSPI_REG_OFFSET, 1318d5a80031SBenoit Cousson }; 1319d5a80031SBenoit Cousson 1320d5a80031SBenoit Cousson static const struct of_device_id omap_mcspi_of_match[] = { 1321d5a80031SBenoit Cousson { 1322d5a80031SBenoit Cousson .compatible = "ti,omap2-mcspi", 1323d5a80031SBenoit Cousson .data = &omap2_pdata, 1324d5a80031SBenoit Cousson }, 1325d5a80031SBenoit Cousson { 1326d5a80031SBenoit Cousson .compatible = "ti,omap4-mcspi", 1327d5a80031SBenoit Cousson .data = &omap4_pdata, 1328d5a80031SBenoit Cousson }, 1329d5a80031SBenoit Cousson { }, 1330d5a80031SBenoit Cousson }; 1331d5a80031SBenoit Cousson MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); 1332ca632f55SGrant Likely 1333fd4a319bSGrant Likely static int omap2_mcspi_probe(struct platform_device *pdev) 1334ca632f55SGrant Likely { 1335ca632f55SGrant Likely struct spi_master *master; 133683a01e72SUwe Kleine-König const struct omap2_mcspi_platform_config *pdata; 1337ca632f55SGrant Likely struct omap2_mcspi *mcspi; 1338ca632f55SGrant Likely struct resource *r; 1339ca632f55SGrant Likely int status = 0, i; 1340d5a80031SBenoit Cousson u32 regs_offset = 0; 1341d5a80031SBenoit Cousson struct device_node *node = pdev->dev.of_node; 1342d5a80031SBenoit Cousson const struct of_device_id *match; 1343ca632f55SGrant Likely 1344ca632f55SGrant Likely master = spi_alloc_master(&pdev->dev, sizeof *mcspi); 1345ca632f55SGrant Likely if (master == NULL) { 1346ca632f55SGrant Likely dev_dbg(&pdev->dev, "master allocation failed\n"); 1347ca632f55SGrant Likely return -ENOMEM; 1348ca632f55SGrant Likely } 1349ca632f55SGrant Likely 1350ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 1351ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 135224778be2SStephen Warren master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1353ca632f55SGrant Likely master->setup = omap2_mcspi_setup; 1354f0278a1aSMark Brown master->auto_runtime_pm = true; 1355468a3208SNeil Armstrong master->prepare_message = omap2_mcspi_prepare_message; 13560ba1870fSFranklin S Cooper Jr master->can_dma = omap2_mcspi_can_dma; 1357b28cb941SMichael Welling master->transfer_one = omap2_mcspi_transfer_one; 1358ddcad7e9SMichael Welling master->set_cs = omap2_mcspi_set_cs; 1359ca632f55SGrant Likely master->cleanup = omap2_mcspi_cleanup; 1360d5a80031SBenoit Cousson master->dev.of_node = node; 1361aca0924bSAxel Lin master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; 1362aca0924bSAxel Lin master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; 1363d5a80031SBenoit Cousson 136424b5a82cSJingoo Han platform_set_drvdata(pdev, master); 13650384e90bSDaniel Mack 13660384e90bSDaniel Mack mcspi = spi_master_get_devdata(master); 13670384e90bSDaniel Mack mcspi->master = master; 13680384e90bSDaniel Mack 1369d5a80031SBenoit Cousson match = of_match_device(omap_mcspi_of_match, &pdev->dev); 1370d5a80031SBenoit Cousson if (match) { 1371d5a80031SBenoit Cousson u32 num_cs = 1; /* default number of chipselect */ 1372d5a80031SBenoit Cousson pdata = match->data; 1373d5a80031SBenoit Cousson 1374d5a80031SBenoit Cousson of_property_read_u32(node, "ti,spi-num-cs", &num_cs); 1375d5a80031SBenoit Cousson master->num_chipselect = num_cs; 13762cd45179SDaniel Mack if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) 13772cd45179SDaniel Mack mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; 1378d5a80031SBenoit Cousson } else { 13798074cf06SJingoo Han pdata = dev_get_platdata(&pdev->dev); 1380ca632f55SGrant Likely master->num_chipselect = pdata->num_cs; 13810384e90bSDaniel Mack mcspi->pin_dir = pdata->pin_dir; 1382d5a80031SBenoit Cousson } 1383d5a80031SBenoit Cousson regs_offset = pdata->regs_offset; 1384ca632f55SGrant Likely 1385ca632f55SGrant Likely r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1386b0ee5605SThierry Reding mcspi->base = devm_ioremap_resource(&pdev->dev, r); 1387b0ee5605SThierry Reding if (IS_ERR(mcspi->base)) { 1388b0ee5605SThierry Reding status = PTR_ERR(mcspi->base); 13891a77b127SShubhrajyoti D goto free_master; 1390ca632f55SGrant Likely } 1391af9e53feSVikram N mcspi->phys = r->start + regs_offset; 1392af9e53feSVikram N mcspi->base += regs_offset; 1393ca632f55SGrant Likely 1394ca632f55SGrant Likely mcspi->dev = &pdev->dev; 1395ca632f55SGrant Likely 13961bd897f8SBenoit Cousson INIT_LIST_HEAD(&mcspi->ctx.cs); 1397ca632f55SGrant Likely 1398a6f936dbSAxel Lin mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, 1399ca632f55SGrant Likely sizeof(struct omap2_mcspi_dma), 1400ca632f55SGrant Likely GFP_KERNEL); 1401a6f936dbSAxel Lin if (mcspi->dma_channels == NULL) { 1402a6f936dbSAxel Lin status = -ENOMEM; 14031a77b127SShubhrajyoti D goto free_master; 1404a6f936dbSAxel Lin } 1405ca632f55SGrant Likely 1406ca632f55SGrant Likely for (i = 0; i < master->num_chipselect; i++) { 1407b085c612SPeter Ujfalusi sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); 1408b085c612SPeter Ujfalusi sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); 1409ca632f55SGrant Likely } 1410ca632f55SGrant Likely 141127b5284cSShubhrajyoti D pm_runtime_use_autosuspend(&pdev->dev); 141227b5284cSShubhrajyoti D pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1413ca632f55SGrant Likely pm_runtime_enable(&pdev->dev); 1414ca632f55SGrant Likely 1415142e07beSWei Yongjun status = omap2_mcspi_master_setup(mcspi); 1416142e07beSWei Yongjun if (status < 0) 141739f1b565SShubhrajyoti D goto disable_pm; 1418ca632f55SGrant Likely 1419b95e02b7SJingoo Han status = devm_spi_register_master(&pdev->dev, master); 1420ca632f55SGrant Likely if (status < 0) 142137a2d84aSShubhrajyoti D goto disable_pm; 1422ca632f55SGrant Likely 1423ca632f55SGrant Likely return status; 1424ca632f55SGrant Likely 142539f1b565SShubhrajyoti D disable_pm: 14260e6f357aSTony Lindgren pm_runtime_dont_use_autosuspend(&pdev->dev); 14270e6f357aSTony Lindgren pm_runtime_put_sync(&pdev->dev); 1428751c925cSShubhrajyoti D pm_runtime_disable(&pdev->dev); 142939f1b565SShubhrajyoti D free_master: 143037a2d84aSShubhrajyoti D spi_master_put(master); 1431ca632f55SGrant Likely return status; 1432ca632f55SGrant Likely } 1433ca632f55SGrant Likely 1434fd4a319bSGrant Likely static int omap2_mcspi_remove(struct platform_device *pdev) 1435ca632f55SGrant Likely { 1436a6f936dbSAxel Lin struct spi_master *master = platform_get_drvdata(pdev); 1437a6f936dbSAxel Lin struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 1438ca632f55SGrant Likely 14390e6f357aSTony Lindgren pm_runtime_dont_use_autosuspend(mcspi->dev); 1440a93a2029SShubhrajyoti D pm_runtime_put_sync(mcspi->dev); 1441751c925cSShubhrajyoti D pm_runtime_disable(&pdev->dev); 1442ca632f55SGrant Likely 1443ca632f55SGrant Likely return 0; 1444ca632f55SGrant Likely } 1445ca632f55SGrant Likely 1446ca632f55SGrant Likely /* work with hotplug and coldplug */ 1447ca632f55SGrant Likely MODULE_ALIAS("platform:omap2_mcspi"); 1448ca632f55SGrant Likely 1449ca632f55SGrant Likely #ifdef CONFIG_SUSPEND 14505a686b2cSTony Lindgren static int omap2_mcspi_suspend_noirq(struct device *dev) 1451ca632f55SGrant Likely { 1452beca3655SPascal Huerst return pinctrl_pm_select_sleep_state(dev); 1453beca3655SPascal Huerst } 1454beca3655SPascal Huerst 14555a686b2cSTony Lindgren static int omap2_mcspi_resume_noirq(struct device *dev) 14565a686b2cSTony Lindgren { 14575a686b2cSTony Lindgren struct spi_master *master = dev_get_drvdata(dev); 14585a686b2cSTony Lindgren struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 14595a686b2cSTony Lindgren int error; 14605a686b2cSTony Lindgren 14615a686b2cSTony Lindgren error = pinctrl_pm_select_default_state(dev); 14625a686b2cSTony Lindgren if (error) 14635a686b2cSTony Lindgren dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", 14645a686b2cSTony Lindgren __func__, error); 14655a686b2cSTony Lindgren 14665a686b2cSTony Lindgren return 0; 14675a686b2cSTony Lindgren } 14685a686b2cSTony Lindgren 1469ca632f55SGrant Likely #else 14705a686b2cSTony Lindgren #define omap2_mcspi_suspend_noirq NULL 14715a686b2cSTony Lindgren #define omap2_mcspi_resume_noirq NULL 1472ca632f55SGrant Likely #endif 1473ca632f55SGrant Likely 1474ca632f55SGrant Likely static const struct dev_pm_ops omap2_mcspi_pm_ops = { 14755a686b2cSTony Lindgren .suspend_noirq = omap2_mcspi_suspend_noirq, 14765a686b2cSTony Lindgren .resume_noirq = omap2_mcspi_resume_noirq, 1477ca632f55SGrant Likely .runtime_resume = omap_mcspi_runtime_resume, 1478ca632f55SGrant Likely }; 1479ca632f55SGrant Likely 1480ca632f55SGrant Likely static struct platform_driver omap2_mcspi_driver = { 1481ca632f55SGrant Likely .driver = { 1482ca632f55SGrant Likely .name = "omap2_mcspi", 1483d5a80031SBenoit Cousson .pm = &omap2_mcspi_pm_ops, 1484d5a80031SBenoit Cousson .of_match_table = omap_mcspi_of_match, 1485ca632f55SGrant Likely }, 14867d6b6d83SFelipe Balbi .probe = omap2_mcspi_probe, 1487fd4a319bSGrant Likely .remove = omap2_mcspi_remove, 1488ca632f55SGrant Likely }; 1489ca632f55SGrant Likely 14909fdca9dfSFelipe Balbi module_platform_driver(omap2_mcspi_driver); 1491ca632f55SGrant Likely MODULE_LICENSE("GPL"); 1492