1ca632f55SGrant Likely /* 2ca632f55SGrant Likely * OMAP2 McSPI controller driver 3ca632f55SGrant Likely * 4ca632f55SGrant Likely * Copyright (C) 2005, 2006 Nokia Corporation 5ca632f55SGrant Likely * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and 6ca632f55SGrant Likely * Juha Yrj�l� <juha.yrjola@nokia.com> 7ca632f55SGrant Likely * 8ca632f55SGrant Likely * This program is free software; you can redistribute it and/or modify 9ca632f55SGrant Likely * it under the terms of the GNU General Public License as published by 10ca632f55SGrant Likely * the Free Software Foundation; either version 2 of the License, or 11ca632f55SGrant Likely * (at your option) any later version. 12ca632f55SGrant Likely * 13ca632f55SGrant Likely * This program is distributed in the hope that it will be useful, 14ca632f55SGrant Likely * but WITHOUT ANY WARRANTY; without even the implied warranty of 15ca632f55SGrant Likely * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16ca632f55SGrant Likely * GNU General Public License for more details. 17ca632f55SGrant Likely * 18ca632f55SGrant Likely * You should have received a copy of the GNU General Public License 19ca632f55SGrant Likely * along with this program; if not, write to the Free Software 20ca632f55SGrant Likely * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21ca632f55SGrant Likely * 22ca632f55SGrant Likely */ 23ca632f55SGrant Likely 24ca632f55SGrant Likely #include <linux/kernel.h> 25ca632f55SGrant Likely #include <linux/init.h> 26ca632f55SGrant Likely #include <linux/interrupt.h> 27ca632f55SGrant Likely #include <linux/module.h> 28ca632f55SGrant Likely #include <linux/device.h> 29ca632f55SGrant Likely #include <linux/delay.h> 30ca632f55SGrant Likely #include <linux/dma-mapping.h> 3153741ed8SRussell King #include <linux/dmaengine.h> 3253741ed8SRussell King #include <linux/omap-dma.h> 33ca632f55SGrant Likely #include <linux/platform_device.h> 34ca632f55SGrant Likely #include <linux/err.h> 35ca632f55SGrant Likely #include <linux/clk.h> 36ca632f55SGrant Likely #include <linux/io.h> 37ca632f55SGrant Likely #include <linux/slab.h> 38ca632f55SGrant Likely #include <linux/pm_runtime.h> 39d5a80031SBenoit Cousson #include <linux/of.h> 40d5a80031SBenoit Cousson #include <linux/of_device.h> 41ec155afaSMatt Porter #include <linux/pinctrl/consumer.h> 42ec155afaSMatt Porter #include <linux/err.h> 43ca632f55SGrant Likely 44ca632f55SGrant Likely #include <linux/spi/spi.h> 45ca632f55SGrant Likely 462203747cSArnd Bergmann #include <linux/platform_data/spi-omap2-mcspi.h> 47ca632f55SGrant Likely 48ca632f55SGrant Likely #define OMAP2_MCSPI_MAX_FREQ 48000000 4927b5284cSShubhrajyoti D #define SPI_AUTOSUSPEND_TIMEOUT 2000 50ca632f55SGrant Likely 51ca632f55SGrant Likely #define OMAP2_MCSPI_REVISION 0x00 52ca632f55SGrant Likely #define OMAP2_MCSPI_SYSSTATUS 0x14 53ca632f55SGrant Likely #define OMAP2_MCSPI_IRQSTATUS 0x18 54ca632f55SGrant Likely #define OMAP2_MCSPI_IRQENABLE 0x1c 55ca632f55SGrant Likely #define OMAP2_MCSPI_WAKEUPENABLE 0x20 56ca632f55SGrant Likely #define OMAP2_MCSPI_SYST 0x24 57ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL 0x28 58ca632f55SGrant Likely 59ca632f55SGrant Likely /* per-channel banks, 0x14 bytes each, first is: */ 60ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF0 0x2c 61ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT0 0x30 62ca632f55SGrant Likely #define OMAP2_MCSPI_CHCTRL0 0x34 63ca632f55SGrant Likely #define OMAP2_MCSPI_TX0 0x38 64ca632f55SGrant Likely #define OMAP2_MCSPI_RX0 0x3c 65ca632f55SGrant Likely 66ca632f55SGrant Likely /* per-register bitmasks: */ 67ca632f55SGrant Likely 68ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) 69ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) 70ca632f55SGrant Likely #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) 71ca632f55SGrant Likely 72ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_PHA BIT(0) 73ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_POL BIT(1) 74ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) 75ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) 76ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) 77ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) 78ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) 79ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) 80ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) 81ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) 82ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) 83ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) 84ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_IS BIT(18) 85ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) 86ca632f55SGrant Likely #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) 87ca632f55SGrant Likely 88ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) 89ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) 90ca632f55SGrant Likely #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) 91ca632f55SGrant Likely 92ca632f55SGrant Likely #define OMAP2_MCSPI_CHCTRL_EN BIT(0) 93ca632f55SGrant Likely 94ca632f55SGrant Likely #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) 95ca632f55SGrant Likely 96ca632f55SGrant Likely /* We have 2 DMA channels per CS, one for RX and one for TX */ 97ca632f55SGrant Likely struct omap2_mcspi_dma { 9853741ed8SRussell King struct dma_chan *dma_tx; 9953741ed8SRussell King struct dma_chan *dma_rx; 100ca632f55SGrant Likely 101ca632f55SGrant Likely int dma_tx_sync_dev; 102ca632f55SGrant Likely int dma_rx_sync_dev; 103ca632f55SGrant Likely 104ca632f55SGrant Likely struct completion dma_tx_completion; 105ca632f55SGrant Likely struct completion dma_rx_completion; 106ca632f55SGrant Likely }; 107ca632f55SGrant Likely 108ca632f55SGrant Likely /* use PIO for small transfers, avoiding DMA setup/teardown overhead and 109ca632f55SGrant Likely * cache operations; better heuristics consider wordsize and bitrate. 110ca632f55SGrant Likely */ 111ca632f55SGrant Likely #define DMA_MIN_BYTES 160 112ca632f55SGrant Likely 113ca632f55SGrant Likely 1141bd897f8SBenoit Cousson /* 1151bd897f8SBenoit Cousson * Used for context save and restore, structure members to be updated whenever 1161bd897f8SBenoit Cousson * corresponding registers are modified. 1171bd897f8SBenoit Cousson */ 1181bd897f8SBenoit Cousson struct omap2_mcspi_regs { 1191bd897f8SBenoit Cousson u32 modulctrl; 1201bd897f8SBenoit Cousson u32 wakeupenable; 1211bd897f8SBenoit Cousson struct list_head cs; 1221bd897f8SBenoit Cousson }; 1231bd897f8SBenoit Cousson 124ca632f55SGrant Likely struct omap2_mcspi { 125ca632f55SGrant Likely struct spi_master *master; 126ca632f55SGrant Likely /* Virtual base address of the controller */ 127ca632f55SGrant Likely void __iomem *base; 128ca632f55SGrant Likely unsigned long phys; 129ca632f55SGrant Likely /* SPI1 has 4 channels, while SPI2 has 2 */ 130ca632f55SGrant Likely struct omap2_mcspi_dma *dma_channels; 131ca632f55SGrant Likely struct device *dev; 1321bd897f8SBenoit Cousson struct omap2_mcspi_regs ctx; 133*0384e90bSDaniel Mack unsigned int pin_dir:1; 134ca632f55SGrant Likely }; 135ca632f55SGrant Likely 136ca632f55SGrant Likely struct omap2_mcspi_cs { 137ca632f55SGrant Likely void __iomem *base; 138ca632f55SGrant Likely unsigned long phys; 139ca632f55SGrant Likely int word_len; 140ca632f55SGrant Likely struct list_head node; 141ca632f55SGrant Likely /* Context save and restore shadow register */ 142ca632f55SGrant Likely u32 chconf0; 143ca632f55SGrant Likely }; 144ca632f55SGrant Likely 145ca632f55SGrant Likely static inline void mcspi_write_reg(struct spi_master *master, 146ca632f55SGrant Likely int idx, u32 val) 147ca632f55SGrant Likely { 148ca632f55SGrant Likely struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 149ca632f55SGrant Likely 150ca632f55SGrant Likely __raw_writel(val, mcspi->base + idx); 151ca632f55SGrant Likely } 152ca632f55SGrant Likely 153ca632f55SGrant Likely static inline u32 mcspi_read_reg(struct spi_master *master, int idx) 154ca632f55SGrant Likely { 155ca632f55SGrant Likely struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 156ca632f55SGrant Likely 157ca632f55SGrant Likely return __raw_readl(mcspi->base + idx); 158ca632f55SGrant Likely } 159ca632f55SGrant Likely 160ca632f55SGrant Likely static inline void mcspi_write_cs_reg(const struct spi_device *spi, 161ca632f55SGrant Likely int idx, u32 val) 162ca632f55SGrant Likely { 163ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 164ca632f55SGrant Likely 165ca632f55SGrant Likely __raw_writel(val, cs->base + idx); 166ca632f55SGrant Likely } 167ca632f55SGrant Likely 168ca632f55SGrant Likely static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) 169ca632f55SGrant Likely { 170ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 171ca632f55SGrant Likely 172ca632f55SGrant Likely return __raw_readl(cs->base + idx); 173ca632f55SGrant Likely } 174ca632f55SGrant Likely 175ca632f55SGrant Likely static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) 176ca632f55SGrant Likely { 177ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 178ca632f55SGrant Likely 179ca632f55SGrant Likely return cs->chconf0; 180ca632f55SGrant Likely } 181ca632f55SGrant Likely 182ca632f55SGrant Likely static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) 183ca632f55SGrant Likely { 184ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 185ca632f55SGrant Likely 186ca632f55SGrant Likely cs->chconf0 = val; 187ca632f55SGrant Likely mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); 188ca632f55SGrant Likely mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); 189ca632f55SGrant Likely } 190ca632f55SGrant Likely 191ca632f55SGrant Likely static void omap2_mcspi_set_dma_req(const struct spi_device *spi, 192ca632f55SGrant Likely int is_read, int enable) 193ca632f55SGrant Likely { 194ca632f55SGrant Likely u32 l, rw; 195ca632f55SGrant Likely 196ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 197ca632f55SGrant Likely 198ca632f55SGrant Likely if (is_read) /* 1 is read, 0 write */ 199ca632f55SGrant Likely rw = OMAP2_MCSPI_CHCONF_DMAR; 200ca632f55SGrant Likely else 201ca632f55SGrant Likely rw = OMAP2_MCSPI_CHCONF_DMAW; 202ca632f55SGrant Likely 203af4e944dSShubhrajyoti D if (enable) 204af4e944dSShubhrajyoti D l |= rw; 205af4e944dSShubhrajyoti D else 206af4e944dSShubhrajyoti D l &= ~rw; 207af4e944dSShubhrajyoti D 208ca632f55SGrant Likely mcspi_write_chconf0(spi, l); 209ca632f55SGrant Likely } 210ca632f55SGrant Likely 211ca632f55SGrant Likely static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) 212ca632f55SGrant Likely { 213ca632f55SGrant Likely u32 l; 214ca632f55SGrant Likely 215ca632f55SGrant Likely l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; 216ca632f55SGrant Likely mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); 217ca632f55SGrant Likely /* Flash post-writes */ 218ca632f55SGrant Likely mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); 219ca632f55SGrant Likely } 220ca632f55SGrant Likely 221ca632f55SGrant Likely static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) 222ca632f55SGrant Likely { 223ca632f55SGrant Likely u32 l; 224ca632f55SGrant Likely 225ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 226af4e944dSShubhrajyoti D if (cs_active) 227af4e944dSShubhrajyoti D l |= OMAP2_MCSPI_CHCONF_FORCE; 228af4e944dSShubhrajyoti D else 229af4e944dSShubhrajyoti D l &= ~OMAP2_MCSPI_CHCONF_FORCE; 230af4e944dSShubhrajyoti D 231ca632f55SGrant Likely mcspi_write_chconf0(spi, l); 232ca632f55SGrant Likely } 233ca632f55SGrant Likely 234ca632f55SGrant Likely static void omap2_mcspi_set_master_mode(struct spi_master *master) 235ca632f55SGrant Likely { 2361bd897f8SBenoit Cousson struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 2371bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 238ca632f55SGrant Likely u32 l; 239ca632f55SGrant Likely 2401bd897f8SBenoit Cousson /* 2411bd897f8SBenoit Cousson * Setup when switching from (reset default) slave mode 242ca632f55SGrant Likely * to single-channel master mode 243ca632f55SGrant Likely */ 244ca632f55SGrant Likely l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); 245af4e944dSShubhrajyoti D l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); 246af4e944dSShubhrajyoti D l |= OMAP2_MCSPI_MODULCTRL_SINGLE; 247ca632f55SGrant Likely mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); 248ca632f55SGrant Likely 2491bd897f8SBenoit Cousson ctx->modulctrl = l; 250ca632f55SGrant Likely } 251ca632f55SGrant Likely 252ca632f55SGrant Likely static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) 253ca632f55SGrant Likely { 2541bd897f8SBenoit Cousson struct spi_master *spi_cntrl = mcspi->master; 2551bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 256ca632f55SGrant Likely struct omap2_mcspi_cs *cs; 257ca632f55SGrant Likely 258ca632f55SGrant Likely /* McSPI: context restore */ 2591bd897f8SBenoit Cousson mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); 2601bd897f8SBenoit Cousson mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); 261ca632f55SGrant Likely 2621bd897f8SBenoit Cousson list_for_each_entry(cs, &ctx->cs, node) 263ca632f55SGrant Likely __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 264ca632f55SGrant Likely } 265ca632f55SGrant Likely 2665fda88f5SShubhrajyoti D static int omap2_prepare_transfer(struct spi_master *master) 2675fda88f5SShubhrajyoti D { 2685fda88f5SShubhrajyoti D struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 2695fda88f5SShubhrajyoti D 2705fda88f5SShubhrajyoti D pm_runtime_get_sync(mcspi->dev); 2715fda88f5SShubhrajyoti D return 0; 2725fda88f5SShubhrajyoti D } 2735fda88f5SShubhrajyoti D 2745fda88f5SShubhrajyoti D static int omap2_unprepare_transfer(struct spi_master *master) 2755fda88f5SShubhrajyoti D { 2765fda88f5SShubhrajyoti D struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 2775fda88f5SShubhrajyoti D 2785fda88f5SShubhrajyoti D pm_runtime_mark_last_busy(mcspi->dev); 2795fda88f5SShubhrajyoti D pm_runtime_put_autosuspend(mcspi->dev); 2805fda88f5SShubhrajyoti D return 0; 2815fda88f5SShubhrajyoti D } 2825fda88f5SShubhrajyoti D 283ca632f55SGrant Likely static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) 284ca632f55SGrant Likely { 285ca632f55SGrant Likely unsigned long timeout; 286ca632f55SGrant Likely 287ca632f55SGrant Likely timeout = jiffies + msecs_to_jiffies(1000); 288ca632f55SGrant Likely while (!(__raw_readl(reg) & bit)) { 289ca632f55SGrant Likely if (time_after(jiffies, timeout)) 290ca632f55SGrant Likely return -1; 291ca632f55SGrant Likely cpu_relax(); 292ca632f55SGrant Likely } 293ca632f55SGrant Likely return 0; 294ca632f55SGrant Likely } 295ca632f55SGrant Likely 29653741ed8SRussell King static void omap2_mcspi_rx_callback(void *data) 29753741ed8SRussell King { 29853741ed8SRussell King struct spi_device *spi = data; 29953741ed8SRussell King struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 30053741ed8SRussell King struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 30153741ed8SRussell King 30253741ed8SRussell King complete(&mcspi_dma->dma_rx_completion); 30353741ed8SRussell King 30453741ed8SRussell King /* We must disable the DMA RX request */ 30553741ed8SRussell King omap2_mcspi_set_dma_req(spi, 1, 0); 30653741ed8SRussell King } 30753741ed8SRussell King 30853741ed8SRussell King static void omap2_mcspi_tx_callback(void *data) 30953741ed8SRussell King { 31053741ed8SRussell King struct spi_device *spi = data; 31153741ed8SRussell King struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 31253741ed8SRussell King struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 31353741ed8SRussell King 31453741ed8SRussell King complete(&mcspi_dma->dma_tx_completion); 31553741ed8SRussell King 31653741ed8SRussell King /* We must disable the DMA TX request */ 31753741ed8SRussell King omap2_mcspi_set_dma_req(spi, 0, 0); 31853741ed8SRussell King } 31953741ed8SRussell King 320d7b4394eSShubhrajyoti D static void omap2_mcspi_tx_dma(struct spi_device *spi, 321d7b4394eSShubhrajyoti D struct spi_transfer *xfer, 322d7b4394eSShubhrajyoti D struct dma_slave_config cfg) 323ca632f55SGrant Likely { 324ca632f55SGrant Likely struct omap2_mcspi *mcspi; 325ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 3268c7494a5SRussell King unsigned int count; 327ca632f55SGrant Likely u8 * rx; 328ca632f55SGrant Likely const u8 * tx; 329ca632f55SGrant Likely void __iomem *chstat_reg; 330d7b4394eSShubhrajyoti D struct omap2_mcspi_cs *cs = spi->controller_state; 331ca632f55SGrant Likely 332ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 333ca632f55SGrant Likely mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 334d7b4394eSShubhrajyoti D count = xfer->len; 335ca632f55SGrant Likely 336d7b4394eSShubhrajyoti D rx = xfer->rx_buf; 337d7b4394eSShubhrajyoti D tx = xfer->tx_buf; 338ca632f55SGrant Likely chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; 339ca632f55SGrant Likely 340d7b4394eSShubhrajyoti D if (mcspi_dma->dma_tx) { 34153741ed8SRussell King struct dma_async_tx_descriptor *tx; 34253741ed8SRussell King struct scatterlist sg; 34353741ed8SRussell King 34453741ed8SRussell King dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); 34553741ed8SRussell King 34653741ed8SRussell King sg_init_table(&sg, 1); 34753741ed8SRussell King sg_dma_address(&sg) = xfer->tx_dma; 34853741ed8SRussell King sg_dma_len(&sg) = xfer->len; 34953741ed8SRussell King 35053741ed8SRussell King tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, 35153741ed8SRussell King DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 35253741ed8SRussell King if (tx) { 35353741ed8SRussell King tx->callback = omap2_mcspi_tx_callback; 35453741ed8SRussell King tx->callback_param = spi; 35553741ed8SRussell King dmaengine_submit(tx); 35653741ed8SRussell King } else { 35753741ed8SRussell King /* FIXME: fall back to PIO? */ 35853741ed8SRussell King } 35953741ed8SRussell King } 36053741ed8SRussell King dma_async_issue_pending(mcspi_dma->dma_tx); 361ca632f55SGrant Likely omap2_mcspi_set_dma_req(spi, 0, 1); 362ca632f55SGrant Likely 363ca632f55SGrant Likely wait_for_completion(&mcspi_dma->dma_tx_completion); 364a3ce9a80SShubhrajyoti D dma_unmap_single(mcspi->dev, xfer->tx_dma, count, 365a3ce9a80SShubhrajyoti D DMA_TO_DEVICE); 366ca632f55SGrant Likely 367ca632f55SGrant Likely /* for TX_ONLY mode, be sure all words have shifted out */ 368ca632f55SGrant Likely if (rx == NULL) { 369ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 370ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) 371ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 372ca632f55SGrant Likely else if (mcspi_wait_for_reg_bit(chstat_reg, 373ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_EOT) < 0) 374ca632f55SGrant Likely dev_err(&spi->dev, "EOT timed out\n"); 375ca632f55SGrant Likely } 376ca632f55SGrant Likely } 377ca632f55SGrant Likely 378d7b4394eSShubhrajyoti D static unsigned 379d7b4394eSShubhrajyoti D omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, 380d7b4394eSShubhrajyoti D struct dma_slave_config cfg, 381d7b4394eSShubhrajyoti D unsigned es) 382d7b4394eSShubhrajyoti D { 383d7b4394eSShubhrajyoti D struct omap2_mcspi *mcspi; 384d7b4394eSShubhrajyoti D struct omap2_mcspi_dma *mcspi_dma; 385d7b4394eSShubhrajyoti D unsigned int count; 386d7b4394eSShubhrajyoti D u32 l; 387d7b4394eSShubhrajyoti D int elements = 0; 388d7b4394eSShubhrajyoti D int word_len, element_count; 389d7b4394eSShubhrajyoti D struct omap2_mcspi_cs *cs = spi->controller_state; 390d7b4394eSShubhrajyoti D mcspi = spi_master_get_devdata(spi->master); 391d7b4394eSShubhrajyoti D mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 392d7b4394eSShubhrajyoti D count = xfer->len; 393d7b4394eSShubhrajyoti D word_len = cs->word_len; 394d7b4394eSShubhrajyoti D l = mcspi_cached_chconf0(spi); 395d7b4394eSShubhrajyoti D 396d7b4394eSShubhrajyoti D if (word_len <= 8) 397d7b4394eSShubhrajyoti D element_count = count; 398d7b4394eSShubhrajyoti D else if (word_len <= 16) 399d7b4394eSShubhrajyoti D element_count = count >> 1; 400d7b4394eSShubhrajyoti D else /* word_len <= 32 */ 401d7b4394eSShubhrajyoti D element_count = count >> 2; 402d7b4394eSShubhrajyoti D 403d7b4394eSShubhrajyoti D if (mcspi_dma->dma_rx) { 404d7b4394eSShubhrajyoti D struct dma_async_tx_descriptor *tx; 405d7b4394eSShubhrajyoti D struct scatterlist sg; 406d7b4394eSShubhrajyoti D size_t len = xfer->len - es; 407d7b4394eSShubhrajyoti D 408d7b4394eSShubhrajyoti D dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); 409d7b4394eSShubhrajyoti D 410d7b4394eSShubhrajyoti D if (l & OMAP2_MCSPI_CHCONF_TURBO) 411d7b4394eSShubhrajyoti D len -= es; 412d7b4394eSShubhrajyoti D 413d7b4394eSShubhrajyoti D sg_init_table(&sg, 1); 414d7b4394eSShubhrajyoti D sg_dma_address(&sg) = xfer->rx_dma; 415d7b4394eSShubhrajyoti D sg_dma_len(&sg) = len; 416d7b4394eSShubhrajyoti D 417d7b4394eSShubhrajyoti D tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, 418d7b4394eSShubhrajyoti D DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | 419d7b4394eSShubhrajyoti D DMA_CTRL_ACK); 420d7b4394eSShubhrajyoti D if (tx) { 421d7b4394eSShubhrajyoti D tx->callback = omap2_mcspi_rx_callback; 422d7b4394eSShubhrajyoti D tx->callback_param = spi; 423d7b4394eSShubhrajyoti D dmaengine_submit(tx); 424d7b4394eSShubhrajyoti D } else { 425d7b4394eSShubhrajyoti D /* FIXME: fall back to PIO? */ 426d7b4394eSShubhrajyoti D } 427d7b4394eSShubhrajyoti D } 428d7b4394eSShubhrajyoti D 429d7b4394eSShubhrajyoti D dma_async_issue_pending(mcspi_dma->dma_rx); 430d7b4394eSShubhrajyoti D omap2_mcspi_set_dma_req(spi, 1, 1); 431d7b4394eSShubhrajyoti D 432ca632f55SGrant Likely wait_for_completion(&mcspi_dma->dma_rx_completion); 433a3ce9a80SShubhrajyoti D dma_unmap_single(mcspi->dev, xfer->rx_dma, count, 434a3ce9a80SShubhrajyoti D DMA_FROM_DEVICE); 435ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 436ca632f55SGrant Likely 43753741ed8SRussell King elements = element_count - 1; 43853741ed8SRussell King 439ca632f55SGrant Likely if (l & OMAP2_MCSPI_CHCONF_TURBO) { 44053741ed8SRussell King elements--; 441ca632f55SGrant Likely 442ca632f55SGrant Likely if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 443ca632f55SGrant Likely & OMAP2_MCSPI_CHSTAT_RXS)) { 444ca632f55SGrant Likely u32 w; 445ca632f55SGrant Likely 446ca632f55SGrant Likely w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 447ca632f55SGrant Likely if (word_len <= 8) 448ca632f55SGrant Likely ((u8 *)xfer->rx_buf)[elements++] = w; 449ca632f55SGrant Likely else if (word_len <= 16) 450ca632f55SGrant Likely ((u16 *)xfer->rx_buf)[elements++] = w; 451ca632f55SGrant Likely else /* word_len <= 32 */ 452ca632f55SGrant Likely ((u32 *)xfer->rx_buf)[elements++] = w; 453ca632f55SGrant Likely } else { 454d7b4394eSShubhrajyoti D dev_err(&spi->dev, "DMA RX penultimate word empty"); 455ca632f55SGrant Likely count -= (word_len <= 8) ? 2 : 456ca632f55SGrant Likely (word_len <= 16) ? 4 : 457ca632f55SGrant Likely /* word_len <= 32 */ 8; 458ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 1); 459ca632f55SGrant Likely return count; 460ca632f55SGrant Likely } 461ca632f55SGrant Likely } 462ca632f55SGrant Likely if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) 463ca632f55SGrant Likely & OMAP2_MCSPI_CHSTAT_RXS)) { 464ca632f55SGrant Likely u32 w; 465ca632f55SGrant Likely 466ca632f55SGrant Likely w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); 467ca632f55SGrant Likely if (word_len <= 8) 468ca632f55SGrant Likely ((u8 *)xfer->rx_buf)[elements] = w; 469ca632f55SGrant Likely else if (word_len <= 16) 470ca632f55SGrant Likely ((u16 *)xfer->rx_buf)[elements] = w; 471ca632f55SGrant Likely else /* word_len <= 32 */ 472ca632f55SGrant Likely ((u32 *)xfer->rx_buf)[elements] = w; 473ca632f55SGrant Likely } else { 474ca632f55SGrant Likely dev_err(&spi->dev, "DMA RX last word empty"); 475ca632f55SGrant Likely count -= (word_len <= 8) ? 1 : 476ca632f55SGrant Likely (word_len <= 16) ? 2 : 477ca632f55SGrant Likely /* word_len <= 32 */ 4; 478ca632f55SGrant Likely } 479ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 1); 480d7b4394eSShubhrajyoti D return count; 481ca632f55SGrant Likely } 482d7b4394eSShubhrajyoti D 483d7b4394eSShubhrajyoti D static unsigned 484d7b4394eSShubhrajyoti D omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) 485d7b4394eSShubhrajyoti D { 486d7b4394eSShubhrajyoti D struct omap2_mcspi *mcspi; 487d7b4394eSShubhrajyoti D struct omap2_mcspi_cs *cs = spi->controller_state; 488d7b4394eSShubhrajyoti D struct omap2_mcspi_dma *mcspi_dma; 489d7b4394eSShubhrajyoti D unsigned int count; 490d7b4394eSShubhrajyoti D u32 l; 491d7b4394eSShubhrajyoti D u8 *rx; 492d7b4394eSShubhrajyoti D const u8 *tx; 493d7b4394eSShubhrajyoti D struct dma_slave_config cfg; 494d7b4394eSShubhrajyoti D enum dma_slave_buswidth width; 495d7b4394eSShubhrajyoti D unsigned es; 496d7b4394eSShubhrajyoti D 497d7b4394eSShubhrajyoti D mcspi = spi_master_get_devdata(spi->master); 498d7b4394eSShubhrajyoti D mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 499d7b4394eSShubhrajyoti D l = mcspi_cached_chconf0(spi); 500d7b4394eSShubhrajyoti D 501d7b4394eSShubhrajyoti D 502d7b4394eSShubhrajyoti D if (cs->word_len <= 8) { 503d7b4394eSShubhrajyoti D width = DMA_SLAVE_BUSWIDTH_1_BYTE; 504d7b4394eSShubhrajyoti D es = 1; 505d7b4394eSShubhrajyoti D } else if (cs->word_len <= 16) { 506d7b4394eSShubhrajyoti D width = DMA_SLAVE_BUSWIDTH_2_BYTES; 507d7b4394eSShubhrajyoti D es = 2; 508d7b4394eSShubhrajyoti D } else { 509d7b4394eSShubhrajyoti D width = DMA_SLAVE_BUSWIDTH_4_BYTES; 510d7b4394eSShubhrajyoti D es = 4; 511d7b4394eSShubhrajyoti D } 512d7b4394eSShubhrajyoti D 513d7b4394eSShubhrajyoti D memset(&cfg, 0, sizeof(cfg)); 514d7b4394eSShubhrajyoti D cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; 515d7b4394eSShubhrajyoti D cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; 516d7b4394eSShubhrajyoti D cfg.src_addr_width = width; 517d7b4394eSShubhrajyoti D cfg.dst_addr_width = width; 518d7b4394eSShubhrajyoti D cfg.src_maxburst = 1; 519d7b4394eSShubhrajyoti D cfg.dst_maxburst = 1; 520d7b4394eSShubhrajyoti D 521d7b4394eSShubhrajyoti D rx = xfer->rx_buf; 522d7b4394eSShubhrajyoti D tx = xfer->tx_buf; 523d7b4394eSShubhrajyoti D 524d7b4394eSShubhrajyoti D count = xfer->len; 525d7b4394eSShubhrajyoti D 526d7b4394eSShubhrajyoti D if (tx != NULL) 527d7b4394eSShubhrajyoti D omap2_mcspi_tx_dma(spi, xfer, cfg); 528d7b4394eSShubhrajyoti D 529d7b4394eSShubhrajyoti D if (rx != NULL) 530d7b4394eSShubhrajyoti D return omap2_mcspi_rx_dma(spi, xfer, cfg, es); 531d7b4394eSShubhrajyoti D 532ca632f55SGrant Likely return count; 533ca632f55SGrant Likely } 534ca632f55SGrant Likely 535ca632f55SGrant Likely static unsigned 536ca632f55SGrant Likely omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) 537ca632f55SGrant Likely { 538ca632f55SGrant Likely struct omap2_mcspi *mcspi; 539ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 540ca632f55SGrant Likely unsigned int count, c; 541ca632f55SGrant Likely u32 l; 542ca632f55SGrant Likely void __iomem *base = cs->base; 543ca632f55SGrant Likely void __iomem *tx_reg; 544ca632f55SGrant Likely void __iomem *rx_reg; 545ca632f55SGrant Likely void __iomem *chstat_reg; 546ca632f55SGrant Likely int word_len; 547ca632f55SGrant Likely 548ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 549ca632f55SGrant Likely count = xfer->len; 550ca632f55SGrant Likely c = count; 551ca632f55SGrant Likely word_len = cs->word_len; 552ca632f55SGrant Likely 553ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 554ca632f55SGrant Likely 555ca632f55SGrant Likely /* We store the pre-calculated register addresses on stack to speed 556ca632f55SGrant Likely * up the transfer loop. */ 557ca632f55SGrant Likely tx_reg = base + OMAP2_MCSPI_TX0; 558ca632f55SGrant Likely rx_reg = base + OMAP2_MCSPI_RX0; 559ca632f55SGrant Likely chstat_reg = base + OMAP2_MCSPI_CHSTAT0; 560ca632f55SGrant Likely 561ca632f55SGrant Likely if (c < (word_len>>3)) 562ca632f55SGrant Likely return 0; 563ca632f55SGrant Likely 564ca632f55SGrant Likely if (word_len <= 8) { 565ca632f55SGrant Likely u8 *rx; 566ca632f55SGrant Likely const u8 *tx; 567ca632f55SGrant Likely 568ca632f55SGrant Likely rx = xfer->rx_buf; 569ca632f55SGrant Likely tx = xfer->tx_buf; 570ca632f55SGrant Likely 571ca632f55SGrant Likely do { 572ca632f55SGrant Likely c -= 1; 573ca632f55SGrant Likely if (tx != NULL) { 574ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 575ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 576ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 577ca632f55SGrant Likely goto out; 578ca632f55SGrant Likely } 579ca632f55SGrant Likely dev_vdbg(&spi->dev, "write-%d %02x\n", 580ca632f55SGrant Likely word_len, *tx); 581ca632f55SGrant Likely __raw_writel(*tx++, tx_reg); 582ca632f55SGrant Likely } 583ca632f55SGrant Likely if (rx != NULL) { 584ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 585ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 586ca632f55SGrant Likely dev_err(&spi->dev, "RXS timed out\n"); 587ca632f55SGrant Likely goto out; 588ca632f55SGrant Likely } 589ca632f55SGrant Likely 590ca632f55SGrant Likely if (c == 1 && tx == NULL && 591ca632f55SGrant Likely (l & OMAP2_MCSPI_CHCONF_TURBO)) { 592ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 593ca632f55SGrant Likely *rx++ = __raw_readl(rx_reg); 594ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %02x\n", 595ca632f55SGrant Likely word_len, *(rx - 1)); 596ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 597ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 598ca632f55SGrant Likely dev_err(&spi->dev, 599ca632f55SGrant Likely "RXS timed out\n"); 600ca632f55SGrant Likely goto out; 601ca632f55SGrant Likely } 602ca632f55SGrant Likely c = 0; 603ca632f55SGrant Likely } else if (c == 0 && tx == NULL) { 604ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 605ca632f55SGrant Likely } 606ca632f55SGrant Likely 607ca632f55SGrant Likely *rx++ = __raw_readl(rx_reg); 608ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %02x\n", 609ca632f55SGrant Likely word_len, *(rx - 1)); 610ca632f55SGrant Likely } 611ca632f55SGrant Likely } while (c); 612ca632f55SGrant Likely } else if (word_len <= 16) { 613ca632f55SGrant Likely u16 *rx; 614ca632f55SGrant Likely const u16 *tx; 615ca632f55SGrant Likely 616ca632f55SGrant Likely rx = xfer->rx_buf; 617ca632f55SGrant Likely tx = xfer->tx_buf; 618ca632f55SGrant Likely do { 619ca632f55SGrant Likely c -= 2; 620ca632f55SGrant Likely if (tx != NULL) { 621ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 622ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 623ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 624ca632f55SGrant Likely goto out; 625ca632f55SGrant Likely } 626ca632f55SGrant Likely dev_vdbg(&spi->dev, "write-%d %04x\n", 627ca632f55SGrant Likely word_len, *tx); 628ca632f55SGrant Likely __raw_writel(*tx++, tx_reg); 629ca632f55SGrant Likely } 630ca632f55SGrant Likely if (rx != NULL) { 631ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 632ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 633ca632f55SGrant Likely dev_err(&spi->dev, "RXS timed out\n"); 634ca632f55SGrant Likely goto out; 635ca632f55SGrant Likely } 636ca632f55SGrant Likely 637ca632f55SGrant Likely if (c == 2 && tx == NULL && 638ca632f55SGrant Likely (l & OMAP2_MCSPI_CHCONF_TURBO)) { 639ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 640ca632f55SGrant Likely *rx++ = __raw_readl(rx_reg); 641ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %04x\n", 642ca632f55SGrant Likely word_len, *(rx - 1)); 643ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 644ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 645ca632f55SGrant Likely dev_err(&spi->dev, 646ca632f55SGrant Likely "RXS timed out\n"); 647ca632f55SGrant Likely goto out; 648ca632f55SGrant Likely } 649ca632f55SGrant Likely c = 0; 650ca632f55SGrant Likely } else if (c == 0 && tx == NULL) { 651ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 652ca632f55SGrant Likely } 653ca632f55SGrant Likely 654ca632f55SGrant Likely *rx++ = __raw_readl(rx_reg); 655ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %04x\n", 656ca632f55SGrant Likely word_len, *(rx - 1)); 657ca632f55SGrant Likely } 658ca632f55SGrant Likely } while (c >= 2); 659ca632f55SGrant Likely } else if (word_len <= 32) { 660ca632f55SGrant Likely u32 *rx; 661ca632f55SGrant Likely const u32 *tx; 662ca632f55SGrant Likely 663ca632f55SGrant Likely rx = xfer->rx_buf; 664ca632f55SGrant Likely tx = xfer->tx_buf; 665ca632f55SGrant Likely do { 666ca632f55SGrant Likely c -= 4; 667ca632f55SGrant Likely if (tx != NULL) { 668ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 669ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 670ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 671ca632f55SGrant Likely goto out; 672ca632f55SGrant Likely } 673ca632f55SGrant Likely dev_vdbg(&spi->dev, "write-%d %08x\n", 674ca632f55SGrant Likely word_len, *tx); 675ca632f55SGrant Likely __raw_writel(*tx++, tx_reg); 676ca632f55SGrant Likely } 677ca632f55SGrant Likely if (rx != NULL) { 678ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 679ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 680ca632f55SGrant Likely dev_err(&spi->dev, "RXS timed out\n"); 681ca632f55SGrant Likely goto out; 682ca632f55SGrant Likely } 683ca632f55SGrant Likely 684ca632f55SGrant Likely if (c == 4 && tx == NULL && 685ca632f55SGrant Likely (l & OMAP2_MCSPI_CHCONF_TURBO)) { 686ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 687ca632f55SGrant Likely *rx++ = __raw_readl(rx_reg); 688ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %08x\n", 689ca632f55SGrant Likely word_len, *(rx - 1)); 690ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 691ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_RXS) < 0) { 692ca632f55SGrant Likely dev_err(&spi->dev, 693ca632f55SGrant Likely "RXS timed out\n"); 694ca632f55SGrant Likely goto out; 695ca632f55SGrant Likely } 696ca632f55SGrant Likely c = 0; 697ca632f55SGrant Likely } else if (c == 0 && tx == NULL) { 698ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 699ca632f55SGrant Likely } 700ca632f55SGrant Likely 701ca632f55SGrant Likely *rx++ = __raw_readl(rx_reg); 702ca632f55SGrant Likely dev_vdbg(&spi->dev, "read-%d %08x\n", 703ca632f55SGrant Likely word_len, *(rx - 1)); 704ca632f55SGrant Likely } 705ca632f55SGrant Likely } while (c >= 4); 706ca632f55SGrant Likely } 707ca632f55SGrant Likely 708ca632f55SGrant Likely /* for TX_ONLY mode, be sure all words have shifted out */ 709ca632f55SGrant Likely if (xfer->rx_buf == NULL) { 710ca632f55SGrant Likely if (mcspi_wait_for_reg_bit(chstat_reg, 711ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_TXS) < 0) { 712ca632f55SGrant Likely dev_err(&spi->dev, "TXS timed out\n"); 713ca632f55SGrant Likely } else if (mcspi_wait_for_reg_bit(chstat_reg, 714ca632f55SGrant Likely OMAP2_MCSPI_CHSTAT_EOT) < 0) 715ca632f55SGrant Likely dev_err(&spi->dev, "EOT timed out\n"); 716ca632f55SGrant Likely 717ca632f55SGrant Likely /* disable chan to purge rx datas received in TX_ONLY transfer, 718ca632f55SGrant Likely * otherwise these rx datas will affect the direct following 719ca632f55SGrant Likely * RX_ONLY transfer. 720ca632f55SGrant Likely */ 721ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 722ca632f55SGrant Likely } 723ca632f55SGrant Likely out: 724ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 1); 725ca632f55SGrant Likely return count - c; 726ca632f55SGrant Likely } 727ca632f55SGrant Likely 728ca632f55SGrant Likely static u32 omap2_mcspi_calc_divisor(u32 speed_hz) 729ca632f55SGrant Likely { 730ca632f55SGrant Likely u32 div; 731ca632f55SGrant Likely 732ca632f55SGrant Likely for (div = 0; div < 15; div++) 733ca632f55SGrant Likely if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) 734ca632f55SGrant Likely return div; 735ca632f55SGrant Likely 736ca632f55SGrant Likely return 15; 737ca632f55SGrant Likely } 738ca632f55SGrant Likely 739ca632f55SGrant Likely /* called only when no transfer is active to this device */ 740ca632f55SGrant Likely static int omap2_mcspi_setup_transfer(struct spi_device *spi, 741ca632f55SGrant Likely struct spi_transfer *t) 742ca632f55SGrant Likely { 743ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 744ca632f55SGrant Likely struct omap2_mcspi *mcspi; 745ca632f55SGrant Likely struct spi_master *spi_cntrl; 746ca632f55SGrant Likely u32 l = 0, div = 0; 747ca632f55SGrant Likely u8 word_len = spi->bits_per_word; 748ca632f55SGrant Likely u32 speed_hz = spi->max_speed_hz; 749ca632f55SGrant Likely 750ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 751ca632f55SGrant Likely spi_cntrl = mcspi->master; 752ca632f55SGrant Likely 753ca632f55SGrant Likely if (t != NULL && t->bits_per_word) 754ca632f55SGrant Likely word_len = t->bits_per_word; 755ca632f55SGrant Likely 756ca632f55SGrant Likely cs->word_len = word_len; 757ca632f55SGrant Likely 758ca632f55SGrant Likely if (t && t->speed_hz) 759ca632f55SGrant Likely speed_hz = t->speed_hz; 760ca632f55SGrant Likely 761ca632f55SGrant Likely speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); 762ca632f55SGrant Likely div = omap2_mcspi_calc_divisor(speed_hz); 763ca632f55SGrant Likely 764ca632f55SGrant Likely l = mcspi_cached_chconf0(spi); 765ca632f55SGrant Likely 766ca632f55SGrant Likely /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS 767ca632f55SGrant Likely * REVISIT: this controller could support SPI_3WIRE mode. 768ca632f55SGrant Likely */ 769*0384e90bSDaniel Mack if (mcspi->pin_dir == MCSPI_PINDIR_D0_OUT_D1_IN) { 770*0384e90bSDaniel Mack l &= ~OMAP2_MCSPI_CHCONF_IS; 771*0384e90bSDaniel Mack l &= ~OMAP2_MCSPI_CHCONF_DPE1; 772ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_DPE0; 773*0384e90bSDaniel Mack } else { 774*0384e90bSDaniel Mack l |= OMAP2_MCSPI_CHCONF_IS; 775*0384e90bSDaniel Mack l |= OMAP2_MCSPI_CHCONF_DPE1; 776*0384e90bSDaniel Mack l &= ~OMAP2_MCSPI_CHCONF_DPE0; 777*0384e90bSDaniel Mack } 778ca632f55SGrant Likely 779ca632f55SGrant Likely /* wordlength */ 780ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; 781ca632f55SGrant Likely l |= (word_len - 1) << 7; 782ca632f55SGrant Likely 783ca632f55SGrant Likely /* set chipselect polarity; manage with FORCE */ 784ca632f55SGrant Likely if (!(spi->mode & SPI_CS_HIGH)) 785ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ 786ca632f55SGrant Likely else 787ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_EPOL; 788ca632f55SGrant Likely 789ca632f55SGrant Likely /* set clock divisor */ 790ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; 791ca632f55SGrant Likely l |= div << 2; 792ca632f55SGrant Likely 793ca632f55SGrant Likely /* set SPI mode 0..3 */ 794ca632f55SGrant Likely if (spi->mode & SPI_CPOL) 795ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_POL; 796ca632f55SGrant Likely else 797ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_POL; 798ca632f55SGrant Likely if (spi->mode & SPI_CPHA) 799ca632f55SGrant Likely l |= OMAP2_MCSPI_CHCONF_PHA; 800ca632f55SGrant Likely else 801ca632f55SGrant Likely l &= ~OMAP2_MCSPI_CHCONF_PHA; 802ca632f55SGrant Likely 803ca632f55SGrant Likely mcspi_write_chconf0(spi, l); 804ca632f55SGrant Likely 805ca632f55SGrant Likely dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", 806ca632f55SGrant Likely OMAP2_MCSPI_MAX_FREQ >> div, 807ca632f55SGrant Likely (spi->mode & SPI_CPHA) ? "trailing" : "leading", 808ca632f55SGrant Likely (spi->mode & SPI_CPOL) ? "inverted" : "normal"); 809ca632f55SGrant Likely 810ca632f55SGrant Likely return 0; 811ca632f55SGrant Likely } 812ca632f55SGrant Likely 813ca632f55SGrant Likely static int omap2_mcspi_request_dma(struct spi_device *spi) 814ca632f55SGrant Likely { 815ca632f55SGrant Likely struct spi_master *master = spi->master; 816ca632f55SGrant Likely struct omap2_mcspi *mcspi; 817ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 81853741ed8SRussell King dma_cap_mask_t mask; 81953741ed8SRussell King unsigned sig; 820ca632f55SGrant Likely 821ca632f55SGrant Likely mcspi = spi_master_get_devdata(master); 822ca632f55SGrant Likely mcspi_dma = mcspi->dma_channels + spi->chip_select; 823ca632f55SGrant Likely 824ca632f55SGrant Likely init_completion(&mcspi_dma->dma_rx_completion); 825ca632f55SGrant Likely init_completion(&mcspi_dma->dma_tx_completion); 826ca632f55SGrant Likely 82753741ed8SRussell King dma_cap_zero(mask); 82853741ed8SRussell King dma_cap_set(DMA_SLAVE, mask); 82953741ed8SRussell King sig = mcspi_dma->dma_rx_sync_dev; 83053741ed8SRussell King mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); 83153741ed8SRussell King if (!mcspi_dma->dma_rx) { 83253741ed8SRussell King dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n"); 83353741ed8SRussell King return -EAGAIN; 83453741ed8SRussell King } 835ca632f55SGrant Likely 83653741ed8SRussell King sig = mcspi_dma->dma_tx_sync_dev; 83753741ed8SRussell King mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); 83853741ed8SRussell King if (!mcspi_dma->dma_tx) { 83953741ed8SRussell King dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n"); 84053741ed8SRussell King dma_release_channel(mcspi_dma->dma_rx); 84153741ed8SRussell King mcspi_dma->dma_rx = NULL; 84253741ed8SRussell King return -EAGAIN; 84353741ed8SRussell King } 844ca632f55SGrant Likely 845ca632f55SGrant Likely return 0; 846ca632f55SGrant Likely } 847ca632f55SGrant Likely 848ca632f55SGrant Likely static int omap2_mcspi_setup(struct spi_device *spi) 849ca632f55SGrant Likely { 850ca632f55SGrant Likely int ret; 8511bd897f8SBenoit Cousson struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); 8521bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 853ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 854ca632f55SGrant Likely struct omap2_mcspi_cs *cs = spi->controller_state; 855ca632f55SGrant Likely 856ca632f55SGrant Likely if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { 857ca632f55SGrant Likely dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", 858ca632f55SGrant Likely spi->bits_per_word); 859ca632f55SGrant Likely return -EINVAL; 860ca632f55SGrant Likely } 861ca632f55SGrant Likely 862ca632f55SGrant Likely mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 863ca632f55SGrant Likely 864ca632f55SGrant Likely if (!cs) { 86510aa5a35SRussell King cs = kzalloc(sizeof *cs, GFP_KERNEL); 866ca632f55SGrant Likely if (!cs) 867ca632f55SGrant Likely return -ENOMEM; 868ca632f55SGrant Likely cs->base = mcspi->base + spi->chip_select * 0x14; 869ca632f55SGrant Likely cs->phys = mcspi->phys + spi->chip_select * 0x14; 870ca632f55SGrant Likely cs->chconf0 = 0; 871ca632f55SGrant Likely spi->controller_state = cs; 872ca632f55SGrant Likely /* Link this to context save list */ 8731bd897f8SBenoit Cousson list_add_tail(&cs->node, &ctx->cs); 874ca632f55SGrant Likely } 875ca632f55SGrant Likely 8768c7494a5SRussell King if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { 877ca632f55SGrant Likely ret = omap2_mcspi_request_dma(spi); 878ca632f55SGrant Likely if (ret < 0) 879ca632f55SGrant Likely return ret; 880ca632f55SGrant Likely } 881ca632f55SGrant Likely 882034d3dc9SShubhrajyoti D ret = pm_runtime_get_sync(mcspi->dev); 883ca632f55SGrant Likely if (ret < 0) 884ca632f55SGrant Likely return ret; 885ca632f55SGrant Likely 886ca632f55SGrant Likely ret = omap2_mcspi_setup_transfer(spi, NULL); 887034d3dc9SShubhrajyoti D pm_runtime_mark_last_busy(mcspi->dev); 888034d3dc9SShubhrajyoti D pm_runtime_put_autosuspend(mcspi->dev); 889ca632f55SGrant Likely 890ca632f55SGrant Likely return ret; 891ca632f55SGrant Likely } 892ca632f55SGrant Likely 893ca632f55SGrant Likely static void omap2_mcspi_cleanup(struct spi_device *spi) 894ca632f55SGrant Likely { 895ca632f55SGrant Likely struct omap2_mcspi *mcspi; 896ca632f55SGrant Likely struct omap2_mcspi_dma *mcspi_dma; 897ca632f55SGrant Likely struct omap2_mcspi_cs *cs; 898ca632f55SGrant Likely 899ca632f55SGrant Likely mcspi = spi_master_get_devdata(spi->master); 900ca632f55SGrant Likely 901ca632f55SGrant Likely if (spi->controller_state) { 902ca632f55SGrant Likely /* Unlink controller state from context save list */ 903ca632f55SGrant Likely cs = spi->controller_state; 904ca632f55SGrant Likely list_del(&cs->node); 905ca632f55SGrant Likely 90610aa5a35SRussell King kfree(cs); 907ca632f55SGrant Likely } 908ca632f55SGrant Likely 909ca632f55SGrant Likely if (spi->chip_select < spi->master->num_chipselect) { 910ca632f55SGrant Likely mcspi_dma = &mcspi->dma_channels[spi->chip_select]; 911ca632f55SGrant Likely 91253741ed8SRussell King if (mcspi_dma->dma_rx) { 91353741ed8SRussell King dma_release_channel(mcspi_dma->dma_rx); 91453741ed8SRussell King mcspi_dma->dma_rx = NULL; 915ca632f55SGrant Likely } 91653741ed8SRussell King if (mcspi_dma->dma_tx) { 91753741ed8SRussell King dma_release_channel(mcspi_dma->dma_tx); 91853741ed8SRussell King mcspi_dma->dma_tx = NULL; 919ca632f55SGrant Likely } 920ca632f55SGrant Likely } 921ca632f55SGrant Likely } 922ca632f55SGrant Likely 9235fda88f5SShubhrajyoti D static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) 924ca632f55SGrant Likely { 925ca632f55SGrant Likely 926ca632f55SGrant Likely /* We only enable one channel at a time -- the one whose message is 9275fda88f5SShubhrajyoti D * -- although this controller would gladly 928ca632f55SGrant Likely * arbitrate among multiple channels. This corresponds to "single 929ca632f55SGrant Likely * channel" master mode. As a side effect, we need to manage the 930ca632f55SGrant Likely * chipselect with the FORCE bit ... CS != channel enable. 931ca632f55SGrant Likely */ 9325fda88f5SShubhrajyoti D 933ca632f55SGrant Likely struct spi_device *spi; 934ca632f55SGrant Likely struct spi_transfer *t = NULL; 935ca632f55SGrant Likely int cs_active = 0; 936ca632f55SGrant Likely struct omap2_mcspi_cs *cs; 937ca632f55SGrant Likely struct omap2_mcspi_device_config *cd; 938ca632f55SGrant Likely int par_override = 0; 939ca632f55SGrant Likely int status = 0; 940ca632f55SGrant Likely u32 chconf; 941ca632f55SGrant Likely 942ca632f55SGrant Likely spi = m->spi; 943ca632f55SGrant Likely cs = spi->controller_state; 944ca632f55SGrant Likely cd = spi->controller_data; 945ca632f55SGrant Likely 946ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 1); 947ca632f55SGrant Likely list_for_each_entry(t, &m->transfers, transfer_list) { 948ca632f55SGrant Likely if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { 949ca632f55SGrant Likely status = -EINVAL; 950ca632f55SGrant Likely break; 951ca632f55SGrant Likely } 952ca632f55SGrant Likely if (par_override || t->speed_hz || t->bits_per_word) { 953ca632f55SGrant Likely par_override = 1; 954ca632f55SGrant Likely status = omap2_mcspi_setup_transfer(spi, t); 955ca632f55SGrant Likely if (status < 0) 956ca632f55SGrant Likely break; 957ca632f55SGrant Likely if (!t->speed_hz && !t->bits_per_word) 958ca632f55SGrant Likely par_override = 0; 959ca632f55SGrant Likely } 960ca632f55SGrant Likely 961ca632f55SGrant Likely if (!cs_active) { 962ca632f55SGrant Likely omap2_mcspi_force_cs(spi, 1); 963ca632f55SGrant Likely cs_active = 1; 964ca632f55SGrant Likely } 965ca632f55SGrant Likely 966ca632f55SGrant Likely chconf = mcspi_cached_chconf0(spi); 967ca632f55SGrant Likely chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; 968ca632f55SGrant Likely chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; 969ca632f55SGrant Likely 970ca632f55SGrant Likely if (t->tx_buf == NULL) 971ca632f55SGrant Likely chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; 972ca632f55SGrant Likely else if (t->rx_buf == NULL) 973ca632f55SGrant Likely chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; 974ca632f55SGrant Likely 975ca632f55SGrant Likely if (cd && cd->turbo_mode && t->tx_buf == NULL) { 976ca632f55SGrant Likely /* Turbo mode is for more than one word */ 977ca632f55SGrant Likely if (t->len > ((cs->word_len + 7) >> 3)) 978ca632f55SGrant Likely chconf |= OMAP2_MCSPI_CHCONF_TURBO; 979ca632f55SGrant Likely } 980ca632f55SGrant Likely 981ca632f55SGrant Likely mcspi_write_chconf0(spi, chconf); 982ca632f55SGrant Likely 983ca632f55SGrant Likely if (t->len) { 984ca632f55SGrant Likely unsigned count; 985ca632f55SGrant Likely 986ca632f55SGrant Likely /* RX_ONLY mode needs dummy data in TX reg */ 987ca632f55SGrant Likely if (t->tx_buf == NULL) 988ca632f55SGrant Likely __raw_writel(0, cs->base 989ca632f55SGrant Likely + OMAP2_MCSPI_TX0); 990ca632f55SGrant Likely 991ca632f55SGrant Likely if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) 992ca632f55SGrant Likely count = omap2_mcspi_txrx_dma(spi, t); 993ca632f55SGrant Likely else 994ca632f55SGrant Likely count = omap2_mcspi_txrx_pio(spi, t); 995ca632f55SGrant Likely m->actual_length += count; 996ca632f55SGrant Likely 997ca632f55SGrant Likely if (count != t->len) { 998ca632f55SGrant Likely status = -EIO; 999ca632f55SGrant Likely break; 1000ca632f55SGrant Likely } 1001ca632f55SGrant Likely } 1002ca632f55SGrant Likely 1003ca632f55SGrant Likely if (t->delay_usecs) 1004ca632f55SGrant Likely udelay(t->delay_usecs); 1005ca632f55SGrant Likely 1006ca632f55SGrant Likely /* ignore the "leave it on after last xfer" hint */ 1007ca632f55SGrant Likely if (t->cs_change) { 1008ca632f55SGrant Likely omap2_mcspi_force_cs(spi, 0); 1009ca632f55SGrant Likely cs_active = 0; 1010ca632f55SGrant Likely } 1011ca632f55SGrant Likely } 1012ca632f55SGrant Likely /* Restore defaults if they were overriden */ 1013ca632f55SGrant Likely if (par_override) { 1014ca632f55SGrant Likely par_override = 0; 1015ca632f55SGrant Likely status = omap2_mcspi_setup_transfer(spi, NULL); 1016ca632f55SGrant Likely } 1017ca632f55SGrant Likely 1018ca632f55SGrant Likely if (cs_active) 1019ca632f55SGrant Likely omap2_mcspi_force_cs(spi, 0); 1020ca632f55SGrant Likely 1021ca632f55SGrant Likely omap2_mcspi_set_enable(spi, 0); 1022ca632f55SGrant Likely 1023ca632f55SGrant Likely m->status = status; 1024ca632f55SGrant Likely 1025ca632f55SGrant Likely } 1026ca632f55SGrant Likely 10275fda88f5SShubhrajyoti D static int omap2_mcspi_transfer_one_message(struct spi_master *master, 10285fda88f5SShubhrajyoti D struct spi_message *m) 1029ca632f55SGrant Likely { 1030ca632f55SGrant Likely struct omap2_mcspi *mcspi; 1031ca632f55SGrant Likely struct spi_transfer *t; 1032ca632f55SGrant Likely 10335fda88f5SShubhrajyoti D mcspi = spi_master_get_devdata(master); 1034ca632f55SGrant Likely m->actual_length = 0; 1035ca632f55SGrant Likely m->status = 0; 1036ca632f55SGrant Likely 1037ca632f55SGrant Likely /* reject invalid messages and transfers */ 10385fda88f5SShubhrajyoti D if (list_empty(&m->transfers)) 1039ca632f55SGrant Likely return -EINVAL; 1040ca632f55SGrant Likely list_for_each_entry(t, &m->transfers, transfer_list) { 1041ca632f55SGrant Likely const void *tx_buf = t->tx_buf; 1042ca632f55SGrant Likely void *rx_buf = t->rx_buf; 1043ca632f55SGrant Likely unsigned len = t->len; 1044ca632f55SGrant Likely 1045ca632f55SGrant Likely if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ 1046ca632f55SGrant Likely || (len && !(rx_buf || tx_buf)) 1047ca632f55SGrant Likely || (t->bits_per_word && 1048ca632f55SGrant Likely ( t->bits_per_word < 4 1049ca632f55SGrant Likely || t->bits_per_word > 32))) { 10505fda88f5SShubhrajyoti D dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", 1051ca632f55SGrant Likely t->speed_hz, 1052ca632f55SGrant Likely len, 1053ca632f55SGrant Likely tx_buf ? "tx" : "", 1054ca632f55SGrant Likely rx_buf ? "rx" : "", 1055ca632f55SGrant Likely t->bits_per_word); 1056ca632f55SGrant Likely return -EINVAL; 1057ca632f55SGrant Likely } 1058ca632f55SGrant Likely if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { 10595fda88f5SShubhrajyoti D dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", 1060ca632f55SGrant Likely t->speed_hz, 1061ca632f55SGrant Likely OMAP2_MCSPI_MAX_FREQ >> 15); 1062ca632f55SGrant Likely return -EINVAL; 1063ca632f55SGrant Likely } 1064ca632f55SGrant Likely 1065ca632f55SGrant Likely if (m->is_dma_mapped || len < DMA_MIN_BYTES) 1066ca632f55SGrant Likely continue; 1067ca632f55SGrant Likely 1068ca632f55SGrant Likely if (tx_buf != NULL) { 10695fda88f5SShubhrajyoti D t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, 1070ca632f55SGrant Likely len, DMA_TO_DEVICE); 10715fda88f5SShubhrajyoti D if (dma_mapping_error(mcspi->dev, t->tx_dma)) { 10725fda88f5SShubhrajyoti D dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 1073ca632f55SGrant Likely 'T', len); 1074ca632f55SGrant Likely return -EINVAL; 1075ca632f55SGrant Likely } 1076ca632f55SGrant Likely } 1077ca632f55SGrant Likely if (rx_buf != NULL) { 10785fda88f5SShubhrajyoti D t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, 1079ca632f55SGrant Likely DMA_FROM_DEVICE); 10805fda88f5SShubhrajyoti D if (dma_mapping_error(mcspi->dev, t->rx_dma)) { 10815fda88f5SShubhrajyoti D dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 1082ca632f55SGrant Likely 'R', len); 1083ca632f55SGrant Likely if (tx_buf != NULL) 10845fda88f5SShubhrajyoti D dma_unmap_single(mcspi->dev, t->tx_dma, 1085ca632f55SGrant Likely len, DMA_TO_DEVICE); 1086ca632f55SGrant Likely return -EINVAL; 1087ca632f55SGrant Likely } 1088ca632f55SGrant Likely } 1089ca632f55SGrant Likely } 1090ca632f55SGrant Likely 10915fda88f5SShubhrajyoti D omap2_mcspi_work(mcspi, m); 10925fda88f5SShubhrajyoti D spi_finalize_current_message(master); 1093ca632f55SGrant Likely return 0; 1094ca632f55SGrant Likely } 1095ca632f55SGrant Likely 109624ab3275SArnd Bergmann static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) 1097ca632f55SGrant Likely { 1098ca632f55SGrant Likely struct spi_master *master = mcspi->master; 10991bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1100ca632f55SGrant Likely int ret = 0; 1101ca632f55SGrant Likely 1102034d3dc9SShubhrajyoti D ret = pm_runtime_get_sync(mcspi->dev); 1103ca632f55SGrant Likely if (ret < 0) 1104ca632f55SGrant Likely return ret; 1105ca632f55SGrant Likely 110639f8052dSShubhrajyoti D mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, 110739f8052dSShubhrajyoti D OMAP2_MCSPI_WAKEUPENABLE_WKEN); 110839f8052dSShubhrajyoti D ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; 1109ca632f55SGrant Likely 1110ca632f55SGrant Likely omap2_mcspi_set_master_mode(master); 1111034d3dc9SShubhrajyoti D pm_runtime_mark_last_busy(mcspi->dev); 1112034d3dc9SShubhrajyoti D pm_runtime_put_autosuspend(mcspi->dev); 1113ca632f55SGrant Likely return 0; 1114ca632f55SGrant Likely } 1115ca632f55SGrant Likely 1116ca632f55SGrant Likely static int omap_mcspi_runtime_resume(struct device *dev) 1117ca632f55SGrant Likely { 1118ca632f55SGrant Likely struct omap2_mcspi *mcspi; 1119ca632f55SGrant Likely struct spi_master *master; 1120ca632f55SGrant Likely 1121ca632f55SGrant Likely master = dev_get_drvdata(dev); 1122ca632f55SGrant Likely mcspi = spi_master_get_devdata(master); 1123ca632f55SGrant Likely omap2_mcspi_restore_ctx(mcspi); 1124ca632f55SGrant Likely 1125ca632f55SGrant Likely return 0; 1126ca632f55SGrant Likely } 1127ca632f55SGrant Likely 1128d5a80031SBenoit Cousson static struct omap2_mcspi_platform_config omap2_pdata = { 1129d5a80031SBenoit Cousson .regs_offset = 0, 1130d5a80031SBenoit Cousson }; 1131d5a80031SBenoit Cousson 1132d5a80031SBenoit Cousson static struct omap2_mcspi_platform_config omap4_pdata = { 1133d5a80031SBenoit Cousson .regs_offset = OMAP4_MCSPI_REG_OFFSET, 1134d5a80031SBenoit Cousson }; 1135d5a80031SBenoit Cousson 1136d5a80031SBenoit Cousson static const struct of_device_id omap_mcspi_of_match[] = { 1137d5a80031SBenoit Cousson { 1138d5a80031SBenoit Cousson .compatible = "ti,omap2-mcspi", 1139d5a80031SBenoit Cousson .data = &omap2_pdata, 1140d5a80031SBenoit Cousson }, 1141d5a80031SBenoit Cousson { 1142d5a80031SBenoit Cousson .compatible = "ti,omap4-mcspi", 1143d5a80031SBenoit Cousson .data = &omap4_pdata, 1144d5a80031SBenoit Cousson }, 1145d5a80031SBenoit Cousson { }, 1146d5a80031SBenoit Cousson }; 1147d5a80031SBenoit Cousson MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); 1148ca632f55SGrant Likely 11497d6b6d83SFelipe Balbi static int __devinit omap2_mcspi_probe(struct platform_device *pdev) 1150ca632f55SGrant Likely { 1151ca632f55SGrant Likely struct spi_master *master; 115283a01e72SUwe Kleine-König const struct omap2_mcspi_platform_config *pdata; 1153ca632f55SGrant Likely struct omap2_mcspi *mcspi; 1154ca632f55SGrant Likely struct resource *r; 1155ca632f55SGrant Likely int status = 0, i; 1156d5a80031SBenoit Cousson u32 regs_offset = 0; 1157d5a80031SBenoit Cousson static int bus_num = 1; 1158d5a80031SBenoit Cousson struct device_node *node = pdev->dev.of_node; 1159d5a80031SBenoit Cousson const struct of_device_id *match; 1160ec155afaSMatt Porter struct pinctrl *pinctrl; 1161ca632f55SGrant Likely 1162ca632f55SGrant Likely master = spi_alloc_master(&pdev->dev, sizeof *mcspi); 1163ca632f55SGrant Likely if (master == NULL) { 1164ca632f55SGrant Likely dev_dbg(&pdev->dev, "master allocation failed\n"); 1165ca632f55SGrant Likely return -ENOMEM; 1166ca632f55SGrant Likely } 1167ca632f55SGrant Likely 1168ca632f55SGrant Likely /* the spi->mode bits understood by this driver: */ 1169ca632f55SGrant Likely master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1170ca632f55SGrant Likely 1171ca632f55SGrant Likely master->setup = omap2_mcspi_setup; 11725fda88f5SShubhrajyoti D master->prepare_transfer_hardware = omap2_prepare_transfer; 11735fda88f5SShubhrajyoti D master->unprepare_transfer_hardware = omap2_unprepare_transfer; 11745fda88f5SShubhrajyoti D master->transfer_one_message = omap2_mcspi_transfer_one_message; 1175ca632f55SGrant Likely master->cleanup = omap2_mcspi_cleanup; 1176d5a80031SBenoit Cousson master->dev.of_node = node; 1177d5a80031SBenoit Cousson 1178*0384e90bSDaniel Mack dev_set_drvdata(&pdev->dev, master); 1179*0384e90bSDaniel Mack 1180*0384e90bSDaniel Mack mcspi = spi_master_get_devdata(master); 1181*0384e90bSDaniel Mack mcspi->master = master; 1182*0384e90bSDaniel Mack 1183d5a80031SBenoit Cousson match = of_match_device(omap_mcspi_of_match, &pdev->dev); 1184d5a80031SBenoit Cousson if (match) { 1185d5a80031SBenoit Cousson u32 num_cs = 1; /* default number of chipselect */ 1186d5a80031SBenoit Cousson pdata = match->data; 1187d5a80031SBenoit Cousson 1188d5a80031SBenoit Cousson of_property_read_u32(node, "ti,spi-num-cs", &num_cs); 1189d5a80031SBenoit Cousson master->num_chipselect = num_cs; 1190d5a80031SBenoit Cousson master->bus_num = bus_num++; 1191*0384e90bSDaniel Mack if (of_get_property(node, "ti,pindir-d0-in-d1-out", NULL)) 1192*0384e90bSDaniel Mack mcspi->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT; 1193d5a80031SBenoit Cousson } else { 1194d5a80031SBenoit Cousson pdata = pdev->dev.platform_data; 1195ca632f55SGrant Likely master->num_chipselect = pdata->num_cs; 1196d5a80031SBenoit Cousson if (pdev->id != -1) 1197d5a80031SBenoit Cousson master->bus_num = pdev->id; 1198*0384e90bSDaniel Mack mcspi->pin_dir = pdata->pin_dir; 1199d5a80031SBenoit Cousson } 1200d5a80031SBenoit Cousson regs_offset = pdata->regs_offset; 1201ca632f55SGrant Likely 1202ca632f55SGrant Likely r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1203ca632f55SGrant Likely if (r == NULL) { 1204ca632f55SGrant Likely status = -ENODEV; 120539f1b565SShubhrajyoti D goto free_master; 1206ca632f55SGrant Likely } 12071458d160SShubhrajyoti D 1208d5a80031SBenoit Cousson r->start += regs_offset; 1209d5a80031SBenoit Cousson r->end += regs_offset; 12101458d160SShubhrajyoti D mcspi->phys = r->start; 1211ca632f55SGrant Likely 12121a77b127SShubhrajyoti D mcspi->base = devm_request_and_ioremap(&pdev->dev, r); 1213ca632f55SGrant Likely if (!mcspi->base) { 1214ca632f55SGrant Likely dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); 1215ca632f55SGrant Likely status = -ENOMEM; 12161a77b127SShubhrajyoti D goto free_master; 1217ca632f55SGrant Likely } 1218ca632f55SGrant Likely 1219ca632f55SGrant Likely mcspi->dev = &pdev->dev; 1220ca632f55SGrant Likely 12211bd897f8SBenoit Cousson INIT_LIST_HEAD(&mcspi->ctx.cs); 1222ca632f55SGrant Likely 1223ca632f55SGrant Likely mcspi->dma_channels = kcalloc(master->num_chipselect, 1224ca632f55SGrant Likely sizeof(struct omap2_mcspi_dma), 1225ca632f55SGrant Likely GFP_KERNEL); 1226ca632f55SGrant Likely 1227ca632f55SGrant Likely if (mcspi->dma_channels == NULL) 12281a77b127SShubhrajyoti D goto free_master; 1229ca632f55SGrant Likely 1230ca632f55SGrant Likely for (i = 0; i < master->num_chipselect; i++) { 1231ca632f55SGrant Likely char dma_ch_name[14]; 1232ca632f55SGrant Likely struct resource *dma_res; 1233ca632f55SGrant Likely 1234ca632f55SGrant Likely sprintf(dma_ch_name, "rx%d", i); 1235ca632f55SGrant Likely dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, 1236ca632f55SGrant Likely dma_ch_name); 1237ca632f55SGrant Likely if (!dma_res) { 1238ca632f55SGrant Likely dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); 1239ca632f55SGrant Likely status = -ENODEV; 1240ca632f55SGrant Likely break; 1241ca632f55SGrant Likely } 1242ca632f55SGrant Likely 1243ca632f55SGrant Likely mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; 1244ca632f55SGrant Likely sprintf(dma_ch_name, "tx%d", i); 1245ca632f55SGrant Likely dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, 1246ca632f55SGrant Likely dma_ch_name); 1247ca632f55SGrant Likely if (!dma_res) { 1248ca632f55SGrant Likely dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); 1249ca632f55SGrant Likely status = -ENODEV; 1250ca632f55SGrant Likely break; 1251ca632f55SGrant Likely } 1252ca632f55SGrant Likely 1253ca632f55SGrant Likely mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; 1254ca632f55SGrant Likely } 1255ca632f55SGrant Likely 125639f1b565SShubhrajyoti D if (status < 0) 125739f1b565SShubhrajyoti D goto dma_chnl_free; 125839f1b565SShubhrajyoti D 1259ec155afaSMatt Porter pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 1260ec155afaSMatt Porter if (IS_ERR(pinctrl)) 1261ec155afaSMatt Porter dev_warn(&pdev->dev, 1262ec155afaSMatt Porter "pins are not configured from the driver\n"); 1263ec155afaSMatt Porter 126427b5284cSShubhrajyoti D pm_runtime_use_autosuspend(&pdev->dev); 126527b5284cSShubhrajyoti D pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1266ca632f55SGrant Likely pm_runtime_enable(&pdev->dev); 1267ca632f55SGrant Likely 1268ca632f55SGrant Likely if (status || omap2_mcspi_master_setup(mcspi) < 0) 126939f1b565SShubhrajyoti D goto disable_pm; 1270ca632f55SGrant Likely 1271ca632f55SGrant Likely status = spi_register_master(master); 1272ca632f55SGrant Likely if (status < 0) 127337a2d84aSShubhrajyoti D goto disable_pm; 1274ca632f55SGrant Likely 1275ca632f55SGrant Likely return status; 1276ca632f55SGrant Likely 127739f1b565SShubhrajyoti D disable_pm: 1278751c925cSShubhrajyoti D pm_runtime_disable(&pdev->dev); 127939f1b565SShubhrajyoti D dma_chnl_free: 1280ca632f55SGrant Likely kfree(mcspi->dma_channels); 128139f1b565SShubhrajyoti D free_master: 128237a2d84aSShubhrajyoti D spi_master_put(master); 1283ca632f55SGrant Likely return status; 1284ca632f55SGrant Likely } 1285ca632f55SGrant Likely 12867d6b6d83SFelipe Balbi static int __devexit omap2_mcspi_remove(struct platform_device *pdev) 1287ca632f55SGrant Likely { 1288ca632f55SGrant Likely struct spi_master *master; 1289ca632f55SGrant Likely struct omap2_mcspi *mcspi; 1290ca632f55SGrant Likely struct omap2_mcspi_dma *dma_channels; 1291ca632f55SGrant Likely 1292ca632f55SGrant Likely master = dev_get_drvdata(&pdev->dev); 1293ca632f55SGrant Likely mcspi = spi_master_get_devdata(master); 1294ca632f55SGrant Likely dma_channels = mcspi->dma_channels; 1295ca632f55SGrant Likely 1296a93a2029SShubhrajyoti D pm_runtime_put_sync(mcspi->dev); 1297751c925cSShubhrajyoti D pm_runtime_disable(&pdev->dev); 1298ca632f55SGrant Likely 1299ca632f55SGrant Likely spi_unregister_master(master); 1300ca632f55SGrant Likely kfree(dma_channels); 1301ca632f55SGrant Likely 1302ca632f55SGrant Likely return 0; 1303ca632f55SGrant Likely } 1304ca632f55SGrant Likely 1305ca632f55SGrant Likely /* work with hotplug and coldplug */ 1306ca632f55SGrant Likely MODULE_ALIAS("platform:omap2_mcspi"); 1307ca632f55SGrant Likely 1308ca632f55SGrant Likely #ifdef CONFIG_SUSPEND 1309ca632f55SGrant Likely /* 1310ca632f55SGrant Likely * When SPI wake up from off-mode, CS is in activate state. If it was in 1311ca632f55SGrant Likely * unactive state when driver was suspend, then force it to unactive state at 1312ca632f55SGrant Likely * wake up. 1313ca632f55SGrant Likely */ 1314ca632f55SGrant Likely static int omap2_mcspi_resume(struct device *dev) 1315ca632f55SGrant Likely { 1316ca632f55SGrant Likely struct spi_master *master = dev_get_drvdata(dev); 1317ca632f55SGrant Likely struct omap2_mcspi *mcspi = spi_master_get_devdata(master); 13181bd897f8SBenoit Cousson struct omap2_mcspi_regs *ctx = &mcspi->ctx; 1319ca632f55SGrant Likely struct omap2_mcspi_cs *cs; 1320ca632f55SGrant Likely 1321034d3dc9SShubhrajyoti D pm_runtime_get_sync(mcspi->dev); 13221bd897f8SBenoit Cousson list_for_each_entry(cs, &ctx->cs, node) { 1323ca632f55SGrant Likely if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { 1324ca632f55SGrant Likely /* 1325ca632f55SGrant Likely * We need to toggle CS state for OMAP take this 1326ca632f55SGrant Likely * change in account. 1327ca632f55SGrant Likely */ 1328af4e944dSShubhrajyoti D cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; 1329ca632f55SGrant Likely __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1330af4e944dSShubhrajyoti D cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; 1331ca632f55SGrant Likely __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); 1332ca632f55SGrant Likely } 1333ca632f55SGrant Likely } 1334034d3dc9SShubhrajyoti D pm_runtime_mark_last_busy(mcspi->dev); 1335034d3dc9SShubhrajyoti D pm_runtime_put_autosuspend(mcspi->dev); 1336ca632f55SGrant Likely return 0; 1337ca632f55SGrant Likely } 1338ca632f55SGrant Likely #else 1339ca632f55SGrant Likely #define omap2_mcspi_resume NULL 1340ca632f55SGrant Likely #endif 1341ca632f55SGrant Likely 1342ca632f55SGrant Likely static const struct dev_pm_ops omap2_mcspi_pm_ops = { 1343ca632f55SGrant Likely .resume = omap2_mcspi_resume, 1344ca632f55SGrant Likely .runtime_resume = omap_mcspi_runtime_resume, 1345ca632f55SGrant Likely }; 1346ca632f55SGrant Likely 1347ca632f55SGrant Likely static struct platform_driver omap2_mcspi_driver = { 1348ca632f55SGrant Likely .driver = { 1349ca632f55SGrant Likely .name = "omap2_mcspi", 1350ca632f55SGrant Likely .owner = THIS_MODULE, 1351d5a80031SBenoit Cousson .pm = &omap2_mcspi_pm_ops, 1352d5a80031SBenoit Cousson .of_match_table = omap_mcspi_of_match, 1353ca632f55SGrant Likely }, 13547d6b6d83SFelipe Balbi .probe = omap2_mcspi_probe, 13557d6b6d83SFelipe Balbi .remove = __devexit_p(omap2_mcspi_remove), 1356ca632f55SGrant Likely }; 1357ca632f55SGrant Likely 13589fdca9dfSFelipe Balbi module_platform_driver(omap2_mcspi_driver); 1359ca632f55SGrant Likely MODULE_LICENSE("GPL"); 1360