1 // SPDX-License-Identifier: GPL-2.0+ 2 3 /* 4 * NXP FlexSPI(FSPI) controller driver. 5 * 6 * Copyright 2019-2020 NXP 7 * Copyright 2020 Puresoftware Ltd. 8 * 9 * FlexSPI is a flexsible SPI host controller which supports two SPI 10 * channels and up to 4 external devices. Each channel supports 11 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional 12 * data lines). 13 * 14 * FlexSPI controller is driven by the LUT(Look-up Table) registers 15 * LUT registers are a look-up-table for sequences of instructions. 16 * A valid sequence consists of four LUT registers. 17 * Maximum 32 LUT sequences can be programmed simultaneously. 18 * 19 * LUTs are being created at run-time based on the commands passed 20 * from the spi-mem framework, thus using single LUT index. 21 * 22 * Software triggered Flash read/write access by IP Bus. 23 * 24 * Memory mapped read access by AHB Bus. 25 * 26 * Based on SPI MEM interface and spi-fsl-qspi.c driver. 27 * 28 * Author: 29 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> 30 * Boris Brezillon <bbrezillon@kernel.org> 31 * Frieder Schrempf <frieder.schrempf@kontron.de> 32 */ 33 34 #include <linux/acpi.h> 35 #include <linux/bitops.h> 36 #include <linux/bitfield.h> 37 #include <linux/clk.h> 38 #include <linux/completion.h> 39 #include <linux/delay.h> 40 #include <linux/err.h> 41 #include <linux/errno.h> 42 #include <linux/interrupt.h> 43 #include <linux/io.h> 44 #include <linux/iopoll.h> 45 #include <linux/jiffies.h> 46 #include <linux/kernel.h> 47 #include <linux/module.h> 48 #include <linux/mutex.h> 49 #include <linux/of.h> 50 #include <linux/platform_device.h> 51 #include <linux/pinctrl/consumer.h> 52 #include <linux/pm_runtime.h> 53 #include <linux/pm_qos.h> 54 #include <linux/regmap.h> 55 #include <linux/sizes.h> 56 #include <linux/sys_soc.h> 57 58 #include <linux/mfd/syscon.h> 59 #include <linux/spi/spi.h> 60 #include <linux/spi/spi-mem.h> 61 62 /* runtime pm timeout */ 63 #define FSPI_RPM_TIMEOUT 50 /* 50ms */ 64 65 /* Registers used by the driver */ 66 #define FSPI_MCR0 0x00 67 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 68 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 69 #define FSPI_MCR0_LEARN_EN BIT(15) 70 #define FSPI_MCR0_SCRFRUN_EN BIT(14) 71 #define FSPI_MCR0_OCTCOMB_EN BIT(13) 72 #define FSPI_MCR0_DOZE_EN BIT(12) 73 #define FSPI_MCR0_HSEN BIT(11) 74 #define FSPI_MCR0_SERCLKDIV BIT(8) 75 #define FSPI_MCR0_ATDF_EN BIT(7) 76 #define FSPI_MCR0_ARDF_EN BIT(6) 77 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 78 #define FSPI_MCR0_END_CFG(x) ((x) << 2) 79 #define FSPI_MCR0_MDIS BIT(1) 80 #define FSPI_MCR0_SWRST BIT(0) 81 82 #define FSPI_MCR1 0x04 83 #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 84 #define FSPI_MCR1_AHB_TIMEOUT(x) (x) 85 86 #define FSPI_MCR2 0x08 87 #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 88 #define FSPI_MCR2_SAMEDEVICEEN BIT(15) 89 #define FSPI_MCR2_CLRLRPHS BIT(14) 90 #define FSPI_MCR2_ABRDATSZ BIT(8) 91 #define FSPI_MCR2_ABRLEARN BIT(7) 92 #define FSPI_MCR2_ABR_READ BIT(6) 93 #define FSPI_MCR2_ABRWRITE BIT(5) 94 #define FSPI_MCR2_ABRDUMMY BIT(4) 95 #define FSPI_MCR2_ABR_MODE BIT(3) 96 #define FSPI_MCR2_ABRCADDR BIT(2) 97 #define FSPI_MCR2_ABRRADDR BIT(1) 98 #define FSPI_MCR2_ABR_CMD BIT(0) 99 100 #define FSPI_AHBCR 0x0c 101 #define FSPI_AHBCR_RDADDROPT BIT(6) 102 #define FSPI_AHBCR_PREF_EN BIT(5) 103 #define FSPI_AHBCR_BUFF_EN BIT(4) 104 #define FSPI_AHBCR_CACH_EN BIT(3) 105 #define FSPI_AHBCR_CLRTXBUF BIT(2) 106 #define FSPI_AHBCR_CLRRXBUF BIT(1) 107 #define FSPI_AHBCR_PAR_EN BIT(0) 108 109 #define FSPI_INTEN 0x10 110 #define FSPI_INTEN_SCLKSBWR BIT(9) 111 #define FSPI_INTEN_SCLKSBRD BIT(8) 112 #define FSPI_INTEN_DATALRNFL BIT(7) 113 #define FSPI_INTEN_IPTXWE BIT(6) 114 #define FSPI_INTEN_IPRXWA BIT(5) 115 #define FSPI_INTEN_AHBCMDERR BIT(4) 116 #define FSPI_INTEN_IPCMDERR BIT(3) 117 #define FSPI_INTEN_AHBCMDGE BIT(2) 118 #define FSPI_INTEN_IPCMDGE BIT(1) 119 #define FSPI_INTEN_IPCMDDONE BIT(0) 120 121 #define FSPI_INTR 0x14 122 #define FSPI_INTR_SCLKSBWR BIT(9) 123 #define FSPI_INTR_SCLKSBRD BIT(8) 124 #define FSPI_INTR_DATALRNFL BIT(7) 125 #define FSPI_INTR_IPTXWE BIT(6) 126 #define FSPI_INTR_IPRXWA BIT(5) 127 #define FSPI_INTR_AHBCMDERR BIT(4) 128 #define FSPI_INTR_IPCMDERR BIT(3) 129 #define FSPI_INTR_AHBCMDGE BIT(2) 130 #define FSPI_INTR_IPCMDGE BIT(1) 131 #define FSPI_INTR_IPCMDDONE BIT(0) 132 133 #define FSPI_LUTKEY 0x18 134 #define FSPI_LUTKEY_VALUE 0x5AF05AF0 135 136 #define FSPI_LCKCR 0x1C 137 138 #define FSPI_LCKER_LOCK 0x1 139 #define FSPI_LCKER_UNLOCK 0x2 140 141 #define FSPI_BUFXCR_INVALID_MSTRID 0xE 142 #define FSPI_AHBRX_BUF0CR0 0x20 143 #define FSPI_AHBRX_BUF1CR0 0x24 144 #define FSPI_AHBRX_BUF2CR0 0x28 145 #define FSPI_AHBRX_BUF3CR0 0x2C 146 #define FSPI_AHBRX_BUF4CR0 0x30 147 #define FSPI_AHBRX_BUF5CR0 0x34 148 #define FSPI_AHBRX_BUF6CR0 0x38 149 #define FSPI_AHBRX_BUF7CR0 0x3C 150 #define FSPI_AHBRXBUF0CR7_PREF BIT(31) 151 152 #define FSPI_AHBRX_BUF0CR1 0x40 153 #define FSPI_AHBRX_BUF1CR1 0x44 154 #define FSPI_AHBRX_BUF2CR1 0x48 155 #define FSPI_AHBRX_BUF3CR1 0x4C 156 #define FSPI_AHBRX_BUF4CR1 0x50 157 #define FSPI_AHBRX_BUF5CR1 0x54 158 #define FSPI_AHBRX_BUF6CR1 0x58 159 #define FSPI_AHBRX_BUF7CR1 0x5C 160 161 #define FSPI_FLSHA1CR0 0x60 162 #define FSPI_FLSHA2CR0 0x64 163 #define FSPI_FLSHB1CR0 0x68 164 #define FSPI_FLSHB2CR0 0x6C 165 #define FSPI_FLSHXCR0_SZ_KB 10 166 #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 167 168 #define FSPI_FLSHA1CR1 0x70 169 #define FSPI_FLSHA2CR1 0x74 170 #define FSPI_FLSHB1CR1 0x78 171 #define FSPI_FLSHB2CR1 0x7C 172 #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 173 #define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 174 #define FSPI_FLSHXCR1_WA BIT(10) 175 #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 176 #define FSPI_FLSHXCR1_TCSS(x) (x) 177 178 #define FSPI_FLSHA1CR2 0x80 179 #define FSPI_FLSHA2CR2 0x84 180 #define FSPI_FLSHB1CR2 0x88 181 #define FSPI_FLSHB2CR2 0x8C 182 #define FSPI_FLSHXCR2_CLRINSP BIT(24) 183 #define FSPI_FLSHXCR2_AWRWAIT BIT(16) 184 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 185 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 186 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 187 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 188 189 #define FSPI_IPCR0 0xA0 190 191 #define FSPI_IPCR1 0xA4 192 #define FSPI_IPCR1_IPAREN BIT(31) 193 #define FSPI_IPCR1_SEQNUM_SHIFT 24 194 #define FSPI_IPCR1_SEQID_SHIFT 16 195 #define FSPI_IPCR1_IDATSZ(x) (x) 196 197 #define FSPI_IPCMD 0xB0 198 #define FSPI_IPCMD_TRG BIT(0) 199 200 #define FSPI_DLPR 0xB4 201 202 #define FSPI_IPRXFCR 0xB8 203 #define FSPI_IPRXFCR_CLR BIT(0) 204 #define FSPI_IPRXFCR_DMA_EN BIT(1) 205 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 206 207 #define FSPI_IPTXFCR 0xBC 208 #define FSPI_IPTXFCR_CLR BIT(0) 209 #define FSPI_IPTXFCR_DMA_EN BIT(1) 210 #define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 211 212 #define FSPI_DLLACR 0xC0 213 #define FSPI_DLLACR_OVRDEN BIT(8) 214 #define FSPI_DLLACR_SLVDLY(x) ((x) << 3) 215 #define FSPI_DLLACR_DLLRESET BIT(1) 216 #define FSPI_DLLACR_DLLEN BIT(0) 217 218 #define FSPI_DLLBCR 0xC4 219 #define FSPI_DLLBCR_OVRDEN BIT(8) 220 #define FSPI_DLLBCR_SLVDLY(x) ((x) << 3) 221 #define FSPI_DLLBCR_DLLRESET BIT(1) 222 #define FSPI_DLLBCR_DLLEN BIT(0) 223 224 #define FSPI_STS0 0xE0 225 #define FSPI_STS0_DLPHB(x) ((x) << 8) 226 #define FSPI_STS0_DLPHA(x) ((x) << 4) 227 #define FSPI_STS0_CMD_SRC(x) ((x) << 2) 228 #define FSPI_STS0_ARB_IDLE BIT(1) 229 #define FSPI_STS0_SEQ_IDLE BIT(0) 230 231 #define FSPI_STS1 0xE4 232 #define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 233 #define FSPI_STS1_IP_ERRID(x) ((x) << 16) 234 #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 235 #define FSPI_STS1_AHB_ERRID(x) (x) 236 237 #define FSPI_STS2 0xE8 238 #define FSPI_STS2_BREFLOCK BIT(17) 239 #define FSPI_STS2_BSLVLOCK BIT(16) 240 #define FSPI_STS2_AREFLOCK BIT(1) 241 #define FSPI_STS2_ASLVLOCK BIT(0) 242 #define FSPI_STS2_AB_LOCK (FSPI_STS2_BREFLOCK | \ 243 FSPI_STS2_BSLVLOCK | \ 244 FSPI_STS2_AREFLOCK | \ 245 FSPI_STS2_ASLVLOCK) 246 247 #define FSPI_AHBSPNST 0xEC 248 #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 249 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 250 #define FSPI_AHBSPNST_ACTIVE BIT(0) 251 252 #define FSPI_IPRXFSTS 0xF0 253 #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 254 #define FSPI_IPRXFSTS_FILL(x) (x) 255 256 #define FSPI_IPTXFSTS 0xF4 257 #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 258 #define FSPI_IPTXFSTS_FILL(x) (x) 259 260 #define FSPI_RFDR 0x100 261 #define FSPI_TFDR 0x180 262 263 #define FSPI_LUT_BASE 0x200 264 265 /* register map end */ 266 267 /* Instruction set for the LUT register. */ 268 #define LUT_STOP 0x00 269 #define LUT_CMD 0x01 270 #define LUT_ADDR 0x02 271 #define LUT_CADDR_SDR 0x03 272 #define LUT_MODE 0x04 273 #define LUT_MODE2 0x05 274 #define LUT_MODE4 0x06 275 #define LUT_MODE8 0x07 276 #define LUT_NXP_WRITE 0x08 277 #define LUT_NXP_READ 0x09 278 #define LUT_LEARN_SDR 0x0A 279 #define LUT_DATSZ_SDR 0x0B 280 #define LUT_DUMMY 0x0C 281 #define LUT_DUMMY_RWDS_SDR 0x0D 282 #define LUT_JMP_ON_CS 0x1F 283 #define LUT_CMD_DDR 0x21 284 #define LUT_ADDR_DDR 0x22 285 #define LUT_CADDR_DDR 0x23 286 #define LUT_MODE_DDR 0x24 287 #define LUT_MODE2_DDR 0x25 288 #define LUT_MODE4_DDR 0x26 289 #define LUT_MODE8_DDR 0x27 290 #define LUT_WRITE_DDR 0x28 291 #define LUT_READ_DDR 0x29 292 #define LUT_LEARN_DDR 0x2A 293 #define LUT_DATSZ_DDR 0x2B 294 #define LUT_DUMMY_DDR 0x2C 295 #define LUT_DUMMY_RWDS_DDR 0x2D 296 297 /* 298 * Calculate number of required PAD bits for LUT register. 299 * 300 * The pad stands for the number of IO lines [0:7]. 301 * For example, the octal read needs eight IO lines, 302 * so you should use LUT_PAD(8). This macro 303 * returns 3 i.e. use eight (2^3) IP lines for read. 304 */ 305 #define LUT_PAD(x) (fls(x) - 1) 306 307 /* 308 * Macro for constructing the LUT entries with the following 309 * register layout: 310 * 311 * --------------------------------------------------- 312 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 313 * --------------------------------------------------- 314 */ 315 #define PAD_SHIFT 8 316 #define INSTR_SHIFT 10 317 #define OPRND_SHIFT 16 318 319 /* Macros for constructing the LUT register. */ 320 #define LUT_DEF(idx, ins, pad, opr) \ 321 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ 322 (opr)) << (((idx) % 2) * OPRND_SHIFT)) 323 324 #define POLL_TOUT 5000 325 #define NXP_FSPI_MAX_CHIPSELECT 4 326 #define NXP_FSPI_MIN_IOMAP SZ_4M 327 328 #define DCFG_RCWSR1 0x100 329 #define SYS_PLL_RAT GENMASK(6, 2) 330 331 /* Access flash memory using IP bus only */ 332 #define FSPI_QUIRK_USE_IP_ONLY BIT(0) 333 /* Disable DTR */ 334 #define FSPI_QUIRK_DISABLE_DTR BIT(1) 335 336 struct nxp_fspi_devtype_data { 337 unsigned int rxfifo; 338 unsigned int txfifo; 339 unsigned int ahb_buf_size; 340 unsigned int quirks; 341 unsigned int lut_num; 342 bool little_endian; 343 }; 344 345 static struct nxp_fspi_devtype_data lx2160a_data = { 346 .rxfifo = SZ_512, /* (64 * 64 bits) */ 347 .txfifo = SZ_1K, /* (128 * 64 bits) */ 348 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 349 .quirks = FSPI_QUIRK_DISABLE_DTR, 350 .lut_num = 32, 351 .little_endian = true, /* little-endian */ 352 }; 353 354 static struct nxp_fspi_devtype_data imx8mm_data = { 355 .rxfifo = SZ_512, /* (64 * 64 bits) */ 356 .txfifo = SZ_1K, /* (128 * 64 bits) */ 357 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 358 .quirks = 0, 359 .lut_num = 32, 360 .little_endian = true, /* little-endian */ 361 }; 362 363 static struct nxp_fspi_devtype_data imx8qxp_data = { 364 .rxfifo = SZ_512, /* (64 * 64 bits) */ 365 .txfifo = SZ_1K, /* (128 * 64 bits) */ 366 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 367 .quirks = 0, 368 .lut_num = 32, 369 .little_endian = true, /* little-endian */ 370 }; 371 372 static struct nxp_fspi_devtype_data imx8dxl_data = { 373 .rxfifo = SZ_512, /* (64 * 64 bits) */ 374 .txfifo = SZ_1K, /* (128 * 64 bits) */ 375 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 376 .quirks = FSPI_QUIRK_USE_IP_ONLY, 377 .lut_num = 32, 378 .little_endian = true, /* little-endian */ 379 }; 380 381 static struct nxp_fspi_devtype_data imx8ulp_data = { 382 .rxfifo = SZ_512, /* (64 * 64 bits) */ 383 .txfifo = SZ_1K, /* (128 * 64 bits) */ 384 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 385 .quirks = 0, 386 .lut_num = 16, 387 .little_endian = true, /* little-endian */ 388 }; 389 390 struct nxp_fspi { 391 void __iomem *iobase; 392 void __iomem *ahb_addr; 393 u32 memmap_phy; 394 u32 memmap_phy_size; 395 u32 memmap_start; 396 u32 memmap_len; 397 struct clk *clk, *clk_en; 398 struct device *dev; 399 struct completion c; 400 struct nxp_fspi_devtype_data *devtype_data; 401 struct mutex lock; 402 struct pm_qos_request pm_qos_req; 403 int selected; 404 #define FSPI_NEED_INIT BIT(0) 405 #define FSPI_DTR_MODE BIT(1) 406 int flags; 407 }; 408 409 static inline int needs_ip_only(struct nxp_fspi *f) 410 { 411 return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; 412 } 413 414 /* 415 * R/W functions for big- or little-endian registers: 416 * The FSPI controller's endianness is independent of 417 * the CPU core's endianness. So far, although the CPU 418 * core is little-endian the FSPI controller can use 419 * big-endian or little-endian. 420 */ 421 static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) 422 { 423 if (f->devtype_data->little_endian) 424 iowrite32(val, addr); 425 else 426 iowrite32be(val, addr); 427 } 428 429 static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) 430 { 431 if (f->devtype_data->little_endian) 432 return ioread32(addr); 433 else 434 return ioread32be(addr); 435 } 436 437 static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id) 438 { 439 struct nxp_fspi *f = dev_id; 440 u32 reg; 441 442 /* clear interrupt */ 443 reg = fspi_readl(f, f->iobase + FSPI_INTR); 444 fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); 445 446 if (reg & FSPI_INTR_IPCMDDONE) 447 complete(&f->c); 448 449 return IRQ_HANDLED; 450 } 451 452 static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) 453 { 454 switch (width) { 455 case 1: 456 case 2: 457 case 4: 458 case 8: 459 return 0; 460 } 461 462 return -ENOTSUPP; 463 } 464 465 static bool nxp_fspi_supports_op(struct spi_mem *mem, 466 const struct spi_mem_op *op) 467 { 468 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); 469 int ret; 470 471 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); 472 473 if (op->addr.nbytes) 474 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); 475 476 if (op->dummy.nbytes) 477 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); 478 479 if (op->data.nbytes) 480 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); 481 482 if (ret) 483 return false; 484 485 /* 486 * The number of address bytes should be equal to or less than 4 bytes. 487 */ 488 if (op->addr.nbytes > 4) 489 return false; 490 491 /* 492 * If requested address value is greater than controller assigned 493 * memory mapped space, return error as it didn't fit in the range 494 * of assigned address space. 495 */ 496 if (op->addr.val >= f->memmap_phy_size) 497 return false; 498 499 /* Max 64 dummy clock cycles supported */ 500 if (op->dummy.buswidth && 501 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 502 return false; 503 504 /* Max data length, check controller limits and alignment */ 505 if (op->data.dir == SPI_MEM_DATA_IN && 506 (op->data.nbytes > f->devtype_data->ahb_buf_size || 507 (op->data.nbytes > f->devtype_data->rxfifo - 4 && 508 !IS_ALIGNED(op->data.nbytes, 8)))) 509 return false; 510 511 if (op->data.dir == SPI_MEM_DATA_OUT && 512 op->data.nbytes > f->devtype_data->txfifo) 513 return false; 514 515 return spi_mem_default_supports_op(mem, op); 516 } 517 518 /* Instead of busy looping invoke readl_poll_timeout functionality. */ 519 static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, 520 u32 mask, u32 delay_us, 521 u32 timeout_us, bool c) 522 { 523 u32 reg; 524 525 if (!f->devtype_data->little_endian) 526 mask = (u32)cpu_to_be32(mask); 527 528 if (c) 529 return readl_poll_timeout(base, reg, (reg & mask), 530 delay_us, timeout_us); 531 else 532 return readl_poll_timeout(base, reg, !(reg & mask), 533 delay_us, timeout_us); 534 } 535 536 /* 537 * If the target device content being changed by Write/Erase, need to 538 * invalidate the AHB buffer. This can be achieved by doing the reset 539 * of controller after setting MCR0[SWRESET] bit. 540 */ 541 static inline void nxp_fspi_invalid(struct nxp_fspi *f) 542 { 543 u32 reg; 544 int ret; 545 546 reg = fspi_readl(f, f->iobase + FSPI_MCR0); 547 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); 548 549 /* w1c register, wait unit clear */ 550 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 551 FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 552 WARN_ON(ret); 553 } 554 555 static void nxp_fspi_prepare_lut(struct nxp_fspi *f, 556 const struct spi_mem_op *op) 557 { 558 void __iomem *base = f->iobase; 559 u32 lutval[4] = {}; 560 int lutidx = 1, i; 561 u32 lut_offset = (f->devtype_data->lut_num - 1) * 4 * 4; 562 u32 target_lut_reg; 563 564 /* cmd */ 565 if (op->cmd.dtr) { 566 lutval[0] |= LUT_DEF(0, LUT_CMD_DDR, LUT_PAD(op->cmd.buswidth), 567 op->cmd.opcode >> 8); 568 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_CMD_DDR, 569 LUT_PAD(op->cmd.buswidth), 570 op->cmd.opcode & 0xFF); 571 lutidx++; 572 } else { 573 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 574 op->cmd.opcode); 575 } 576 577 /* addr bytes */ 578 if (op->addr.nbytes) { 579 lutval[lutidx / 2] |= LUT_DEF(lutidx, op->addr.dtr ? LUT_ADDR_DDR : LUT_ADDR, 580 LUT_PAD(op->addr.buswidth), 581 op->addr.nbytes * 8); 582 lutidx++; 583 } 584 585 /* dummy bytes, if needed */ 586 if (op->dummy.nbytes) { 587 lutval[lutidx / 2] |= LUT_DEF(lutidx, op->dummy.dtr ? LUT_DUMMY_DDR : LUT_DUMMY, 588 /* 589 * Due to FlexSPI controller limitation number of PAD for dummy 590 * buswidth needs to be programmed as equal to data buswidth. 591 */ 592 LUT_PAD(op->data.buswidth), 593 op->dummy.nbytes * 8 / 594 op->dummy.buswidth); 595 lutidx++; 596 } 597 598 /* read/write data bytes */ 599 if (op->data.nbytes) { 600 lutval[lutidx / 2] |= LUT_DEF(lutidx, 601 op->data.dir == SPI_MEM_DATA_IN ? 602 (op->data.dtr ? LUT_READ_DDR : LUT_NXP_READ) : 603 (op->data.dtr ? LUT_WRITE_DDR : LUT_NXP_WRITE), 604 LUT_PAD(op->data.buswidth), 605 0); 606 lutidx++; 607 } 608 609 /* stop condition. */ 610 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 611 612 /* unlock LUT */ 613 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 614 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); 615 616 /* fill LUT */ 617 for (i = 0; i < ARRAY_SIZE(lutval); i++) { 618 target_lut_reg = FSPI_LUT_BASE + lut_offset + i * 4; 619 fspi_writel(f, lutval[i], base + target_lut_reg); 620 } 621 622 dev_dbg(f->dev, "CMD[%02x] lutval[0:%08x 1:%08x 2:%08x 3:%08x], size: 0x%08x\n", 623 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); 624 625 /* lock LUT */ 626 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 627 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); 628 } 629 630 static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f) 631 { 632 int ret; 633 634 if (is_acpi_node(dev_fwnode(f->dev))) 635 return 0; 636 637 ret = clk_prepare_enable(f->clk_en); 638 if (ret) 639 return ret; 640 641 ret = clk_prepare_enable(f->clk); 642 if (ret) { 643 clk_disable_unprepare(f->clk_en); 644 return ret; 645 } 646 647 return 0; 648 } 649 650 static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) 651 { 652 if (is_acpi_node(dev_fwnode(f->dev))) 653 return; 654 655 clk_disable_unprepare(f->clk); 656 clk_disable_unprepare(f->clk_en); 657 658 return; 659 } 660 661 /* 662 * Sample Clock source selection for Flash Reading 663 * Four modes defined by fspi: 664 * mode 0: Dummy Read strobe generated by FlexSPI Controller 665 * and loopback internally 666 * mode 1: Dummy Read strobe generated by FlexSPI Controller 667 * and loopback from DQS pad 668 * mode 2: Reserved 669 * mode 3: Flash provided Read strobe and input from DQS pad 670 * 671 * fspi default use mode 0 after reset 672 */ 673 static void nxp_fspi_select_rx_sample_clk_source(struct nxp_fspi *f, 674 bool op_is_dtr) 675 { 676 u32 reg; 677 678 /* 679 * For 8D-8D-8D mode, need to use mode 3 (Flash provided Read 680 * strobe and input from DQS pad), otherwise read operaton may 681 * meet issue. 682 * This mode require flash device connect the DQS pad on board. 683 * For other modes, still use mode 0, keep align with before. 684 * spi_nor_suspend will disable 8D-8D-8D mode, also need to 685 * change the mode back to mode 0. 686 */ 687 reg = fspi_readl(f, f->iobase + FSPI_MCR0); 688 if (op_is_dtr) 689 reg |= FSPI_MCR0_RXCLKSRC(3); 690 else /*select mode 0 */ 691 reg &= ~FSPI_MCR0_RXCLKSRC(3); 692 fspi_writel(f, reg, f->iobase + FSPI_MCR0); 693 } 694 695 static void nxp_fspi_dll_calibration(struct nxp_fspi *f) 696 { 697 int ret; 698 699 /* Reset the DLL, set the DLLRESET to 1 and then set to 0 */ 700 fspi_writel(f, FSPI_DLLACR_DLLRESET, f->iobase + FSPI_DLLACR); 701 fspi_writel(f, FSPI_DLLBCR_DLLRESET, f->iobase + FSPI_DLLBCR); 702 fspi_writel(f, 0, f->iobase + FSPI_DLLACR); 703 fspi_writel(f, 0, f->iobase + FSPI_DLLBCR); 704 705 /* 706 * Enable the DLL calibration mode. 707 * The delay target for slave delay line is: 708 * ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock. 709 * When clock rate > 100MHz, recommend SLVDLYTARGET is 0xF, which 710 * means half of clock cycle of reference clock. 711 */ 712 fspi_writel(f, FSPI_DLLACR_DLLEN | FSPI_DLLACR_SLVDLY(0xF), 713 f->iobase + FSPI_DLLACR); 714 fspi_writel(f, FSPI_DLLBCR_DLLEN | FSPI_DLLBCR_SLVDLY(0xF), 715 f->iobase + FSPI_DLLBCR); 716 717 /* Wait to get REF/SLV lock */ 718 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_STS2, FSPI_STS2_AB_LOCK, 719 0, POLL_TOUT, true); 720 if (ret) 721 dev_warn(f->dev, "DLL lock failed, please fix it!\n"); 722 } 723 724 /* 725 * Config the DLL register to default value, enable the target clock delay 726 * line delay cell override mode, and use 1 fixed delay cell in DLL delay 727 * chain, this is the suggested setting when clock rate < 100MHz. 728 */ 729 static void nxp_fspi_dll_override(struct nxp_fspi *f) 730 { 731 fspi_writel(f, FSPI_DLLACR_OVRDEN, f->iobase + FSPI_DLLACR); 732 fspi_writel(f, FSPI_DLLBCR_OVRDEN, f->iobase + FSPI_DLLBCR); 733 } 734 735 /* 736 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 737 * register and start base address of the target device. 738 * 739 * (Higher address) 740 * -------- <-- FLSHB2CR0 741 * | B2 | 742 * | | 743 * B2 start address --> -------- <-- FLSHB1CR0 744 * | B1 | 745 * | | 746 * B1 start address --> -------- <-- FLSHA2CR0 747 * | A2 | 748 * | | 749 * A2 start address --> -------- <-- FLSHA1CR0 750 * | A1 | 751 * | | 752 * A1 start address --> -------- (Lower address) 753 * 754 * 755 * Start base address defines the starting address range for given CS and 756 * FSPI_FLSHXXCR0 defines the size of the target device connected at given CS. 757 * 758 * But, different targets are having different combinations of number of CS, 759 * some targets only have single CS or two CS covering controller's full 760 * memory mapped space area. 761 * Thus, implementation is being done as independent of the size and number 762 * of the connected target device. 763 * Assign controller memory mapped space size as the size to the connected 764 * target device. 765 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected 766 * chip-select Flash configuration register. 767 * 768 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the 769 * memory mapped size of the controller. 770 * Value for rest of the CS FLSHxxCR0 register would be zero. 771 * 772 */ 773 static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi, 774 const struct spi_mem_op *op) 775 { 776 /* flexspi only support one DTR mode: 8D-8D-8D */ 777 bool op_is_dtr = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr; 778 unsigned long rate = op->max_freq; 779 int ret; 780 uint64_t size_kb; 781 782 /* 783 * Return, if previously selected target device is same as current 784 * requested target device. Also the DTR or STR mode do not change. 785 */ 786 if ((f->selected == spi_get_chipselect(spi, 0)) && 787 (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr)) 788 return; 789 790 /* Reset FLSHxxCR0 registers */ 791 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); 792 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); 793 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); 794 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); 795 796 /* Assign controller memory mapped space as size, KBytes, of flash. */ 797 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); 798 799 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + 800 4 * spi_get_chipselect(spi, 0)); 801 802 dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0)); 803 804 nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr); 805 806 if (op_is_dtr) { 807 f->flags |= FSPI_DTR_MODE; 808 /* For DTR mode, flexspi will default div 2 and output to device. 809 * so here to config the root clock to 2 * device rate. 810 */ 811 rate = rate * 2; 812 } else { 813 f->flags &= ~FSPI_DTR_MODE; 814 } 815 816 nxp_fspi_clk_disable_unprep(f); 817 818 ret = clk_set_rate(f->clk, rate); 819 if (ret) 820 return; 821 822 ret = nxp_fspi_clk_prep_enable(f); 823 if (ret) 824 return; 825 826 /* 827 * If clock rate > 100MHz, then switch from DLL override mode to 828 * DLL calibration mode. 829 */ 830 if (rate > 100000000) 831 nxp_fspi_dll_calibration(f); 832 else 833 nxp_fspi_dll_override(f); 834 835 f->selected = spi_get_chipselect(spi, 0); 836 } 837 838 static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) 839 { 840 u32 start = op->addr.val; 841 u32 len = op->data.nbytes; 842 843 /* if necessary, ioremap before AHB read */ 844 if ((!f->ahb_addr) || start < f->memmap_start || 845 start + len > f->memmap_start + f->memmap_len) { 846 if (f->ahb_addr) 847 iounmap(f->ahb_addr); 848 849 f->memmap_start = start; 850 f->memmap_len = max_t(u32, len, NXP_FSPI_MIN_IOMAP); 851 852 f->ahb_addr = ioremap(f->memmap_phy + f->memmap_start, 853 f->memmap_len); 854 855 if (!f->ahb_addr) { 856 dev_err(f->dev, "failed to alloc memory\n"); 857 return -ENOMEM; 858 } 859 } 860 861 /* Read out the data directly from the AHB buffer. */ 862 memcpy_fromio(op->data.buf.in, 863 f->ahb_addr + start - f->memmap_start, len); 864 865 return 0; 866 } 867 868 static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, 869 const struct spi_mem_op *op) 870 { 871 void __iomem *base = f->iobase; 872 int i, ret; 873 u8 *buf = (u8 *) op->data.buf.out; 874 875 /* clear the TX FIFO. */ 876 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); 877 878 /* 879 * Default value of water mark level is 8 bytes, hence in single 880 * write request controller can write max 8 bytes of data. 881 */ 882 883 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { 884 /* Wait for TXFIFO empty */ 885 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 886 FSPI_INTR_IPTXWE, 0, 887 POLL_TOUT, true); 888 WARN_ON(ret); 889 890 fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR); 891 fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4); 892 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 893 } 894 895 if (i < op->data.nbytes) { 896 u32 data = 0; 897 int j; 898 int remaining = op->data.nbytes - i; 899 /* Wait for TXFIFO empty */ 900 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 901 FSPI_INTR_IPTXWE, 0, 902 POLL_TOUT, true); 903 WARN_ON(ret); 904 905 for (j = 0; j < ALIGN(remaining, 4); j += 4) { 906 memcpy(&data, buf + i + j, min_t(int, 4, remaining - j)); 907 fspi_writel(f, data, base + FSPI_TFDR + j); 908 } 909 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 910 } 911 } 912 913 static void nxp_fspi_read_rxfifo(struct nxp_fspi *f, 914 const struct spi_mem_op *op) 915 { 916 void __iomem *base = f->iobase; 917 int i, ret; 918 int len = op->data.nbytes; 919 u8 *buf = (u8 *) op->data.buf.in; 920 921 /* 922 * Default value of water mark level is 8 bytes, hence in single 923 * read request controller can read max 8 bytes of data. 924 */ 925 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) { 926 /* Wait for RXFIFO available */ 927 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 928 FSPI_INTR_IPRXWA, 0, 929 POLL_TOUT, true); 930 WARN_ON(ret); 931 932 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); 933 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); 934 /* move the FIFO pointer */ 935 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 936 } 937 938 if (i < len) { 939 u32 tmp; 940 int size, j; 941 942 buf = op->data.buf.in + i; 943 /* Wait for RXFIFO available */ 944 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 945 FSPI_INTR_IPRXWA, 0, 946 POLL_TOUT, true); 947 WARN_ON(ret); 948 949 len = op->data.nbytes - i; 950 for (j = 0; j < op->data.nbytes - i; j += 4) { 951 tmp = fspi_readl(f, base + FSPI_RFDR + j); 952 size = min(len, 4); 953 memcpy(buf + j, &tmp, size); 954 len -= size; 955 } 956 } 957 958 /* invalid the RXFIFO */ 959 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); 960 /* move the FIFO pointer */ 961 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 962 } 963 964 static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) 965 { 966 void __iomem *base = f->iobase; 967 int seqnum = 0; 968 int err = 0; 969 u32 reg, seqid_lut; 970 971 reg = fspi_readl(f, base + FSPI_IPRXFCR); 972 /* invalid RXFIFO first */ 973 reg &= ~FSPI_IPRXFCR_DMA_EN; 974 reg = reg | FSPI_IPRXFCR_CLR; 975 fspi_writel(f, reg, base + FSPI_IPRXFCR); 976 977 init_completion(&f->c); 978 979 fspi_writel(f, op->addr.val, base + FSPI_IPCR0); 980 /* 981 * Always start the sequence at the same index since we update 982 * the LUT at each exec_op() call. And also specify the DATA 983 * length, since it's has not been specified in the LUT. 984 */ 985 seqid_lut = f->devtype_data->lut_num - 1; 986 fspi_writel(f, op->data.nbytes | 987 (seqid_lut << FSPI_IPCR1_SEQID_SHIFT) | 988 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), 989 base + FSPI_IPCR1); 990 991 /* Trigger the LUT now. */ 992 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); 993 994 /* Wait for the interrupt. */ 995 if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) 996 err = -ETIMEDOUT; 997 998 /* Invoke IP data read, if request is of data read. */ 999 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 1000 nxp_fspi_read_rxfifo(f, op); 1001 1002 return err; 1003 } 1004 1005 static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 1006 { 1007 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); 1008 int err = 0; 1009 1010 guard(mutex)(&f->lock); 1011 1012 err = pm_runtime_get_sync(f->dev); 1013 if (err < 0) { 1014 dev_err(f->dev, "Failed to enable clock %d\n", __LINE__); 1015 return err; 1016 } 1017 1018 /* Wait for controller being ready. */ 1019 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, 1020 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); 1021 WARN_ON(err); 1022 1023 nxp_fspi_select_mem(f, mem->spi, op); 1024 1025 nxp_fspi_prepare_lut(f, op); 1026 /* 1027 * If we have large chunks of data, we read them through the AHB bus by 1028 * accessing the mapped memory. In all other cases we use IP commands 1029 * to access the flash. Read via AHB bus may be corrupted due to 1030 * existence of an errata and therefore discard AHB read in such cases. 1031 */ 1032 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && 1033 op->data.dir == SPI_MEM_DATA_IN && 1034 !needs_ip_only(f)) { 1035 err = nxp_fspi_read_ahb(f, op); 1036 } else { 1037 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 1038 nxp_fspi_fill_txfifo(f, op); 1039 1040 err = nxp_fspi_do_op(f, op); 1041 } 1042 1043 /* Invalidate the data in the AHB buffer. */ 1044 nxp_fspi_invalid(f); 1045 1046 pm_runtime_put_autosuspend(f->dev); 1047 1048 return err; 1049 } 1050 1051 static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 1052 { 1053 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); 1054 1055 if (op->data.dir == SPI_MEM_DATA_OUT) { 1056 if (op->data.nbytes > f->devtype_data->txfifo) 1057 op->data.nbytes = f->devtype_data->txfifo; 1058 } else { 1059 if (op->data.nbytes > f->devtype_data->ahb_buf_size) 1060 op->data.nbytes = f->devtype_data->ahb_buf_size; 1061 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) 1062 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 1063 } 1064 1065 /* Limit data bytes to RX FIFO in case of IP read only */ 1066 if (op->data.dir == SPI_MEM_DATA_IN && 1067 needs_ip_only(f) && 1068 op->data.nbytes > f->devtype_data->rxfifo) 1069 op->data.nbytes = f->devtype_data->rxfifo; 1070 1071 return 0; 1072 } 1073 1074 static void erratum_err050568(struct nxp_fspi *f) 1075 { 1076 static const struct soc_device_attribute ls1028a_soc_attr[] = { 1077 { .family = "QorIQ LS1028A" }, 1078 { /* sentinel */ } 1079 }; 1080 struct regmap *map; 1081 u32 val, sys_pll_ratio; 1082 int ret; 1083 1084 /* Check for LS1028A family */ 1085 if (!soc_device_match(ls1028a_soc_attr)) { 1086 dev_dbg(f->dev, "Errata applicable only for LS1028A\n"); 1087 return; 1088 } 1089 1090 map = syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg"); 1091 if (IS_ERR(map)) { 1092 dev_err(f->dev, "No syscon regmap\n"); 1093 goto err; 1094 } 1095 1096 ret = regmap_read(map, DCFG_RCWSR1, &val); 1097 if (ret < 0) 1098 goto err; 1099 1100 sys_pll_ratio = FIELD_GET(SYS_PLL_RAT, val); 1101 dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio); 1102 1103 /* Use IP bus only if platform clock is 300MHz */ 1104 if (sys_pll_ratio == 3) 1105 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; 1106 1107 return; 1108 1109 err: 1110 dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n"); 1111 } 1112 1113 static int nxp_fspi_default_setup(struct nxp_fspi *f) 1114 { 1115 void __iomem *base = f->iobase; 1116 int ret, i; 1117 u32 reg, seqid_lut; 1118 1119 /* disable and unprepare clock to avoid glitch pass to controller */ 1120 nxp_fspi_clk_disable_unprep(f); 1121 1122 /* the default frequency, we will change it later if necessary. */ 1123 ret = clk_set_rate(f->clk, 20000000); 1124 if (ret) 1125 return ret; 1126 1127 ret = nxp_fspi_clk_prep_enable(f); 1128 if (ret) 1129 return ret; 1130 1131 /* 1132 * ERR050568: Flash access by FlexSPI AHB command may not work with 1133 * platform frequency equal to 300 MHz on LS1028A. 1134 * LS1028A reuses LX2160A compatible entry. Make errata applicable for 1135 * Layerscape LS1028A platform. 1136 */ 1137 if (of_device_is_compatible(f->dev->of_node, "nxp,lx2160a-fspi")) 1138 erratum_err050568(f); 1139 1140 /* Reset the module */ 1141 /* w1c register, wait unit clear */ 1142 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 1143 FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 1144 WARN_ON(ret); 1145 1146 /* Disable the module */ 1147 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); 1148 1149 nxp_fspi_dll_override(f); 1150 1151 /* enable module */ 1152 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | 1153 FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN, 1154 base + FSPI_MCR0); 1155 1156 /* 1157 * Disable same device enable bit and configure all target devices 1158 * independently. 1159 */ 1160 reg = fspi_readl(f, f->iobase + FSPI_MCR2); 1161 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); 1162 fspi_writel(f, reg, base + FSPI_MCR2); 1163 1164 /* AHB configuration for access buffer 0~7. */ 1165 for (i = 0; i < 7; i++) 1166 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); 1167 1168 /* 1169 * Set ADATSZ with the maximum AHB buffer size to improve the read 1170 * performance. 1171 */ 1172 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | 1173 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); 1174 1175 /* prefetch and no start address alignment limitation */ 1176 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, 1177 base + FSPI_AHBCR); 1178 1179 /* Reset the FLSHxCR1 registers. */ 1180 reg = FSPI_FLSHXCR1_TCSH(0x3) | FSPI_FLSHXCR1_TCSS(0x3); 1181 fspi_writel(f, reg, base + FSPI_FLSHA1CR1); 1182 fspi_writel(f, reg, base + FSPI_FLSHA2CR1); 1183 fspi_writel(f, reg, base + FSPI_FLSHB1CR1); 1184 fspi_writel(f, reg, base + FSPI_FLSHB2CR1); 1185 1186 /* 1187 * The driver only uses one single LUT entry, that is updated on 1188 * each call of exec_op(). Index 0 is preset at boot with a basic 1189 * read operation, so let's use the last entry. 1190 */ 1191 seqid_lut = f->devtype_data->lut_num - 1; 1192 /* AHB Read - Set lut sequence ID for all CS. */ 1193 fspi_writel(f, seqid_lut, base + FSPI_FLSHA1CR2); 1194 fspi_writel(f, seqid_lut, base + FSPI_FLSHA2CR2); 1195 fspi_writel(f, seqid_lut, base + FSPI_FLSHB1CR2); 1196 fspi_writel(f, seqid_lut, base + FSPI_FLSHB2CR2); 1197 1198 f->selected = -1; 1199 1200 /* enable the interrupt */ 1201 fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN); 1202 1203 return 0; 1204 } 1205 1206 static const char *nxp_fspi_get_name(struct spi_mem *mem) 1207 { 1208 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); 1209 struct device *dev = &mem->spi->dev; 1210 const char *name; 1211 1212 // Set custom name derived from the platform_device of the controller. 1213 if (of_get_available_child_count(f->dev->of_node) == 1) 1214 return dev_name(f->dev); 1215 1216 name = devm_kasprintf(dev, GFP_KERNEL, 1217 "%s-%d", dev_name(f->dev), 1218 spi_get_chipselect(mem->spi, 0)); 1219 1220 if (!name) { 1221 dev_err(dev, "failed to get memory for custom flash name\n"); 1222 return ERR_PTR(-ENOMEM); 1223 } 1224 1225 return name; 1226 } 1227 1228 static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { 1229 .adjust_op_size = nxp_fspi_adjust_op_size, 1230 .supports_op = nxp_fspi_supports_op, 1231 .exec_op = nxp_fspi_exec_op, 1232 .get_name = nxp_fspi_get_name, 1233 }; 1234 1235 static const struct spi_controller_mem_caps nxp_fspi_mem_caps = { 1236 .dtr = true, 1237 .swap16 = false, 1238 .per_op_freq = true, 1239 }; 1240 1241 static const struct spi_controller_mem_caps nxp_fspi_mem_caps_disable_dtr = { 1242 .dtr = false, 1243 .per_op_freq = true, 1244 }; 1245 1246 static void nxp_fspi_cleanup(void *data) 1247 { 1248 struct nxp_fspi *f = data; 1249 1250 /* enable clock first since there is register access */ 1251 pm_runtime_get_sync(f->dev); 1252 1253 /* disable the hardware */ 1254 fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); 1255 1256 pm_runtime_disable(f->dev); 1257 pm_runtime_put_noidle(f->dev); 1258 nxp_fspi_clk_disable_unprep(f); 1259 1260 if (f->ahb_addr) 1261 iounmap(f->ahb_addr); 1262 } 1263 1264 static int nxp_fspi_probe(struct platform_device *pdev) 1265 { 1266 struct spi_controller *ctlr; 1267 struct device *dev = &pdev->dev; 1268 struct device_node *np = dev->of_node; 1269 struct resource *res; 1270 struct nxp_fspi *f; 1271 int ret, irq; 1272 u32 reg; 1273 1274 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*f)); 1275 if (!ctlr) 1276 return -ENOMEM; 1277 1278 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | 1279 SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; 1280 1281 f = spi_controller_get_devdata(ctlr); 1282 f->dev = dev; 1283 f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev); 1284 if (!f->devtype_data) 1285 return -ENODEV; 1286 1287 platform_set_drvdata(pdev, f); 1288 1289 /* find the resources - configuration register address space */ 1290 if (is_acpi_node(dev_fwnode(f->dev))) 1291 f->iobase = devm_platform_ioremap_resource(pdev, 0); 1292 else 1293 f->iobase = devm_platform_ioremap_resource_byname(pdev, "fspi_base"); 1294 if (IS_ERR(f->iobase)) 1295 return PTR_ERR(f->iobase); 1296 1297 /* find the resources - controller memory mapped space */ 1298 if (is_acpi_node(dev_fwnode(f->dev))) 1299 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1300 else 1301 res = platform_get_resource_byname(pdev, 1302 IORESOURCE_MEM, "fspi_mmap"); 1303 if (!res) 1304 return -ENODEV; 1305 1306 /* assign memory mapped starting address and mapped size. */ 1307 f->memmap_phy = res->start; 1308 f->memmap_phy_size = resource_size(res); 1309 1310 /* find the clocks */ 1311 if (dev_of_node(&pdev->dev)) { 1312 f->clk_en = devm_clk_get(dev, "fspi_en"); 1313 if (IS_ERR(f->clk_en)) 1314 return PTR_ERR(f->clk_en); 1315 1316 f->clk = devm_clk_get(dev, "fspi"); 1317 if (IS_ERR(f->clk)) 1318 return PTR_ERR(f->clk); 1319 } 1320 1321 /* find the irq */ 1322 irq = platform_get_irq(pdev, 0); 1323 if (irq < 0) 1324 return dev_err_probe(dev, irq, "Failed to get irq source"); 1325 1326 pm_runtime_enable(dev); 1327 pm_runtime_set_autosuspend_delay(dev, FSPI_RPM_TIMEOUT); 1328 pm_runtime_use_autosuspend(dev); 1329 1330 /* enable clock */ 1331 ret = pm_runtime_get_sync(f->dev); 1332 if (ret < 0) 1333 return dev_err_probe(dev, ret, "Failed to enable clock"); 1334 1335 /* Clear potential interrupts */ 1336 reg = fspi_readl(f, f->iobase + FSPI_INTR); 1337 if (reg) 1338 fspi_writel(f, reg, f->iobase + FSPI_INTR); 1339 1340 nxp_fspi_default_setup(f); 1341 1342 ret = pm_runtime_put_sync(dev); 1343 if (ret < 0) 1344 return dev_err_probe(dev, ret, "Failed to disable clock"); 1345 1346 ret = devm_request_irq(dev, irq, 1347 nxp_fspi_irq_handler, 0, pdev->name, f); 1348 if (ret) 1349 return dev_err_probe(dev, ret, "Failed to request irq\n"); 1350 1351 ret = devm_mutex_init(dev, &f->lock); 1352 if (ret) 1353 return dev_err_probe(dev, ret, "Failed to initialize lock\n"); 1354 1355 ctlr->bus_num = -1; 1356 ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; 1357 ctlr->mem_ops = &nxp_fspi_mem_ops; 1358 1359 if (f->devtype_data->quirks & FSPI_QUIRK_DISABLE_DTR) 1360 ctlr->mem_caps = &nxp_fspi_mem_caps_disable_dtr; 1361 else 1362 ctlr->mem_caps = &nxp_fspi_mem_caps; 1363 1364 ctlr->dev.of_node = np; 1365 1366 ret = devm_add_action_or_reset(dev, nxp_fspi_cleanup, f); 1367 if (ret) 1368 return ret; 1369 1370 return devm_spi_register_controller(&pdev->dev, ctlr); 1371 } 1372 1373 static int nxp_fspi_runtime_suspend(struct device *dev) 1374 { 1375 struct nxp_fspi *f = dev_get_drvdata(dev); 1376 1377 nxp_fspi_clk_disable_unprep(f); 1378 1379 return 0; 1380 } 1381 1382 static int nxp_fspi_runtime_resume(struct device *dev) 1383 { 1384 struct nxp_fspi *f = dev_get_drvdata(dev); 1385 int ret; 1386 1387 ret = nxp_fspi_clk_prep_enable(f); 1388 if (ret) 1389 return ret; 1390 1391 if (f->flags & FSPI_NEED_INIT) { 1392 nxp_fspi_default_setup(f); 1393 ret = pinctrl_pm_select_default_state(dev); 1394 if (ret) 1395 dev_err(dev, "select flexspi default pinctrl failed!\n"); 1396 f->flags &= ~FSPI_NEED_INIT; 1397 } 1398 1399 return ret; 1400 } 1401 1402 static int nxp_fspi_suspend(struct device *dev) 1403 { 1404 struct nxp_fspi *f = dev_get_drvdata(dev); 1405 int ret; 1406 1407 ret = pinctrl_pm_select_sleep_state(dev); 1408 if (ret) { 1409 dev_err(dev, "select flexspi sleep pinctrl failed!\n"); 1410 return ret; 1411 } 1412 1413 f->flags |= FSPI_NEED_INIT; 1414 1415 return pm_runtime_force_suspend(dev); 1416 } 1417 1418 static const struct dev_pm_ops nxp_fspi_pm_ops = { 1419 RUNTIME_PM_OPS(nxp_fspi_runtime_suspend, nxp_fspi_runtime_resume, NULL) 1420 SYSTEM_SLEEP_PM_OPS(nxp_fspi_suspend, pm_runtime_force_resume) 1421 }; 1422 1423 static const struct of_device_id nxp_fspi_dt_ids[] = { 1424 { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, }, 1425 { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, }, 1426 { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, }, 1427 { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, 1428 { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, }, 1429 { .compatible = "nxp,imx8ulp-fspi", .data = (void *)&imx8ulp_data, }, 1430 { /* sentinel */ } 1431 }; 1432 MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids); 1433 1434 #ifdef CONFIG_ACPI 1435 static const struct acpi_device_id nxp_fspi_acpi_ids[] = { 1436 { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, }, 1437 {} 1438 }; 1439 MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids); 1440 #endif 1441 1442 static struct platform_driver nxp_fspi_driver = { 1443 .driver = { 1444 .name = "nxp-fspi", 1445 .of_match_table = nxp_fspi_dt_ids, 1446 .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids), 1447 .pm = pm_ptr(&nxp_fspi_pm_ops), 1448 }, 1449 .probe = nxp_fspi_probe, 1450 }; 1451 module_platform_driver(nxp_fspi_driver); 1452 1453 MODULE_DESCRIPTION("NXP FSPI Controller Driver"); 1454 MODULE_AUTHOR("NXP Semiconductor"); 1455 MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>"); 1456 MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>"); 1457 MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>"); 1458 MODULE_LICENSE("GPL v2"); 1459