1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019 Nuvoton Technology corporation. 3 4 #include <linux/bits.h> 5 #include <linux/init.h> 6 #include <linux/kernel.h> 7 #include <linux/device.h> 8 #include <linux/module.h> 9 #include <linux/ioport.h> 10 #include <linux/clk.h> 11 #include <linux/platform_device.h> 12 #include <linux/io.h> 13 #include <linux/vmalloc.h> 14 #include <linux/regmap.h> 15 #include <linux/of.h> 16 #include <linux/minmax.h> 17 #include <linux/spi/spi-mem.h> 18 #include <linux/mfd/syscon.h> 19 20 /* NPCM7xx GCR module */ 21 #define NPCM7XX_INTCR3_OFFSET 0x9C 22 #define NPCM7XX_INTCR3_FIU_FIX BIT(6) 23 24 /* Flash Interface Unit (FIU) Registers */ 25 #define NPCM_FIU_DRD_CFG 0x00 26 #define NPCM_FIU_DWR_CFG 0x04 27 #define NPCM_FIU_UMA_CFG 0x08 28 #define NPCM_FIU_UMA_CTS 0x0C 29 #define NPCM_FIU_UMA_CMD 0x10 30 #define NPCM_FIU_UMA_ADDR 0x14 31 #define NPCM_FIU_PRT_CFG 0x18 32 #define NPCM_FIU_UMA_DW0 0x20 33 #define NPCM_FIU_UMA_DW1 0x24 34 #define NPCM_FIU_UMA_DW2 0x28 35 #define NPCM_FIU_UMA_DW3 0x2C 36 #define NPCM_FIU_UMA_DR0 0x30 37 #define NPCM_FIU_UMA_DR1 0x34 38 #define NPCM_FIU_UMA_DR2 0x38 39 #define NPCM_FIU_UMA_DR3 0x3C 40 #define NPCM_FIU_CFG 0x78 41 #define NPCM_FIU_MAX_REG_LIMIT 0x80 42 43 /* FIU Direct Read Configuration Register */ 44 #define NPCM_FIU_DRD_CFG_LCK BIT(31) 45 #define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24) 46 #define NPCM_FIU_DRD_CFG_ADDSIZ GENMASK(17, 16) 47 #define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12) 48 #define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8) 49 #define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0) 50 #define NPCM_FIU_DRD_ADDSIZ_SHIFT 16 51 #define NPCM_FIU_DRD_DBW_SHIFT 12 52 #define NPCM_FIU_DRD_ACCTYPE_SHIFT 8 53 54 /* FIU Direct Write Configuration Register */ 55 #define NPCM_FIU_DWR_CFG_LCK BIT(31) 56 #define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24) 57 #define NPCM_FIU_DWR_CFG_ADDSIZ GENMASK(17, 16) 58 #define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10) 59 #define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8) 60 #define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0) 61 #define NPCM_FIU_DWR_ADDSIZ_SHIFT 16 62 #define NPCM_FIU_DWR_ABPCK_SHIFT 10 63 #define NPCM_FIU_DWR_DBPCK_SHIFT 8 64 65 /* FIU UMA Configuration Register */ 66 #define NPCM_FIU_UMA_CFG_LCK BIT(31) 67 #define NPCM_FIU_UMA_CFG_CMMLCK BIT(30) 68 #define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24) 69 #define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21) 70 #define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16) 71 #define NPCM_FIU_UMA_CFG_ADDSIZ GENMASK(13, 11) 72 #define NPCM_FIU_UMA_CFG_CMDSIZ BIT(10) 73 #define NPCM_FIU_UMA_CFG_RDBPCK GENMASK(9, 8) 74 #define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6) 75 #define NPCM_FIU_UMA_CFG_WDBPCK GENMASK(5, 4) 76 #define NPCM_FIU_UMA_CFG_ADBPCK GENMASK(3, 2) 77 #define NPCM_FIU_UMA_CFG_CMBPCK GENMASK(1, 0) 78 #define NPCM_FIU_UMA_CFG_ADBPCK_SHIFT 2 79 #define NPCM_FIU_UMA_CFG_WDBPCK_SHIFT 4 80 #define NPCM_FIU_UMA_CFG_DBPCK_SHIFT 6 81 #define NPCM_FIU_UMA_CFG_RDBPCK_SHIFT 8 82 #define NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT 11 83 #define NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT 16 84 #define NPCM_FIU_UMA_CFG_DBSIZ_SHIFT 21 85 #define NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT 24 86 87 /* FIU UMA Control and Status Register */ 88 #define NPCM_FIU_UMA_CTS_RDYIE BIT(25) 89 #define NPCM_FIU_UMA_CTS_RDYST BIT(24) 90 #define NPCM_FIU_UMA_CTS_SW_CS BIT(16) 91 #define NPCM_FIU_UMA_CTS_DEV_NUM GENMASK(9, 8) 92 #define NPCM_FIU_UMA_CTS_EXEC_DONE BIT(0) 93 #define NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT 8 94 95 /* FIU UMA Command Register */ 96 #define NPCM_FIU_UMA_CMD_DUM3 GENMASK(31, 24) 97 #define NPCM_FIU_UMA_CMD_DUM2 GENMASK(23, 16) 98 #define NPCM_FIU_UMA_CMD_DUM1 GENMASK(15, 8) 99 #define NPCM_FIU_UMA_CMD_CMD GENMASK(7, 0) 100 101 /* FIU UMA Address Register */ 102 #define NPCM_FIU_UMA_ADDR_UMA_ADDR GENMASK(31, 0) 103 #define NPCM_FIU_UMA_ADDR_AB3 GENMASK(31, 24) 104 #define NPCM_FIU_UMA_ADDR_AB2 GENMASK(23, 16) 105 #define NPCM_FIU_UMA_ADDR_AB1 GENMASK(15, 8) 106 #define NPCM_FIU_UMA_ADDR_AB0 GENMASK(7, 0) 107 108 /* FIU UMA Write Data Bytes 0-3 Register */ 109 #define NPCM_FIU_UMA_DW0_WB3 GENMASK(31, 24) 110 #define NPCM_FIU_UMA_DW0_WB2 GENMASK(23, 16) 111 #define NPCM_FIU_UMA_DW0_WB1 GENMASK(15, 8) 112 #define NPCM_FIU_UMA_DW0_WB0 GENMASK(7, 0) 113 114 /* FIU UMA Write Data Bytes 4-7 Register */ 115 #define NPCM_FIU_UMA_DW1_WB7 GENMASK(31, 24) 116 #define NPCM_FIU_UMA_DW1_WB6 GENMASK(23, 16) 117 #define NPCM_FIU_UMA_DW1_WB5 GENMASK(15, 8) 118 #define NPCM_FIU_UMA_DW1_WB4 GENMASK(7, 0) 119 120 /* FIU UMA Write Data Bytes 8-11 Register */ 121 #define NPCM_FIU_UMA_DW2_WB11 GENMASK(31, 24) 122 #define NPCM_FIU_UMA_DW2_WB10 GENMASK(23, 16) 123 #define NPCM_FIU_UMA_DW2_WB9 GENMASK(15, 8) 124 #define NPCM_FIU_UMA_DW2_WB8 GENMASK(7, 0) 125 126 /* FIU UMA Write Data Bytes 12-15 Register */ 127 #define NPCM_FIU_UMA_DW3_WB15 GENMASK(31, 24) 128 #define NPCM_FIU_UMA_DW3_WB14 GENMASK(23, 16) 129 #define NPCM_FIU_UMA_DW3_WB13 GENMASK(15, 8) 130 #define NPCM_FIU_UMA_DW3_WB12 GENMASK(7, 0) 131 132 /* FIU UMA Read Data Bytes 0-3 Register */ 133 #define NPCM_FIU_UMA_DR0_RB3 GENMASK(31, 24) 134 #define NPCM_FIU_UMA_DR0_RB2 GENMASK(23, 16) 135 #define NPCM_FIU_UMA_DR0_RB1 GENMASK(15, 8) 136 #define NPCM_FIU_UMA_DR0_RB0 GENMASK(7, 0) 137 138 /* FIU UMA Read Data Bytes 4-7 Register */ 139 #define NPCM_FIU_UMA_DR1_RB15 GENMASK(31, 24) 140 #define NPCM_FIU_UMA_DR1_RB14 GENMASK(23, 16) 141 #define NPCM_FIU_UMA_DR1_RB13 GENMASK(15, 8) 142 #define NPCM_FIU_UMA_DR1_RB12 GENMASK(7, 0) 143 144 /* FIU UMA Read Data Bytes 8-11 Register */ 145 #define NPCM_FIU_UMA_DR2_RB15 GENMASK(31, 24) 146 #define NPCM_FIU_UMA_DR2_RB14 GENMASK(23, 16) 147 #define NPCM_FIU_UMA_DR2_RB13 GENMASK(15, 8) 148 #define NPCM_FIU_UMA_DR2_RB12 GENMASK(7, 0) 149 150 /* FIU UMA Read Data Bytes 12-15 Register */ 151 #define NPCM_FIU_UMA_DR3_RB15 GENMASK(31, 24) 152 #define NPCM_FIU_UMA_DR3_RB14 GENMASK(23, 16) 153 #define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8) 154 #define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0) 155 156 /* FIU Configuration Register */ 157 #define NPCM_FIU_CFG_FIU_FIX BIT(31) 158 159 /* FIU Read Mode */ 160 enum { 161 DRD_SINGLE_WIRE_MODE = 0, 162 DRD_DUAL_IO_MODE = 1, 163 DRD_QUAD_IO_MODE = 2, 164 DRD_SPI_X_MODE = 3, 165 }; 166 167 enum { 168 DWR_ABPCK_BIT_PER_CLK = 0, 169 DWR_ABPCK_2_BIT_PER_CLK = 1, 170 DWR_ABPCK_4_BIT_PER_CLK = 2, 171 }; 172 173 enum { 174 DWR_DBPCK_BIT_PER_CLK = 0, 175 DWR_DBPCK_2_BIT_PER_CLK = 1, 176 DWR_DBPCK_4_BIT_PER_CLK = 2, 177 }; 178 179 #define NPCM_FIU_DRD_16_BYTE_BURST 0x3000000 180 #define NPCM_FIU_DWR_16_BYTE_BURST 0x3000000 181 182 #define MAP_SIZE_128MB 0x8000000 183 #define MAP_SIZE_16MB 0x1000000 184 #define MAP_SIZE_8MB 0x800000 185 186 #define FIU_DRD_MAX_DUMMY_NUMBER 3 187 #define NPCM_MAX_CHIP_NUM 4 188 #define CHUNK_SIZE 16 189 #define UMA_MICRO_SEC_TIMEOUT 150 190 191 enum { 192 FIU0 = 0, 193 FIU3, 194 FIUX, 195 FIU1, 196 }; 197 198 struct npcm_fiu_info { 199 char *name; 200 u32 fiu_id; 201 u32 max_map_size; 202 u32 max_cs; 203 }; 204 205 struct fiu_data { 206 const struct npcm_fiu_info *npcm_fiu_data_info; 207 int fiu_max; 208 }; 209 210 static const struct npcm_fiu_info npcm7xx_fiu_info[] = { 211 {.name = "FIU0", .fiu_id = FIU0, 212 .max_map_size = MAP_SIZE_128MB, .max_cs = 2}, 213 {.name = "FIU3", .fiu_id = FIU3, 214 .max_map_size = MAP_SIZE_128MB, .max_cs = 4}, 215 {.name = "FIUX", .fiu_id = FIUX, 216 .max_map_size = MAP_SIZE_16MB, .max_cs = 2} }; 217 218 static const struct fiu_data npcm7xx_fiu_data = { 219 .npcm_fiu_data_info = npcm7xx_fiu_info, 220 .fiu_max = 3, 221 }; 222 223 static const struct npcm_fiu_info npxm8xx_fiu_info[] = { 224 {.name = "FIU0", .fiu_id = FIU0, 225 .max_map_size = MAP_SIZE_128MB, .max_cs = 2}, 226 {.name = "FIU3", .fiu_id = FIU3, 227 .max_map_size = MAP_SIZE_128MB, .max_cs = 4}, 228 {.name = "FIUX", .fiu_id = FIUX, 229 .max_map_size = MAP_SIZE_16MB, .max_cs = 2}, 230 {.name = "FIU1", .fiu_id = FIU1, 231 .max_map_size = MAP_SIZE_16MB, .max_cs = 4} }; 232 233 static const struct fiu_data npxm8xx_fiu_data = { 234 .npcm_fiu_data_info = npxm8xx_fiu_info, 235 .fiu_max = 4, 236 }; 237 238 struct npcm_fiu_spi; 239 240 struct npcm_fiu_chip { 241 void __iomem *flash_region_mapped_ptr; 242 struct npcm_fiu_spi *fiu; 243 unsigned long clkrate; 244 u32 chipselect; 245 }; 246 247 struct npcm_fiu_spi { 248 struct npcm_fiu_chip chip[NPCM_MAX_CHIP_NUM]; 249 const struct npcm_fiu_info *info; 250 struct spi_mem_op drd_op; 251 struct resource *res_mem; 252 struct regmap *regmap; 253 unsigned long clkrate; 254 struct device *dev; 255 struct clk *clk; 256 bool spix_mode; 257 }; 258 259 static const struct regmap_config npcm_mtd_regmap_config = { 260 .reg_bits = 32, 261 .val_bits = 32, 262 .reg_stride = 4, 263 .max_register = NPCM_FIU_MAX_REG_LIMIT, 264 }; 265 266 static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu, 267 const struct spi_mem_op *op) 268 { 269 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 270 NPCM_FIU_DRD_CFG_ACCTYPE, 271 ilog2(op->addr.buswidth) << 272 NPCM_FIU_DRD_ACCTYPE_SHIFT); 273 fiu->drd_op.addr.buswidth = op->addr.buswidth; 274 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 275 NPCM_FIU_DRD_CFG_DBW, 276 op->dummy.nbytes << NPCM_FIU_DRD_DBW_SHIFT); 277 fiu->drd_op.dummy.nbytes = op->dummy.nbytes; 278 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 279 NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode); 280 fiu->drd_op.cmd.opcode = op->cmd.opcode; 281 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 282 NPCM_FIU_DRD_CFG_ADDSIZ, 283 (op->addr.nbytes - 3) << NPCM_FIU_DRD_ADDSIZ_SHIFT); 284 fiu->drd_op.addr.nbytes = op->addr.nbytes; 285 } 286 287 static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, 288 u64 offs, size_t len, void *buf) 289 { 290 struct npcm_fiu_spi *fiu = 291 spi_controller_get_devdata(desc->mem->spi->controller); 292 struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)]; 293 void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr + 294 offs); 295 u8 *buf_rx = buf; 296 u32 i; 297 298 if (fiu->spix_mode) { 299 for (i = 0 ; i < len ; i++) 300 *(buf_rx + i) = ioread8(src + i); 301 } else { 302 if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth || 303 desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes || 304 desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode || 305 desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes) 306 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl); 307 308 memcpy_fromio(buf_rx, src, len); 309 } 310 311 return len; 312 } 313 314 static ssize_t npcm_fiu_direct_write(struct spi_mem_dirmap_desc *desc, 315 u64 offs, size_t len, const void *buf) 316 { 317 struct npcm_fiu_spi *fiu = 318 spi_controller_get_devdata(desc->mem->spi->controller); 319 struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)]; 320 void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr + 321 offs); 322 const u8 *buf_tx = buf; 323 u32 i; 324 325 if (fiu->spix_mode) 326 for (i = 0 ; i < len ; i++) 327 iowrite8(*(buf_tx + i), dst + i); 328 else 329 memcpy_toio(dst, buf_tx, len); 330 331 return len; 332 } 333 334 static int npcm_fiu_uma_read(struct spi_mem *mem, 335 const struct spi_mem_op *op, u32 addr, 336 bool is_address_size, u8 *data, u32 data_size) 337 { 338 struct npcm_fiu_spi *fiu = 339 spi_controller_get_devdata(mem->spi->controller); 340 u32 uma_cfg = BIT(10); 341 u32 data_reg[4]; 342 int ret; 343 u32 val; 344 u32 i; 345 346 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 347 NPCM_FIU_UMA_CTS_DEV_NUM, 348 (spi_get_chipselect(mem->spi, 0) << 349 NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); 350 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, 351 NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode); 352 353 if (is_address_size) { 354 uma_cfg |= ilog2(op->cmd.buswidth); 355 uma_cfg |= ilog2(op->addr.buswidth) 356 << NPCM_FIU_UMA_CFG_ADBPCK_SHIFT; 357 if (op->dummy.nbytes) 358 uma_cfg |= ilog2(op->dummy.buswidth) 359 << NPCM_FIU_UMA_CFG_DBPCK_SHIFT; 360 uma_cfg |= ilog2(op->data.buswidth) 361 << NPCM_FIU_UMA_CFG_RDBPCK_SHIFT; 362 uma_cfg |= op->dummy.nbytes << NPCM_FIU_UMA_CFG_DBSIZ_SHIFT; 363 uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT; 364 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr); 365 } else { 366 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0); 367 } 368 369 uma_cfg |= data_size << NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT; 370 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg); 371 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 372 NPCM_FIU_UMA_CTS_EXEC_DONE, 373 NPCM_FIU_UMA_CTS_EXEC_DONE); 374 ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, 375 (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0, 376 UMA_MICRO_SEC_TIMEOUT); 377 if (ret) 378 return ret; 379 380 if (data_size) { 381 for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++) 382 regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4), 383 &data_reg[i]); 384 memcpy(data, data_reg, data_size); 385 } 386 387 return 0; 388 } 389 390 static int npcm_fiu_uma_write(struct spi_mem *mem, 391 const struct spi_mem_op *op, u8 cmd, 392 bool is_address_size, u8 *data, u32 data_size) 393 { 394 struct npcm_fiu_spi *fiu = 395 spi_controller_get_devdata(mem->spi->controller); 396 u32 uma_cfg = BIT(10); 397 u32 data_reg[4] = {0}; 398 u32 val; 399 u32 i; 400 401 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 402 NPCM_FIU_UMA_CTS_DEV_NUM, 403 (spi_get_chipselect(mem->spi, 0) << 404 NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); 405 406 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, 407 NPCM_FIU_UMA_CMD_CMD, cmd); 408 409 if (data_size) { 410 memcpy(data_reg, data, data_size); 411 for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++) 412 regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4), 413 data_reg[i]); 414 } 415 416 if (is_address_size) { 417 uma_cfg |= ilog2(op->cmd.buswidth); 418 uma_cfg |= ilog2(op->addr.buswidth) << 419 NPCM_FIU_UMA_CFG_ADBPCK_SHIFT; 420 uma_cfg |= ilog2(op->data.buswidth) << 421 NPCM_FIU_UMA_CFG_WDBPCK_SHIFT; 422 uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT; 423 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val); 424 } else { 425 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0); 426 } 427 428 uma_cfg |= (data_size << NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT); 429 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg); 430 431 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 432 NPCM_FIU_UMA_CTS_EXEC_DONE, 433 NPCM_FIU_UMA_CTS_EXEC_DONE); 434 435 return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, 436 (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0, 437 UMA_MICRO_SEC_TIMEOUT); 438 } 439 440 static int npcm_fiu_manualwrite(struct spi_mem *mem, 441 const struct spi_mem_op *op) 442 { 443 struct npcm_fiu_spi *fiu = 444 spi_controller_get_devdata(mem->spi->controller); 445 u8 *data = (u8 *)op->data.buf.out; 446 u32 num_data_chunks; 447 u32 remain_data; 448 u32 idx = 0; 449 int ret; 450 451 num_data_chunks = op->data.nbytes / CHUNK_SIZE; 452 remain_data = op->data.nbytes % CHUNK_SIZE; 453 454 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 455 NPCM_FIU_UMA_CTS_DEV_NUM, 456 (spi_get_chipselect(mem->spi, 0) << 457 NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); 458 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 459 NPCM_FIU_UMA_CTS_SW_CS, 0); 460 461 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, true, NULL, 0); 462 if (ret) 463 return ret; 464 465 /* Starting the data writing loop in multiples of 8 */ 466 for (idx = 0; idx < num_data_chunks; ++idx) { 467 ret = npcm_fiu_uma_write(mem, op, data[0], false, 468 &data[1], CHUNK_SIZE - 1); 469 if (ret) 470 return ret; 471 472 data += CHUNK_SIZE; 473 } 474 475 /* Handling chunk remains */ 476 if (remain_data > 0) { 477 ret = npcm_fiu_uma_write(mem, op, data[0], false, 478 &data[1], remain_data - 1); 479 if (ret) 480 return ret; 481 } 482 483 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, 484 NPCM_FIU_UMA_CTS_SW_CS, NPCM_FIU_UMA_CTS_SW_CS); 485 486 return 0; 487 } 488 489 static int npcm_fiu_read(struct spi_mem *mem, const struct spi_mem_op *op) 490 { 491 u8 *data = op->data.buf.in; 492 int i, readlen, currlen; 493 u8 *buf_ptr; 494 u32 addr; 495 int ret; 496 497 i = 0; 498 currlen = op->data.nbytes; 499 500 do { 501 addr = ((u32)op->addr.val + i); 502 readlen = min_t(int, currlen, 16); 503 504 buf_ptr = data + i; 505 ret = npcm_fiu_uma_read(mem, op, addr, true, buf_ptr, 506 readlen); 507 if (ret) 508 return ret; 509 510 i += readlen; 511 currlen -= 16; 512 } while (currlen > 0); 513 514 return 0; 515 } 516 517 static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu) 518 { 519 regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG, 520 NPCM_FIU_DWR_16_BYTE_BURST); 521 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG, 522 NPCM_FIU_DWR_CFG_ABPCK, 523 DWR_ABPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_ABPCK_SHIFT); 524 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG, 525 NPCM_FIU_DWR_CFG_DBPCK, 526 DWR_DBPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_DBPCK_SHIFT); 527 } 528 529 static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu) 530 { 531 u32 rx_dummy = 0; 532 533 regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG, 534 NPCM_FIU_DRD_16_BYTE_BURST); 535 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 536 NPCM_FIU_DRD_CFG_ACCTYPE, 537 DRD_SPI_X_MODE << NPCM_FIU_DRD_ACCTYPE_SHIFT); 538 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, 539 NPCM_FIU_DRD_CFG_DBW, 540 rx_dummy << NPCM_FIU_DRD_DBW_SHIFT); 541 } 542 543 static int npcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 544 { 545 struct npcm_fiu_spi *fiu = 546 spi_controller_get_devdata(mem->spi->controller); 547 struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(mem->spi, 0)]; 548 int ret = 0; 549 u8 *buf; 550 551 if (fiu->spix_mode || op->addr.nbytes > 4) 552 return -EOPNOTSUPP; 553 554 if (fiu->clkrate != chip->clkrate) { 555 ret = clk_set_rate(fiu->clk, chip->clkrate); 556 if (ret < 0) 557 dev_warn(fiu->dev, "Failed setting %lu frequency, stay at %lu frequency\n", 558 chip->clkrate, fiu->clkrate); 559 else 560 fiu->clkrate = chip->clkrate; 561 } 562 563 if (op->data.dir == SPI_MEM_DATA_IN) { 564 if (!op->addr.nbytes) { 565 buf = op->data.buf.in; 566 ret = npcm_fiu_uma_read(mem, op, op->addr.val, false, 567 buf, op->data.nbytes); 568 } else { 569 ret = npcm_fiu_read(mem, op); 570 } 571 } else { 572 if (!op->addr.nbytes && !op->data.nbytes) 573 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, 574 NULL, 0); 575 if (op->addr.nbytes && !op->data.nbytes) { 576 int i; 577 u8 buf_addr[4]; 578 u32 addr = op->addr.val; 579 580 for (i = op->addr.nbytes - 1; i >= 0; i--) { 581 buf_addr[i] = addr & 0xff; 582 addr >>= 8; 583 } 584 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, 585 buf_addr, op->addr.nbytes); 586 } 587 if (!op->addr.nbytes && op->data.nbytes) 588 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, 589 (u8 *)op->data.buf.out, 590 op->data.nbytes); 591 if (op->addr.nbytes && op->data.nbytes) 592 ret = npcm_fiu_manualwrite(mem, op); 593 } 594 595 return ret; 596 } 597 598 static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) 599 { 600 struct npcm_fiu_spi *fiu = 601 spi_controller_get_devdata(desc->mem->spi->controller); 602 struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)]; 603 struct regmap *gcr_regmap; 604 605 if (!fiu->res_mem) { 606 dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n"); 607 desc->nodirmap = true; 608 return 0; 609 } 610 611 if (!fiu->spix_mode && 612 desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { 613 desc->nodirmap = true; 614 return 0; 615 } 616 617 if (!chip->flash_region_mapped_ptr) { 618 chip->flash_region_mapped_ptr = 619 devm_ioremap(fiu->dev, (fiu->res_mem->start + 620 (fiu->info->max_map_size * 621 spi_get_chipselect(desc->mem->spi, 0))), 622 (u32)desc->info.length); 623 if (!chip->flash_region_mapped_ptr) { 624 dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n"); 625 desc->nodirmap = true; 626 return 0; 627 } 628 } 629 630 if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) { 631 gcr_regmap = 632 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); 633 if (IS_ERR(gcr_regmap)) { 634 dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n"); 635 desc->nodirmap = true; 636 return 0; 637 } 638 regmap_update_bits(gcr_regmap, NPCM7XX_INTCR3_OFFSET, 639 NPCM7XX_INTCR3_FIU_FIX, 640 NPCM7XX_INTCR3_FIU_FIX); 641 } else { 642 regmap_update_bits(fiu->regmap, NPCM_FIU_CFG, 643 NPCM_FIU_CFG_FIU_FIX, 644 NPCM_FIU_CFG_FIU_FIX); 645 } 646 647 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) { 648 if (!fiu->spix_mode) 649 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl); 650 else 651 npcm_fiux_set_direct_rd(fiu); 652 653 } else { 654 npcm_fiux_set_direct_wr(fiu); 655 } 656 657 return 0; 658 } 659 660 static int npcm_fiu_setup(struct spi_device *spi) 661 { 662 struct spi_controller *ctrl = spi->controller; 663 struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl); 664 struct npcm_fiu_chip *chip; 665 666 chip = &fiu->chip[spi_get_chipselect(spi, 0)]; 667 chip->fiu = fiu; 668 chip->chipselect = spi_get_chipselect(spi, 0); 669 chip->clkrate = spi->max_speed_hz; 670 671 fiu->clkrate = clk_get_rate(fiu->clk); 672 673 return 0; 674 } 675 676 static const struct spi_controller_mem_ops npcm_fiu_mem_ops = { 677 .exec_op = npcm_fiu_exec_op, 678 .dirmap_create = npcm_fiu_dirmap_create, 679 .dirmap_read = npcm_fiu_direct_read, 680 .dirmap_write = npcm_fiu_direct_write, 681 }; 682 683 static const struct of_device_id npcm_fiu_dt_ids[] = { 684 { .compatible = "nuvoton,npcm750-fiu", .data = &npcm7xx_fiu_data }, 685 { .compatible = "nuvoton,npcm845-fiu", .data = &npxm8xx_fiu_data }, 686 { /* sentinel */ } 687 }; 688 689 static int npcm_fiu_probe(struct platform_device *pdev) 690 { 691 const struct fiu_data *fiu_data_match; 692 struct device *dev = &pdev->dev; 693 struct spi_controller *ctrl; 694 struct npcm_fiu_spi *fiu; 695 void __iomem *regbase; 696 int id; 697 698 ctrl = devm_spi_alloc_host(dev, sizeof(*fiu)); 699 if (!ctrl) 700 return -ENOMEM; 701 702 fiu = spi_controller_get_devdata(ctrl); 703 704 fiu_data_match = of_device_get_match_data(dev); 705 if (!fiu_data_match) { 706 dev_err(dev, "No compatible OF match\n"); 707 return -ENODEV; 708 } 709 710 id = of_alias_get_id(dev->of_node, "fiu"); 711 if (id < 0 || id >= fiu_data_match->fiu_max) { 712 dev_err(dev, "Invalid platform device id: %d\n", id); 713 return -EINVAL; 714 } 715 716 fiu->info = &fiu_data_match->npcm_fiu_data_info[id]; 717 718 platform_set_drvdata(pdev, fiu); 719 fiu->dev = dev; 720 721 regbase = devm_platform_ioremap_resource_byname(pdev, "control"); 722 if (IS_ERR(regbase)) 723 return PTR_ERR(regbase); 724 725 fiu->regmap = devm_regmap_init_mmio(dev, regbase, 726 &npcm_mtd_regmap_config); 727 if (IS_ERR(fiu->regmap)) { 728 dev_err(dev, "Failed to create regmap\n"); 729 return PTR_ERR(fiu->regmap); 730 } 731 732 fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, 733 "memory"); 734 fiu->clk = devm_clk_get_enabled(dev, NULL); 735 if (IS_ERR(fiu->clk)) 736 return PTR_ERR(fiu->clk); 737 738 fiu->spix_mode = of_property_read_bool(dev->of_node, 739 "nuvoton,spix-mode"); 740 741 platform_set_drvdata(pdev, fiu); 742 743 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD 744 | SPI_TX_DUAL | SPI_TX_QUAD; 745 ctrl->setup = npcm_fiu_setup; 746 ctrl->bus_num = -1; 747 ctrl->mem_ops = &npcm_fiu_mem_ops; 748 ctrl->num_chipselect = fiu->info->max_cs; 749 ctrl->dev.of_node = dev->of_node; 750 751 return devm_spi_register_controller(dev, ctrl); 752 } 753 754 static void npcm_fiu_remove(struct platform_device *pdev) 755 { 756 } 757 758 MODULE_DEVICE_TABLE(of, npcm_fiu_dt_ids); 759 760 static struct platform_driver npcm_fiu_driver = { 761 .driver = { 762 .name = "NPCM-FIU", 763 .bus = &platform_bus_type, 764 .of_match_table = npcm_fiu_dt_ids, 765 }, 766 .probe = npcm_fiu_probe, 767 .remove = npcm_fiu_remove, 768 }; 769 module_platform_driver(npcm_fiu_driver); 770 771 MODULE_DESCRIPTION("Nuvoton FLASH Interface Unit SPI Controller Driver"); 772 MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); 773 MODULE_LICENSE("GPL v2"); 774