1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Leilk Liu <leilk.liu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/platform_data/spi-mt65xx.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/spi-mem.h> 22 #include <linux/dma-mapping.h> 23 24 #define SPI_CFG0_REG 0x0000 25 #define SPI_CFG1_REG 0x0004 26 #define SPI_TX_SRC_REG 0x0008 27 #define SPI_RX_DST_REG 0x000c 28 #define SPI_TX_DATA_REG 0x0010 29 #define SPI_RX_DATA_REG 0x0014 30 #define SPI_CMD_REG 0x0018 31 #define SPI_STATUS0_REG 0x001c 32 #define SPI_PAD_SEL_REG 0x0024 33 #define SPI_CFG2_REG 0x0028 34 #define SPI_TX_SRC_REG_64 0x002c 35 #define SPI_RX_DST_REG_64 0x0030 36 #define SPI_CFG3_IPM_REG 0x0040 37 38 #define SPI_CFG0_SCK_HIGH_OFFSET 0 39 #define SPI_CFG0_SCK_LOW_OFFSET 8 40 #define SPI_CFG0_CS_HOLD_OFFSET 16 41 #define SPI_CFG0_CS_SETUP_OFFSET 24 42 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 43 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 44 45 #define SPI_CFG1_CS_IDLE_OFFSET 0 46 #define SPI_CFG1_PACKET_LOOP_OFFSET 8 47 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 48 #define SPI_CFG1_GET_TICK_DLY_OFFSET 29 49 #define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30 50 51 #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000 52 #define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000 53 54 #define SPI_CFG1_CS_IDLE_MASK 0xff 55 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 56 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 57 #define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) 58 #define SPI_CFG2_SCK_HIGH_OFFSET 0 59 #define SPI_CFG2_SCK_LOW_OFFSET 16 60 61 #define SPI_CMD_ACT BIT(0) 62 #define SPI_CMD_RESUME BIT(1) 63 #define SPI_CMD_RST BIT(2) 64 #define SPI_CMD_PAUSE_EN BIT(4) 65 #define SPI_CMD_DEASSERT BIT(5) 66 #define SPI_CMD_SAMPLE_SEL BIT(6) 67 #define SPI_CMD_CS_POL BIT(7) 68 #define SPI_CMD_CPHA BIT(8) 69 #define SPI_CMD_CPOL BIT(9) 70 #define SPI_CMD_RX_DMA BIT(10) 71 #define SPI_CMD_TX_DMA BIT(11) 72 #define SPI_CMD_TXMSBF BIT(12) 73 #define SPI_CMD_RXMSBF BIT(13) 74 #define SPI_CMD_RX_ENDIAN BIT(14) 75 #define SPI_CMD_TX_ENDIAN BIT(15) 76 #define SPI_CMD_FINISH_IE BIT(16) 77 #define SPI_CMD_PAUSE_IE BIT(17) 78 #define SPI_CMD_IPM_NONIDLE_MODE BIT(19) 79 #define SPI_CMD_IPM_SPIM_LOOP BIT(21) 80 #define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 81 82 #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) 83 84 #define PIN_MODE_CFG(x) ((x) / 2) 85 86 #define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) 87 #define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) 88 #define SPI_CFG3_IPM_XMODE_EN BIT(4) 89 #define SPI_CFG3_IPM_NODATA_FLAG BIT(5) 90 #define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 91 #define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 92 93 #define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) 94 #define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) 95 #define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) 96 97 #define MT8173_SPI_MAX_PAD_SEL 3 98 99 #define MTK_SPI_PAUSE_INT_STATUS 0x2 100 101 #define MTK_SPI_MAX_FIFO_SIZE 32U 102 #define MTK_SPI_PACKET_SIZE 1024 103 #define MTK_SPI_IPM_PACKET_SIZE SZ_64K 104 #define MTK_SPI_IPM_PACKET_LOOP SZ_256 105 106 #define MTK_SPI_IDLE 0 107 #define MTK_SPI_PAUSED 1 108 109 #define MTK_SPI_32BITS_MASK (0xffffffff) 110 111 #define DMA_ADDR_EXT_BITS (36) 112 #define DMA_ADDR_DEF_BITS (32) 113 114 /** 115 * struct mtk_spi_compatible - device data structure 116 * @need_pad_sel: Enable pad (pins) selection in SPI controller 117 * @must_tx: Must explicitly send dummy TX bytes to do RX only transfer 118 * @enhance_timing: Enable adjusting cfg register to enhance time accuracy 119 * @dma_ext: DMA address extension supported 120 * @no_need_unprepare: Don't unprepare the SPI clk during runtime 121 * @ipm_design: Adjust/extend registers to support IPM design IP features 122 */ 123 struct mtk_spi_compatible { 124 bool need_pad_sel; 125 bool must_tx; 126 bool enhance_timing; 127 bool dma_ext; 128 bool no_need_unprepare; 129 bool ipm_design; 130 }; 131 132 /** 133 * struct mtk_spi - SPI driver instance 134 * @base: Start address of the SPI controller registers 135 * @state: SPI controller state 136 * @pad_num: Number of pad_sel entries 137 * @pad_sel: Groups of pins to select 138 * @parent_clk: Parent of sel_clk 139 * @sel_clk: SPI host mux clock 140 * @spi_clk: Peripheral clock 141 * @spi_hclk: AHB bus clock 142 * @cur_transfer: Currently processed SPI transfer 143 * @xfer_len: Number of bytes to transfer 144 * @num_xfered: Number of transferred bytes 145 * @tx_sgl: TX transfer scatterlist 146 * @rx_sgl: RX transfer scatterlist 147 * @tx_sgl_len: Size of TX DMA transfer 148 * @rx_sgl_len: Size of RX DMA transfer 149 * @dev_comp: Device data structure 150 * @spi_clk_hz: Current SPI clock in Hz 151 * @spimem_done: SPI-MEM operation completion 152 * @use_spimem: Enables SPI-MEM 153 * @dev: Device pointer 154 * @tx_dma: DMA start for SPI-MEM TX 155 * @rx_dma: DMA start for SPI-MEM RX 156 */ 157 struct mtk_spi { 158 void __iomem *base; 159 u32 state; 160 int pad_num; 161 u32 *pad_sel; 162 struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk; 163 struct spi_transfer *cur_transfer; 164 u32 xfer_len; 165 u32 num_xfered; 166 struct scatterlist *tx_sgl, *rx_sgl; 167 u32 tx_sgl_len, rx_sgl_len; 168 const struct mtk_spi_compatible *dev_comp; 169 u32 spi_clk_hz; 170 struct completion spimem_done; 171 bool use_spimem; 172 struct device *dev; 173 dma_addr_t tx_dma; 174 dma_addr_t rx_dma; 175 }; 176 177 static const struct mtk_spi_compatible mtk_common_compat; 178 179 static const struct mtk_spi_compatible mt2712_compat = { 180 .must_tx = true, 181 }; 182 183 static const struct mtk_spi_compatible mtk_ipm_compat = { 184 .enhance_timing = true, 185 .dma_ext = true, 186 .ipm_design = true, 187 }; 188 189 static const struct mtk_spi_compatible mt6765_compat = { 190 .need_pad_sel = true, 191 .must_tx = true, 192 .enhance_timing = true, 193 .dma_ext = true, 194 }; 195 196 static const struct mtk_spi_compatible mt7622_compat = { 197 .must_tx = true, 198 .enhance_timing = true, 199 }; 200 201 static const struct mtk_spi_compatible mt8173_compat = { 202 .need_pad_sel = true, 203 .must_tx = true, 204 }; 205 206 static const struct mtk_spi_compatible mt8183_compat = { 207 .need_pad_sel = true, 208 .must_tx = true, 209 .enhance_timing = true, 210 }; 211 212 static const struct mtk_spi_compatible mt6893_compat = { 213 .need_pad_sel = true, 214 .must_tx = true, 215 .enhance_timing = true, 216 .dma_ext = true, 217 .no_need_unprepare = true, 218 }; 219 220 /* 221 * A piece of default chip info unless the platform 222 * supplies it. 223 */ 224 static const struct mtk_chip_config mtk_default_chip_info = { 225 .sample_sel = 0, 226 .tick_delay = 0, 227 }; 228 229 static const struct of_device_id mtk_spi_of_match[] = { 230 { .compatible = "mediatek,spi-ipm", 231 .data = (void *)&mtk_ipm_compat, 232 }, 233 { .compatible = "mediatek,mt2701-spi", 234 .data = (void *)&mtk_common_compat, 235 }, 236 { .compatible = "mediatek,mt2712-spi", 237 .data = (void *)&mt2712_compat, 238 }, 239 { .compatible = "mediatek,mt6589-spi", 240 .data = (void *)&mtk_common_compat, 241 }, 242 { .compatible = "mediatek,mt6765-spi", 243 .data = (void *)&mt6765_compat, 244 }, 245 { .compatible = "mediatek,mt7622-spi", 246 .data = (void *)&mt7622_compat, 247 }, 248 { .compatible = "mediatek,mt7629-spi", 249 .data = (void *)&mt7622_compat, 250 }, 251 { .compatible = "mediatek,mt8135-spi", 252 .data = (void *)&mtk_common_compat, 253 }, 254 { .compatible = "mediatek,mt8173-spi", 255 .data = (void *)&mt8173_compat, 256 }, 257 { .compatible = "mediatek,mt8183-spi", 258 .data = (void *)&mt8183_compat, 259 }, 260 { .compatible = "mediatek,mt8192-spi", 261 .data = (void *)&mt6765_compat, 262 }, 263 { .compatible = "mediatek,mt6893-spi", 264 .data = (void *)&mt6893_compat, 265 }, 266 {} 267 }; 268 MODULE_DEVICE_TABLE(of, mtk_spi_of_match); 269 270 static void mtk_spi_reset(struct mtk_spi *mdata) 271 { 272 u32 reg_val; 273 274 /* set the software reset bit in SPI_CMD_REG. */ 275 reg_val = readl(mdata->base + SPI_CMD_REG); 276 reg_val |= SPI_CMD_RST; 277 writel(reg_val, mdata->base + SPI_CMD_REG); 278 279 reg_val = readl(mdata->base + SPI_CMD_REG); 280 reg_val &= ~SPI_CMD_RST; 281 writel(reg_val, mdata->base + SPI_CMD_REG); 282 } 283 284 static int mtk_spi_set_hw_cs_timing(struct spi_device *spi) 285 { 286 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); 287 struct spi_delay *cs_setup = &spi->cs_setup; 288 struct spi_delay *cs_hold = &spi->cs_hold; 289 struct spi_delay *cs_inactive = &spi->cs_inactive; 290 u32 setup, hold, inactive; 291 u32 reg_val; 292 int delay; 293 294 delay = spi_delay_to_ns(cs_setup, NULL); 295 if (delay < 0) 296 return delay; 297 setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; 298 299 delay = spi_delay_to_ns(cs_hold, NULL); 300 if (delay < 0) 301 return delay; 302 hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; 303 304 delay = spi_delay_to_ns(cs_inactive, NULL); 305 if (delay < 0) 306 return delay; 307 inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; 308 309 if (hold || setup) { 310 reg_val = readl(mdata->base + SPI_CFG0_REG); 311 if (mdata->dev_comp->enhance_timing) { 312 if (hold) { 313 hold = min_t(u32, hold, 0x10000); 314 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 315 reg_val |= (((hold - 1) & 0xffff) 316 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 317 } 318 if (setup) { 319 setup = min_t(u32, setup, 0x10000); 320 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 321 reg_val |= (((setup - 1) & 0xffff) 322 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 323 } 324 } else { 325 if (hold) { 326 hold = min_t(u32, hold, 0x100); 327 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); 328 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); 329 } 330 if (setup) { 331 setup = min_t(u32, setup, 0x100); 332 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); 333 reg_val |= (((setup - 1) & 0xff) 334 << SPI_CFG0_CS_SETUP_OFFSET); 335 } 336 } 337 writel(reg_val, mdata->base + SPI_CFG0_REG); 338 } 339 340 if (inactive) { 341 inactive = min_t(u32, inactive, 0x100); 342 reg_val = readl(mdata->base + SPI_CFG1_REG); 343 reg_val &= ~SPI_CFG1_CS_IDLE_MASK; 344 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); 345 writel(reg_val, mdata->base + SPI_CFG1_REG); 346 } 347 348 return 0; 349 } 350 351 static int mtk_spi_hw_init(struct spi_controller *host, 352 struct spi_device *spi) 353 { 354 u16 cpha, cpol; 355 u32 reg_val; 356 struct mtk_chip_config *chip_config = spi->controller_data; 357 struct mtk_spi *mdata = spi_controller_get_devdata(host); 358 359 cpha = spi->mode & SPI_CPHA ? 1 : 0; 360 cpol = spi->mode & SPI_CPOL ? 1 : 0; 361 362 reg_val = readl(mdata->base + SPI_CMD_REG); 363 if (mdata->dev_comp->ipm_design) { 364 /* SPI transfer without idle time until packet length done */ 365 reg_val |= SPI_CMD_IPM_NONIDLE_MODE; 366 if (spi->mode & SPI_LOOP) 367 reg_val |= SPI_CMD_IPM_SPIM_LOOP; 368 else 369 reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; 370 } 371 372 if (cpha) 373 reg_val |= SPI_CMD_CPHA; 374 else 375 reg_val &= ~SPI_CMD_CPHA; 376 if (cpol) 377 reg_val |= SPI_CMD_CPOL; 378 else 379 reg_val &= ~SPI_CMD_CPOL; 380 381 /* set the mlsbx and mlsbtx */ 382 if (spi->mode & SPI_LSB_FIRST) { 383 reg_val &= ~SPI_CMD_TXMSBF; 384 reg_val &= ~SPI_CMD_RXMSBF; 385 } else { 386 reg_val |= SPI_CMD_TXMSBF; 387 reg_val |= SPI_CMD_RXMSBF; 388 } 389 390 /* set the tx/rx endian */ 391 #ifdef __LITTLE_ENDIAN 392 reg_val &= ~SPI_CMD_TX_ENDIAN; 393 reg_val &= ~SPI_CMD_RX_ENDIAN; 394 #else 395 reg_val |= SPI_CMD_TX_ENDIAN; 396 reg_val |= SPI_CMD_RX_ENDIAN; 397 #endif 398 399 if (mdata->dev_comp->enhance_timing) { 400 /* set CS polarity */ 401 if (spi->mode & SPI_CS_HIGH) 402 reg_val |= SPI_CMD_CS_POL; 403 else 404 reg_val &= ~SPI_CMD_CS_POL; 405 406 if (chip_config->sample_sel) 407 reg_val |= SPI_CMD_SAMPLE_SEL; 408 else 409 reg_val &= ~SPI_CMD_SAMPLE_SEL; 410 } 411 412 /* set finish and pause interrupt always enable */ 413 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; 414 415 /* disable dma mode */ 416 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); 417 418 /* disable deassert mode */ 419 reg_val &= ~SPI_CMD_DEASSERT; 420 421 writel(reg_val, mdata->base + SPI_CMD_REG); 422 423 /* pad select */ 424 if (mdata->dev_comp->need_pad_sel) 425 writel(mdata->pad_sel[spi_get_chipselect(spi, 0)], 426 mdata->base + SPI_PAD_SEL_REG); 427 428 /* tick delay */ 429 if (mdata->dev_comp->enhance_timing) { 430 if (mdata->dev_comp->ipm_design) { 431 reg_val = readl(mdata->base + SPI_CMD_REG); 432 reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; 433 reg_val |= ((chip_config->tick_delay & 0x7) 434 << SPI_CMD_IPM_GET_TICKDLY_OFFSET); 435 writel(reg_val, mdata->base + SPI_CMD_REG); 436 } else { 437 reg_val = readl(mdata->base + SPI_CFG1_REG); 438 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; 439 reg_val |= ((chip_config->tick_delay & 0x7) 440 << SPI_CFG1_GET_TICK_DLY_OFFSET); 441 writel(reg_val, mdata->base + SPI_CFG1_REG); 442 } 443 } else { 444 reg_val = readl(mdata->base + SPI_CFG1_REG); 445 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; 446 reg_val |= ((chip_config->tick_delay & 0x3) 447 << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); 448 writel(reg_val, mdata->base + SPI_CFG1_REG); 449 } 450 451 /* set hw cs timing */ 452 mtk_spi_set_hw_cs_timing(spi); 453 return 0; 454 } 455 456 static int mtk_spi_prepare_message(struct spi_controller *host, 457 struct spi_message *msg) 458 { 459 return mtk_spi_hw_init(host, msg->spi); 460 } 461 462 static void mtk_spi_set_cs(struct spi_device *spi, bool enable) 463 { 464 u32 reg_val; 465 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); 466 467 if (spi->mode & SPI_CS_HIGH) 468 enable = !enable; 469 470 reg_val = readl(mdata->base + SPI_CMD_REG); 471 if (!enable) { 472 reg_val |= SPI_CMD_PAUSE_EN; 473 writel(reg_val, mdata->base + SPI_CMD_REG); 474 } else { 475 reg_val &= ~SPI_CMD_PAUSE_EN; 476 writel(reg_val, mdata->base + SPI_CMD_REG); 477 mdata->state = MTK_SPI_IDLE; 478 mtk_spi_reset(mdata); 479 } 480 } 481 482 static void mtk_spi_prepare_transfer(struct spi_controller *host, 483 u32 speed_hz) 484 { 485 u32 div, sck_time, reg_val; 486 struct mtk_spi *mdata = spi_controller_get_devdata(host); 487 488 if (speed_hz < mdata->spi_clk_hz / 2) 489 div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); 490 else 491 div = 1; 492 493 sck_time = (div + 1) / 2; 494 495 if (mdata->dev_comp->enhance_timing) { 496 reg_val = readl(mdata->base + SPI_CFG2_REG); 497 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET); 498 reg_val |= (((sck_time - 1) & 0xffff) 499 << SPI_CFG2_SCK_HIGH_OFFSET); 500 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET); 501 reg_val |= (((sck_time - 1) & 0xffff) 502 << SPI_CFG2_SCK_LOW_OFFSET); 503 writel(reg_val, mdata->base + SPI_CFG2_REG); 504 } else { 505 reg_val = readl(mdata->base + SPI_CFG0_REG); 506 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET); 507 reg_val |= (((sck_time - 1) & 0xff) 508 << SPI_CFG0_SCK_HIGH_OFFSET); 509 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET); 510 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); 511 writel(reg_val, mdata->base + SPI_CFG0_REG); 512 } 513 } 514 515 static void mtk_spi_setup_packet(struct spi_controller *host) 516 { 517 u32 packet_size, packet_loop, reg_val; 518 struct mtk_spi *mdata = spi_controller_get_devdata(host); 519 520 if (mdata->dev_comp->ipm_design) 521 packet_size = min_t(u32, 522 mdata->xfer_len, 523 MTK_SPI_IPM_PACKET_SIZE); 524 else 525 packet_size = min_t(u32, 526 mdata->xfer_len, 527 MTK_SPI_PACKET_SIZE); 528 529 packet_loop = mdata->xfer_len / packet_size; 530 531 reg_val = readl(mdata->base + SPI_CFG1_REG); 532 if (mdata->dev_comp->ipm_design) 533 reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; 534 else 535 reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; 536 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; 537 reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; 538 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; 539 writel(reg_val, mdata->base + SPI_CFG1_REG); 540 } 541 542 static void mtk_spi_enable_transfer(struct spi_controller *host) 543 { 544 u32 cmd; 545 struct mtk_spi *mdata = spi_controller_get_devdata(host); 546 547 cmd = readl(mdata->base + SPI_CMD_REG); 548 if (mdata->state == MTK_SPI_IDLE) 549 cmd |= SPI_CMD_ACT; 550 else 551 cmd |= SPI_CMD_RESUME; 552 writel(cmd, mdata->base + SPI_CMD_REG); 553 } 554 555 static int mtk_spi_get_mult_delta(struct mtk_spi *mdata, u32 xfer_len) 556 { 557 u32 mult_delta = 0; 558 559 if (mdata->dev_comp->ipm_design) { 560 if (xfer_len > MTK_SPI_IPM_PACKET_SIZE) 561 mult_delta = xfer_len % MTK_SPI_IPM_PACKET_SIZE; 562 } else { 563 if (xfer_len > MTK_SPI_PACKET_SIZE) 564 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; 565 } 566 567 return mult_delta; 568 } 569 570 static void mtk_spi_update_mdata_len(struct spi_controller *host) 571 { 572 int mult_delta; 573 struct mtk_spi *mdata = spi_controller_get_devdata(host); 574 575 if (mdata->tx_sgl_len && mdata->rx_sgl_len) { 576 if (mdata->tx_sgl_len > mdata->rx_sgl_len) { 577 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len); 578 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 579 mdata->rx_sgl_len = mult_delta; 580 mdata->tx_sgl_len -= mdata->xfer_len; 581 } else { 582 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len); 583 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 584 mdata->tx_sgl_len = mult_delta; 585 mdata->rx_sgl_len -= mdata->xfer_len; 586 } 587 } else if (mdata->tx_sgl_len) { 588 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len); 589 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 590 mdata->tx_sgl_len = mult_delta; 591 } else if (mdata->rx_sgl_len) { 592 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len); 593 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 594 mdata->rx_sgl_len = mult_delta; 595 } 596 } 597 598 static void mtk_spi_setup_dma_addr(struct spi_controller *host, 599 struct spi_transfer *xfer) 600 { 601 struct mtk_spi *mdata = spi_controller_get_devdata(host); 602 603 if (mdata->tx_sgl) { 604 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), 605 mdata->base + SPI_TX_SRC_REG); 606 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 607 if (mdata->dev_comp->dma_ext) 608 writel((u32)(xfer->tx_dma >> 32), 609 mdata->base + SPI_TX_SRC_REG_64); 610 #endif 611 } 612 613 if (mdata->rx_sgl) { 614 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), 615 mdata->base + SPI_RX_DST_REG); 616 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 617 if (mdata->dev_comp->dma_ext) 618 writel((u32)(xfer->rx_dma >> 32), 619 mdata->base + SPI_RX_DST_REG_64); 620 #endif 621 } 622 } 623 624 static int mtk_spi_fifo_transfer(struct spi_controller *host, 625 struct spi_device *spi, 626 struct spi_transfer *xfer) 627 { 628 int cnt, remainder; 629 u32 reg_val; 630 struct mtk_spi *mdata = spi_controller_get_devdata(host); 631 632 mdata->cur_transfer = xfer; 633 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); 634 mdata->num_xfered = 0; 635 mtk_spi_prepare_transfer(host, xfer->speed_hz); 636 mtk_spi_setup_packet(host); 637 638 if (xfer->tx_buf) { 639 cnt = xfer->len / 4; 640 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); 641 remainder = xfer->len % 4; 642 if (remainder > 0) { 643 reg_val = 0; 644 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); 645 writel(reg_val, mdata->base + SPI_TX_DATA_REG); 646 } 647 } 648 649 mtk_spi_enable_transfer(host); 650 651 return 1; 652 } 653 654 static int mtk_spi_dma_transfer(struct spi_controller *host, 655 struct spi_device *spi, 656 struct spi_transfer *xfer) 657 { 658 int cmd; 659 struct mtk_spi *mdata = spi_controller_get_devdata(host); 660 661 mdata->tx_sgl = NULL; 662 mdata->rx_sgl = NULL; 663 mdata->tx_sgl_len = 0; 664 mdata->rx_sgl_len = 0; 665 mdata->cur_transfer = xfer; 666 mdata->num_xfered = 0; 667 668 mtk_spi_prepare_transfer(host, xfer->speed_hz); 669 670 cmd = readl(mdata->base + SPI_CMD_REG); 671 if (xfer->tx_buf) 672 cmd |= SPI_CMD_TX_DMA; 673 if (xfer->rx_buf) 674 cmd |= SPI_CMD_RX_DMA; 675 writel(cmd, mdata->base + SPI_CMD_REG); 676 677 if (xfer->tx_buf) 678 mdata->tx_sgl = xfer->tx_sg.sgl; 679 if (xfer->rx_buf) 680 mdata->rx_sgl = xfer->rx_sg.sgl; 681 682 if (mdata->tx_sgl) { 683 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); 684 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 685 } 686 if (mdata->rx_sgl) { 687 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); 688 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 689 } 690 691 mtk_spi_update_mdata_len(host); 692 mtk_spi_setup_packet(host); 693 mtk_spi_setup_dma_addr(host, xfer); 694 mtk_spi_enable_transfer(host); 695 696 return 1; 697 } 698 699 static int mtk_spi_transfer_one(struct spi_controller *host, 700 struct spi_device *spi, 701 struct spi_transfer *xfer) 702 { 703 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); 704 u32 reg_val = 0; 705 706 /* prepare xfer direction and duplex mode */ 707 if (mdata->dev_comp->ipm_design) { 708 if (!xfer->tx_buf || !xfer->rx_buf) { 709 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; 710 if (xfer->rx_buf) 711 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; 712 } 713 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); 714 } 715 716 if (host->can_dma(host, spi, xfer)) 717 return mtk_spi_dma_transfer(host, spi, xfer); 718 else 719 return mtk_spi_fifo_transfer(host, spi, xfer); 720 } 721 722 static bool mtk_spi_can_dma(struct spi_controller *host, 723 struct spi_device *spi, 724 struct spi_transfer *xfer) 725 { 726 /* Buffers for DMA transactions must be 4-byte aligned */ 727 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && 728 (unsigned long)xfer->tx_buf % 4 == 0 && 729 (unsigned long)xfer->rx_buf % 4 == 0); 730 } 731 732 static int mtk_spi_setup(struct spi_device *spi) 733 { 734 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller); 735 736 if (!spi->controller_data) 737 spi->controller_data = (void *)&mtk_default_chip_info; 738 739 if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0)) 740 /* CS de-asserted, gpiolib will handle inversion */ 741 gpiod_direction_output(spi_get_csgpiod(spi, 0), 0); 742 743 return 0; 744 } 745 746 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) 747 { 748 u32 cmd, reg_val, cnt, remainder, len; 749 struct spi_controller *host = dev_id; 750 struct mtk_spi *mdata = spi_controller_get_devdata(host); 751 struct spi_transfer *xfer = mdata->cur_transfer; 752 753 reg_val = readl(mdata->base + SPI_STATUS0_REG); 754 if (reg_val & MTK_SPI_PAUSE_INT_STATUS) 755 mdata->state = MTK_SPI_PAUSED; 756 else 757 mdata->state = MTK_SPI_IDLE; 758 759 /* SPI-MEM ops */ 760 if (mdata->use_spimem) { 761 complete(&mdata->spimem_done); 762 return IRQ_HANDLED; 763 } 764 765 if (!host->can_dma(host, NULL, xfer)) { 766 if (xfer->rx_buf) { 767 cnt = mdata->xfer_len / 4; 768 ioread32_rep(mdata->base + SPI_RX_DATA_REG, 769 xfer->rx_buf + mdata->num_xfered, cnt); 770 remainder = mdata->xfer_len % 4; 771 if (remainder > 0) { 772 reg_val = readl(mdata->base + SPI_RX_DATA_REG); 773 memcpy(xfer->rx_buf + (cnt * 4) + mdata->num_xfered, 774 ®_val, 775 remainder); 776 } 777 } 778 779 mdata->num_xfered += mdata->xfer_len; 780 if (mdata->num_xfered == xfer->len) { 781 spi_finalize_current_transfer(host); 782 return IRQ_HANDLED; 783 } 784 785 len = xfer->len - mdata->num_xfered; 786 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); 787 mtk_spi_setup_packet(host); 788 789 if (xfer->tx_buf) { 790 cnt = mdata->xfer_len / 4; 791 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, 792 xfer->tx_buf + mdata->num_xfered, cnt); 793 794 remainder = mdata->xfer_len % 4; 795 if (remainder > 0) { 796 reg_val = 0; 797 memcpy(®_val, 798 xfer->tx_buf + (cnt * 4) + mdata->num_xfered, 799 remainder); 800 writel(reg_val, mdata->base + SPI_TX_DATA_REG); 801 } 802 } 803 804 mtk_spi_enable_transfer(host); 805 806 return IRQ_HANDLED; 807 } 808 809 if (mdata->tx_sgl) 810 xfer->tx_dma += mdata->xfer_len; 811 if (mdata->rx_sgl) 812 xfer->rx_dma += mdata->xfer_len; 813 814 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { 815 mdata->tx_sgl = sg_next(mdata->tx_sgl); 816 if (mdata->tx_sgl) { 817 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); 818 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 819 } 820 } 821 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { 822 mdata->rx_sgl = sg_next(mdata->rx_sgl); 823 if (mdata->rx_sgl) { 824 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); 825 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 826 } 827 } 828 829 if (!mdata->tx_sgl && !mdata->rx_sgl) { 830 /* spi disable dma */ 831 cmd = readl(mdata->base + SPI_CMD_REG); 832 cmd &= ~SPI_CMD_TX_DMA; 833 cmd &= ~SPI_CMD_RX_DMA; 834 writel(cmd, mdata->base + SPI_CMD_REG); 835 836 spi_finalize_current_transfer(host); 837 return IRQ_HANDLED; 838 } 839 840 mtk_spi_update_mdata_len(host); 841 mtk_spi_setup_packet(host); 842 mtk_spi_setup_dma_addr(host, xfer); 843 mtk_spi_enable_transfer(host); 844 845 return IRQ_HANDLED; 846 } 847 848 static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, 849 struct spi_mem_op *op) 850 { 851 int opcode_len; 852 853 if (op->data.dir != SPI_MEM_NO_DATA) { 854 opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; 855 if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { 856 op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; 857 /* force data buffer dma-aligned. */ 858 op->data.nbytes -= op->data.nbytes % 4; 859 } 860 } 861 862 return 0; 863 } 864 865 static bool mtk_spi_mem_supports_op(struct spi_mem *mem, 866 const struct spi_mem_op *op) 867 { 868 if (!spi_mem_default_supports_op(mem, op)) 869 return false; 870 871 if (op->addr.nbytes && op->dummy.nbytes && 872 op->addr.buswidth != op->dummy.buswidth) 873 return false; 874 875 if (op->addr.nbytes + op->dummy.nbytes > 16) 876 return false; 877 878 if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { 879 if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > 880 MTK_SPI_IPM_PACKET_LOOP || 881 op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) 882 return false; 883 } 884 885 return true; 886 } 887 888 static void mtk_spi_mem_setup_dma_xfer(struct spi_controller *host, 889 const struct spi_mem_op *op) 890 { 891 struct mtk_spi *mdata = spi_controller_get_devdata(host); 892 893 writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), 894 mdata->base + SPI_TX_SRC_REG); 895 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 896 if (mdata->dev_comp->dma_ext) 897 writel((u32)(mdata->tx_dma >> 32), 898 mdata->base + SPI_TX_SRC_REG_64); 899 #endif 900 901 if (op->data.dir == SPI_MEM_DATA_IN) { 902 writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), 903 mdata->base + SPI_RX_DST_REG); 904 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 905 if (mdata->dev_comp->dma_ext) 906 writel((u32)(mdata->rx_dma >> 32), 907 mdata->base + SPI_RX_DST_REG_64); 908 #endif 909 } 910 } 911 912 static int mtk_spi_transfer_wait(struct spi_mem *mem, 913 const struct spi_mem_op *op) 914 { 915 struct mtk_spi *mdata = spi_controller_get_devdata(mem->spi->controller); 916 /* 917 * For each byte we wait for 8 cycles of the SPI clock. 918 * Since speed is defined in Hz and we want milliseconds, 919 * so it should be 8 * 1000. 920 */ 921 u64 ms = 8000LL; 922 923 if (op->data.dir == SPI_MEM_NO_DATA) 924 ms *= 32; /* prevent we may get 0 for short transfers. */ 925 else 926 ms *= op->data.nbytes; 927 ms = div_u64(ms, mem->spi->max_speed_hz); 928 ms += ms + 1000; /* 1s tolerance */ 929 930 if (ms > UINT_MAX) 931 ms = UINT_MAX; 932 933 if (!wait_for_completion_timeout(&mdata->spimem_done, 934 msecs_to_jiffies(ms))) { 935 dev_err(mdata->dev, "spi-mem transfer timeout\n"); 936 return -ETIMEDOUT; 937 } 938 939 return 0; 940 } 941 942 static int mtk_spi_mem_exec_op(struct spi_mem *mem, 943 const struct spi_mem_op *op) 944 { 945 struct mtk_spi *mdata = spi_controller_get_devdata(mem->spi->controller); 946 u32 reg_val, nio, tx_size; 947 char *tx_tmp_buf, *rx_tmp_buf; 948 int ret = 0; 949 950 mdata->use_spimem = true; 951 reinit_completion(&mdata->spimem_done); 952 953 mtk_spi_reset(mdata); 954 mtk_spi_hw_init(mem->spi->controller, mem->spi); 955 mtk_spi_prepare_transfer(mem->spi->controller, mem->spi->max_speed_hz); 956 957 reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); 958 /* opcode byte len */ 959 reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; 960 reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; 961 962 /* addr & dummy byte len */ 963 reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; 964 if (op->addr.nbytes || op->dummy.nbytes) 965 reg_val |= (op->addr.nbytes + op->dummy.nbytes) << 966 SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; 967 968 /* data byte len */ 969 if (op->data.dir == SPI_MEM_NO_DATA) { 970 reg_val |= SPI_CFG3_IPM_NODATA_FLAG; 971 writel(0, mdata->base + SPI_CFG1_REG); 972 } else { 973 reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; 974 mdata->xfer_len = op->data.nbytes; 975 mtk_spi_setup_packet(mem->spi->controller); 976 } 977 978 if (op->addr.nbytes || op->dummy.nbytes) { 979 if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) 980 reg_val |= SPI_CFG3_IPM_XMODE_EN; 981 else 982 reg_val &= ~SPI_CFG3_IPM_XMODE_EN; 983 } 984 985 if (op->addr.buswidth == 2 || 986 op->dummy.buswidth == 2 || 987 op->data.buswidth == 2) 988 nio = 2; 989 else if (op->addr.buswidth == 4 || 990 op->dummy.buswidth == 4 || 991 op->data.buswidth == 4) 992 nio = 4; 993 else 994 nio = 1; 995 996 reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; 997 reg_val |= PIN_MODE_CFG(nio); 998 999 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; 1000 if (op->data.dir == SPI_MEM_DATA_IN) 1001 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; 1002 else 1003 reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; 1004 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); 1005 1006 tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; 1007 if (op->data.dir == SPI_MEM_DATA_OUT) 1008 tx_size += op->data.nbytes; 1009 1010 tx_size = max_t(u32, tx_size, 32); 1011 1012 tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA); 1013 if (!tx_tmp_buf) { 1014 mdata->use_spimem = false; 1015 return -ENOMEM; 1016 } 1017 1018 tx_tmp_buf[0] = op->cmd.opcode; 1019 1020 if (op->addr.nbytes) { 1021 int i; 1022 1023 for (i = 0; i < op->addr.nbytes; i++) 1024 tx_tmp_buf[i + 1] = op->addr.val >> 1025 (8 * (op->addr.nbytes - i - 1)); 1026 } 1027 1028 if (op->dummy.nbytes) 1029 memset(tx_tmp_buf + op->addr.nbytes + 1, 1030 0xff, 1031 op->dummy.nbytes); 1032 1033 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 1034 memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, 1035 op->data.buf.out, 1036 op->data.nbytes); 1037 1038 mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf, 1039 tx_size, DMA_TO_DEVICE); 1040 if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { 1041 ret = -ENOMEM; 1042 goto err_exit; 1043 } 1044 1045 if (op->data.dir == SPI_MEM_DATA_IN) { 1046 if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { 1047 rx_tmp_buf = kzalloc(op->data.nbytes, 1048 GFP_KERNEL | GFP_DMA); 1049 if (!rx_tmp_buf) { 1050 ret = -ENOMEM; 1051 goto unmap_tx_dma; 1052 } 1053 } else { 1054 rx_tmp_buf = op->data.buf.in; 1055 } 1056 1057 mdata->rx_dma = dma_map_single(mdata->dev, 1058 rx_tmp_buf, 1059 op->data.nbytes, 1060 DMA_FROM_DEVICE); 1061 if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { 1062 ret = -ENOMEM; 1063 goto kfree_rx_tmp_buf; 1064 } 1065 } 1066 1067 reg_val = readl(mdata->base + SPI_CMD_REG); 1068 reg_val |= SPI_CMD_TX_DMA; 1069 if (op->data.dir == SPI_MEM_DATA_IN) 1070 reg_val |= SPI_CMD_RX_DMA; 1071 writel(reg_val, mdata->base + SPI_CMD_REG); 1072 1073 mtk_spi_mem_setup_dma_xfer(mem->spi->controller, op); 1074 1075 mtk_spi_enable_transfer(mem->spi->controller); 1076 1077 /* Wait for the interrupt. */ 1078 ret = mtk_spi_transfer_wait(mem, op); 1079 if (ret) 1080 goto unmap_rx_dma; 1081 1082 /* spi disable dma */ 1083 reg_val = readl(mdata->base + SPI_CMD_REG); 1084 reg_val &= ~SPI_CMD_TX_DMA; 1085 if (op->data.dir == SPI_MEM_DATA_IN) 1086 reg_val &= ~SPI_CMD_RX_DMA; 1087 writel(reg_val, mdata->base + SPI_CMD_REG); 1088 1089 unmap_rx_dma: 1090 if (op->data.dir == SPI_MEM_DATA_IN) { 1091 dma_unmap_single(mdata->dev, mdata->rx_dma, 1092 op->data.nbytes, DMA_FROM_DEVICE); 1093 if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) 1094 memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); 1095 } 1096 kfree_rx_tmp_buf: 1097 if (op->data.dir == SPI_MEM_DATA_IN && 1098 !IS_ALIGNED((size_t)op->data.buf.in, 4)) 1099 kfree(rx_tmp_buf); 1100 unmap_tx_dma: 1101 dma_unmap_single(mdata->dev, mdata->tx_dma, 1102 tx_size, DMA_TO_DEVICE); 1103 err_exit: 1104 kfree(tx_tmp_buf); 1105 mdata->use_spimem = false; 1106 1107 return ret; 1108 } 1109 1110 static const struct spi_controller_mem_ops mtk_spi_mem_ops = { 1111 .adjust_op_size = mtk_spi_mem_adjust_op_size, 1112 .supports_op = mtk_spi_mem_supports_op, 1113 .exec_op = mtk_spi_mem_exec_op, 1114 }; 1115 1116 static int mtk_spi_probe(struct platform_device *pdev) 1117 { 1118 struct device *dev = &pdev->dev; 1119 struct spi_controller *host; 1120 struct mtk_spi *mdata; 1121 int i, irq, ret, addr_bits; 1122 1123 host = devm_spi_alloc_host(dev, sizeof(*mdata)); 1124 if (!host) 1125 return dev_err_probe(dev, -ENOMEM, "failed to alloc spi host\n"); 1126 1127 host->auto_runtime_pm = true; 1128 host->dev.of_node = dev->of_node; 1129 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 1130 1131 host->set_cs = mtk_spi_set_cs; 1132 host->prepare_message = mtk_spi_prepare_message; 1133 host->transfer_one = mtk_spi_transfer_one; 1134 host->can_dma = mtk_spi_can_dma; 1135 host->setup = mtk_spi_setup; 1136 host->set_cs_timing = mtk_spi_set_hw_cs_timing; 1137 host->use_gpio_descriptors = true; 1138 1139 mdata = spi_controller_get_devdata(host); 1140 mdata->dev_comp = device_get_match_data(dev); 1141 1142 if (mdata->dev_comp->enhance_timing) 1143 host->mode_bits |= SPI_CS_HIGH; 1144 1145 if (mdata->dev_comp->must_tx) 1146 host->flags = SPI_CONTROLLER_MUST_TX; 1147 if (mdata->dev_comp->ipm_design) 1148 host->mode_bits |= SPI_LOOP | SPI_RX_DUAL | SPI_TX_DUAL | 1149 SPI_RX_QUAD | SPI_TX_QUAD; 1150 1151 if (mdata->dev_comp->ipm_design) { 1152 mdata->dev = dev; 1153 host->mem_ops = &mtk_spi_mem_ops; 1154 init_completion(&mdata->spimem_done); 1155 } 1156 1157 if (mdata->dev_comp->need_pad_sel) { 1158 mdata->pad_num = of_property_count_u32_elems(dev->of_node, 1159 "mediatek,pad-select"); 1160 if (mdata->pad_num < 0) 1161 return dev_err_probe(dev, -EINVAL, 1162 "No 'mediatek,pad-select' property\n"); 1163 1164 mdata->pad_sel = devm_kmalloc_array(dev, mdata->pad_num, 1165 sizeof(u32), GFP_KERNEL); 1166 if (!mdata->pad_sel) 1167 return -ENOMEM; 1168 1169 for (i = 0; i < mdata->pad_num; i++) { 1170 of_property_read_u32_index(dev->of_node, 1171 "mediatek,pad-select", 1172 i, &mdata->pad_sel[i]); 1173 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) 1174 return dev_err_probe(dev, -EINVAL, 1175 "wrong pad-sel[%d]: %u\n", 1176 i, mdata->pad_sel[i]); 1177 } 1178 } 1179 1180 platform_set_drvdata(pdev, host); 1181 mdata->base = devm_platform_ioremap_resource(pdev, 0); 1182 if (IS_ERR(mdata->base)) 1183 return PTR_ERR(mdata->base); 1184 1185 irq = platform_get_irq(pdev, 0); 1186 if (irq < 0) 1187 return irq; 1188 1189 if (!dev->dma_mask) 1190 dev->dma_mask = &dev->coherent_dma_mask; 1191 1192 if (mdata->dev_comp->ipm_design) 1193 dma_set_max_seg_size(dev, SZ_16M); 1194 else 1195 dma_set_max_seg_size(dev, SZ_256K); 1196 1197 mdata->parent_clk = devm_clk_get(dev, "parent-clk"); 1198 if (IS_ERR(mdata->parent_clk)) 1199 return dev_err_probe(dev, PTR_ERR(mdata->parent_clk), 1200 "failed to get parent-clk\n"); 1201 1202 mdata->sel_clk = devm_clk_get(dev, "sel-clk"); 1203 if (IS_ERR(mdata->sel_clk)) 1204 return dev_err_probe(dev, PTR_ERR(mdata->sel_clk), "failed to get sel-clk\n"); 1205 1206 mdata->spi_clk = devm_clk_get(dev, "spi-clk"); 1207 if (IS_ERR(mdata->spi_clk)) 1208 return dev_err_probe(dev, PTR_ERR(mdata->spi_clk), "failed to get spi-clk\n"); 1209 1210 mdata->spi_hclk = devm_clk_get_optional(dev, "hclk"); 1211 if (IS_ERR(mdata->spi_hclk)) 1212 return dev_err_probe(dev, PTR_ERR(mdata->spi_hclk), "failed to get hclk\n"); 1213 1214 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); 1215 if (ret < 0) 1216 return dev_err_probe(dev, ret, "failed to clk_set_parent\n"); 1217 1218 ret = clk_prepare_enable(mdata->spi_hclk); 1219 if (ret < 0) 1220 return dev_err_probe(dev, ret, "failed to enable hclk\n"); 1221 1222 ret = clk_prepare_enable(mdata->spi_clk); 1223 if (ret < 0) { 1224 clk_disable_unprepare(mdata->spi_hclk); 1225 return dev_err_probe(dev, ret, "failed to enable spi_clk\n"); 1226 } 1227 1228 mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); 1229 1230 if (mdata->dev_comp->no_need_unprepare) { 1231 clk_disable(mdata->spi_clk); 1232 clk_disable(mdata->spi_hclk); 1233 } else { 1234 clk_disable_unprepare(mdata->spi_clk); 1235 clk_disable_unprepare(mdata->spi_hclk); 1236 } 1237 1238 if (mdata->dev_comp->need_pad_sel) { 1239 if (mdata->pad_num != host->num_chipselect) 1240 return dev_err_probe(dev, -EINVAL, 1241 "pad_num does not match num_chipselect(%d != %d)\n", 1242 mdata->pad_num, host->num_chipselect); 1243 1244 if (!host->cs_gpiods && host->num_chipselect > 1) 1245 return dev_err_probe(dev, -EINVAL, 1246 "cs_gpios not specified and num_chipselect > 1\n"); 1247 } 1248 1249 if (mdata->dev_comp->dma_ext) 1250 addr_bits = DMA_ADDR_EXT_BITS; 1251 else 1252 addr_bits = DMA_ADDR_DEF_BITS; 1253 ret = dma_set_mask(dev, DMA_BIT_MASK(addr_bits)); 1254 if (ret) 1255 dev_notice(dev, "SPI dma_set_mask(%d) failed, ret:%d\n", 1256 addr_bits, ret); 1257 1258 ret = devm_request_irq(dev, irq, mtk_spi_interrupt, 1259 IRQF_TRIGGER_NONE, dev_name(dev), host); 1260 if (ret) 1261 return dev_err_probe(dev, ret, "failed to register irq\n"); 1262 1263 pm_runtime_enable(dev); 1264 1265 ret = devm_spi_register_controller(dev, host); 1266 if (ret) { 1267 pm_runtime_disable(dev); 1268 return dev_err_probe(dev, ret, "failed to register host\n"); 1269 } 1270 1271 return 0; 1272 } 1273 1274 static void mtk_spi_remove(struct platform_device *pdev) 1275 { 1276 struct spi_controller *host = platform_get_drvdata(pdev); 1277 struct mtk_spi *mdata = spi_controller_get_devdata(host); 1278 int ret; 1279 1280 if (mdata->use_spimem && !completion_done(&mdata->spimem_done)) 1281 complete(&mdata->spimem_done); 1282 1283 ret = pm_runtime_get_sync(&pdev->dev); 1284 if (ret < 0) { 1285 dev_warn(&pdev->dev, "Failed to resume hardware (%pe)\n", ERR_PTR(ret)); 1286 } else { 1287 /* 1288 * If pm runtime resume failed, clks are disabled and 1289 * unprepared. So don't access the hardware and skip clk 1290 * unpreparing. 1291 */ 1292 mtk_spi_reset(mdata); 1293 1294 if (mdata->dev_comp->no_need_unprepare) { 1295 clk_unprepare(mdata->spi_clk); 1296 clk_unprepare(mdata->spi_hclk); 1297 } 1298 } 1299 1300 pm_runtime_put_noidle(&pdev->dev); 1301 pm_runtime_disable(&pdev->dev); 1302 } 1303 1304 #ifdef CONFIG_PM_SLEEP 1305 static int mtk_spi_suspend(struct device *dev) 1306 { 1307 int ret; 1308 struct spi_controller *host = dev_get_drvdata(dev); 1309 struct mtk_spi *mdata = spi_controller_get_devdata(host); 1310 1311 ret = spi_controller_suspend(host); 1312 if (ret) 1313 return ret; 1314 1315 if (!pm_runtime_suspended(dev)) { 1316 clk_disable_unprepare(mdata->spi_clk); 1317 clk_disable_unprepare(mdata->spi_hclk); 1318 } 1319 1320 pinctrl_pm_select_sleep_state(dev); 1321 1322 return 0; 1323 } 1324 1325 static int mtk_spi_resume(struct device *dev) 1326 { 1327 int ret; 1328 struct spi_controller *host = dev_get_drvdata(dev); 1329 struct mtk_spi *mdata = spi_controller_get_devdata(host); 1330 1331 pinctrl_pm_select_default_state(dev); 1332 1333 if (!pm_runtime_suspended(dev)) { 1334 ret = clk_prepare_enable(mdata->spi_clk); 1335 if (ret < 0) { 1336 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 1337 return ret; 1338 } 1339 1340 ret = clk_prepare_enable(mdata->spi_hclk); 1341 if (ret < 0) { 1342 dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); 1343 clk_disable_unprepare(mdata->spi_clk); 1344 return ret; 1345 } 1346 } 1347 1348 ret = spi_controller_resume(host); 1349 if (ret < 0) { 1350 clk_disable_unprepare(mdata->spi_clk); 1351 clk_disable_unprepare(mdata->spi_hclk); 1352 } 1353 1354 return ret; 1355 } 1356 #endif /* CONFIG_PM_SLEEP */ 1357 1358 #ifdef CONFIG_PM 1359 static int mtk_spi_runtime_suspend(struct device *dev) 1360 { 1361 struct spi_controller *host = dev_get_drvdata(dev); 1362 struct mtk_spi *mdata = spi_controller_get_devdata(host); 1363 1364 if (mdata->dev_comp->no_need_unprepare) { 1365 clk_disable(mdata->spi_clk); 1366 clk_disable(mdata->spi_hclk); 1367 } else { 1368 clk_disable_unprepare(mdata->spi_clk); 1369 clk_disable_unprepare(mdata->spi_hclk); 1370 } 1371 1372 return 0; 1373 } 1374 1375 static int mtk_spi_runtime_resume(struct device *dev) 1376 { 1377 struct spi_controller *host = dev_get_drvdata(dev); 1378 struct mtk_spi *mdata = spi_controller_get_devdata(host); 1379 int ret; 1380 1381 if (mdata->dev_comp->no_need_unprepare) { 1382 ret = clk_enable(mdata->spi_clk); 1383 if (ret < 0) { 1384 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 1385 return ret; 1386 } 1387 ret = clk_enable(mdata->spi_hclk); 1388 if (ret < 0) { 1389 dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); 1390 clk_disable(mdata->spi_clk); 1391 return ret; 1392 } 1393 } else { 1394 ret = clk_prepare_enable(mdata->spi_clk); 1395 if (ret < 0) { 1396 dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret); 1397 return ret; 1398 } 1399 1400 ret = clk_prepare_enable(mdata->spi_hclk); 1401 if (ret < 0) { 1402 dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret); 1403 clk_disable_unprepare(mdata->spi_clk); 1404 return ret; 1405 } 1406 } 1407 1408 return 0; 1409 } 1410 #endif /* CONFIG_PM */ 1411 1412 static const struct dev_pm_ops mtk_spi_pm = { 1413 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) 1414 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, 1415 mtk_spi_runtime_resume, NULL) 1416 }; 1417 1418 static struct platform_driver mtk_spi_driver = { 1419 .driver = { 1420 .name = "mtk-spi", 1421 .pm = &mtk_spi_pm, 1422 .of_match_table = mtk_spi_of_match, 1423 }, 1424 .probe = mtk_spi_probe, 1425 .remove_new = mtk_spi_remove, 1426 }; 1427 1428 module_platform_driver(mtk_spi_driver); 1429 1430 MODULE_DESCRIPTION("MTK SPI Controller driver"); 1431 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); 1432 MODULE_LICENSE("GPL v2"); 1433 MODULE_ALIAS("platform:mtk-spi"); 1434