1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MPC52xx SPI bus driver. 4 * 5 * Copyright (C) 2008 Secret Lab Technologies Ltd. 6 * 7 * This is the driver for the MPC5200's dedicated SPI controller. 8 * 9 * Note: this driver does not support the MPC5200 PSC in SPI mode. For 10 * that driver see drivers/spi/mpc52xx_psc_spi.c 11 */ 12 13 #include <linux/module.h> 14 #include <linux/errno.h> 15 #include <linux/of_platform.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/spi/spi.h> 19 #include <linux/io.h> 20 #include <linux/of_gpio.h> 21 #include <linux/slab.h> 22 #include <asm/time.h> 23 #include <asm/mpc52xx.h> 24 25 MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); 26 MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver"); 27 MODULE_LICENSE("GPL"); 28 29 /* Register offsets */ 30 #define SPI_CTRL1 0x00 31 #define SPI_CTRL1_SPIE (1 << 7) 32 #define SPI_CTRL1_SPE (1 << 6) 33 #define SPI_CTRL1_MSTR (1 << 4) 34 #define SPI_CTRL1_CPOL (1 << 3) 35 #define SPI_CTRL1_CPHA (1 << 2) 36 #define SPI_CTRL1_SSOE (1 << 1) 37 #define SPI_CTRL1_LSBFE (1 << 0) 38 39 #define SPI_CTRL2 0x01 40 #define SPI_BRR 0x04 41 42 #define SPI_STATUS 0x05 43 #define SPI_STATUS_SPIF (1 << 7) 44 #define SPI_STATUS_WCOL (1 << 6) 45 #define SPI_STATUS_MODF (1 << 4) 46 47 #define SPI_DATA 0x09 48 #define SPI_PORTDATA 0x0d 49 #define SPI_DATADIR 0x10 50 51 /* FSM state return values */ 52 #define FSM_STOP 0 /* Nothing more for the state machine to */ 53 /* do. If something interesting happens */ 54 /* then an IRQ will be received */ 55 #define FSM_POLL 1 /* need to poll for completion, an IRQ is */ 56 /* not expected */ 57 #define FSM_CONTINUE 2 /* Keep iterating the state machine */ 58 59 /* Driver internal data */ 60 struct mpc52xx_spi { 61 struct spi_master *master; 62 void __iomem *regs; 63 int irq0; /* MODF irq */ 64 int irq1; /* SPIF irq */ 65 unsigned int ipb_freq; 66 67 /* Statistics; not used now, but will be reintroduced for debugfs */ 68 int msg_count; 69 int wcol_count; 70 int wcol_ticks; 71 u32 wcol_tx_timestamp; 72 int modf_count; 73 int byte_count; 74 75 struct list_head queue; /* queue of pending messages */ 76 spinlock_t lock; 77 struct work_struct work; 78 79 /* Details of current transfer (length, and buffer pointers) */ 80 struct spi_message *message; /* current message */ 81 struct spi_transfer *transfer; /* current transfer */ 82 int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data); 83 int len; 84 int timestamp; 85 u8 *rx_buf; 86 const u8 *tx_buf; 87 int cs_change; 88 int gpio_cs_count; 89 unsigned int *gpio_cs; 90 }; 91 92 /* 93 * CS control function 94 */ 95 static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value) 96 { 97 int cs; 98 99 if (ms->gpio_cs_count > 0) { 100 cs = ms->message->spi->chip_select; 101 gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1); 102 } else 103 out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08); 104 } 105 106 /* 107 * Start a new transfer. This is called both by the idle state 108 * for the first transfer in a message, and by the wait state when the 109 * previous transfer in a message is complete. 110 */ 111 static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms) 112 { 113 ms->rx_buf = ms->transfer->rx_buf; 114 ms->tx_buf = ms->transfer->tx_buf; 115 ms->len = ms->transfer->len; 116 117 /* Activate the chip select */ 118 if (ms->cs_change) 119 mpc52xx_spi_chipsel(ms, 1); 120 ms->cs_change = ms->transfer->cs_change; 121 122 /* Write out the first byte */ 123 ms->wcol_tx_timestamp = mftb(); 124 if (ms->tx_buf) 125 out_8(ms->regs + SPI_DATA, *ms->tx_buf++); 126 else 127 out_8(ms->regs + SPI_DATA, 0); 128 } 129 130 /* Forward declaration of state handlers */ 131 static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, 132 u8 status, u8 data); 133 static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, 134 u8 status, u8 data); 135 136 /* 137 * IDLE state 138 * 139 * No transfers are in progress; if another transfer is pending then retrieve 140 * it and kick it off. Otherwise, stop processing the state machine 141 */ 142 static int 143 mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) 144 { 145 struct spi_device *spi; 146 int spr, sppr; 147 u8 ctrl1; 148 149 if (status && (irq != NO_IRQ)) 150 dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", 151 status); 152 153 /* Check if there is another transfer waiting. */ 154 if (list_empty(&ms->queue)) 155 return FSM_STOP; 156 157 /* get the head of the queue */ 158 ms->message = list_first_entry(&ms->queue, struct spi_message, queue); 159 list_del_init(&ms->message->queue); 160 161 /* Setup the controller parameters */ 162 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; 163 spi = ms->message->spi; 164 if (spi->mode & SPI_CPHA) 165 ctrl1 |= SPI_CTRL1_CPHA; 166 if (spi->mode & SPI_CPOL) 167 ctrl1 |= SPI_CTRL1_CPOL; 168 if (spi->mode & SPI_LSB_FIRST) 169 ctrl1 |= SPI_CTRL1_LSBFE; 170 out_8(ms->regs + SPI_CTRL1, ctrl1); 171 172 /* Setup the controller speed */ 173 /* minimum divider is '2'. Also, add '1' to force rounding the 174 * divider up. */ 175 sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1; 176 spr = 0; 177 if (sppr < 1) 178 sppr = 1; 179 while (((sppr - 1) & ~0x7) != 0) { 180 sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */ 181 spr++; 182 } 183 sppr--; /* sppr quantity in register is offset by 1 */ 184 if (spr > 7) { 185 /* Don't overrun limits of SPI baudrate register */ 186 spr = 7; 187 sppr = 7; 188 } 189 out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */ 190 191 ms->cs_change = 1; 192 ms->transfer = container_of(ms->message->transfers.next, 193 struct spi_transfer, transfer_list); 194 195 mpc52xx_spi_start_transfer(ms); 196 ms->state = mpc52xx_spi_fsmstate_transfer; 197 198 return FSM_CONTINUE; 199 } 200 201 /* 202 * TRANSFER state 203 * 204 * In the middle of a transfer. If the SPI core has completed processing 205 * a byte, then read out the received data and write out the next byte 206 * (unless this transfer is finished; in which case go on to the wait 207 * state) 208 */ 209 static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms, 210 u8 status, u8 data) 211 { 212 if (!status) 213 return ms->irq0 ? FSM_STOP : FSM_POLL; 214 215 if (status & SPI_STATUS_WCOL) { 216 /* The SPI controller is stoopid. At slower speeds, it may 217 * raise the SPIF flag before the state machine is actually 218 * finished, which causes a collision (internal to the state 219 * machine only). The manual recommends inserting a delay 220 * between receiving the interrupt and sending the next byte, 221 * but it can also be worked around simply by retrying the 222 * transfer which is what we do here. */ 223 ms->wcol_count++; 224 ms->wcol_ticks += mftb() - ms->wcol_tx_timestamp; 225 ms->wcol_tx_timestamp = mftb(); 226 data = 0; 227 if (ms->tx_buf) 228 data = *(ms->tx_buf - 1); 229 out_8(ms->regs + SPI_DATA, data); /* try again */ 230 return FSM_CONTINUE; 231 } else if (status & SPI_STATUS_MODF) { 232 ms->modf_count++; 233 dev_err(&ms->master->dev, "mode fault\n"); 234 mpc52xx_spi_chipsel(ms, 0); 235 ms->message->status = -EIO; 236 if (ms->message->complete) 237 ms->message->complete(ms->message->context); 238 ms->state = mpc52xx_spi_fsmstate_idle; 239 return FSM_CONTINUE; 240 } 241 242 /* Read data out of the spi device */ 243 ms->byte_count++; 244 if (ms->rx_buf) 245 *ms->rx_buf++ = data; 246 247 /* Is the transfer complete? */ 248 ms->len--; 249 if (ms->len == 0) { 250 ms->timestamp = mftb(); 251 if (ms->transfer->delay.unit == SPI_DELAY_UNIT_USECS) 252 ms->timestamp += ms->transfer->delay.value * 253 tb_ticks_per_usec; 254 ms->state = mpc52xx_spi_fsmstate_wait; 255 return FSM_CONTINUE; 256 } 257 258 /* Write out the next byte */ 259 ms->wcol_tx_timestamp = mftb(); 260 if (ms->tx_buf) 261 out_8(ms->regs + SPI_DATA, *ms->tx_buf++); 262 else 263 out_8(ms->regs + SPI_DATA, 0); 264 265 return FSM_CONTINUE; 266 } 267 268 /* 269 * WAIT state 270 * 271 * A transfer has completed; need to wait for the delay period to complete 272 * before starting the next transfer 273 */ 274 static int 275 mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) 276 { 277 if (status && irq) 278 dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", 279 status); 280 281 if (((int)mftb()) - ms->timestamp < 0) 282 return FSM_POLL; 283 284 ms->message->actual_length += ms->transfer->len; 285 286 /* Check if there is another transfer in this message. If there 287 * aren't then deactivate CS, notify sender, and drop back to idle 288 * to start the next message. */ 289 if (ms->transfer->transfer_list.next == &ms->message->transfers) { 290 ms->msg_count++; 291 mpc52xx_spi_chipsel(ms, 0); 292 ms->message->status = 0; 293 if (ms->message->complete) 294 ms->message->complete(ms->message->context); 295 ms->state = mpc52xx_spi_fsmstate_idle; 296 return FSM_CONTINUE; 297 } 298 299 /* There is another transfer; kick it off */ 300 301 if (ms->cs_change) 302 mpc52xx_spi_chipsel(ms, 0); 303 304 ms->transfer = container_of(ms->transfer->transfer_list.next, 305 struct spi_transfer, transfer_list); 306 mpc52xx_spi_start_transfer(ms); 307 ms->state = mpc52xx_spi_fsmstate_transfer; 308 return FSM_CONTINUE; 309 } 310 311 /** 312 * mpc52xx_spi_fsm_process - Finite State Machine iteration function 313 * @irq: irq number that triggered the FSM or 0 for polling 314 * @ms: pointer to mpc52xx_spi driver data 315 */ 316 static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms) 317 { 318 int rc = FSM_CONTINUE; 319 u8 status, data; 320 321 while (rc == FSM_CONTINUE) { 322 /* Interrupt cleared by read of STATUS followed by 323 * read of DATA registers */ 324 status = in_8(ms->regs + SPI_STATUS); 325 data = in_8(ms->regs + SPI_DATA); 326 rc = ms->state(irq, ms, status, data); 327 } 328 329 if (rc == FSM_POLL) 330 schedule_work(&ms->work); 331 } 332 333 /** 334 * mpc52xx_spi_irq - IRQ handler 335 */ 336 static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms) 337 { 338 struct mpc52xx_spi *ms = _ms; 339 spin_lock(&ms->lock); 340 mpc52xx_spi_fsm_process(irq, ms); 341 spin_unlock(&ms->lock); 342 return IRQ_HANDLED; 343 } 344 345 /** 346 * mpc52xx_spi_wq - Workqueue function for polling the state machine 347 */ 348 static void mpc52xx_spi_wq(struct work_struct *work) 349 { 350 struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work); 351 unsigned long flags; 352 353 spin_lock_irqsave(&ms->lock, flags); 354 mpc52xx_spi_fsm_process(0, ms); 355 spin_unlock_irqrestore(&ms->lock, flags); 356 } 357 358 /* 359 * spi_master ops 360 */ 361 362 static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m) 363 { 364 struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master); 365 unsigned long flags; 366 367 m->actual_length = 0; 368 m->status = -EINPROGRESS; 369 370 spin_lock_irqsave(&ms->lock, flags); 371 list_add_tail(&m->queue, &ms->queue); 372 spin_unlock_irqrestore(&ms->lock, flags); 373 schedule_work(&ms->work); 374 375 return 0; 376 } 377 378 /* 379 * OF Platform Bus Binding 380 */ 381 static int mpc52xx_spi_probe(struct platform_device *op) 382 { 383 struct spi_master *master; 384 struct mpc52xx_spi *ms; 385 void __iomem *regs; 386 u8 ctrl1; 387 int rc, i = 0; 388 int gpio_cs; 389 390 /* MMIO registers */ 391 dev_dbg(&op->dev, "probing mpc5200 SPI device\n"); 392 regs = of_iomap(op->dev.of_node, 0); 393 if (!regs) 394 return -ENODEV; 395 396 /* initialize the device */ 397 ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR; 398 out_8(regs + SPI_CTRL1, ctrl1); 399 out_8(regs + SPI_CTRL2, 0x0); 400 out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */ 401 out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */ 402 403 /* Clear the status register and re-read it to check for a MODF 404 * failure. This driver cannot currently handle multiple masters 405 * on the SPI bus. This fault will also occur if the SPI signals 406 * are not connected to any pins (port_config setting) */ 407 in_8(regs + SPI_STATUS); 408 out_8(regs + SPI_CTRL1, ctrl1); 409 410 in_8(regs + SPI_DATA); 411 if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) { 412 dev_err(&op->dev, "mode fault; is port_config correct?\n"); 413 rc = -EIO; 414 goto err_init; 415 } 416 417 dev_dbg(&op->dev, "allocating spi_master struct\n"); 418 master = spi_alloc_master(&op->dev, sizeof(*ms)); 419 if (!master) { 420 rc = -ENOMEM; 421 goto err_alloc; 422 } 423 424 master->transfer = mpc52xx_spi_transfer; 425 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 426 master->bits_per_word_mask = SPI_BPW_MASK(8); 427 master->dev.of_node = op->dev.of_node; 428 429 platform_set_drvdata(op, master); 430 431 ms = spi_master_get_devdata(master); 432 ms->master = master; 433 ms->regs = regs; 434 ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0); 435 ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1); 436 ms->state = mpc52xx_spi_fsmstate_idle; 437 ms->ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node); 438 ms->gpio_cs_count = of_gpio_count(op->dev.of_node); 439 if (ms->gpio_cs_count > 0) { 440 master->num_chipselect = ms->gpio_cs_count; 441 ms->gpio_cs = kmalloc_array(ms->gpio_cs_count, 442 sizeof(*ms->gpio_cs), 443 GFP_KERNEL); 444 if (!ms->gpio_cs) { 445 rc = -ENOMEM; 446 goto err_alloc_gpio; 447 } 448 449 for (i = 0; i < ms->gpio_cs_count; i++) { 450 gpio_cs = of_get_gpio(op->dev.of_node, i); 451 if (!gpio_is_valid(gpio_cs)) { 452 dev_err(&op->dev, 453 "could not parse the gpio field in oftree\n"); 454 rc = -ENODEV; 455 goto err_gpio; 456 } 457 458 rc = gpio_request(gpio_cs, dev_name(&op->dev)); 459 if (rc) { 460 dev_err(&op->dev, 461 "can't request spi cs gpio #%d on gpio line %d\n", 462 i, gpio_cs); 463 goto err_gpio; 464 } 465 466 gpio_direction_output(gpio_cs, 1); 467 ms->gpio_cs[i] = gpio_cs; 468 } 469 } 470 471 spin_lock_init(&ms->lock); 472 INIT_LIST_HEAD(&ms->queue); 473 INIT_WORK(&ms->work, mpc52xx_spi_wq); 474 475 /* Decide if interrupts can be used */ 476 if (ms->irq0 && ms->irq1) { 477 rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0, 478 "mpc5200-spi-modf", ms); 479 rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0, 480 "mpc5200-spi-spif", ms); 481 if (rc) { 482 free_irq(ms->irq0, ms); 483 free_irq(ms->irq1, ms); 484 ms->irq0 = ms->irq1 = 0; 485 } 486 } else { 487 /* operate in polled mode */ 488 ms->irq0 = ms->irq1 = 0; 489 } 490 491 if (!ms->irq0) 492 dev_info(&op->dev, "using polled mode\n"); 493 494 dev_dbg(&op->dev, "registering spi_master struct\n"); 495 rc = spi_register_master(master); 496 if (rc) 497 goto err_register; 498 499 dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n"); 500 501 return rc; 502 503 err_register: 504 dev_err(&ms->master->dev, "initialization failed\n"); 505 err_gpio: 506 while (i-- > 0) 507 gpio_free(ms->gpio_cs[i]); 508 509 kfree(ms->gpio_cs); 510 err_alloc_gpio: 511 spi_master_put(master); 512 err_alloc: 513 err_init: 514 iounmap(regs); 515 return rc; 516 } 517 518 static int mpc52xx_spi_remove(struct platform_device *op) 519 { 520 struct spi_master *master = spi_master_get(platform_get_drvdata(op)); 521 struct mpc52xx_spi *ms = spi_master_get_devdata(master); 522 int i; 523 524 free_irq(ms->irq0, ms); 525 free_irq(ms->irq1, ms); 526 527 for (i = 0; i < ms->gpio_cs_count; i++) 528 gpio_free(ms->gpio_cs[i]); 529 530 kfree(ms->gpio_cs); 531 spi_unregister_master(master); 532 iounmap(ms->regs); 533 spi_master_put(master); 534 535 return 0; 536 } 537 538 static const struct of_device_id mpc52xx_spi_match[] = { 539 { .compatible = "fsl,mpc5200-spi", }, 540 {} 541 }; 542 MODULE_DEVICE_TABLE(of, mpc52xx_spi_match); 543 544 static struct platform_driver mpc52xx_spi_of_driver = { 545 .driver = { 546 .name = "mpc52xx-spi", 547 .of_match_table = mpc52xx_spi_match, 548 }, 549 .probe = mpc52xx_spi_probe, 550 .remove = mpc52xx_spi_remove, 551 }; 552 module_platform_driver(mpc52xx_spi_of_driver); 553