1 /* 2 * Driver for Amlogic Meson SPI communication controller (SPICC) 3 * 4 * Copyright (C) BayLibre, SAS 5 * Author: Neil Armstrong <narmstrong@baylibre.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/spi/spi.h> 21 #include <linux/types.h> 22 #include <linux/interrupt.h> 23 #include <linux/reset.h> 24 25 /* 26 * The Meson SPICC controller could support DMA based transfers, but is not 27 * implemented by the vendor code, and while having the registers documentation 28 * it has never worked on the GXL Hardware. 29 * The PIO mode is the only mode implemented, and due to badly designed HW : 30 * - all transfers are cutted in 16 words burst because the FIFO hangs on 31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by 32 * FIFO max size chunk only 33 * - CS management is dumb, and goes UP between every burst, so is really a 34 * "Data Valid" signal than a Chip Select, GPIO link should be used instead 35 * to have a CS go down over the full transfer 36 */ 37 38 #define SPICC_MAX_BURST 128 39 40 /* Register Map */ 41 #define SPICC_RXDATA 0x00 42 43 #define SPICC_TXDATA 0x04 44 45 #define SPICC_CONREG 0x08 46 #define SPICC_ENABLE BIT(0) 47 #define SPICC_MODE_MASTER BIT(1) 48 #define SPICC_XCH BIT(2) 49 #define SPICC_SMC BIT(3) 50 #define SPICC_POL BIT(4) 51 #define SPICC_PHA BIT(5) 52 #define SPICC_SSCTL BIT(6) 53 #define SPICC_SSPOL BIT(7) 54 #define SPICC_DRCTL_MASK GENMASK(9, 8) 55 #define SPICC_DRCTL_IGNORE 0 56 #define SPICC_DRCTL_FALLING 1 57 #define SPICC_DRCTL_LOWLEVEL 2 58 #define SPICC_CS_MASK GENMASK(13, 12) 59 #define SPICC_DATARATE_MASK GENMASK(18, 16) 60 #define SPICC_DATARATE_DIV4 0 61 #define SPICC_DATARATE_DIV8 1 62 #define SPICC_DATARATE_DIV16 2 63 #define SPICC_DATARATE_DIV32 3 64 #define SPICC_BITLENGTH_MASK GENMASK(24, 19) 65 #define SPICC_BURSTLENGTH_MASK GENMASK(31, 25) 66 67 #define SPICC_INTREG 0x0c 68 #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */ 69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */ 70 #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */ 71 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */ 72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */ 73 #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */ 74 #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */ 75 #define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */ 76 77 #define SPICC_DMAREG 0x10 78 #define SPICC_DMA_ENABLE BIT(0) 79 #define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1) 80 #define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6) 81 #define SPICC_READ_BURST_MASK GENMASK(14, 11) 82 #define SPICC_WRITE_BURST_MASK GENMASK(18, 15) 83 #define SPICC_DMA_URGENT BIT(19) 84 #define SPICC_DMA_THREADID_MASK GENMASK(25, 20) 85 #define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26) 86 87 #define SPICC_STATREG 0x14 88 #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */ 89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */ 90 #define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */ 91 #define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */ 92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */ 93 #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */ 94 #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */ 95 #define SPICC_TC BIT(7) /* Transfert Complete Interrupt */ 96 97 #define SPICC_PERIODREG 0x18 98 #define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */ 99 100 #define SPICC_TESTREG 0x1c 101 #define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */ 102 #define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */ 103 #define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */ 104 #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */ 105 #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */ 106 #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */ 107 #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */ 108 #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */ 109 #define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */ 110 #define SPICC_MO_NO_DELAY 0 111 #define SPICC_MO_DELAY_1_CYCLE 1 112 #define SPICC_MO_DELAY_2_CYCLE 2 113 #define SPICC_MO_DELAY_3_CYCLE 3 114 #define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */ 115 #define SPICC_MI_NO_DELAY 0 116 #define SPICC_MI_DELAY_1_CYCLE 1 117 #define SPICC_MI_DELAY_2_CYCLE 2 118 #define SPICC_MI_DELAY_3_CYCLE 3 119 #define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */ 120 #define SPICC_CAP_AHEAD_2_CYCLE 0 121 #define SPICC_CAP_AHEAD_1_CYCLE 1 122 #define SPICC_CAP_NO_DELAY 2 123 #define SPICC_CAP_DELAY_1_CYCLE 3 124 #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */ 125 #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */ 126 127 #define SPICC_DRADDR 0x20 /* Read Address of DMA */ 128 129 #define SPICC_DWADDR 0x24 /* Write Address of DMA */ 130 131 #define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */ 132 #define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0) 133 #define SPICC_ENH_DATARATE_MASK GENMASK(23, 16) 134 #define SPICC_ENH_DATARATE_EN BIT(24) 135 #define SPICC_ENH_MOSI_OEN BIT(25) 136 #define SPICC_ENH_CLK_OEN BIT(26) 137 #define SPICC_ENH_CS_OEN BIT(27) 138 #define SPICC_ENH_CLK_CS_DELAY_EN BIT(28) 139 #define SPICC_ENH_MAIN_CLK_AO BIT(29) 140 141 #define writel_bits_relaxed(mask, val, addr) \ 142 writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) 143 144 struct meson_spicc_data { 145 unsigned int max_speed_hz; 146 unsigned int min_speed_hz; 147 unsigned int fifo_size; 148 bool has_oen; 149 bool has_enhance_clk_div; 150 bool has_pclk; 151 }; 152 153 struct meson_spicc_device { 154 struct spi_master *master; 155 struct platform_device *pdev; 156 void __iomem *base; 157 struct clk *core; 158 struct clk *pclk; 159 struct clk *clk; 160 struct spi_message *message; 161 struct spi_transfer *xfer; 162 const struct meson_spicc_data *data; 163 u8 *tx_buf; 164 u8 *rx_buf; 165 unsigned int bytes_per_word; 166 unsigned long tx_remain; 167 unsigned long rx_remain; 168 unsigned long xfer_remain; 169 }; 170 171 static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) 172 { 173 u32 conf; 174 175 if (!spicc->data->has_oen) 176 return; 177 178 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | 179 SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; 180 181 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); 182 } 183 184 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc) 185 { 186 return !!FIELD_GET(SPICC_TF, 187 readl_relaxed(spicc->base + SPICC_STATREG)); 188 } 189 190 static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc) 191 { 192 return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF, 193 readl_relaxed(spicc->base + SPICC_STATREG)); 194 } 195 196 static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc) 197 { 198 unsigned int bytes = spicc->bytes_per_word; 199 unsigned int byte_shift = 0; 200 u32 data = 0; 201 u8 byte; 202 203 while (bytes--) { 204 byte = *spicc->tx_buf++; 205 data |= (byte & 0xff) << byte_shift; 206 byte_shift += 8; 207 } 208 209 spicc->tx_remain--; 210 return data; 211 } 212 213 static inline void meson_spicc_push_data(struct meson_spicc_device *spicc, 214 u32 data) 215 { 216 unsigned int bytes = spicc->bytes_per_word; 217 unsigned int byte_shift = 0; 218 u8 byte; 219 220 while (bytes--) { 221 byte = (data >> byte_shift) & 0xff; 222 *spicc->rx_buf++ = byte; 223 byte_shift += 8; 224 } 225 226 spicc->rx_remain--; 227 } 228 229 static inline void meson_spicc_rx(struct meson_spicc_device *spicc) 230 { 231 /* Empty RX FIFO */ 232 while (spicc->rx_remain && 233 meson_spicc_rxready(spicc)) 234 meson_spicc_push_data(spicc, 235 readl_relaxed(spicc->base + SPICC_RXDATA)); 236 } 237 238 static inline void meson_spicc_tx(struct meson_spicc_device *spicc) 239 { 240 /* Fill Up TX FIFO */ 241 while (spicc->tx_remain && 242 !meson_spicc_txfull(spicc)) 243 writel_relaxed(meson_spicc_pull_data(spicc), 244 spicc->base + SPICC_TXDATA); 245 } 246 247 static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc) 248 { 249 250 unsigned int burst_len = min_t(unsigned int, 251 spicc->xfer_remain / 252 spicc->bytes_per_word, 253 spicc->data->fifo_size); 254 /* Setup Xfer variables */ 255 spicc->tx_remain = burst_len; 256 spicc->rx_remain = burst_len; 257 spicc->xfer_remain -= burst_len * spicc->bytes_per_word; 258 259 /* Setup burst length */ 260 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, 261 FIELD_PREP(SPICC_BURSTLENGTH_MASK, 262 burst_len - 1), 263 spicc->base + SPICC_CONREG); 264 265 /* Fill TX FIFO */ 266 meson_spicc_tx(spicc); 267 } 268 269 static irqreturn_t meson_spicc_irq(int irq, void *data) 270 { 271 struct meson_spicc_device *spicc = (void *) data; 272 273 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); 274 275 /* Empty RX FIFO */ 276 meson_spicc_rx(spicc); 277 278 if (!spicc->xfer_remain) { 279 /* Disable all IRQs */ 280 writel(0, spicc->base + SPICC_INTREG); 281 282 spi_finalize_current_transfer(spicc->master); 283 284 return IRQ_HANDLED; 285 } 286 287 /* Setup burst */ 288 meson_spicc_setup_burst(spicc); 289 290 /* Start burst */ 291 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); 292 293 return IRQ_HANDLED; 294 } 295 296 static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc) 297 { 298 u32 div, hz; 299 u32 mi_delay, cap_delay; 300 u32 conf; 301 302 if (spicc->data->has_enhance_clk_div) { 303 div = FIELD_GET(SPICC_ENH_DATARATE_MASK, 304 readl_relaxed(spicc->base + SPICC_ENH_CTL0)); 305 div++; 306 div <<= 1; 307 } else { 308 div = FIELD_GET(SPICC_DATARATE_MASK, 309 readl_relaxed(spicc->base + SPICC_CONREG)); 310 div += 2; 311 div = 1 << div; 312 } 313 314 mi_delay = SPICC_MI_NO_DELAY; 315 cap_delay = SPICC_CAP_AHEAD_2_CYCLE; 316 hz = clk_get_rate(spicc->clk); 317 318 if (hz >= 100000000) 319 cap_delay = SPICC_CAP_DELAY_1_CYCLE; 320 else if (hz >= 80000000) 321 cap_delay = SPICC_CAP_NO_DELAY; 322 else if (hz >= 40000000) 323 cap_delay = SPICC_CAP_AHEAD_1_CYCLE; 324 else if (div >= 16) 325 mi_delay = SPICC_MI_DELAY_3_CYCLE; 326 else if (div >= 8) 327 mi_delay = SPICC_MI_DELAY_2_CYCLE; 328 else if (div >= 6) 329 mi_delay = SPICC_MI_DELAY_1_CYCLE; 330 331 conf = readl_relaxed(spicc->base + SPICC_TESTREG); 332 conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK 333 | SPICC_MI_CAP_DELAY_MASK); 334 conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay); 335 conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay); 336 writel_relaxed(conf, spicc->base + SPICC_TESTREG); 337 } 338 339 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, 340 struct spi_transfer *xfer) 341 { 342 u32 conf, conf_orig; 343 344 /* Read original configuration */ 345 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); 346 347 /* Setup word width */ 348 conf &= ~SPICC_BITLENGTH_MASK; 349 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 350 (spicc->bytes_per_word << 3) - 1); 351 352 /* Ignore if unchanged */ 353 if (conf != conf_orig) 354 writel_relaxed(conf, spicc->base + SPICC_CONREG); 355 356 clk_set_rate(spicc->clk, xfer->speed_hz); 357 358 meson_spicc_auto_io_delay(spicc); 359 360 writel_relaxed(0, spicc->base + SPICC_DMAREG); 361 } 362 363 static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc) 364 { 365 if (spicc->data->has_oen) 366 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 367 SPICC_ENH_MAIN_CLK_AO, 368 spicc->base + SPICC_ENH_CTL0); 369 370 writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK, 371 spicc->base + SPICC_TESTREG); 372 373 while (meson_spicc_rxready(spicc)) 374 readl_relaxed(spicc->base + SPICC_RXDATA); 375 376 if (spicc->data->has_oen) 377 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0, 378 spicc->base + SPICC_ENH_CTL0); 379 } 380 381 static int meson_spicc_transfer_one(struct spi_master *master, 382 struct spi_device *spi, 383 struct spi_transfer *xfer) 384 { 385 struct meson_spicc_device *spicc = spi_master_get_devdata(master); 386 387 /* Store current transfer */ 388 spicc->xfer = xfer; 389 390 /* Setup transfer parameters */ 391 spicc->tx_buf = (u8 *)xfer->tx_buf; 392 spicc->rx_buf = (u8 *)xfer->rx_buf; 393 spicc->xfer_remain = xfer->len; 394 395 /* Pre-calculate word size */ 396 spicc->bytes_per_word = 397 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8); 398 399 if (xfer->len % spicc->bytes_per_word) 400 return -EINVAL; 401 402 /* Setup transfer parameters */ 403 meson_spicc_setup_xfer(spicc, xfer); 404 405 meson_spicc_reset_fifo(spicc); 406 407 /* Setup burst */ 408 meson_spicc_setup_burst(spicc); 409 410 /* Start burst */ 411 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); 412 413 /* Enable interrupts */ 414 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG); 415 416 return 1; 417 } 418 419 static int meson_spicc_prepare_message(struct spi_master *master, 420 struct spi_message *message) 421 { 422 struct meson_spicc_device *spicc = spi_master_get_devdata(master); 423 struct spi_device *spi = message->spi; 424 u32 conf = 0; 425 426 /* Store current message */ 427 spicc->message = message; 428 429 /* Enable Master */ 430 conf |= SPICC_ENABLE; 431 conf |= SPICC_MODE_MASTER; 432 433 /* SMC = 0 */ 434 435 /* Setup transfer mode */ 436 if (spi->mode & SPI_CPOL) 437 conf |= SPICC_POL; 438 else 439 conf &= ~SPICC_POL; 440 441 if (spi->mode & SPI_CPHA) 442 conf |= SPICC_PHA; 443 else 444 conf &= ~SPICC_PHA; 445 446 /* SSCTL = 0 */ 447 448 if (spi->mode & SPI_CS_HIGH) 449 conf |= SPICC_SSPOL; 450 else 451 conf &= ~SPICC_SSPOL; 452 453 if (spi->mode & SPI_READY) 454 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL); 455 else 456 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE); 457 458 /* Select CS */ 459 conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select); 460 461 /* Default Clock rate core/4 */ 462 463 /* Default 8bit word */ 464 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1); 465 466 writel_relaxed(conf, spicc->base + SPICC_CONREG); 467 468 /* Setup no wait cycles by default */ 469 writel_relaxed(0, spicc->base + SPICC_PERIODREG); 470 471 writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG); 472 473 return 0; 474 } 475 476 static int meson_spicc_unprepare_transfer(struct spi_master *master) 477 { 478 struct meson_spicc_device *spicc = spi_master_get_devdata(master); 479 480 /* Disable all IRQs */ 481 writel(0, spicc->base + SPICC_INTREG); 482 483 device_reset_optional(&spicc->pdev->dev); 484 485 return 0; 486 } 487 488 static int meson_spicc_setup(struct spi_device *spi) 489 { 490 if (!spi->controller_state) 491 spi->controller_state = spi_master_get_devdata(spi->master); 492 493 return 0; 494 } 495 496 static void meson_spicc_cleanup(struct spi_device *spi) 497 { 498 spi->controller_state = NULL; 499 } 500 501 /* 502 * The Clock Mux 503 * x-----------------x x------------x x------\ 504 * |---| pow2 fixed div |---| pow2 div |----| | 505 * | x-----------------x x------------x | | 506 * src ---| | mux |-- out 507 * | x-----------------x x------------x | | 508 * |---| enh fixed div |---| enh div |0---| | 509 * x-----------------x x------------x x------/ 510 * 511 * Clk path for GX series: 512 * src -> pow2 fixed div -> pow2 div -> out 513 * 514 * Clk path for AXG series: 515 * src -> pow2 fixed div -> pow2 div -> mux -> out 516 * src -> enh fixed div -> enh div -> mux -> out 517 * 518 * Clk path for G12A series: 519 * pclk -> pow2 fixed div -> pow2 div -> mux -> out 520 * pclk -> enh fixed div -> enh div -> mux -> out 521 */ 522 523 static int meson_spicc_clk_init(struct meson_spicc_device *spicc) 524 { 525 struct device *dev = &spicc->pdev->dev; 526 struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div; 527 struct clk_divider *pow2_div, *enh_div; 528 struct clk_mux *mux; 529 struct clk_init_data init; 530 struct clk *clk; 531 struct clk_parent_data parent_data[2]; 532 char name[64]; 533 534 memset(&init, 0, sizeof(init)); 535 memset(&parent_data, 0, sizeof(parent_data)); 536 537 init.parent_data = parent_data; 538 539 /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */ 540 541 pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL); 542 if (!pow2_fixed_div) 543 return -ENOMEM; 544 545 snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev)); 546 init.name = name; 547 init.ops = &clk_fixed_factor_ops; 548 init.flags = 0; 549 if (spicc->data->has_pclk) 550 parent_data[0].hw = __clk_get_hw(spicc->pclk); 551 else 552 parent_data[0].hw = __clk_get_hw(spicc->core); 553 init.num_parents = 1; 554 555 pow2_fixed_div->mult = 1, 556 pow2_fixed_div->div = 4, 557 pow2_fixed_div->hw.init = &init; 558 559 clk = devm_clk_register(dev, &pow2_fixed_div->hw); 560 if (WARN_ON(IS_ERR(clk))) 561 return PTR_ERR(clk); 562 563 pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL); 564 if (!pow2_div) 565 return -ENOMEM; 566 567 snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev)); 568 init.name = name; 569 init.ops = &clk_divider_ops; 570 init.flags = CLK_SET_RATE_PARENT; 571 parent_data[0].hw = &pow2_fixed_div->hw; 572 init.num_parents = 1; 573 574 pow2_div->shift = 16, 575 pow2_div->width = 3, 576 pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO, 577 pow2_div->reg = spicc->base + SPICC_CONREG; 578 pow2_div->hw.init = &init; 579 580 clk = devm_clk_register(dev, &pow2_div->hw); 581 if (WARN_ON(IS_ERR(clk))) 582 return PTR_ERR(clk); 583 584 if (!spicc->data->has_enhance_clk_div) { 585 spicc->clk = clk; 586 return 0; 587 } 588 589 /* algorithm for enh div: rate = freq / 2 / (N + 1) */ 590 591 enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL); 592 if (!enh_fixed_div) 593 return -ENOMEM; 594 595 snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev)); 596 init.name = name; 597 init.ops = &clk_fixed_factor_ops; 598 init.flags = 0; 599 if (spicc->data->has_pclk) 600 parent_data[0].hw = __clk_get_hw(spicc->pclk); 601 else 602 parent_data[0].hw = __clk_get_hw(spicc->core); 603 init.num_parents = 1; 604 605 enh_fixed_div->mult = 1, 606 enh_fixed_div->div = 2, 607 enh_fixed_div->hw.init = &init; 608 609 clk = devm_clk_register(dev, &enh_fixed_div->hw); 610 if (WARN_ON(IS_ERR(clk))) 611 return PTR_ERR(clk); 612 613 enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL); 614 if (!enh_div) 615 return -ENOMEM; 616 617 snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev)); 618 init.name = name; 619 init.ops = &clk_divider_ops; 620 init.flags = CLK_SET_RATE_PARENT; 621 parent_data[0].hw = &enh_fixed_div->hw; 622 init.num_parents = 1; 623 624 enh_div->shift = 16, 625 enh_div->width = 8, 626 enh_div->reg = spicc->base + SPICC_ENH_CTL0; 627 enh_div->hw.init = &init; 628 629 clk = devm_clk_register(dev, &enh_div->hw); 630 if (WARN_ON(IS_ERR(clk))) 631 return PTR_ERR(clk); 632 633 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 634 if (!mux) 635 return -ENOMEM; 636 637 snprintf(name, sizeof(name), "%s#sel", dev_name(dev)); 638 init.name = name; 639 init.ops = &clk_mux_ops; 640 parent_data[0].hw = &pow2_div->hw; 641 parent_data[1].hw = &enh_div->hw; 642 init.num_parents = 2; 643 init.flags = CLK_SET_RATE_PARENT; 644 645 mux->mask = 0x1, 646 mux->shift = 24, 647 mux->reg = spicc->base + SPICC_ENH_CTL0; 648 mux->hw.init = &init; 649 650 spicc->clk = devm_clk_register(dev, &mux->hw); 651 if (WARN_ON(IS_ERR(spicc->clk))) 652 return PTR_ERR(spicc->clk); 653 654 return 0; 655 } 656 657 static int meson_spicc_probe(struct platform_device *pdev) 658 { 659 struct spi_master *master; 660 struct meson_spicc_device *spicc; 661 int ret, irq; 662 663 master = spi_alloc_master(&pdev->dev, sizeof(*spicc)); 664 if (!master) { 665 dev_err(&pdev->dev, "master allocation failed\n"); 666 return -ENOMEM; 667 } 668 spicc = spi_master_get_devdata(master); 669 spicc->master = master; 670 671 spicc->data = of_device_get_match_data(&pdev->dev); 672 if (!spicc->data) { 673 dev_err(&pdev->dev, "failed to get match data\n"); 674 ret = -EINVAL; 675 goto out_master; 676 } 677 678 spicc->pdev = pdev; 679 platform_set_drvdata(pdev, spicc); 680 681 spicc->base = devm_platform_ioremap_resource(pdev, 0); 682 if (IS_ERR(spicc->base)) { 683 dev_err(&pdev->dev, "io resource mapping failed\n"); 684 ret = PTR_ERR(spicc->base); 685 goto out_master; 686 } 687 688 /* Set master mode and enable controller */ 689 writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER, 690 spicc->base + SPICC_CONREG); 691 692 /* Disable all IRQs */ 693 writel_relaxed(0, spicc->base + SPICC_INTREG); 694 695 irq = platform_get_irq(pdev, 0); 696 ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq, 697 0, NULL, spicc); 698 if (ret) { 699 dev_err(&pdev->dev, "irq request failed\n"); 700 goto out_master; 701 } 702 703 spicc->core = devm_clk_get(&pdev->dev, "core"); 704 if (IS_ERR(spicc->core)) { 705 dev_err(&pdev->dev, "core clock request failed\n"); 706 ret = PTR_ERR(spicc->core); 707 goto out_master; 708 } 709 710 if (spicc->data->has_pclk) { 711 spicc->pclk = devm_clk_get(&pdev->dev, "pclk"); 712 if (IS_ERR(spicc->pclk)) { 713 dev_err(&pdev->dev, "pclk clock request failed\n"); 714 ret = PTR_ERR(spicc->pclk); 715 goto out_master; 716 } 717 } 718 719 ret = clk_prepare_enable(spicc->core); 720 if (ret) { 721 dev_err(&pdev->dev, "core clock enable failed\n"); 722 goto out_master; 723 } 724 725 ret = clk_prepare_enable(spicc->pclk); 726 if (ret) { 727 dev_err(&pdev->dev, "pclk clock enable failed\n"); 728 goto out_core_clk; 729 } 730 731 device_reset_optional(&pdev->dev); 732 733 master->num_chipselect = 4; 734 master->dev.of_node = pdev->dev.of_node; 735 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH; 736 master->bits_per_word_mask = SPI_BPW_MASK(32) | 737 SPI_BPW_MASK(24) | 738 SPI_BPW_MASK(16) | 739 SPI_BPW_MASK(8); 740 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); 741 master->min_speed_hz = spicc->data->min_speed_hz; 742 master->max_speed_hz = spicc->data->max_speed_hz; 743 master->setup = meson_spicc_setup; 744 master->cleanup = meson_spicc_cleanup; 745 master->prepare_message = meson_spicc_prepare_message; 746 master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer; 747 master->transfer_one = meson_spicc_transfer_one; 748 master->use_gpio_descriptors = true; 749 750 meson_spicc_oen_enable(spicc); 751 752 ret = meson_spicc_clk_init(spicc); 753 if (ret) { 754 dev_err(&pdev->dev, "clock registration failed\n"); 755 goto out_clk; 756 } 757 758 ret = devm_spi_register_master(&pdev->dev, master); 759 if (ret) { 760 dev_err(&pdev->dev, "spi master registration failed\n"); 761 goto out_clk; 762 } 763 764 return 0; 765 766 out_clk: 767 clk_disable_unprepare(spicc->pclk); 768 769 out_core_clk: 770 clk_disable_unprepare(spicc->core); 771 772 out_master: 773 spi_master_put(master); 774 775 return ret; 776 } 777 778 static int meson_spicc_remove(struct platform_device *pdev) 779 { 780 struct meson_spicc_device *spicc = platform_get_drvdata(pdev); 781 782 /* Disable SPI */ 783 writel(0, spicc->base + SPICC_CONREG); 784 785 clk_disable_unprepare(spicc->core); 786 clk_disable_unprepare(spicc->pclk); 787 788 spi_master_put(spicc->master); 789 790 return 0; 791 } 792 793 static const struct meson_spicc_data meson_spicc_gx_data = { 794 .max_speed_hz = 30000000, 795 .min_speed_hz = 325000, 796 .fifo_size = 16, 797 }; 798 799 static const struct meson_spicc_data meson_spicc_axg_data = { 800 .max_speed_hz = 80000000, 801 .min_speed_hz = 325000, 802 .fifo_size = 16, 803 .has_oen = true, 804 .has_enhance_clk_div = true, 805 }; 806 807 static const struct meson_spicc_data meson_spicc_g12a_data = { 808 .max_speed_hz = 166666666, 809 .min_speed_hz = 50000, 810 .fifo_size = 15, 811 .has_oen = true, 812 .has_enhance_clk_div = true, 813 .has_pclk = true, 814 }; 815 816 static const struct of_device_id meson_spicc_of_match[] = { 817 { 818 .compatible = "amlogic,meson-gx-spicc", 819 .data = &meson_spicc_gx_data, 820 }, 821 { 822 .compatible = "amlogic,meson-axg-spicc", 823 .data = &meson_spicc_axg_data, 824 }, 825 { 826 .compatible = "amlogic,meson-g12a-spicc", 827 .data = &meson_spicc_g12a_data, 828 }, 829 { /* sentinel */ } 830 }; 831 MODULE_DEVICE_TABLE(of, meson_spicc_of_match); 832 833 static struct platform_driver meson_spicc_driver = { 834 .probe = meson_spicc_probe, 835 .remove = meson_spicc_remove, 836 .driver = { 837 .name = "meson-spicc", 838 .of_match_table = of_match_ptr(meson_spicc_of_match), 839 }, 840 }; 841 842 module_platform_driver(meson_spicc_driver); 843 844 MODULE_DESCRIPTION("Meson SPI Communication Controller driver"); 845 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 846 MODULE_LICENSE("GPL"); 847