1 /* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright (C) 2008 Juergen Beisert 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the 16 * Free Software Foundation 17 * 51 Franklin Street, Fifth Floor 18 * Boston, MA 02110-1301, USA. 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/completion.h> 23 #include <linux/delay.h> 24 #include <linux/err.h> 25 #include <linux/gpio.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/irq.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/platform_device.h> 33 #include <linux/slab.h> 34 #include <linux/spi/spi.h> 35 #include <linux/spi/spi_bitbang.h> 36 #include <linux/types.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 #include <linux/of_gpio.h> 40 #include <linux/pinctrl/consumer.h> 41 42 #include <linux/platform_data/spi-imx.h> 43 44 #define DRIVER_NAME "spi_imx" 45 46 #define MXC_CSPIRXDATA 0x00 47 #define MXC_CSPITXDATA 0x04 48 #define MXC_CSPICTRL 0x08 49 #define MXC_CSPIINT 0x0c 50 #define MXC_RESET 0x1c 51 52 /* generic defines to abstract from the different register layouts */ 53 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 54 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 55 56 struct spi_imx_config { 57 unsigned int speed_hz; 58 unsigned int bpw; 59 unsigned int mode; 60 u8 cs; 61 }; 62 63 enum spi_imx_devtype { 64 IMX1_CSPI, 65 IMX21_CSPI, 66 IMX27_CSPI, 67 IMX31_CSPI, 68 IMX35_CSPI, /* CSPI on all i.mx except above */ 69 IMX51_ECSPI, /* ECSPI on i.mx51 and later */ 70 }; 71 72 struct spi_imx_data; 73 74 struct spi_imx_devtype_data { 75 void (*intctrl)(struct spi_imx_data *, int); 76 int (*config)(struct spi_imx_data *, struct spi_imx_config *); 77 void (*trigger)(struct spi_imx_data *); 78 int (*rx_available)(struct spi_imx_data *); 79 void (*reset)(struct spi_imx_data *); 80 enum spi_imx_devtype devtype; 81 }; 82 83 struct spi_imx_data { 84 struct spi_bitbang bitbang; 85 86 struct completion xfer_done; 87 void __iomem *base; 88 int irq; 89 struct clk *clk_per; 90 struct clk *clk_ipg; 91 unsigned long spi_clk; 92 93 unsigned int count; 94 void (*tx)(struct spi_imx_data *); 95 void (*rx)(struct spi_imx_data *); 96 void *rx_buf; 97 const void *tx_buf; 98 unsigned int txfifo; /* number of words pushed in tx FIFO */ 99 100 const struct spi_imx_devtype_data *devtype_data; 101 int chipselect[0]; 102 }; 103 104 static inline int is_imx27_cspi(struct spi_imx_data *d) 105 { 106 return d->devtype_data->devtype == IMX27_CSPI; 107 } 108 109 static inline int is_imx35_cspi(struct spi_imx_data *d) 110 { 111 return d->devtype_data->devtype == IMX35_CSPI; 112 } 113 114 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) 115 { 116 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8; 117 } 118 119 #define MXC_SPI_BUF_RX(type) \ 120 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 121 { \ 122 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 123 \ 124 if (spi_imx->rx_buf) { \ 125 *(type *)spi_imx->rx_buf = val; \ 126 spi_imx->rx_buf += sizeof(type); \ 127 } \ 128 } 129 130 #define MXC_SPI_BUF_TX(type) \ 131 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 132 { \ 133 type val = 0; \ 134 \ 135 if (spi_imx->tx_buf) { \ 136 val = *(type *)spi_imx->tx_buf; \ 137 spi_imx->tx_buf += sizeof(type); \ 138 } \ 139 \ 140 spi_imx->count -= sizeof(type); \ 141 \ 142 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 143 } 144 145 MXC_SPI_BUF_RX(u8) 146 MXC_SPI_BUF_TX(u8) 147 MXC_SPI_BUF_RX(u16) 148 MXC_SPI_BUF_TX(u16) 149 MXC_SPI_BUF_RX(u32) 150 MXC_SPI_BUF_TX(u32) 151 152 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 153 * (which is currently not the case in this driver) 154 */ 155 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 156 256, 384, 512, 768, 1024}; 157 158 /* MX21, MX27 */ 159 static unsigned int spi_imx_clkdiv_1(unsigned int fin, 160 unsigned int fspi, unsigned int max) 161 { 162 int i; 163 164 for (i = 2; i < max; i++) 165 if (fspi * mxc_clkdivs[i] >= fin) 166 return i; 167 168 return max; 169 } 170 171 /* MX1, MX31, MX35, MX51 CSPI */ 172 static unsigned int spi_imx_clkdiv_2(unsigned int fin, 173 unsigned int fspi) 174 { 175 int i, div = 4; 176 177 for (i = 0; i < 7; i++) { 178 if (fspi * div >= fin) 179 return i; 180 div <<= 1; 181 } 182 183 return 7; 184 } 185 186 #define MX51_ECSPI_CTRL 0x08 187 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) 188 #define MX51_ECSPI_CTRL_XCH (1 << 2) 189 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 190 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 191 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 192 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 193 #define MX51_ECSPI_CTRL_BL_OFFSET 20 194 195 #define MX51_ECSPI_CONFIG 0x0c 196 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 197 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) 198 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) 199 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) 200 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) 201 202 #define MX51_ECSPI_INT 0x10 203 #define MX51_ECSPI_INT_TEEN (1 << 0) 204 #define MX51_ECSPI_INT_RREN (1 << 3) 205 206 #define MX51_ECSPI_STAT 0x18 207 #define MX51_ECSPI_STAT_RR (1 << 3) 208 209 /* MX51 eCSPI */ 210 static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi) 211 { 212 /* 213 * there are two 4-bit dividers, the pre-divider divides by 214 * $pre, the post-divider by 2^$post 215 */ 216 unsigned int pre, post; 217 218 if (unlikely(fspi > fin)) 219 return 0; 220 221 post = fls(fin) - fls(fspi); 222 if (fin > fspi << post) 223 post++; 224 225 /* now we have: (fin <= fspi << post) with post being minimal */ 226 227 post = max(4U, post) - 4; 228 if (unlikely(post > 0xf)) { 229 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n", 230 __func__, fspi, fin); 231 return 0xff; 232 } 233 234 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 235 236 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 237 __func__, fin, fspi, post, pre); 238 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 239 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 240 } 241 242 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 243 { 244 unsigned val = 0; 245 246 if (enable & MXC_INT_TE) 247 val |= MX51_ECSPI_INT_TEEN; 248 249 if (enable & MXC_INT_RR) 250 val |= MX51_ECSPI_INT_RREN; 251 252 writel(val, spi_imx->base + MX51_ECSPI_INT); 253 } 254 255 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 256 { 257 u32 reg; 258 259 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 260 reg |= MX51_ECSPI_CTRL_XCH; 261 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 262 } 263 264 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, 265 struct spi_imx_config *config) 266 { 267 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0; 268 269 /* 270 * The hardware seems to have a race condition when changing modes. The 271 * current assumption is that the selection of the channel arrives 272 * earlier in the hardware than the mode bits when they are written at 273 * the same time. 274 * So set master mode for all channels as we do not support slave mode. 275 */ 276 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 277 278 /* set clock speed */ 279 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz); 280 281 /* set chip select to use */ 282 ctrl |= MX51_ECSPI_CTRL_CS(config->cs); 283 284 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; 285 286 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); 287 288 if (config->mode & SPI_CPHA) 289 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); 290 291 if (config->mode & SPI_CPOL) { 292 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); 293 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); 294 } 295 if (config->mode & SPI_CS_HIGH) 296 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); 297 298 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 299 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 300 301 return 0; 302 } 303 304 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 305 { 306 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 307 } 308 309 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) 310 { 311 /* drain receive buffer */ 312 while (mx51_ecspi_rx_available(spi_imx)) 313 readl(spi_imx->base + MXC_CSPIRXDATA); 314 } 315 316 #define MX31_INTREG_TEEN (1 << 0) 317 #define MX31_INTREG_RREN (1 << 3) 318 319 #define MX31_CSPICTRL_ENABLE (1 << 0) 320 #define MX31_CSPICTRL_MASTER (1 << 1) 321 #define MX31_CSPICTRL_XCH (1 << 2) 322 #define MX31_CSPICTRL_POL (1 << 4) 323 #define MX31_CSPICTRL_PHA (1 << 5) 324 #define MX31_CSPICTRL_SSCTL (1 << 6) 325 #define MX31_CSPICTRL_SSPOL (1 << 7) 326 #define MX31_CSPICTRL_BC_SHIFT 8 327 #define MX35_CSPICTRL_BL_SHIFT 20 328 #define MX31_CSPICTRL_CS_SHIFT 24 329 #define MX35_CSPICTRL_CS_SHIFT 12 330 #define MX31_CSPICTRL_DR_SHIFT 16 331 332 #define MX31_CSPISTATUS 0x14 333 #define MX31_STATUS_RR (1 << 3) 334 335 /* These functions also work for the i.MX35, but be aware that 336 * the i.MX35 has a slightly different register layout for bits 337 * we do not use here. 338 */ 339 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 340 { 341 unsigned int val = 0; 342 343 if (enable & MXC_INT_TE) 344 val |= MX31_INTREG_TEEN; 345 if (enable & MXC_INT_RR) 346 val |= MX31_INTREG_RREN; 347 348 writel(val, spi_imx->base + MXC_CSPIINT); 349 } 350 351 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) 352 { 353 unsigned int reg; 354 355 reg = readl(spi_imx->base + MXC_CSPICTRL); 356 reg |= MX31_CSPICTRL_XCH; 357 writel(reg, spi_imx->base + MXC_CSPICTRL); 358 } 359 360 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, 361 struct spi_imx_config *config) 362 { 363 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 364 int cs = spi_imx->chipselect[config->cs]; 365 366 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << 367 MX31_CSPICTRL_DR_SHIFT; 368 369 if (is_imx35_cspi(spi_imx)) { 370 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; 371 reg |= MX31_CSPICTRL_SSCTL; 372 } else { 373 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; 374 } 375 376 if (config->mode & SPI_CPHA) 377 reg |= MX31_CSPICTRL_PHA; 378 if (config->mode & SPI_CPOL) 379 reg |= MX31_CSPICTRL_POL; 380 if (config->mode & SPI_CS_HIGH) 381 reg |= MX31_CSPICTRL_SSPOL; 382 if (cs < 0) 383 reg |= (cs + 32) << 384 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 385 MX31_CSPICTRL_CS_SHIFT); 386 387 writel(reg, spi_imx->base + MXC_CSPICTRL); 388 389 return 0; 390 } 391 392 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) 393 { 394 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 395 } 396 397 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) 398 { 399 /* drain receive buffer */ 400 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 401 readl(spi_imx->base + MXC_CSPIRXDATA); 402 } 403 404 #define MX21_INTREG_RR (1 << 4) 405 #define MX21_INTREG_TEEN (1 << 9) 406 #define MX21_INTREG_RREN (1 << 13) 407 408 #define MX21_CSPICTRL_POL (1 << 5) 409 #define MX21_CSPICTRL_PHA (1 << 6) 410 #define MX21_CSPICTRL_SSPOL (1 << 8) 411 #define MX21_CSPICTRL_XCH (1 << 9) 412 #define MX21_CSPICTRL_ENABLE (1 << 10) 413 #define MX21_CSPICTRL_MASTER (1 << 11) 414 #define MX21_CSPICTRL_DR_SHIFT 14 415 #define MX21_CSPICTRL_CS_SHIFT 19 416 417 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 418 { 419 unsigned int val = 0; 420 421 if (enable & MXC_INT_TE) 422 val |= MX21_INTREG_TEEN; 423 if (enable & MXC_INT_RR) 424 val |= MX21_INTREG_RREN; 425 426 writel(val, spi_imx->base + MXC_CSPIINT); 427 } 428 429 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) 430 { 431 unsigned int reg; 432 433 reg = readl(spi_imx->base + MXC_CSPICTRL); 434 reg |= MX21_CSPICTRL_XCH; 435 writel(reg, spi_imx->base + MXC_CSPICTRL); 436 } 437 438 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, 439 struct spi_imx_config *config) 440 { 441 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; 442 int cs = spi_imx->chipselect[config->cs]; 443 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 444 445 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) << 446 MX21_CSPICTRL_DR_SHIFT; 447 reg |= config->bpw - 1; 448 449 if (config->mode & SPI_CPHA) 450 reg |= MX21_CSPICTRL_PHA; 451 if (config->mode & SPI_CPOL) 452 reg |= MX21_CSPICTRL_POL; 453 if (config->mode & SPI_CS_HIGH) 454 reg |= MX21_CSPICTRL_SSPOL; 455 if (cs < 0) 456 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; 457 458 writel(reg, spi_imx->base + MXC_CSPICTRL); 459 460 return 0; 461 } 462 463 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) 464 { 465 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 466 } 467 468 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) 469 { 470 writel(1, spi_imx->base + MXC_RESET); 471 } 472 473 #define MX1_INTREG_RR (1 << 3) 474 #define MX1_INTREG_TEEN (1 << 8) 475 #define MX1_INTREG_RREN (1 << 11) 476 477 #define MX1_CSPICTRL_POL (1 << 4) 478 #define MX1_CSPICTRL_PHA (1 << 5) 479 #define MX1_CSPICTRL_XCH (1 << 8) 480 #define MX1_CSPICTRL_ENABLE (1 << 9) 481 #define MX1_CSPICTRL_MASTER (1 << 10) 482 #define MX1_CSPICTRL_DR_SHIFT 13 483 484 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 485 { 486 unsigned int val = 0; 487 488 if (enable & MXC_INT_TE) 489 val |= MX1_INTREG_TEEN; 490 if (enable & MXC_INT_RR) 491 val |= MX1_INTREG_RREN; 492 493 writel(val, spi_imx->base + MXC_CSPIINT); 494 } 495 496 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) 497 { 498 unsigned int reg; 499 500 reg = readl(spi_imx->base + MXC_CSPICTRL); 501 reg |= MX1_CSPICTRL_XCH; 502 writel(reg, spi_imx->base + MXC_CSPICTRL); 503 } 504 505 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, 506 struct spi_imx_config *config) 507 { 508 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 509 510 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << 511 MX1_CSPICTRL_DR_SHIFT; 512 reg |= config->bpw - 1; 513 514 if (config->mode & SPI_CPHA) 515 reg |= MX1_CSPICTRL_PHA; 516 if (config->mode & SPI_CPOL) 517 reg |= MX1_CSPICTRL_POL; 518 519 writel(reg, spi_imx->base + MXC_CSPICTRL); 520 521 return 0; 522 } 523 524 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) 525 { 526 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 527 } 528 529 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) 530 { 531 writel(1, spi_imx->base + MXC_RESET); 532 } 533 534 static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 535 .intctrl = mx1_intctrl, 536 .config = mx1_config, 537 .trigger = mx1_trigger, 538 .rx_available = mx1_rx_available, 539 .reset = mx1_reset, 540 .devtype = IMX1_CSPI, 541 }; 542 543 static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 544 .intctrl = mx21_intctrl, 545 .config = mx21_config, 546 .trigger = mx21_trigger, 547 .rx_available = mx21_rx_available, 548 .reset = mx21_reset, 549 .devtype = IMX21_CSPI, 550 }; 551 552 static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 553 /* i.mx27 cspi shares the functions with i.mx21 one */ 554 .intctrl = mx21_intctrl, 555 .config = mx21_config, 556 .trigger = mx21_trigger, 557 .rx_available = mx21_rx_available, 558 .reset = mx21_reset, 559 .devtype = IMX27_CSPI, 560 }; 561 562 static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 563 .intctrl = mx31_intctrl, 564 .config = mx31_config, 565 .trigger = mx31_trigger, 566 .rx_available = mx31_rx_available, 567 .reset = mx31_reset, 568 .devtype = IMX31_CSPI, 569 }; 570 571 static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 572 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 573 .intctrl = mx31_intctrl, 574 .config = mx31_config, 575 .trigger = mx31_trigger, 576 .rx_available = mx31_rx_available, 577 .reset = mx31_reset, 578 .devtype = IMX35_CSPI, 579 }; 580 581 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 582 .intctrl = mx51_ecspi_intctrl, 583 .config = mx51_ecspi_config, 584 .trigger = mx51_ecspi_trigger, 585 .rx_available = mx51_ecspi_rx_available, 586 .reset = mx51_ecspi_reset, 587 .devtype = IMX51_ECSPI, 588 }; 589 590 static struct platform_device_id spi_imx_devtype[] = { 591 { 592 .name = "imx1-cspi", 593 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, 594 }, { 595 .name = "imx21-cspi", 596 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, 597 }, { 598 .name = "imx27-cspi", 599 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, 600 }, { 601 .name = "imx31-cspi", 602 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, 603 }, { 604 .name = "imx35-cspi", 605 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, 606 }, { 607 .name = "imx51-ecspi", 608 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, 609 }, { 610 /* sentinel */ 611 } 612 }; 613 614 static const struct of_device_id spi_imx_dt_ids[] = { 615 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 616 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 617 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 618 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 619 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 620 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 621 { /* sentinel */ } 622 }; 623 624 static void spi_imx_chipselect(struct spi_device *spi, int is_active) 625 { 626 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 627 int gpio = spi_imx->chipselect[spi->chip_select]; 628 int active = is_active != BITBANG_CS_INACTIVE; 629 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); 630 631 if (!gpio_is_valid(gpio)) 632 return; 633 634 gpio_set_value(gpio, dev_is_lowactive ^ active); 635 } 636 637 static void spi_imx_push(struct spi_imx_data *spi_imx) 638 { 639 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { 640 if (!spi_imx->count) 641 break; 642 spi_imx->tx(spi_imx); 643 spi_imx->txfifo++; 644 } 645 646 spi_imx->devtype_data->trigger(spi_imx); 647 } 648 649 static irqreturn_t spi_imx_isr(int irq, void *dev_id) 650 { 651 struct spi_imx_data *spi_imx = dev_id; 652 653 while (spi_imx->devtype_data->rx_available(spi_imx)) { 654 spi_imx->rx(spi_imx); 655 spi_imx->txfifo--; 656 } 657 658 if (spi_imx->count) { 659 spi_imx_push(spi_imx); 660 return IRQ_HANDLED; 661 } 662 663 if (spi_imx->txfifo) { 664 /* No data left to push, but still waiting for rx data, 665 * enable receive data available interrupt. 666 */ 667 spi_imx->devtype_data->intctrl( 668 spi_imx, MXC_INT_RR); 669 return IRQ_HANDLED; 670 } 671 672 spi_imx->devtype_data->intctrl(spi_imx, 0); 673 complete(&spi_imx->xfer_done); 674 675 return IRQ_HANDLED; 676 } 677 678 static int spi_imx_setupxfer(struct spi_device *spi, 679 struct spi_transfer *t) 680 { 681 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 682 struct spi_imx_config config; 683 684 config.bpw = t ? t->bits_per_word : spi->bits_per_word; 685 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; 686 config.mode = spi->mode; 687 config.cs = spi->chip_select; 688 689 if (!config.speed_hz) 690 config.speed_hz = spi->max_speed_hz; 691 if (!config.bpw) 692 config.bpw = spi->bits_per_word; 693 694 /* Initialize the functions for transfer */ 695 if (config.bpw <= 8) { 696 spi_imx->rx = spi_imx_buf_rx_u8; 697 spi_imx->tx = spi_imx_buf_tx_u8; 698 } else if (config.bpw <= 16) { 699 spi_imx->rx = spi_imx_buf_rx_u16; 700 spi_imx->tx = spi_imx_buf_tx_u16; 701 } else if (config.bpw <= 32) { 702 spi_imx->rx = spi_imx_buf_rx_u32; 703 spi_imx->tx = spi_imx_buf_tx_u32; 704 } else 705 BUG(); 706 707 spi_imx->devtype_data->config(spi_imx, &config); 708 709 return 0; 710 } 711 712 static int spi_imx_transfer(struct spi_device *spi, 713 struct spi_transfer *transfer) 714 { 715 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 716 717 spi_imx->tx_buf = transfer->tx_buf; 718 spi_imx->rx_buf = transfer->rx_buf; 719 spi_imx->count = transfer->len; 720 spi_imx->txfifo = 0; 721 722 init_completion(&spi_imx->xfer_done); 723 724 spi_imx_push(spi_imx); 725 726 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 727 728 wait_for_completion(&spi_imx->xfer_done); 729 730 return transfer->len; 731 } 732 733 static int spi_imx_setup(struct spi_device *spi) 734 { 735 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 736 int gpio = spi_imx->chipselect[spi->chip_select]; 737 738 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 739 spi->mode, spi->bits_per_word, spi->max_speed_hz); 740 741 if (gpio_is_valid(gpio)) 742 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); 743 744 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); 745 746 return 0; 747 } 748 749 static void spi_imx_cleanup(struct spi_device *spi) 750 { 751 } 752 753 static int spi_imx_probe(struct platform_device *pdev) 754 { 755 struct device_node *np = pdev->dev.of_node; 756 const struct of_device_id *of_id = 757 of_match_device(spi_imx_dt_ids, &pdev->dev); 758 struct spi_imx_master *mxc_platform_info = 759 dev_get_platdata(&pdev->dev); 760 struct spi_master *master; 761 struct spi_imx_data *spi_imx; 762 struct resource *res; 763 struct pinctrl *pinctrl; 764 int i, ret, num_cs; 765 766 if (!np && !mxc_platform_info) { 767 dev_err(&pdev->dev, "can't get the platform data\n"); 768 return -EINVAL; 769 } 770 771 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); 772 if (ret < 0) { 773 if (mxc_platform_info) 774 num_cs = mxc_platform_info->num_chipselect; 775 else 776 return ret; 777 } 778 779 master = spi_alloc_master(&pdev->dev, 780 sizeof(struct spi_imx_data) + sizeof(int) * num_cs); 781 if (!master) 782 return -ENOMEM; 783 784 platform_set_drvdata(pdev, master); 785 786 master->bus_num = pdev->id; 787 master->num_chipselect = num_cs; 788 789 spi_imx = spi_master_get_devdata(master); 790 spi_imx->bitbang.master = spi_master_get(master); 791 792 for (i = 0; i < master->num_chipselect; i++) { 793 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); 794 if (!gpio_is_valid(cs_gpio) && mxc_platform_info) 795 cs_gpio = mxc_platform_info->chipselect[i]; 796 797 spi_imx->chipselect[i] = cs_gpio; 798 if (!gpio_is_valid(cs_gpio)) 799 continue; 800 801 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME); 802 if (ret) { 803 dev_err(&pdev->dev, "can't get cs gpios\n"); 804 goto out_gpio_free; 805 } 806 } 807 808 spi_imx->bitbang.chipselect = spi_imx_chipselect; 809 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; 810 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; 811 spi_imx->bitbang.master->setup = spi_imx_setup; 812 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; 813 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 814 815 init_completion(&spi_imx->xfer_done); 816 817 spi_imx->devtype_data = of_id ? of_id->data : 818 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data; 819 820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 821 if (!res) { 822 dev_err(&pdev->dev, "can't get platform resource\n"); 823 ret = -ENOMEM; 824 goto out_gpio_free; 825 } 826 827 if (!request_mem_region(res->start, resource_size(res), pdev->name)) { 828 dev_err(&pdev->dev, "request_mem_region failed\n"); 829 ret = -EBUSY; 830 goto out_gpio_free; 831 } 832 833 spi_imx->base = ioremap(res->start, resource_size(res)); 834 if (!spi_imx->base) { 835 ret = -EINVAL; 836 goto out_release_mem; 837 } 838 839 spi_imx->irq = platform_get_irq(pdev, 0); 840 if (spi_imx->irq < 0) { 841 ret = -EINVAL; 842 goto out_iounmap; 843 } 844 845 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx); 846 if (ret) { 847 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret); 848 goto out_iounmap; 849 } 850 851 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 852 if (IS_ERR(pinctrl)) { 853 ret = PTR_ERR(pinctrl); 854 goto out_free_irq; 855 } 856 857 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 858 if (IS_ERR(spi_imx->clk_ipg)) { 859 ret = PTR_ERR(spi_imx->clk_ipg); 860 goto out_free_irq; 861 } 862 863 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 864 if (IS_ERR(spi_imx->clk_per)) { 865 ret = PTR_ERR(spi_imx->clk_per); 866 goto out_free_irq; 867 } 868 869 clk_prepare_enable(spi_imx->clk_per); 870 clk_prepare_enable(spi_imx->clk_ipg); 871 872 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 873 874 spi_imx->devtype_data->reset(spi_imx); 875 876 spi_imx->devtype_data->intctrl(spi_imx, 0); 877 878 master->dev.of_node = pdev->dev.of_node; 879 ret = spi_bitbang_start(&spi_imx->bitbang); 880 if (ret) { 881 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); 882 goto out_clk_put; 883 } 884 885 dev_info(&pdev->dev, "probed\n"); 886 887 return ret; 888 889 out_clk_put: 890 clk_disable_unprepare(spi_imx->clk_per); 891 clk_disable_unprepare(spi_imx->clk_ipg); 892 out_free_irq: 893 free_irq(spi_imx->irq, spi_imx); 894 out_iounmap: 895 iounmap(spi_imx->base); 896 out_release_mem: 897 release_mem_region(res->start, resource_size(res)); 898 out_gpio_free: 899 while (--i >= 0) { 900 if (gpio_is_valid(spi_imx->chipselect[i])) 901 gpio_free(spi_imx->chipselect[i]); 902 } 903 spi_master_put(master); 904 kfree(master); 905 platform_set_drvdata(pdev, NULL); 906 return ret; 907 } 908 909 static int spi_imx_remove(struct platform_device *pdev) 910 { 911 struct spi_master *master = platform_get_drvdata(pdev); 912 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 913 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 914 int i; 915 916 spi_bitbang_stop(&spi_imx->bitbang); 917 918 writel(0, spi_imx->base + MXC_CSPICTRL); 919 clk_disable_unprepare(spi_imx->clk_per); 920 clk_disable_unprepare(spi_imx->clk_ipg); 921 free_irq(spi_imx->irq, spi_imx); 922 iounmap(spi_imx->base); 923 924 for (i = 0; i < master->num_chipselect; i++) 925 if (gpio_is_valid(spi_imx->chipselect[i])) 926 gpio_free(spi_imx->chipselect[i]); 927 928 spi_master_put(master); 929 930 release_mem_region(res->start, resource_size(res)); 931 932 platform_set_drvdata(pdev, NULL); 933 934 return 0; 935 } 936 937 static struct platform_driver spi_imx_driver = { 938 .driver = { 939 .name = DRIVER_NAME, 940 .owner = THIS_MODULE, 941 .of_match_table = spi_imx_dt_ids, 942 }, 943 .id_table = spi_imx_devtype, 944 .probe = spi_imx_probe, 945 .remove = spi_imx_remove, 946 }; 947 module_platform_driver(spi_imx_driver); 948 949 MODULE_DESCRIPTION("SPI Master Controller driver"); 950 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 951 MODULE_LICENSE("GPL"); 952