1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 // Copyright (C) 2008 Juergen Beisert 4 5 #include <linux/clk.h> 6 #include <linux/completion.h> 7 #include <linux/delay.h> 8 #include <linux/dmaengine.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/err.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/slab.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/spi_bitbang.h> 22 #include <linux/types.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/property.h> 26 27 #include <linux/platform_data/dma-imx.h> 28 29 #define DRIVER_NAME "spi_imx" 30 31 static bool use_dma = true; 32 module_param(use_dma, bool, 0644); 33 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)"); 34 35 #define MXC_RPM_TIMEOUT 2000 /* 2000ms */ 36 37 #define MXC_CSPIRXDATA 0x00 38 #define MXC_CSPITXDATA 0x04 39 #define MXC_CSPICTRL 0x08 40 #define MXC_CSPIINT 0x0c 41 #define MXC_RESET 0x1c 42 43 /* generic defines to abstract from the different register layouts */ 44 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 45 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 46 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ 47 48 /* The maximum bytes that a sdma BD can transfer. */ 49 #define MAX_SDMA_BD_BYTES (1 << 15) 50 #define MX51_ECSPI_CTRL_MAX_BURST 512 51 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/ 52 #define MX53_MAX_TRANSFER_BYTES 512 53 54 enum spi_imx_devtype { 55 IMX1_CSPI, 56 IMX21_CSPI, 57 IMX27_CSPI, 58 IMX31_CSPI, 59 IMX35_CSPI, /* CSPI on all i.mx except above */ 60 IMX51_ECSPI, /* ECSPI on i.mx51 */ 61 IMX53_ECSPI, /* ECSPI on i.mx53 and later */ 62 }; 63 64 struct spi_imx_data; 65 66 struct spi_imx_devtype_data { 67 void (*intctrl)(struct spi_imx_data *, int); 68 int (*prepare_message)(struct spi_imx_data *, struct spi_message *); 69 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *); 70 void (*trigger)(struct spi_imx_data *); 71 int (*rx_available)(struct spi_imx_data *); 72 void (*reset)(struct spi_imx_data *); 73 void (*setup_wml)(struct spi_imx_data *); 74 void (*disable)(struct spi_imx_data *); 75 void (*disable_dma)(struct spi_imx_data *); 76 bool has_dmamode; 77 bool has_slavemode; 78 unsigned int fifo_size; 79 bool dynamic_burst; 80 enum spi_imx_devtype devtype; 81 }; 82 83 struct spi_imx_data { 84 struct spi_bitbang bitbang; 85 struct device *dev; 86 87 struct completion xfer_done; 88 void __iomem *base; 89 unsigned long base_phys; 90 91 struct clk *clk_per; 92 struct clk *clk_ipg; 93 unsigned long spi_clk; 94 unsigned int spi_bus_clk; 95 96 unsigned int bits_per_word; 97 unsigned int spi_drctl; 98 99 unsigned int count, remainder; 100 void (*tx)(struct spi_imx_data *); 101 void (*rx)(struct spi_imx_data *); 102 void *rx_buf; 103 const void *tx_buf; 104 unsigned int txfifo; /* number of words pushed in tx FIFO */ 105 unsigned int dynamic_burst; 106 107 /* Slave mode */ 108 bool slave_mode; 109 bool slave_aborted; 110 unsigned int slave_burst; 111 112 /* DMA */ 113 bool usedma; 114 u32 wml; 115 struct completion dma_rx_completion; 116 struct completion dma_tx_completion; 117 118 const struct spi_imx_devtype_data *devtype_data; 119 }; 120 121 static inline int is_imx27_cspi(struct spi_imx_data *d) 122 { 123 return d->devtype_data->devtype == IMX27_CSPI; 124 } 125 126 static inline int is_imx35_cspi(struct spi_imx_data *d) 127 { 128 return d->devtype_data->devtype == IMX35_CSPI; 129 } 130 131 static inline int is_imx51_ecspi(struct spi_imx_data *d) 132 { 133 return d->devtype_data->devtype == IMX51_ECSPI; 134 } 135 136 static inline int is_imx53_ecspi(struct spi_imx_data *d) 137 { 138 return d->devtype_data->devtype == IMX53_ECSPI; 139 } 140 141 #define MXC_SPI_BUF_RX(type) \ 142 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 143 { \ 144 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 145 \ 146 if (spi_imx->rx_buf) { \ 147 *(type *)spi_imx->rx_buf = val; \ 148 spi_imx->rx_buf += sizeof(type); \ 149 } \ 150 \ 151 spi_imx->remainder -= sizeof(type); \ 152 } 153 154 #define MXC_SPI_BUF_TX(type) \ 155 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 156 { \ 157 type val = 0; \ 158 \ 159 if (spi_imx->tx_buf) { \ 160 val = *(type *)spi_imx->tx_buf; \ 161 spi_imx->tx_buf += sizeof(type); \ 162 } \ 163 \ 164 spi_imx->count -= sizeof(type); \ 165 \ 166 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 167 } 168 169 MXC_SPI_BUF_RX(u8) 170 MXC_SPI_BUF_TX(u8) 171 MXC_SPI_BUF_RX(u16) 172 MXC_SPI_BUF_TX(u16) 173 MXC_SPI_BUF_RX(u32) 174 MXC_SPI_BUF_TX(u32) 175 176 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 177 * (which is currently not the case in this driver) 178 */ 179 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 180 256, 384, 512, 768, 1024}; 181 182 /* MX21, MX27 */ 183 static unsigned int spi_imx_clkdiv_1(unsigned int fin, 184 unsigned int fspi, unsigned int max, unsigned int *fres) 185 { 186 int i; 187 188 for (i = 2; i < max; i++) 189 if (fspi * mxc_clkdivs[i] >= fin) 190 break; 191 192 *fres = fin / mxc_clkdivs[i]; 193 return i; 194 } 195 196 /* MX1, MX31, MX35, MX51 CSPI */ 197 static unsigned int spi_imx_clkdiv_2(unsigned int fin, 198 unsigned int fspi, unsigned int *fres) 199 { 200 int i, div = 4; 201 202 for (i = 0; i < 7; i++) { 203 if (fspi * div >= fin) 204 goto out; 205 div <<= 1; 206 } 207 208 out: 209 *fres = fin / div; 210 return i; 211 } 212 213 static int spi_imx_bytes_per_word(const int bits_per_word) 214 { 215 if (bits_per_word <= 8) 216 return 1; 217 else if (bits_per_word <= 16) 218 return 2; 219 else 220 return 4; 221 } 222 223 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, 224 struct spi_transfer *transfer) 225 { 226 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 227 228 if (!use_dma || master->fallback) 229 return false; 230 231 if (!master->dma_rx) 232 return false; 233 234 if (spi_imx->slave_mode) 235 return false; 236 237 if (transfer->len < spi_imx->devtype_data->fifo_size) 238 return false; 239 240 spi_imx->dynamic_burst = 0; 241 242 return true; 243 } 244 245 #define MX51_ECSPI_CTRL 0x08 246 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) 247 #define MX51_ECSPI_CTRL_XCH (1 << 2) 248 #define MX51_ECSPI_CTRL_SMC (1 << 3) 249 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 250 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) 251 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 252 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 253 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 254 #define MX51_ECSPI_CTRL_BL_OFFSET 20 255 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) 256 257 #define MX51_ECSPI_CONFIG 0x0c 258 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 259 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) 260 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) 261 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) 262 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) 263 264 #define MX51_ECSPI_INT 0x10 265 #define MX51_ECSPI_INT_TEEN (1 << 0) 266 #define MX51_ECSPI_INT_RREN (1 << 3) 267 #define MX51_ECSPI_INT_RDREN (1 << 4) 268 269 #define MX51_ECSPI_DMA 0x14 270 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) 271 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) 272 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) 273 274 #define MX51_ECSPI_DMA_TEDEN (1 << 7) 275 #define MX51_ECSPI_DMA_RXDEN (1 << 23) 276 #define MX51_ECSPI_DMA_RXTDEN (1 << 31) 277 278 #define MX51_ECSPI_STAT 0x18 279 #define MX51_ECSPI_STAT_RR (1 << 3) 280 281 #define MX51_ECSPI_TESTREG 0x20 282 #define MX51_ECSPI_TESTREG_LBC BIT(31) 283 284 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) 285 { 286 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); 287 #ifdef __LITTLE_ENDIAN 288 unsigned int bytes_per_word; 289 #endif 290 291 if (spi_imx->rx_buf) { 292 #ifdef __LITTLE_ENDIAN 293 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 294 if (bytes_per_word == 1) 295 val = cpu_to_be32(val); 296 else if (bytes_per_word == 2) 297 val = (val << 16) | (val >> 16); 298 #endif 299 *(u32 *)spi_imx->rx_buf = val; 300 spi_imx->rx_buf += sizeof(u32); 301 } 302 303 spi_imx->remainder -= sizeof(u32); 304 } 305 306 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) 307 { 308 int unaligned; 309 u32 val; 310 311 unaligned = spi_imx->remainder % 4; 312 313 if (!unaligned) { 314 spi_imx_buf_rx_swap_u32(spi_imx); 315 return; 316 } 317 318 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 319 spi_imx_buf_rx_u16(spi_imx); 320 return; 321 } 322 323 val = readl(spi_imx->base + MXC_CSPIRXDATA); 324 325 while (unaligned--) { 326 if (spi_imx->rx_buf) { 327 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; 328 spi_imx->rx_buf++; 329 } 330 spi_imx->remainder--; 331 } 332 } 333 334 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) 335 { 336 u32 val = 0; 337 #ifdef __LITTLE_ENDIAN 338 unsigned int bytes_per_word; 339 #endif 340 341 if (spi_imx->tx_buf) { 342 val = *(u32 *)spi_imx->tx_buf; 343 spi_imx->tx_buf += sizeof(u32); 344 } 345 346 spi_imx->count -= sizeof(u32); 347 #ifdef __LITTLE_ENDIAN 348 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 349 350 if (bytes_per_word == 1) 351 val = cpu_to_be32(val); 352 else if (bytes_per_word == 2) 353 val = (val << 16) | (val >> 16); 354 #endif 355 writel(val, spi_imx->base + MXC_CSPITXDATA); 356 } 357 358 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) 359 { 360 int unaligned; 361 u32 val = 0; 362 363 unaligned = spi_imx->count % 4; 364 365 if (!unaligned) { 366 spi_imx_buf_tx_swap_u32(spi_imx); 367 return; 368 } 369 370 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 371 spi_imx_buf_tx_u16(spi_imx); 372 return; 373 } 374 375 while (unaligned--) { 376 if (spi_imx->tx_buf) { 377 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); 378 spi_imx->tx_buf++; 379 } 380 spi_imx->count--; 381 } 382 383 writel(val, spi_imx->base + MXC_CSPITXDATA); 384 } 385 386 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx) 387 { 388 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); 389 390 if (spi_imx->rx_buf) { 391 int n_bytes = spi_imx->slave_burst % sizeof(val); 392 393 if (!n_bytes) 394 n_bytes = sizeof(val); 395 396 memcpy(spi_imx->rx_buf, 397 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); 398 399 spi_imx->rx_buf += n_bytes; 400 spi_imx->slave_burst -= n_bytes; 401 } 402 403 spi_imx->remainder -= sizeof(u32); 404 } 405 406 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx) 407 { 408 u32 val = 0; 409 int n_bytes = spi_imx->count % sizeof(val); 410 411 if (!n_bytes) 412 n_bytes = sizeof(val); 413 414 if (spi_imx->tx_buf) { 415 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, 416 spi_imx->tx_buf, n_bytes); 417 val = cpu_to_be32(val); 418 spi_imx->tx_buf += n_bytes; 419 } 420 421 spi_imx->count -= n_bytes; 422 423 writel(val, spi_imx->base + MXC_CSPITXDATA); 424 } 425 426 /* MX51 eCSPI */ 427 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, 428 unsigned int fspi, unsigned int *fres) 429 { 430 /* 431 * there are two 4-bit dividers, the pre-divider divides by 432 * $pre, the post-divider by 2^$post 433 */ 434 unsigned int pre, post; 435 unsigned int fin = spi_imx->spi_clk; 436 437 if (unlikely(fspi > fin)) 438 return 0; 439 440 post = fls(fin) - fls(fspi); 441 if (fin > fspi << post) 442 post++; 443 444 /* now we have: (fin <= fspi << post) with post being minimal */ 445 446 post = max(4U, post) - 4; 447 if (unlikely(post > 0xf)) { 448 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", 449 fspi, fin); 450 return 0xff; 451 } 452 453 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 454 455 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 456 __func__, fin, fspi, post, pre); 457 458 /* Resulting frequency for the SCLK line. */ 459 *fres = (fin / (pre + 1)) >> post; 460 461 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 462 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 463 } 464 465 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 466 { 467 unsigned val = 0; 468 469 if (enable & MXC_INT_TE) 470 val |= MX51_ECSPI_INT_TEEN; 471 472 if (enable & MXC_INT_RR) 473 val |= MX51_ECSPI_INT_RREN; 474 475 if (enable & MXC_INT_RDR) 476 val |= MX51_ECSPI_INT_RDREN; 477 478 writel(val, spi_imx->base + MX51_ECSPI_INT); 479 } 480 481 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 482 { 483 u32 reg; 484 485 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 486 reg |= MX51_ECSPI_CTRL_XCH; 487 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 488 } 489 490 static void mx51_disable_dma(struct spi_imx_data *spi_imx) 491 { 492 writel(0, spi_imx->base + MX51_ECSPI_DMA); 493 } 494 495 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) 496 { 497 u32 ctrl; 498 499 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 500 ctrl &= ~MX51_ECSPI_CTRL_ENABLE; 501 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 502 } 503 504 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, 505 struct spi_message *msg) 506 { 507 struct spi_device *spi = msg->spi; 508 struct spi_transfer *xfer; 509 u32 ctrl = MX51_ECSPI_CTRL_ENABLE; 510 u32 min_speed_hz = ~0U; 511 u32 testreg, delay; 512 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); 513 514 /* set Master or Slave mode */ 515 if (spi_imx->slave_mode) 516 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; 517 else 518 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 519 520 /* 521 * Enable SPI_RDY handling (falling edge/level triggered). 522 */ 523 if (spi->mode & SPI_READY) 524 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); 525 526 /* set chip select to use */ 527 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); 528 529 /* 530 * The ctrl register must be written first, with the EN bit set other 531 * registers must not be written to. 532 */ 533 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 534 535 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); 536 if (spi->mode & SPI_LOOP) 537 testreg |= MX51_ECSPI_TESTREG_LBC; 538 else 539 testreg &= ~MX51_ECSPI_TESTREG_LBC; 540 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); 541 542 /* 543 * eCSPI burst completion by Chip Select signal in Slave mode 544 * is not functional for imx53 Soc, config SPI burst completed when 545 * BURST_LENGTH + 1 bits are received 546 */ 547 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 548 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 549 else 550 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); 551 552 if (spi->mode & SPI_CPHA) 553 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 554 else 555 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); 556 557 if (spi->mode & SPI_CPOL) { 558 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 559 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 560 } else { 561 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); 562 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); 563 } 564 565 if (spi->mode & SPI_CS_HIGH) 566 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 567 else 568 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); 569 570 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 571 572 /* 573 * Wait until the changes in the configuration register CONFIGREG 574 * propagate into the hardware. It takes exactly one tick of the 575 * SCLK clock, but we will wait two SCLK clock just to be sure. The 576 * effect of the delay it takes for the hardware to apply changes 577 * is noticable if the SCLK clock run very slow. In such a case, if 578 * the polarity of SCLK should be inverted, the GPIO ChipSelect might 579 * be asserted before the SCLK polarity changes, which would disrupt 580 * the SPI communication as the device on the other end would consider 581 * the change of SCLK polarity as a clock tick already. 582 * 583 * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message 584 * callback, iterate over all the transfers in spi_message, find the 585 * one with lowest bus frequency, and use that bus frequency for the 586 * delay calculation. In case all transfers have speed_hz == 0, then 587 * min_speed_hz is ~0 and the resulting delay is zero. 588 */ 589 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 590 if (!xfer->speed_hz) 591 continue; 592 min_speed_hz = min(xfer->speed_hz, min_speed_hz); 593 } 594 595 delay = (2 * 1000000) / min_speed_hz; 596 if (likely(delay < 10)) /* SCLK is faster than 200 kHz */ 597 udelay(delay); 598 else /* SCLK is _very_ slow */ 599 usleep_range(delay, delay + 10); 600 601 return 0; 602 } 603 604 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, 605 struct spi_device *spi) 606 { 607 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 608 u32 clk; 609 610 /* Clear BL field and set the right value */ 611 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 612 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) 613 ctrl |= (spi_imx->slave_burst * 8 - 1) 614 << MX51_ECSPI_CTRL_BL_OFFSET; 615 else 616 ctrl |= (spi_imx->bits_per_word - 1) 617 << MX51_ECSPI_CTRL_BL_OFFSET; 618 619 /* set clock speed */ 620 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | 621 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET); 622 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); 623 spi_imx->spi_bus_clk = clk; 624 625 if (spi_imx->usedma) 626 ctrl |= MX51_ECSPI_CTRL_SMC; 627 628 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 629 630 return 0; 631 } 632 633 static void mx51_setup_wml(struct spi_imx_data *spi_imx) 634 { 635 /* 636 * Configure the DMA register: setup the watermark 637 * and enable DMA request. 638 */ 639 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | 640 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | 641 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | 642 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN | 643 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); 644 } 645 646 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 647 { 648 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 649 } 650 651 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) 652 { 653 /* drain receive buffer */ 654 while (mx51_ecspi_rx_available(spi_imx)) 655 readl(spi_imx->base + MXC_CSPIRXDATA); 656 } 657 658 #define MX31_INTREG_TEEN (1 << 0) 659 #define MX31_INTREG_RREN (1 << 3) 660 661 #define MX31_CSPICTRL_ENABLE (1 << 0) 662 #define MX31_CSPICTRL_MASTER (1 << 1) 663 #define MX31_CSPICTRL_XCH (1 << 2) 664 #define MX31_CSPICTRL_SMC (1 << 3) 665 #define MX31_CSPICTRL_POL (1 << 4) 666 #define MX31_CSPICTRL_PHA (1 << 5) 667 #define MX31_CSPICTRL_SSCTL (1 << 6) 668 #define MX31_CSPICTRL_SSPOL (1 << 7) 669 #define MX31_CSPICTRL_BC_SHIFT 8 670 #define MX35_CSPICTRL_BL_SHIFT 20 671 #define MX31_CSPICTRL_CS_SHIFT 24 672 #define MX35_CSPICTRL_CS_SHIFT 12 673 #define MX31_CSPICTRL_DR_SHIFT 16 674 675 #define MX31_CSPI_DMAREG 0x10 676 #define MX31_DMAREG_RH_DEN (1<<4) 677 #define MX31_DMAREG_TH_DEN (1<<1) 678 679 #define MX31_CSPISTATUS 0x14 680 #define MX31_STATUS_RR (1 << 3) 681 682 #define MX31_CSPI_TESTREG 0x1C 683 #define MX31_TEST_LBC (1 << 14) 684 685 /* These functions also work for the i.MX35, but be aware that 686 * the i.MX35 has a slightly different register layout for bits 687 * we do not use here. 688 */ 689 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 690 { 691 unsigned int val = 0; 692 693 if (enable & MXC_INT_TE) 694 val |= MX31_INTREG_TEEN; 695 if (enable & MXC_INT_RR) 696 val |= MX31_INTREG_RREN; 697 698 writel(val, spi_imx->base + MXC_CSPIINT); 699 } 700 701 static void mx31_trigger(struct spi_imx_data *spi_imx) 702 { 703 unsigned int reg; 704 705 reg = readl(spi_imx->base + MXC_CSPICTRL); 706 reg |= MX31_CSPICTRL_XCH; 707 writel(reg, spi_imx->base + MXC_CSPICTRL); 708 } 709 710 static int mx31_prepare_message(struct spi_imx_data *spi_imx, 711 struct spi_message *msg) 712 { 713 return 0; 714 } 715 716 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, 717 struct spi_device *spi) 718 { 719 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; 720 unsigned int clk; 721 722 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << 723 MX31_CSPICTRL_DR_SHIFT; 724 spi_imx->spi_bus_clk = clk; 725 726 if (is_imx35_cspi(spi_imx)) { 727 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; 728 reg |= MX31_CSPICTRL_SSCTL; 729 } else { 730 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; 731 } 732 733 if (spi->mode & SPI_CPHA) 734 reg |= MX31_CSPICTRL_PHA; 735 if (spi->mode & SPI_CPOL) 736 reg |= MX31_CSPICTRL_POL; 737 if (spi->mode & SPI_CS_HIGH) 738 reg |= MX31_CSPICTRL_SSPOL; 739 if (!spi->cs_gpiod) 740 reg |= (spi->chip_select) << 741 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 742 MX31_CSPICTRL_CS_SHIFT); 743 744 if (spi_imx->usedma) 745 reg |= MX31_CSPICTRL_SMC; 746 747 writel(reg, spi_imx->base + MXC_CSPICTRL); 748 749 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); 750 if (spi->mode & SPI_LOOP) 751 reg |= MX31_TEST_LBC; 752 else 753 reg &= ~MX31_TEST_LBC; 754 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); 755 756 if (spi_imx->usedma) { 757 /* 758 * configure DMA requests when RXFIFO is half full and 759 * when TXFIFO is half empty 760 */ 761 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, 762 spi_imx->base + MX31_CSPI_DMAREG); 763 } 764 765 return 0; 766 } 767 768 static int mx31_rx_available(struct spi_imx_data *spi_imx) 769 { 770 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 771 } 772 773 static void mx31_reset(struct spi_imx_data *spi_imx) 774 { 775 /* drain receive buffer */ 776 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 777 readl(spi_imx->base + MXC_CSPIRXDATA); 778 } 779 780 #define MX21_INTREG_RR (1 << 4) 781 #define MX21_INTREG_TEEN (1 << 9) 782 #define MX21_INTREG_RREN (1 << 13) 783 784 #define MX21_CSPICTRL_POL (1 << 5) 785 #define MX21_CSPICTRL_PHA (1 << 6) 786 #define MX21_CSPICTRL_SSPOL (1 << 8) 787 #define MX21_CSPICTRL_XCH (1 << 9) 788 #define MX21_CSPICTRL_ENABLE (1 << 10) 789 #define MX21_CSPICTRL_MASTER (1 << 11) 790 #define MX21_CSPICTRL_DR_SHIFT 14 791 #define MX21_CSPICTRL_CS_SHIFT 19 792 793 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 794 { 795 unsigned int val = 0; 796 797 if (enable & MXC_INT_TE) 798 val |= MX21_INTREG_TEEN; 799 if (enable & MXC_INT_RR) 800 val |= MX21_INTREG_RREN; 801 802 writel(val, spi_imx->base + MXC_CSPIINT); 803 } 804 805 static void mx21_trigger(struct spi_imx_data *spi_imx) 806 { 807 unsigned int reg; 808 809 reg = readl(spi_imx->base + MXC_CSPICTRL); 810 reg |= MX21_CSPICTRL_XCH; 811 writel(reg, spi_imx->base + MXC_CSPICTRL); 812 } 813 814 static int mx21_prepare_message(struct spi_imx_data *spi_imx, 815 struct spi_message *msg) 816 { 817 return 0; 818 } 819 820 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, 821 struct spi_device *spi) 822 { 823 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; 824 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 825 unsigned int clk; 826 827 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) 828 << MX21_CSPICTRL_DR_SHIFT; 829 spi_imx->spi_bus_clk = clk; 830 831 reg |= spi_imx->bits_per_word - 1; 832 833 if (spi->mode & SPI_CPHA) 834 reg |= MX21_CSPICTRL_PHA; 835 if (spi->mode & SPI_CPOL) 836 reg |= MX21_CSPICTRL_POL; 837 if (spi->mode & SPI_CS_HIGH) 838 reg |= MX21_CSPICTRL_SSPOL; 839 if (!spi->cs_gpiod) 840 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; 841 842 writel(reg, spi_imx->base + MXC_CSPICTRL); 843 844 return 0; 845 } 846 847 static int mx21_rx_available(struct spi_imx_data *spi_imx) 848 { 849 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 850 } 851 852 static void mx21_reset(struct spi_imx_data *spi_imx) 853 { 854 writel(1, spi_imx->base + MXC_RESET); 855 } 856 857 #define MX1_INTREG_RR (1 << 3) 858 #define MX1_INTREG_TEEN (1 << 8) 859 #define MX1_INTREG_RREN (1 << 11) 860 861 #define MX1_CSPICTRL_POL (1 << 4) 862 #define MX1_CSPICTRL_PHA (1 << 5) 863 #define MX1_CSPICTRL_XCH (1 << 8) 864 #define MX1_CSPICTRL_ENABLE (1 << 9) 865 #define MX1_CSPICTRL_MASTER (1 << 10) 866 #define MX1_CSPICTRL_DR_SHIFT 13 867 868 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 869 { 870 unsigned int val = 0; 871 872 if (enable & MXC_INT_TE) 873 val |= MX1_INTREG_TEEN; 874 if (enable & MXC_INT_RR) 875 val |= MX1_INTREG_RREN; 876 877 writel(val, spi_imx->base + MXC_CSPIINT); 878 } 879 880 static void mx1_trigger(struct spi_imx_data *spi_imx) 881 { 882 unsigned int reg; 883 884 reg = readl(spi_imx->base + MXC_CSPICTRL); 885 reg |= MX1_CSPICTRL_XCH; 886 writel(reg, spi_imx->base + MXC_CSPICTRL); 887 } 888 889 static int mx1_prepare_message(struct spi_imx_data *spi_imx, 890 struct spi_message *msg) 891 { 892 return 0; 893 } 894 895 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx, 896 struct spi_device *spi) 897 { 898 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; 899 unsigned int clk; 900 901 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << 902 MX1_CSPICTRL_DR_SHIFT; 903 spi_imx->spi_bus_clk = clk; 904 905 reg |= spi_imx->bits_per_word - 1; 906 907 if (spi->mode & SPI_CPHA) 908 reg |= MX1_CSPICTRL_PHA; 909 if (spi->mode & SPI_CPOL) 910 reg |= MX1_CSPICTRL_POL; 911 912 writel(reg, spi_imx->base + MXC_CSPICTRL); 913 914 return 0; 915 } 916 917 static int mx1_rx_available(struct spi_imx_data *spi_imx) 918 { 919 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 920 } 921 922 static void mx1_reset(struct spi_imx_data *spi_imx) 923 { 924 writel(1, spi_imx->base + MXC_RESET); 925 } 926 927 static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 928 .intctrl = mx1_intctrl, 929 .prepare_message = mx1_prepare_message, 930 .prepare_transfer = mx1_prepare_transfer, 931 .trigger = mx1_trigger, 932 .rx_available = mx1_rx_available, 933 .reset = mx1_reset, 934 .fifo_size = 8, 935 .has_dmamode = false, 936 .dynamic_burst = false, 937 .has_slavemode = false, 938 .devtype = IMX1_CSPI, 939 }; 940 941 static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 942 .intctrl = mx21_intctrl, 943 .prepare_message = mx21_prepare_message, 944 .prepare_transfer = mx21_prepare_transfer, 945 .trigger = mx21_trigger, 946 .rx_available = mx21_rx_available, 947 .reset = mx21_reset, 948 .fifo_size = 8, 949 .has_dmamode = false, 950 .dynamic_burst = false, 951 .has_slavemode = false, 952 .devtype = IMX21_CSPI, 953 }; 954 955 static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 956 /* i.mx27 cspi shares the functions with i.mx21 one */ 957 .intctrl = mx21_intctrl, 958 .prepare_message = mx21_prepare_message, 959 .prepare_transfer = mx21_prepare_transfer, 960 .trigger = mx21_trigger, 961 .rx_available = mx21_rx_available, 962 .reset = mx21_reset, 963 .fifo_size = 8, 964 .has_dmamode = false, 965 .dynamic_burst = false, 966 .has_slavemode = false, 967 .devtype = IMX27_CSPI, 968 }; 969 970 static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 971 .intctrl = mx31_intctrl, 972 .prepare_message = mx31_prepare_message, 973 .prepare_transfer = mx31_prepare_transfer, 974 .trigger = mx31_trigger, 975 .rx_available = mx31_rx_available, 976 .reset = mx31_reset, 977 .fifo_size = 8, 978 .has_dmamode = false, 979 .dynamic_burst = false, 980 .has_slavemode = false, 981 .devtype = IMX31_CSPI, 982 }; 983 984 static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 985 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 986 .intctrl = mx31_intctrl, 987 .prepare_message = mx31_prepare_message, 988 .prepare_transfer = mx31_prepare_transfer, 989 .trigger = mx31_trigger, 990 .rx_available = mx31_rx_available, 991 .reset = mx31_reset, 992 .fifo_size = 8, 993 .has_dmamode = true, 994 .dynamic_burst = false, 995 .has_slavemode = false, 996 .devtype = IMX35_CSPI, 997 }; 998 999 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 1000 .intctrl = mx51_ecspi_intctrl, 1001 .prepare_message = mx51_ecspi_prepare_message, 1002 .prepare_transfer = mx51_ecspi_prepare_transfer, 1003 .trigger = mx51_ecspi_trigger, 1004 .rx_available = mx51_ecspi_rx_available, 1005 .reset = mx51_ecspi_reset, 1006 .setup_wml = mx51_setup_wml, 1007 .disable_dma = mx51_disable_dma, 1008 .fifo_size = 64, 1009 .has_dmamode = true, 1010 .dynamic_burst = true, 1011 .has_slavemode = true, 1012 .disable = mx51_ecspi_disable, 1013 .devtype = IMX51_ECSPI, 1014 }; 1015 1016 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { 1017 .intctrl = mx51_ecspi_intctrl, 1018 .prepare_message = mx51_ecspi_prepare_message, 1019 .prepare_transfer = mx51_ecspi_prepare_transfer, 1020 .trigger = mx51_ecspi_trigger, 1021 .rx_available = mx51_ecspi_rx_available, 1022 .disable_dma = mx51_disable_dma, 1023 .reset = mx51_ecspi_reset, 1024 .fifo_size = 64, 1025 .has_dmamode = true, 1026 .has_slavemode = true, 1027 .disable = mx51_ecspi_disable, 1028 .devtype = IMX53_ECSPI, 1029 }; 1030 1031 static const struct of_device_id spi_imx_dt_ids[] = { 1032 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 1033 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 1034 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 1035 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 1036 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 1037 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 1038 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, 1039 { /* sentinel */ } 1040 }; 1041 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 1042 1043 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits) 1044 { 1045 u32 ctrl; 1046 1047 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 1048 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 1049 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); 1050 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 1051 } 1052 1053 static void spi_imx_push(struct spi_imx_data *spi_imx) 1054 { 1055 unsigned int burst_len; 1056 1057 /* 1058 * Reload the FIFO when the remaining bytes to be transferred in the 1059 * current burst is 0. This only applies when bits_per_word is a 1060 * multiple of 8. 1061 */ 1062 if (!spi_imx->remainder) { 1063 if (spi_imx->dynamic_burst) { 1064 1065 /* We need to deal unaligned data first */ 1066 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; 1067 1068 if (!burst_len) 1069 burst_len = MX51_ECSPI_CTRL_MAX_BURST; 1070 1071 spi_imx_set_burst_len(spi_imx, burst_len * 8); 1072 1073 spi_imx->remainder = burst_len; 1074 } else { 1075 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word); 1076 } 1077 } 1078 1079 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { 1080 if (!spi_imx->count) 1081 break; 1082 if (spi_imx->dynamic_burst && 1083 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4)) 1084 break; 1085 spi_imx->tx(spi_imx); 1086 spi_imx->txfifo++; 1087 } 1088 1089 if (!spi_imx->slave_mode) 1090 spi_imx->devtype_data->trigger(spi_imx); 1091 } 1092 1093 static irqreturn_t spi_imx_isr(int irq, void *dev_id) 1094 { 1095 struct spi_imx_data *spi_imx = dev_id; 1096 1097 while (spi_imx->txfifo && 1098 spi_imx->devtype_data->rx_available(spi_imx)) { 1099 spi_imx->rx(spi_imx); 1100 spi_imx->txfifo--; 1101 } 1102 1103 if (spi_imx->count) { 1104 spi_imx_push(spi_imx); 1105 return IRQ_HANDLED; 1106 } 1107 1108 if (spi_imx->txfifo) { 1109 /* No data left to push, but still waiting for rx data, 1110 * enable receive data available interrupt. 1111 */ 1112 spi_imx->devtype_data->intctrl( 1113 spi_imx, MXC_INT_RR); 1114 return IRQ_HANDLED; 1115 } 1116 1117 spi_imx->devtype_data->intctrl(spi_imx, 0); 1118 complete(&spi_imx->xfer_done); 1119 1120 return IRQ_HANDLED; 1121 } 1122 1123 static int spi_imx_dma_configure(struct spi_master *master) 1124 { 1125 int ret; 1126 enum dma_slave_buswidth buswidth; 1127 struct dma_slave_config rx = {}, tx = {}; 1128 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1129 1130 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { 1131 case 4: 1132 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 1133 break; 1134 case 2: 1135 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 1136 break; 1137 case 1: 1138 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 1139 break; 1140 default: 1141 return -EINVAL; 1142 } 1143 1144 tx.direction = DMA_MEM_TO_DEV; 1145 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; 1146 tx.dst_addr_width = buswidth; 1147 tx.dst_maxburst = spi_imx->wml; 1148 ret = dmaengine_slave_config(master->dma_tx, &tx); 1149 if (ret) { 1150 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); 1151 return ret; 1152 } 1153 1154 rx.direction = DMA_DEV_TO_MEM; 1155 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; 1156 rx.src_addr_width = buswidth; 1157 rx.src_maxburst = spi_imx->wml; 1158 ret = dmaengine_slave_config(master->dma_rx, &rx); 1159 if (ret) { 1160 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); 1161 return ret; 1162 } 1163 1164 return 0; 1165 } 1166 1167 static int spi_imx_setupxfer(struct spi_device *spi, 1168 struct spi_transfer *t) 1169 { 1170 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1171 1172 if (!t) 1173 return 0; 1174 1175 if (!t->speed_hz) { 1176 if (!spi->max_speed_hz) { 1177 dev_err(&spi->dev, "no speed_hz provided!\n"); 1178 return -EINVAL; 1179 } 1180 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); 1181 spi_imx->spi_bus_clk = spi->max_speed_hz; 1182 } else 1183 spi_imx->spi_bus_clk = t->speed_hz; 1184 1185 spi_imx->bits_per_word = t->bits_per_word; 1186 1187 /* 1188 * Initialize the functions for transfer. To transfer non byte-aligned 1189 * words, we have to use multiple word-size bursts, we can't use 1190 * dynamic_burst in that case. 1191 */ 1192 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && 1193 !(spi->mode & SPI_CS_WORD) && 1194 (spi_imx->bits_per_word == 8 || 1195 spi_imx->bits_per_word == 16 || 1196 spi_imx->bits_per_word == 32)) { 1197 1198 spi_imx->rx = spi_imx_buf_rx_swap; 1199 spi_imx->tx = spi_imx_buf_tx_swap; 1200 spi_imx->dynamic_burst = 1; 1201 1202 } else { 1203 if (spi_imx->bits_per_word <= 8) { 1204 spi_imx->rx = spi_imx_buf_rx_u8; 1205 spi_imx->tx = spi_imx_buf_tx_u8; 1206 } else if (spi_imx->bits_per_word <= 16) { 1207 spi_imx->rx = spi_imx_buf_rx_u16; 1208 spi_imx->tx = spi_imx_buf_tx_u16; 1209 } else { 1210 spi_imx->rx = spi_imx_buf_rx_u32; 1211 spi_imx->tx = spi_imx_buf_tx_u32; 1212 } 1213 spi_imx->dynamic_burst = 0; 1214 } 1215 1216 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) 1217 spi_imx->usedma = true; 1218 else 1219 spi_imx->usedma = false; 1220 1221 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { 1222 spi_imx->rx = mx53_ecspi_rx_slave; 1223 spi_imx->tx = mx53_ecspi_tx_slave; 1224 spi_imx->slave_burst = t->len; 1225 } 1226 1227 spi_imx->devtype_data->prepare_transfer(spi_imx, spi); 1228 1229 return 0; 1230 } 1231 1232 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) 1233 { 1234 struct spi_master *master = spi_imx->bitbang.master; 1235 1236 if (master->dma_rx) { 1237 dma_release_channel(master->dma_rx); 1238 master->dma_rx = NULL; 1239 } 1240 1241 if (master->dma_tx) { 1242 dma_release_channel(master->dma_tx); 1243 master->dma_tx = NULL; 1244 } 1245 } 1246 1247 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, 1248 struct spi_master *master) 1249 { 1250 int ret; 1251 1252 /* use pio mode for i.mx6dl chip TKT238285 */ 1253 if (of_machine_is_compatible("fsl,imx6dl")) 1254 return 0; 1255 1256 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; 1257 1258 /* Prepare for TX DMA: */ 1259 master->dma_tx = dma_request_chan(dev, "tx"); 1260 if (IS_ERR(master->dma_tx)) { 1261 ret = PTR_ERR(master->dma_tx); 1262 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 1263 master->dma_tx = NULL; 1264 goto err; 1265 } 1266 1267 /* Prepare for RX : */ 1268 master->dma_rx = dma_request_chan(dev, "rx"); 1269 if (IS_ERR(master->dma_rx)) { 1270 ret = PTR_ERR(master->dma_rx); 1271 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 1272 master->dma_rx = NULL; 1273 goto err; 1274 } 1275 1276 init_completion(&spi_imx->dma_rx_completion); 1277 init_completion(&spi_imx->dma_tx_completion); 1278 master->can_dma = spi_imx_can_dma; 1279 master->max_dma_len = MAX_SDMA_BD_BYTES; 1280 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | 1281 SPI_MASTER_MUST_TX; 1282 1283 return 0; 1284 err: 1285 spi_imx_sdma_exit(spi_imx); 1286 return ret; 1287 } 1288 1289 static void spi_imx_dma_rx_callback(void *cookie) 1290 { 1291 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1292 1293 complete(&spi_imx->dma_rx_completion); 1294 } 1295 1296 static void spi_imx_dma_tx_callback(void *cookie) 1297 { 1298 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1299 1300 complete(&spi_imx->dma_tx_completion); 1301 } 1302 1303 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) 1304 { 1305 unsigned long timeout = 0; 1306 1307 /* Time with actual data transfer and CS change delay related to HW */ 1308 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; 1309 1310 /* Add extra second for scheduler related activities */ 1311 timeout += 1; 1312 1313 /* Double calculated timeout */ 1314 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); 1315 } 1316 1317 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, 1318 struct spi_transfer *transfer) 1319 { 1320 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 1321 unsigned long transfer_timeout; 1322 unsigned long timeout; 1323 struct spi_master *master = spi_imx->bitbang.master; 1324 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 1325 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); 1326 unsigned int bytes_per_word, i; 1327 int ret; 1328 1329 /* Get the right burst length from the last sg to ensure no tail data */ 1330 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); 1331 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { 1332 if (!(sg_dma_len(last_sg) % (i * bytes_per_word))) 1333 break; 1334 } 1335 /* Use 1 as wml in case no available burst length got */ 1336 if (i == 0) 1337 i = 1; 1338 1339 spi_imx->wml = i; 1340 1341 ret = spi_imx_dma_configure(master); 1342 if (ret) 1343 goto dma_failure_no_start; 1344 1345 if (!spi_imx->devtype_data->setup_wml) { 1346 dev_err(spi_imx->dev, "No setup_wml()?\n"); 1347 ret = -EINVAL; 1348 goto dma_failure_no_start; 1349 } 1350 spi_imx->devtype_data->setup_wml(spi_imx); 1351 1352 /* 1353 * The TX DMA setup starts the transfer, so make sure RX is configured 1354 * before TX. 1355 */ 1356 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, 1357 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 1358 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1359 if (!desc_rx) { 1360 ret = -EINVAL; 1361 goto dma_failure_no_start; 1362 } 1363 1364 desc_rx->callback = spi_imx_dma_rx_callback; 1365 desc_rx->callback_param = (void *)spi_imx; 1366 dmaengine_submit(desc_rx); 1367 reinit_completion(&spi_imx->dma_rx_completion); 1368 dma_async_issue_pending(master->dma_rx); 1369 1370 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, 1371 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 1372 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1373 if (!desc_tx) { 1374 dmaengine_terminate_all(master->dma_tx); 1375 dmaengine_terminate_all(master->dma_rx); 1376 return -EINVAL; 1377 } 1378 1379 desc_tx->callback = spi_imx_dma_tx_callback; 1380 desc_tx->callback_param = (void *)spi_imx; 1381 dmaengine_submit(desc_tx); 1382 reinit_completion(&spi_imx->dma_tx_completion); 1383 dma_async_issue_pending(master->dma_tx); 1384 1385 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1386 1387 /* Wait SDMA to finish the data transfer.*/ 1388 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 1389 transfer_timeout); 1390 if (!timeout) { 1391 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); 1392 dmaengine_terminate_all(master->dma_tx); 1393 dmaengine_terminate_all(master->dma_rx); 1394 return -ETIMEDOUT; 1395 } 1396 1397 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, 1398 transfer_timeout); 1399 if (!timeout) { 1400 dev_err(&master->dev, "I/O Error in DMA RX\n"); 1401 spi_imx->devtype_data->reset(spi_imx); 1402 dmaengine_terminate_all(master->dma_rx); 1403 return -ETIMEDOUT; 1404 } 1405 1406 return transfer->len; 1407 /* fallback to pio */ 1408 dma_failure_no_start: 1409 transfer->error |= SPI_TRANS_FAIL_NO_START; 1410 return ret; 1411 } 1412 1413 static int spi_imx_pio_transfer(struct spi_device *spi, 1414 struct spi_transfer *transfer) 1415 { 1416 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1417 unsigned long transfer_timeout; 1418 unsigned long timeout; 1419 1420 spi_imx->tx_buf = transfer->tx_buf; 1421 spi_imx->rx_buf = transfer->rx_buf; 1422 spi_imx->count = transfer->len; 1423 spi_imx->txfifo = 0; 1424 spi_imx->remainder = 0; 1425 1426 reinit_completion(&spi_imx->xfer_done); 1427 1428 spi_imx_push(spi_imx); 1429 1430 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 1431 1432 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1433 1434 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, 1435 transfer_timeout); 1436 if (!timeout) { 1437 dev_err(&spi->dev, "I/O Error in PIO\n"); 1438 spi_imx->devtype_data->reset(spi_imx); 1439 return -ETIMEDOUT; 1440 } 1441 1442 return transfer->len; 1443 } 1444 1445 static int spi_imx_pio_transfer_slave(struct spi_device *spi, 1446 struct spi_transfer *transfer) 1447 { 1448 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1449 int ret = transfer->len; 1450 1451 if (is_imx53_ecspi(spi_imx) && 1452 transfer->len > MX53_MAX_TRANSFER_BYTES) { 1453 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", 1454 MX53_MAX_TRANSFER_BYTES); 1455 return -EMSGSIZE; 1456 } 1457 1458 spi_imx->tx_buf = transfer->tx_buf; 1459 spi_imx->rx_buf = transfer->rx_buf; 1460 spi_imx->count = transfer->len; 1461 spi_imx->txfifo = 0; 1462 spi_imx->remainder = 0; 1463 1464 reinit_completion(&spi_imx->xfer_done); 1465 spi_imx->slave_aborted = false; 1466 1467 spi_imx_push(spi_imx); 1468 1469 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); 1470 1471 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || 1472 spi_imx->slave_aborted) { 1473 dev_dbg(&spi->dev, "interrupted\n"); 1474 ret = -EINTR; 1475 } 1476 1477 /* ecspi has a HW issue when works in Slave mode, 1478 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty, 1479 * ECSPI_TXDATA keeps shift out the last word data, 1480 * so we have to disable ECSPI when in slave mode after the 1481 * transfer completes 1482 */ 1483 if (spi_imx->devtype_data->disable) 1484 spi_imx->devtype_data->disable(spi_imx); 1485 1486 return ret; 1487 } 1488 1489 static int spi_imx_transfer(struct spi_device *spi, 1490 struct spi_transfer *transfer) 1491 { 1492 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); 1493 1494 transfer->effective_speed_hz = spi_imx->spi_bus_clk; 1495 1496 /* flush rxfifo before transfer */ 1497 while (spi_imx->devtype_data->rx_available(spi_imx)) 1498 readl(spi_imx->base + MXC_CSPIRXDATA); 1499 1500 if (spi_imx->slave_mode) 1501 return spi_imx_pio_transfer_slave(spi, transfer); 1502 1503 if (spi_imx->usedma) 1504 return spi_imx_dma_transfer(spi_imx, transfer); 1505 1506 return spi_imx_pio_transfer(spi, transfer); 1507 } 1508 1509 static int spi_imx_setup(struct spi_device *spi) 1510 { 1511 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1512 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1513 1514 return 0; 1515 } 1516 1517 static void spi_imx_cleanup(struct spi_device *spi) 1518 { 1519 } 1520 1521 static int 1522 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) 1523 { 1524 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1525 int ret; 1526 1527 ret = pm_runtime_get_sync(spi_imx->dev); 1528 if (ret < 0) { 1529 pm_runtime_put_noidle(spi_imx->dev); 1530 dev_err(spi_imx->dev, "failed to enable clock\n"); 1531 return ret; 1532 } 1533 1534 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); 1535 if (ret) { 1536 pm_runtime_mark_last_busy(spi_imx->dev); 1537 pm_runtime_put_autosuspend(spi_imx->dev); 1538 } 1539 1540 return ret; 1541 } 1542 1543 static int 1544 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) 1545 { 1546 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1547 1548 pm_runtime_mark_last_busy(spi_imx->dev); 1549 pm_runtime_put_autosuspend(spi_imx->dev); 1550 return 0; 1551 } 1552 1553 static int spi_imx_slave_abort(struct spi_master *master) 1554 { 1555 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1556 1557 spi_imx->slave_aborted = true; 1558 complete(&spi_imx->xfer_done); 1559 1560 return 0; 1561 } 1562 1563 static int spi_imx_probe(struct platform_device *pdev) 1564 { 1565 struct device_node *np = pdev->dev.of_node; 1566 struct spi_master *master; 1567 struct spi_imx_data *spi_imx; 1568 struct resource *res; 1569 int ret, irq, spi_drctl; 1570 const struct spi_imx_devtype_data *devtype_data = 1571 of_device_get_match_data(&pdev->dev); 1572 bool slave_mode; 1573 u32 val; 1574 1575 slave_mode = devtype_data->has_slavemode && 1576 of_property_read_bool(np, "spi-slave"); 1577 if (slave_mode) 1578 master = spi_alloc_slave(&pdev->dev, 1579 sizeof(struct spi_imx_data)); 1580 else 1581 master = spi_alloc_master(&pdev->dev, 1582 sizeof(struct spi_imx_data)); 1583 if (!master) 1584 return -ENOMEM; 1585 1586 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); 1587 if ((ret < 0) || (spi_drctl >= 0x3)) { 1588 /* '11' is reserved */ 1589 spi_drctl = 0; 1590 } 1591 1592 platform_set_drvdata(pdev, master); 1593 1594 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 1595 master->bus_num = np ? -1 : pdev->id; 1596 master->use_gpio_descriptors = true; 1597 1598 spi_imx = spi_master_get_devdata(master); 1599 spi_imx->bitbang.master = master; 1600 spi_imx->dev = &pdev->dev; 1601 spi_imx->slave_mode = slave_mode; 1602 1603 spi_imx->devtype_data = devtype_data; 1604 1605 /* 1606 * Get number of chip selects from device properties. This can be 1607 * coming from device tree or boardfiles, if it is not defined, 1608 * a default value of 3 chip selects will be used, as all the legacy 1609 * board files have <= 3 chip selects. 1610 */ 1611 if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) 1612 master->num_chipselect = val; 1613 else 1614 master->num_chipselect = 3; 1615 1616 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; 1617 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; 1618 spi_imx->bitbang.master->setup = spi_imx_setup; 1619 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; 1620 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; 1621 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; 1622 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort; 1623 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ 1624 | SPI_NO_CS; 1625 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || 1626 is_imx53_ecspi(spi_imx)) 1627 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; 1628 1629 if (is_imx51_ecspi(spi_imx) && 1630 device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) 1631 /* 1632 * When using HW-CS implementing SPI_CS_WORD can be done by just 1633 * setting the burst length to the word size. This is 1634 * considerably faster than manually controlling the CS. 1635 */ 1636 spi_imx->bitbang.master->mode_bits |= SPI_CS_WORD; 1637 1638 spi_imx->spi_drctl = spi_drctl; 1639 1640 init_completion(&spi_imx->xfer_done); 1641 1642 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1643 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); 1644 if (IS_ERR(spi_imx->base)) { 1645 ret = PTR_ERR(spi_imx->base); 1646 goto out_master_put; 1647 } 1648 spi_imx->base_phys = res->start; 1649 1650 irq = platform_get_irq(pdev, 0); 1651 if (irq < 0) { 1652 ret = irq; 1653 goto out_master_put; 1654 } 1655 1656 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 1657 dev_name(&pdev->dev), spi_imx); 1658 if (ret) { 1659 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 1660 goto out_master_put; 1661 } 1662 1663 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1664 if (IS_ERR(spi_imx->clk_ipg)) { 1665 ret = PTR_ERR(spi_imx->clk_ipg); 1666 goto out_master_put; 1667 } 1668 1669 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1670 if (IS_ERR(spi_imx->clk_per)) { 1671 ret = PTR_ERR(spi_imx->clk_per); 1672 goto out_master_put; 1673 } 1674 1675 ret = clk_prepare_enable(spi_imx->clk_per); 1676 if (ret) 1677 goto out_master_put; 1678 1679 ret = clk_prepare_enable(spi_imx->clk_ipg); 1680 if (ret) 1681 goto out_put_per; 1682 1683 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); 1684 pm_runtime_use_autosuspend(spi_imx->dev); 1685 pm_runtime_get_noresume(spi_imx->dev); 1686 pm_runtime_set_active(spi_imx->dev); 1687 pm_runtime_enable(spi_imx->dev); 1688 1689 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1690 /* 1691 * Only validated on i.mx35 and i.mx6 now, can remove the constraint 1692 * if validated on other chips. 1693 */ 1694 if (spi_imx->devtype_data->has_dmamode) { 1695 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); 1696 if (ret == -EPROBE_DEFER) 1697 goto out_runtime_pm_put; 1698 1699 if (ret < 0) 1700 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", 1701 ret); 1702 } 1703 1704 spi_imx->devtype_data->reset(spi_imx); 1705 1706 spi_imx->devtype_data->intctrl(spi_imx, 0); 1707 1708 master->dev.of_node = pdev->dev.of_node; 1709 ret = spi_bitbang_start(&spi_imx->bitbang); 1710 if (ret) { 1711 dev_err_probe(&pdev->dev, ret, "bitbang start failed\n"); 1712 goto out_bitbang_start; 1713 } 1714 1715 pm_runtime_mark_last_busy(spi_imx->dev); 1716 pm_runtime_put_autosuspend(spi_imx->dev); 1717 1718 return ret; 1719 1720 out_bitbang_start: 1721 if (spi_imx->devtype_data->has_dmamode) 1722 spi_imx_sdma_exit(spi_imx); 1723 out_runtime_pm_put: 1724 pm_runtime_dont_use_autosuspend(spi_imx->dev); 1725 pm_runtime_set_suspended(&pdev->dev); 1726 pm_runtime_disable(spi_imx->dev); 1727 1728 clk_disable_unprepare(spi_imx->clk_ipg); 1729 out_put_per: 1730 clk_disable_unprepare(spi_imx->clk_per); 1731 out_master_put: 1732 spi_master_put(master); 1733 1734 return ret; 1735 } 1736 1737 static int spi_imx_remove(struct platform_device *pdev) 1738 { 1739 struct spi_master *master = platform_get_drvdata(pdev); 1740 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 1741 int ret; 1742 1743 spi_bitbang_stop(&spi_imx->bitbang); 1744 1745 ret = pm_runtime_get_sync(spi_imx->dev); 1746 if (ret < 0) { 1747 pm_runtime_put_noidle(spi_imx->dev); 1748 dev_err(spi_imx->dev, "failed to enable clock\n"); 1749 return ret; 1750 } 1751 1752 writel(0, spi_imx->base + MXC_CSPICTRL); 1753 1754 pm_runtime_dont_use_autosuspend(spi_imx->dev); 1755 pm_runtime_put_sync(spi_imx->dev); 1756 pm_runtime_disable(spi_imx->dev); 1757 1758 spi_imx_sdma_exit(spi_imx); 1759 spi_master_put(master); 1760 1761 return 0; 1762 } 1763 1764 static int __maybe_unused spi_imx_runtime_resume(struct device *dev) 1765 { 1766 struct spi_master *master = dev_get_drvdata(dev); 1767 struct spi_imx_data *spi_imx; 1768 int ret; 1769 1770 spi_imx = spi_master_get_devdata(master); 1771 1772 ret = clk_prepare_enable(spi_imx->clk_per); 1773 if (ret) 1774 return ret; 1775 1776 ret = clk_prepare_enable(spi_imx->clk_ipg); 1777 if (ret) { 1778 clk_disable_unprepare(spi_imx->clk_per); 1779 return ret; 1780 } 1781 1782 return 0; 1783 } 1784 1785 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev) 1786 { 1787 struct spi_master *master = dev_get_drvdata(dev); 1788 struct spi_imx_data *spi_imx; 1789 1790 spi_imx = spi_master_get_devdata(master); 1791 1792 clk_disable_unprepare(spi_imx->clk_per); 1793 clk_disable_unprepare(spi_imx->clk_ipg); 1794 1795 return 0; 1796 } 1797 1798 static int __maybe_unused spi_imx_suspend(struct device *dev) 1799 { 1800 pinctrl_pm_select_sleep_state(dev); 1801 return 0; 1802 } 1803 1804 static int __maybe_unused spi_imx_resume(struct device *dev) 1805 { 1806 pinctrl_pm_select_default_state(dev); 1807 return 0; 1808 } 1809 1810 static const struct dev_pm_ops imx_spi_pm = { 1811 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend, 1812 spi_imx_runtime_resume, NULL) 1813 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume) 1814 }; 1815 1816 static struct platform_driver spi_imx_driver = { 1817 .driver = { 1818 .name = DRIVER_NAME, 1819 .of_match_table = spi_imx_dt_ids, 1820 .pm = &imx_spi_pm, 1821 }, 1822 .probe = spi_imx_probe, 1823 .remove = spi_imx_remove, 1824 }; 1825 module_platform_driver(spi_imx_driver); 1826 1827 MODULE_DESCRIPTION("i.MX SPI Controller driver"); 1828 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1829 MODULE_LICENSE("GPL"); 1830 MODULE_ALIAS("platform:" DRIVER_NAME); 1831