1*e8beacbbSAndreas Larsson /* 2*e8beacbbSAndreas Larsson * Freescale SPI controller driver. 3*e8beacbbSAndreas Larsson * 4*e8beacbbSAndreas Larsson * Maintainer: Kumar Gala 5*e8beacbbSAndreas Larsson * 6*e8beacbbSAndreas Larsson * Copyright (C) 2006 Polycom, Inc. 7*e8beacbbSAndreas Larsson * Copyright 2010 Freescale Semiconductor, Inc. 8*e8beacbbSAndreas Larsson * 9*e8beacbbSAndreas Larsson * CPM SPI and QE buffer descriptors mode support: 10*e8beacbbSAndreas Larsson * Copyright (c) 2009 MontaVista Software, Inc. 11*e8beacbbSAndreas Larsson * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 12*e8beacbbSAndreas Larsson * 13*e8beacbbSAndreas Larsson * This program is free software; you can redistribute it and/or modify it 14*e8beacbbSAndreas Larsson * under the terms of the GNU General Public License as published by the 15*e8beacbbSAndreas Larsson * Free Software Foundation; either version 2 of the License, or (at your 16*e8beacbbSAndreas Larsson * option) any later version. 17*e8beacbbSAndreas Larsson */ 18*e8beacbbSAndreas Larsson 19*e8beacbbSAndreas Larsson #ifndef __SPI_FSL_SPI_H__ 20*e8beacbbSAndreas Larsson #define __SPI_FSL_SPI_H__ 21*e8beacbbSAndreas Larsson 22*e8beacbbSAndreas Larsson /* SPI Controller registers */ 23*e8beacbbSAndreas Larsson struct fsl_spi_reg { 24*e8beacbbSAndreas Larsson u8 res1[0x20]; 25*e8beacbbSAndreas Larsson __be32 mode; 26*e8beacbbSAndreas Larsson __be32 event; 27*e8beacbbSAndreas Larsson __be32 mask; 28*e8beacbbSAndreas Larsson __be32 command; 29*e8beacbbSAndreas Larsson __be32 transmit; 30*e8beacbbSAndreas Larsson __be32 receive; 31*e8beacbbSAndreas Larsson }; 32*e8beacbbSAndreas Larsson 33*e8beacbbSAndreas Larsson /* SPI Controller mode register definitions */ 34*e8beacbbSAndreas Larsson #define SPMODE_LOOP (1 << 30) 35*e8beacbbSAndreas Larsson #define SPMODE_CI_INACTIVEHIGH (1 << 29) 36*e8beacbbSAndreas Larsson #define SPMODE_CP_BEGIN_EDGECLK (1 << 28) 37*e8beacbbSAndreas Larsson #define SPMODE_DIV16 (1 << 27) 38*e8beacbbSAndreas Larsson #define SPMODE_REV (1 << 26) 39*e8beacbbSAndreas Larsson #define SPMODE_MS (1 << 25) 40*e8beacbbSAndreas Larsson #define SPMODE_ENABLE (1 << 24) 41*e8beacbbSAndreas Larsson #define SPMODE_LEN(x) ((x) << 20) 42*e8beacbbSAndreas Larsson #define SPMODE_PM(x) ((x) << 16) 43*e8beacbbSAndreas Larsson #define SPMODE_OP (1 << 14) 44*e8beacbbSAndreas Larsson #define SPMODE_CG(x) ((x) << 7) 45*e8beacbbSAndreas Larsson 46*e8beacbbSAndreas Larsson /* 47*e8beacbbSAndreas Larsson * Default for SPI Mode: 48*e8beacbbSAndreas Larsson * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk 49*e8beacbbSAndreas Larsson */ 50*e8beacbbSAndreas Larsson #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ 51*e8beacbbSAndreas Larsson SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) 52*e8beacbbSAndreas Larsson 53*e8beacbbSAndreas Larsson /* SPIE register values */ 54*e8beacbbSAndreas Larsson #define SPIE_NE 0x00000200 /* Not empty */ 55*e8beacbbSAndreas Larsson #define SPIE_NF 0x00000100 /* Not full */ 56*e8beacbbSAndreas Larsson 57*e8beacbbSAndreas Larsson /* SPIM register values */ 58*e8beacbbSAndreas Larsson #define SPIM_NE 0x00000200 /* Not empty */ 59*e8beacbbSAndreas Larsson #define SPIM_NF 0x00000100 /* Not full */ 60*e8beacbbSAndreas Larsson 61*e8beacbbSAndreas Larsson #endif /* __SPI_FSL_SPI_H__ */ 62