1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2e8beacbbSAndreas Larsson /* 3e8beacbbSAndreas Larsson * Freescale SPI controller driver. 4e8beacbbSAndreas Larsson * 5e8beacbbSAndreas Larsson * Maintainer: Kumar Gala 6e8beacbbSAndreas Larsson * 7e8beacbbSAndreas Larsson * Copyright (C) 2006 Polycom, Inc. 8e8beacbbSAndreas Larsson * Copyright 2010 Freescale Semiconductor, Inc. 9e8beacbbSAndreas Larsson * 10e8beacbbSAndreas Larsson * CPM SPI and QE buffer descriptors mode support: 11e8beacbbSAndreas Larsson * Copyright (c) 2009 MontaVista Software, Inc. 12e8beacbbSAndreas Larsson * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 13e8beacbbSAndreas Larsson * 14447b0c7bSAndreas Larsson * GRLIB support: 15447b0c7bSAndreas Larsson * Copyright (c) 2012 Aeroflex Gaisler AB. 16447b0c7bSAndreas Larsson * Author: Andreas Larsson <andreas@gaisler.com> 17e8beacbbSAndreas Larsson */ 18e8beacbbSAndreas Larsson 19e8beacbbSAndreas Larsson #ifndef __SPI_FSL_SPI_H__ 20e8beacbbSAndreas Larsson #define __SPI_FSL_SPI_H__ 21e8beacbbSAndreas Larsson 22e8beacbbSAndreas Larsson /* SPI Controller registers */ 23e8beacbbSAndreas Larsson struct fsl_spi_reg { 24447b0c7bSAndreas Larsson __be32 cap; /* TYPE_GRLIB specific */ 25447b0c7bSAndreas Larsson u8 res1[0x1C]; 26e8beacbbSAndreas Larsson __be32 mode; 27e8beacbbSAndreas Larsson __be32 event; 28e8beacbbSAndreas Larsson __be32 mask; 29e8beacbbSAndreas Larsson __be32 command; 30e8beacbbSAndreas Larsson __be32 transmit; 31e8beacbbSAndreas Larsson __be32 receive; 32447b0c7bSAndreas Larsson __be32 slvsel; /* TYPE_GRLIB specific */ 33e8beacbbSAndreas Larsson }; 34e8beacbbSAndreas Larsson 35e8beacbbSAndreas Larsson /* SPI Controller mode register definitions */ 36e8beacbbSAndreas Larsson #define SPMODE_LOOP (1 << 30) 37e8beacbbSAndreas Larsson #define SPMODE_CI_INACTIVEHIGH (1 << 29) 38e8beacbbSAndreas Larsson #define SPMODE_CP_BEGIN_EDGECLK (1 << 28) 39e8beacbbSAndreas Larsson #define SPMODE_DIV16 (1 << 27) 40e8beacbbSAndreas Larsson #define SPMODE_REV (1 << 26) 41e8beacbbSAndreas Larsson #define SPMODE_MS (1 << 25) 42e8beacbbSAndreas Larsson #define SPMODE_ENABLE (1 << 24) 43e8beacbbSAndreas Larsson #define SPMODE_LEN(x) ((x) << 20) 44e8beacbbSAndreas Larsson #define SPMODE_PM(x) ((x) << 16) 45e8beacbbSAndreas Larsson #define SPMODE_OP (1 << 14) 46e8beacbbSAndreas Larsson #define SPMODE_CG(x) ((x) << 7) 47e8beacbbSAndreas Larsson 48447b0c7bSAndreas Larsson /* TYPE_GRLIB SPI Controller capability register definitions */ 49447b0c7bSAndreas Larsson #define SPCAP_SSEN(x) (((x) >> 16) & 0x1) 50447b0c7bSAndreas Larsson #define SPCAP_SSSZ(x) (((x) >> 24) & 0xff) 51447b0c7bSAndreas Larsson #define SPCAP_MAXWLEN(x) (((x) >> 20) & 0xf) 52447b0c7bSAndreas Larsson 53e8beacbbSAndreas Larsson /* 54e8beacbbSAndreas Larsson * Default for SPI Mode: 55e8beacbbSAndreas Larsson * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk 56e8beacbbSAndreas Larsson */ 57e8beacbbSAndreas Larsson #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ 58e8beacbbSAndreas Larsson SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) 59e8beacbbSAndreas Larsson 60e8beacbbSAndreas Larsson /* SPIE register values */ 61e8beacbbSAndreas Larsson #define SPIE_NE 0x00000200 /* Not empty */ 62e8beacbbSAndreas Larsson #define SPIE_NF 0x00000100 /* Not full */ 63e8beacbbSAndreas Larsson 64e8beacbbSAndreas Larsson /* SPIM register values */ 65e8beacbbSAndreas Larsson #define SPIM_NE 0x00000200 /* Not empty */ 66e8beacbbSAndreas Larsson #define SPIM_NF 0x00000100 /* Not full */ 67e8beacbbSAndreas Larsson 68e8beacbbSAndreas Larsson #endif /* __SPI_FSL_SPI_H__ */ 69