1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale SPI controller driver. 4 * 5 * Maintainer: Kumar Gala 6 * 7 * Copyright (C) 2006 Polycom, Inc. 8 * Copyright 2010 Freescale Semiconductor, Inc. 9 * 10 * CPM SPI and QE buffer descriptors mode support: 11 * Copyright (c) 2009 MontaVista Software, Inc. 12 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 13 * 14 * GRLIB support: 15 * Copyright (c) 2012 Aeroflex Gaisler AB. 16 * Author: Andreas Larsson <andreas@gaisler.com> 17 */ 18 #include <linux/delay.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/fsl_devices.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/kernel.h> 25 #include <linux/mm.h> 26 #include <linux/module.h> 27 #include <linux/mutex.h> 28 #include <linux/of.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/of_platform.h> 32 #include <linux/platform_device.h> 33 #include <linux/spi/spi.h> 34 #include <linux/spi/spi_bitbang.h> 35 #include <linux/types.h> 36 37 #ifdef CONFIG_FSL_SOC 38 #include <sysdev/fsl_soc.h> 39 #endif 40 41 /* Specific to the MPC8306/MPC8309 */ 42 #define IMMR_SPI_CS_OFFSET 0x14c 43 #define SPI_BOOT_SEL_BIT 0x80000000 44 45 #include "spi-fsl-lib.h" 46 #include "spi-fsl-cpm.h" 47 #include "spi-fsl-spi.h" 48 49 #define TYPE_FSL 0 50 #define TYPE_GRLIB 1 51 52 struct fsl_spi_match_data { 53 int type; 54 }; 55 56 static struct fsl_spi_match_data of_fsl_spi_fsl_config = { 57 .type = TYPE_FSL, 58 }; 59 60 static struct fsl_spi_match_data of_fsl_spi_grlib_config = { 61 .type = TYPE_GRLIB, 62 }; 63 64 static const struct of_device_id of_fsl_spi_match[] = { 65 { 66 .compatible = "fsl,spi", 67 .data = &of_fsl_spi_fsl_config, 68 }, 69 { 70 .compatible = "aeroflexgaisler,spictrl", 71 .data = &of_fsl_spi_grlib_config, 72 }, 73 {} 74 }; 75 MODULE_DEVICE_TABLE(of, of_fsl_spi_match); 76 77 static int fsl_spi_get_type(struct device *dev) 78 { 79 const struct of_device_id *match; 80 81 if (dev->of_node) { 82 match = of_match_node(of_fsl_spi_match, dev->of_node); 83 if (match && match->data) 84 return ((struct fsl_spi_match_data *)match->data)->type; 85 } 86 return TYPE_FSL; 87 } 88 89 static void fsl_spi_change_mode(struct spi_device *spi) 90 { 91 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 92 struct spi_mpc8xxx_cs *cs = spi->controller_state; 93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; 94 __be32 __iomem *mode = ®_base->mode; 95 unsigned long flags; 96 97 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) 98 return; 99 100 /* Turn off IRQs locally to minimize time that SPI is disabled. */ 101 local_irq_save(flags); 102 103 /* Turn off SPI unit prior changing mode */ 104 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); 105 106 /* When in CPM mode, we need to reinit tx and rx. */ 107 if (mspi->flags & SPI_CPM_MODE) { 108 fsl_spi_cpm_reinit_txrx(mspi); 109 } 110 mpc8xxx_spi_write_reg(mode, cs->hw_mode); 111 local_irq_restore(flags); 112 } 113 114 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, 115 int bits_per_word, int msb_first) 116 { 117 *rx_shift = 0; 118 *tx_shift = 0; 119 if (msb_first) { 120 if (bits_per_word <= 8) { 121 *rx_shift = 16; 122 *tx_shift = 24; 123 } else if (bits_per_word <= 16) { 124 *rx_shift = 16; 125 *tx_shift = 16; 126 } 127 } else { 128 if (bits_per_word <= 8) 129 *rx_shift = 8; 130 } 131 } 132 133 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift, 134 int bits_per_word, int msb_first) 135 { 136 *rx_shift = 0; 137 *tx_shift = 0; 138 if (bits_per_word <= 16) { 139 if (msb_first) { 140 *rx_shift = 16; /* LSB in bit 16 */ 141 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ 142 } else { 143 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ 144 } 145 } 146 } 147 148 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, 149 struct spi_device *spi, 150 struct mpc8xxx_spi *mpc8xxx_spi, 151 int bits_per_word) 152 { 153 cs->rx_shift = 0; 154 cs->tx_shift = 0; 155 if (bits_per_word <= 8) { 156 cs->get_rx = mpc8xxx_spi_rx_buf_u8; 157 cs->get_tx = mpc8xxx_spi_tx_buf_u8; 158 } else if (bits_per_word <= 16) { 159 cs->get_rx = mpc8xxx_spi_rx_buf_u16; 160 cs->get_tx = mpc8xxx_spi_tx_buf_u16; 161 } else if (bits_per_word <= 32) { 162 cs->get_rx = mpc8xxx_spi_rx_buf_u32; 163 cs->get_tx = mpc8xxx_spi_tx_buf_u32; 164 } else 165 return -EINVAL; 166 167 if (mpc8xxx_spi->set_shifts) 168 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, 169 bits_per_word, 170 !(spi->mode & SPI_LSB_FIRST)); 171 172 mpc8xxx_spi->rx_shift = cs->rx_shift; 173 mpc8xxx_spi->tx_shift = cs->tx_shift; 174 mpc8xxx_spi->get_rx = cs->get_rx; 175 mpc8xxx_spi->get_tx = cs->get_tx; 176 177 return bits_per_word; 178 } 179 180 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, 181 struct spi_device *spi, 182 int bits_per_word) 183 { 184 /* QE uses Little Endian for words > 8 185 * so transform all words > 8 into 8 bits 186 * Unfortnatly that doesn't work for LSB so 187 * reject these for now */ 188 /* Note: 32 bits word, LSB works iff 189 * tfcr/rfcr is set to CPMFCR_GBL */ 190 if (spi->mode & SPI_LSB_FIRST && 191 bits_per_word > 8) 192 return -EINVAL; 193 if (bits_per_word > 8) 194 return 8; /* pretend its 8 bits */ 195 return bits_per_word; 196 } 197 198 static int fsl_spi_setup_transfer(struct spi_device *spi, 199 struct spi_transfer *t) 200 { 201 struct mpc8xxx_spi *mpc8xxx_spi; 202 int bits_per_word = 0; 203 u8 pm; 204 u32 hz = 0; 205 struct spi_mpc8xxx_cs *cs = spi->controller_state; 206 207 mpc8xxx_spi = spi_master_get_devdata(spi->master); 208 209 if (t) { 210 bits_per_word = t->bits_per_word; 211 hz = t->speed_hz; 212 } 213 214 /* spi_transfer level calls that work per-word */ 215 if (!bits_per_word) 216 bits_per_word = spi->bits_per_word; 217 218 if (!hz) 219 hz = spi->max_speed_hz; 220 221 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) 222 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, 223 mpc8xxx_spi, 224 bits_per_word); 225 else if (mpc8xxx_spi->flags & SPI_QE) 226 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, 227 bits_per_word); 228 229 if (bits_per_word < 0) 230 return bits_per_word; 231 232 if (bits_per_word == 32) 233 bits_per_word = 0; 234 else 235 bits_per_word = bits_per_word - 1; 236 237 /* mask out bits we are going to set */ 238 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 239 | SPMODE_PM(0xF)); 240 241 cs->hw_mode |= SPMODE_LEN(bits_per_word); 242 243 if ((mpc8xxx_spi->spibrg / hz) > 64) { 244 cs->hw_mode |= SPMODE_DIV16; 245 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; 246 WARN_ONCE(pm > 16, 247 "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n", 248 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024); 249 if (pm > 16) 250 pm = 16; 251 } else { 252 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; 253 } 254 if (pm) 255 pm--; 256 257 cs->hw_mode |= SPMODE_PM(pm); 258 259 fsl_spi_change_mode(spi); 260 return 0; 261 } 262 263 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, 264 struct spi_transfer *t, unsigned int len) 265 { 266 u32 word; 267 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; 268 269 mspi->count = len; 270 271 /* enable rx ints */ 272 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 273 274 /* transmit word */ 275 word = mspi->get_tx(mspi); 276 mpc8xxx_spi_write_reg(®_base->transmit, word); 277 278 return 0; 279 } 280 281 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, 282 bool is_dma_mapped) 283 { 284 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 285 struct fsl_spi_reg __iomem *reg_base; 286 unsigned int len = t->len; 287 u8 bits_per_word; 288 int ret; 289 290 reg_base = mpc8xxx_spi->reg_base; 291 bits_per_word = spi->bits_per_word; 292 if (t->bits_per_word) 293 bits_per_word = t->bits_per_word; 294 295 if (bits_per_word > 8) { 296 /* invalid length? */ 297 if (len & 1) 298 return -EINVAL; 299 len /= 2; 300 } 301 if (bits_per_word > 16) { 302 /* invalid length? */ 303 if (len & 1) 304 return -EINVAL; 305 len /= 2; 306 } 307 308 mpc8xxx_spi->tx = t->tx_buf; 309 mpc8xxx_spi->rx = t->rx_buf; 310 311 reinit_completion(&mpc8xxx_spi->done); 312 313 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 314 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); 315 else 316 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); 317 if (ret) 318 return ret; 319 320 wait_for_completion(&mpc8xxx_spi->done); 321 322 /* disable rx ints */ 323 mpc8xxx_spi_write_reg(®_base->mask, 0); 324 325 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 326 fsl_spi_cpm_bufs_complete(mpc8xxx_spi); 327 328 return mpc8xxx_spi->count; 329 } 330 331 static int fsl_spi_prepare_message(struct spi_controller *ctlr, 332 struct spi_message *m) 333 { 334 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr); 335 struct spi_transfer *t; 336 struct spi_transfer *first; 337 338 first = list_first_entry(&m->transfers, struct spi_transfer, 339 transfer_list); 340 341 /* 342 * In CPU mode, optimize large byte transfers to use larger 343 * bits_per_word values to reduce number of interrupts taken. 344 * 345 * Some glitches can appear on the SPI clock when the mode changes. 346 * Check that there is no speed change during the transfer and set it up 347 * now to change the mode without having a chip-select asserted. 348 */ 349 list_for_each_entry(t, &m->transfers, transfer_list) { 350 if (t->speed_hz != first->speed_hz) { 351 dev_err(&m->spi->dev, 352 "speed_hz cannot change during message.\n"); 353 return -EINVAL; 354 } 355 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { 356 if (t->len < 256 || t->bits_per_word != 8) 357 continue; 358 if ((t->len & 3) == 0) 359 t->bits_per_word = 32; 360 else if ((t->len & 1) == 0) 361 t->bits_per_word = 16; 362 } 363 } 364 return fsl_spi_setup_transfer(m->spi, first); 365 } 366 367 static int fsl_spi_transfer_one(struct spi_controller *controller, 368 struct spi_device *spi, 369 struct spi_transfer *t) 370 { 371 int status; 372 373 status = fsl_spi_setup_transfer(spi, t); 374 if (status < 0) 375 return status; 376 if (t->len) 377 status = fsl_spi_bufs(spi, t, !!t->tx_dma || !!t->rx_dma); 378 if (status > 0) 379 return -EMSGSIZE; 380 381 return status; 382 } 383 384 static int fsl_spi_unprepare_message(struct spi_controller *controller, 385 struct spi_message *msg) 386 { 387 return fsl_spi_setup_transfer(msg->spi, NULL); 388 } 389 390 static int fsl_spi_setup(struct spi_device *spi) 391 { 392 struct mpc8xxx_spi *mpc8xxx_spi; 393 struct fsl_spi_reg __iomem *reg_base; 394 bool initial_setup = false; 395 int retval; 396 u32 hw_mode; 397 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 398 399 if (!spi->max_speed_hz) 400 return -EINVAL; 401 402 if (!cs) { 403 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 404 if (!cs) 405 return -ENOMEM; 406 spi_set_ctldata(spi, cs); 407 initial_setup = true; 408 } 409 mpc8xxx_spi = spi_master_get_devdata(spi->master); 410 411 reg_base = mpc8xxx_spi->reg_base; 412 413 hw_mode = cs->hw_mode; /* Save original settings */ 414 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); 415 /* mask out bits we are going to set */ 416 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH 417 | SPMODE_REV | SPMODE_LOOP); 418 419 if (spi->mode & SPI_CPHA) 420 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; 421 if (spi->mode & SPI_CPOL) 422 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; 423 if (!(spi->mode & SPI_LSB_FIRST)) 424 cs->hw_mode |= SPMODE_REV; 425 if (spi->mode & SPI_LOOP) 426 cs->hw_mode |= SPMODE_LOOP; 427 428 retval = fsl_spi_setup_transfer(spi, NULL); 429 if (retval < 0) { 430 cs->hw_mode = hw_mode; /* Restore settings */ 431 if (initial_setup) 432 kfree(cs); 433 return retval; 434 } 435 436 return 0; 437 } 438 439 static void fsl_spi_cleanup(struct spi_device *spi) 440 { 441 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 442 443 kfree(cs); 444 spi_set_ctldata(spi, NULL); 445 } 446 447 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 448 { 449 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; 450 451 /* We need handle RX first */ 452 if (events & SPIE_NE) { 453 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); 454 455 if (mspi->rx) 456 mspi->get_rx(rx_data, mspi); 457 } 458 459 if ((events & SPIE_NF) == 0) 460 /* spin until TX is done */ 461 while (((events = 462 mpc8xxx_spi_read_reg(®_base->event)) & 463 SPIE_NF) == 0) 464 cpu_relax(); 465 466 /* Clear the events */ 467 mpc8xxx_spi_write_reg(®_base->event, events); 468 469 mspi->count -= 1; 470 if (mspi->count) { 471 u32 word = mspi->get_tx(mspi); 472 473 mpc8xxx_spi_write_reg(®_base->transmit, word); 474 } else { 475 complete(&mspi->done); 476 } 477 } 478 479 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) 480 { 481 struct mpc8xxx_spi *mspi = context_data; 482 irqreturn_t ret = IRQ_NONE; 483 u32 events; 484 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; 485 486 /* Get interrupt events(tx/rx) */ 487 events = mpc8xxx_spi_read_reg(®_base->event); 488 if (events) 489 ret = IRQ_HANDLED; 490 491 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); 492 493 if (mspi->flags & SPI_CPM_MODE) 494 fsl_spi_cpm_irq(mspi, events); 495 else 496 fsl_spi_cpu_irq(mspi, events); 497 498 return ret; 499 } 500 501 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) 502 { 503 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 504 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; 505 u32 slvsel; 506 u16 cs = spi->chip_select; 507 508 if (cs < mpc8xxx_spi->native_chipselects) { 509 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); 510 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); 511 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); 512 } 513 } 514 515 static void fsl_spi_grlib_probe(struct device *dev) 516 { 517 struct spi_master *master = dev_get_drvdata(dev); 518 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 519 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; 520 int mbits; 521 u32 capabilities; 522 523 capabilities = mpc8xxx_spi_read_reg(®_base->cap); 524 525 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; 526 mbits = SPCAP_MAXWLEN(capabilities); 527 if (mbits) 528 mpc8xxx_spi->max_bits_per_word = mbits + 1; 529 530 mpc8xxx_spi->native_chipselects = 0; 531 if (SPCAP_SSEN(capabilities)) { 532 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); 533 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); 534 } 535 master->num_chipselect = mpc8xxx_spi->native_chipselects; 536 master->set_cs = fsl_spi_grlib_cs_control; 537 } 538 539 static void fsl_spi_cs_control(struct spi_device *spi, bool on) 540 { 541 struct device *dev = spi->dev.parent->parent; 542 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 543 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 544 545 if (WARN_ON_ONCE(!pinfo->immr_spi_cs)) 546 return; 547 iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs); 548 } 549 550 static struct spi_master *fsl_spi_probe(struct device *dev, 551 struct resource *mem, unsigned int irq) 552 { 553 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 554 struct spi_master *master; 555 struct mpc8xxx_spi *mpc8xxx_spi; 556 struct fsl_spi_reg __iomem *reg_base; 557 u32 regval; 558 int ret = 0; 559 560 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); 561 if (master == NULL) { 562 ret = -ENOMEM; 563 goto err; 564 } 565 566 dev_set_drvdata(dev, master); 567 568 mpc8xxx_spi_probe(dev, mem, irq); 569 570 master->setup = fsl_spi_setup; 571 master->cleanup = fsl_spi_cleanup; 572 master->prepare_message = fsl_spi_prepare_message; 573 master->transfer_one = fsl_spi_transfer_one; 574 master->unprepare_message = fsl_spi_unprepare_message; 575 master->use_gpio_descriptors = true; 576 master->set_cs = fsl_spi_cs_control; 577 578 mpc8xxx_spi = spi_master_get_devdata(master); 579 mpc8xxx_spi->max_bits_per_word = 32; 580 mpc8xxx_spi->type = fsl_spi_get_type(dev); 581 582 ret = fsl_spi_cpm_init(mpc8xxx_spi); 583 if (ret) 584 goto err_cpm_init; 585 586 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); 587 if (IS_ERR(mpc8xxx_spi->reg_base)) { 588 ret = PTR_ERR(mpc8xxx_spi->reg_base); 589 goto err_probe; 590 } 591 592 if (mpc8xxx_spi->type == TYPE_GRLIB) 593 fsl_spi_grlib_probe(dev); 594 595 master->bits_per_word_mask = 596 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) & 597 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); 598 599 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 600 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; 601 602 if (mpc8xxx_spi->set_shifts) 603 /* 8 bits per word and MSB first */ 604 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, 605 &mpc8xxx_spi->tx_shift, 8, 1); 606 607 /* Register for SPI Interrupt */ 608 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq, 609 0, "fsl_spi", mpc8xxx_spi); 610 611 if (ret != 0) 612 goto err_probe; 613 614 reg_base = mpc8xxx_spi->reg_base; 615 616 /* SPI controller initializations */ 617 mpc8xxx_spi_write_reg(®_base->mode, 0); 618 mpc8xxx_spi_write_reg(®_base->mask, 0); 619 mpc8xxx_spi_write_reg(®_base->command, 0); 620 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 621 622 /* Enable SPI interface */ 623 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 624 if (mpc8xxx_spi->max_bits_per_word < 8) { 625 regval &= ~SPMODE_LEN(0xF); 626 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); 627 } 628 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 629 regval |= SPMODE_OP; 630 631 mpc8xxx_spi_write_reg(®_base->mode, regval); 632 633 ret = devm_spi_register_master(dev, master); 634 if (ret < 0) 635 goto err_probe; 636 637 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, 638 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); 639 640 return master; 641 642 err_probe: 643 fsl_spi_cpm_free(mpc8xxx_spi); 644 err_cpm_init: 645 spi_master_put(master); 646 err: 647 return ERR_PTR(ret); 648 } 649 650 static int of_fsl_spi_probe(struct platform_device *ofdev) 651 { 652 struct device *dev = &ofdev->dev; 653 struct device_node *np = ofdev->dev.of_node; 654 struct spi_master *master; 655 struct resource mem; 656 int irq, type; 657 int ret; 658 bool spisel_boot = false; 659 #if IS_ENABLED(CONFIG_FSL_SOC) 660 struct mpc8xxx_spi_probe_info *pinfo = NULL; 661 #endif 662 663 664 ret = of_mpc8xxx_spi_probe(ofdev); 665 if (ret) 666 return ret; 667 668 type = fsl_spi_get_type(&ofdev->dev); 669 if (type == TYPE_FSL) { 670 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 671 #if IS_ENABLED(CONFIG_FSL_SOC) 672 pinfo = to_of_pinfo(pdata); 673 674 spisel_boot = of_property_read_bool(np, "fsl,spisel_boot"); 675 if (spisel_boot) { 676 pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4); 677 if (!pinfo->immr_spi_cs) 678 return -ENOMEM; 679 } 680 #endif 681 /* 682 * Handle the case where we have one hardwired (always selected) 683 * device on the first "chipselect". Else we let the core code 684 * handle any GPIOs or native chip selects and assign the 685 * appropriate callback for dealing with the CS lines. This isn't 686 * supported on the GRLIB variant. 687 */ 688 ret = gpiod_count(dev, "cs"); 689 if (ret < 0) 690 ret = 0; 691 if (ret == 0 && !spisel_boot) 692 pdata->max_chipselect = 1; 693 else 694 pdata->max_chipselect = ret + spisel_boot; 695 } 696 697 ret = of_address_to_resource(np, 0, &mem); 698 if (ret) 699 goto unmap_out; 700 701 irq = platform_get_irq(ofdev, 0); 702 if (irq < 0) { 703 ret = irq; 704 goto unmap_out; 705 } 706 707 master = fsl_spi_probe(dev, &mem, irq); 708 709 return PTR_ERR_OR_ZERO(master); 710 711 unmap_out: 712 #if IS_ENABLED(CONFIG_FSL_SOC) 713 if (spisel_boot) 714 iounmap(pinfo->immr_spi_cs); 715 #endif 716 return ret; 717 } 718 719 static int of_fsl_spi_remove(struct platform_device *ofdev) 720 { 721 struct spi_master *master = platform_get_drvdata(ofdev); 722 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 723 724 fsl_spi_cpm_free(mpc8xxx_spi); 725 return 0; 726 } 727 728 static struct platform_driver of_fsl_spi_driver = { 729 .driver = { 730 .name = "fsl_spi", 731 .of_match_table = of_fsl_spi_match, 732 }, 733 .probe = of_fsl_spi_probe, 734 .remove = of_fsl_spi_remove, 735 }; 736 737 #ifdef CONFIG_MPC832x_RDB 738 /* 739 * XXX XXX XXX 740 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards 741 * only. The driver should go away soon, since newer MPC8323E-RDB's device 742 * tree can work with OpenFirmware driver. But for now we support old trees 743 * as well. 744 */ 745 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) 746 { 747 struct resource *mem; 748 int irq; 749 struct spi_master *master; 750 751 if (!dev_get_platdata(&pdev->dev)) 752 return -EINVAL; 753 754 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 755 if (!mem) 756 return -EINVAL; 757 758 irq = platform_get_irq(pdev, 0); 759 if (irq <= 0) 760 return -EINVAL; 761 762 master = fsl_spi_probe(&pdev->dev, mem, irq); 763 return PTR_ERR_OR_ZERO(master); 764 } 765 766 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) 767 { 768 struct spi_master *master = platform_get_drvdata(pdev); 769 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 770 771 fsl_spi_cpm_free(mpc8xxx_spi); 772 773 return 0; 774 } 775 776 MODULE_ALIAS("platform:mpc8xxx_spi"); 777 static struct platform_driver mpc8xxx_spi_driver = { 778 .probe = plat_mpc8xxx_spi_probe, 779 .remove = plat_mpc8xxx_spi_remove, 780 .driver = { 781 .name = "mpc8xxx_spi", 782 }, 783 }; 784 785 static bool legacy_driver_failed; 786 787 static void __init legacy_driver_register(void) 788 { 789 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); 790 } 791 792 static void __exit legacy_driver_unregister(void) 793 { 794 if (legacy_driver_failed) 795 return; 796 platform_driver_unregister(&mpc8xxx_spi_driver); 797 } 798 #else 799 static void __init legacy_driver_register(void) {} 800 static void __exit legacy_driver_unregister(void) {} 801 #endif /* CONFIG_MPC832x_RDB */ 802 803 static int __init fsl_spi_init(void) 804 { 805 legacy_driver_register(); 806 return platform_driver_register(&of_fsl_spi_driver); 807 } 808 module_init(fsl_spi_init); 809 810 static void __exit fsl_spi_exit(void) 811 { 812 platform_driver_unregister(&of_fsl_spi_driver); 813 legacy_driver_unregister(); 814 } 815 module_exit(fsl_spi_exit); 816 817 MODULE_AUTHOR("Kumar Gala"); 818 MODULE_DESCRIPTION("Simple Freescale SPI Driver"); 819 MODULE_LICENSE("GPL"); 820