1 /* 2 * Freescale SPI controller driver. 3 * 4 * Maintainer: Kumar Gala 5 * 6 * Copyright (C) 2006 Polycom, Inc. 7 * Copyright 2010 Freescale Semiconductor, Inc. 8 * 9 * CPM SPI and QE buffer descriptors mode support: 10 * Copyright (c) 2009 MontaVista Software, Inc. 11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 12 * 13 * GRLIB support: 14 * Copyright (c) 2012 Aeroflex Gaisler AB. 15 * Author: Andreas Larsson <andreas@gaisler.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the 19 * Free Software Foundation; either version 2 of the License, or (at your 20 * option) any later version. 21 */ 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/fsl_devices.h> 25 #include <linux/gpio.h> 26 #include <linux/interrupt.h> 27 #include <linux/irq.h> 28 #include <linux/kernel.h> 29 #include <linux/mm.h> 30 #include <linux/module.h> 31 #include <linux/mutex.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_gpio.h> 36 #include <linux/of_platform.h> 37 #include <linux/platform_device.h> 38 #include <linux/spi/spi.h> 39 #include <linux/spi/spi_bitbang.h> 40 #include <linux/types.h> 41 42 #include "spi-fsl-lib.h" 43 #include "spi-fsl-cpm.h" 44 #include "spi-fsl-spi.h" 45 46 #define TYPE_FSL 0 47 #define TYPE_GRLIB 1 48 49 struct fsl_spi_match_data { 50 int type; 51 }; 52 53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = { 54 .type = TYPE_FSL, 55 }; 56 57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = { 58 .type = TYPE_GRLIB, 59 }; 60 61 static const struct of_device_id of_fsl_spi_match[] = { 62 { 63 .compatible = "fsl,spi", 64 .data = &of_fsl_spi_fsl_config, 65 }, 66 { 67 .compatible = "aeroflexgaisler,spictrl", 68 .data = &of_fsl_spi_grlib_config, 69 }, 70 {} 71 }; 72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match); 73 74 static int fsl_spi_get_type(struct device *dev) 75 { 76 const struct of_device_id *match; 77 78 if (dev->of_node) { 79 match = of_match_node(of_fsl_spi_match, dev->of_node); 80 if (match && match->data) 81 return ((struct fsl_spi_match_data *)match->data)->type; 82 } 83 return TYPE_FSL; 84 } 85 86 static void fsl_spi_change_mode(struct spi_device *spi) 87 { 88 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 89 struct spi_mpc8xxx_cs *cs = spi->controller_state; 90 struct fsl_spi_reg *reg_base = mspi->reg_base; 91 __be32 __iomem *mode = ®_base->mode; 92 unsigned long flags; 93 94 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) 95 return; 96 97 /* Turn off IRQs locally to minimize time that SPI is disabled. */ 98 local_irq_save(flags); 99 100 /* Turn off SPI unit prior changing mode */ 101 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); 102 103 /* When in CPM mode, we need to reinit tx and rx. */ 104 if (mspi->flags & SPI_CPM_MODE) { 105 fsl_spi_cpm_reinit_txrx(mspi); 106 } 107 mpc8xxx_spi_write_reg(mode, cs->hw_mode); 108 local_irq_restore(flags); 109 } 110 111 static void fsl_spi_chipselect(struct spi_device *spi, int value) 112 { 113 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 114 struct fsl_spi_platform_data *pdata; 115 bool pol = spi->mode & SPI_CS_HIGH; 116 struct spi_mpc8xxx_cs *cs = spi->controller_state; 117 118 pdata = spi->dev.parent->parent->platform_data; 119 120 if (value == BITBANG_CS_INACTIVE) { 121 if (pdata->cs_control) 122 pdata->cs_control(spi, !pol); 123 } 124 125 if (value == BITBANG_CS_ACTIVE) { 126 mpc8xxx_spi->rx_shift = cs->rx_shift; 127 mpc8xxx_spi->tx_shift = cs->tx_shift; 128 mpc8xxx_spi->get_rx = cs->get_rx; 129 mpc8xxx_spi->get_tx = cs->get_tx; 130 131 fsl_spi_change_mode(spi); 132 133 if (pdata->cs_control) 134 pdata->cs_control(spi, pol); 135 } 136 } 137 138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, 139 int bits_per_word, int msb_first) 140 { 141 *rx_shift = 0; 142 *tx_shift = 0; 143 if (msb_first) { 144 if (bits_per_word <= 8) { 145 *rx_shift = 16; 146 *tx_shift = 24; 147 } else if (bits_per_word <= 16) { 148 *rx_shift = 16; 149 *tx_shift = 16; 150 } 151 } else { 152 if (bits_per_word <= 8) 153 *rx_shift = 8; 154 } 155 } 156 157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift, 158 int bits_per_word, int msb_first) 159 { 160 *rx_shift = 0; 161 *tx_shift = 0; 162 if (bits_per_word <= 16) { 163 if (msb_first) { 164 *rx_shift = 16; /* LSB in bit 16 */ 165 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ 166 } else { 167 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ 168 } 169 } 170 } 171 172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, 173 struct spi_device *spi, 174 struct mpc8xxx_spi *mpc8xxx_spi, 175 int bits_per_word) 176 { 177 cs->rx_shift = 0; 178 cs->tx_shift = 0; 179 if (bits_per_word <= 8) { 180 cs->get_rx = mpc8xxx_spi_rx_buf_u8; 181 cs->get_tx = mpc8xxx_spi_tx_buf_u8; 182 } else if (bits_per_word <= 16) { 183 cs->get_rx = mpc8xxx_spi_rx_buf_u16; 184 cs->get_tx = mpc8xxx_spi_tx_buf_u16; 185 } else if (bits_per_word <= 32) { 186 cs->get_rx = mpc8xxx_spi_rx_buf_u32; 187 cs->get_tx = mpc8xxx_spi_tx_buf_u32; 188 } else 189 return -EINVAL; 190 191 if (mpc8xxx_spi->set_shifts) 192 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, 193 bits_per_word, 194 !(spi->mode & SPI_LSB_FIRST)); 195 196 mpc8xxx_spi->rx_shift = cs->rx_shift; 197 mpc8xxx_spi->tx_shift = cs->tx_shift; 198 mpc8xxx_spi->get_rx = cs->get_rx; 199 mpc8xxx_spi->get_tx = cs->get_tx; 200 201 return bits_per_word; 202 } 203 204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, 205 struct spi_device *spi, 206 int bits_per_word) 207 { 208 /* QE uses Little Endian for words > 8 209 * so transform all words > 8 into 8 bits 210 * Unfortnatly that doesn't work for LSB so 211 * reject these for now */ 212 /* Note: 32 bits word, LSB works iff 213 * tfcr/rfcr is set to CPMFCR_GBL */ 214 if (spi->mode & SPI_LSB_FIRST && 215 bits_per_word > 8) 216 return -EINVAL; 217 if (bits_per_word > 8) 218 return 8; /* pretend its 8 bits */ 219 return bits_per_word; 220 } 221 222 static int fsl_spi_setup_transfer(struct spi_device *spi, 223 struct spi_transfer *t) 224 { 225 struct mpc8xxx_spi *mpc8xxx_spi; 226 int bits_per_word = 0; 227 u8 pm; 228 u32 hz = 0; 229 struct spi_mpc8xxx_cs *cs = spi->controller_state; 230 231 mpc8xxx_spi = spi_master_get_devdata(spi->master); 232 233 if (t) { 234 bits_per_word = t->bits_per_word; 235 hz = t->speed_hz; 236 } 237 238 /* spi_transfer level calls that work per-word */ 239 if (!bits_per_word) 240 bits_per_word = spi->bits_per_word; 241 242 if (!hz) 243 hz = spi->max_speed_hz; 244 245 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) 246 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, 247 mpc8xxx_spi, 248 bits_per_word); 249 else if (mpc8xxx_spi->flags & SPI_QE) 250 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, 251 bits_per_word); 252 253 if (bits_per_word < 0) 254 return bits_per_word; 255 256 if (bits_per_word == 32) 257 bits_per_word = 0; 258 else 259 bits_per_word = bits_per_word - 1; 260 261 /* mask out bits we are going to set */ 262 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 263 | SPMODE_PM(0xF)); 264 265 cs->hw_mode |= SPMODE_LEN(bits_per_word); 266 267 if ((mpc8xxx_spi->spibrg / hz) > 64) { 268 cs->hw_mode |= SPMODE_DIV16; 269 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; 270 WARN_ONCE(pm > 16, 271 "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n", 272 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024); 273 if (pm > 16) 274 pm = 16; 275 } else { 276 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; 277 } 278 if (pm) 279 pm--; 280 281 cs->hw_mode |= SPMODE_PM(pm); 282 283 fsl_spi_change_mode(spi); 284 return 0; 285 } 286 287 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, 288 struct spi_transfer *t, unsigned int len) 289 { 290 u32 word; 291 struct fsl_spi_reg *reg_base = mspi->reg_base; 292 293 mspi->count = len; 294 295 /* enable rx ints */ 296 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 297 298 /* transmit word */ 299 word = mspi->get_tx(mspi); 300 mpc8xxx_spi_write_reg(®_base->transmit, word); 301 302 return 0; 303 } 304 305 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, 306 bool is_dma_mapped) 307 { 308 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 309 struct fsl_spi_reg *reg_base; 310 unsigned int len = t->len; 311 u8 bits_per_word; 312 int ret; 313 314 reg_base = mpc8xxx_spi->reg_base; 315 bits_per_word = spi->bits_per_word; 316 if (t->bits_per_word) 317 bits_per_word = t->bits_per_word; 318 319 if (bits_per_word > 8) { 320 /* invalid length? */ 321 if (len & 1) 322 return -EINVAL; 323 len /= 2; 324 } 325 if (bits_per_word > 16) { 326 /* invalid length? */ 327 if (len & 1) 328 return -EINVAL; 329 len /= 2; 330 } 331 332 mpc8xxx_spi->tx = t->tx_buf; 333 mpc8xxx_spi->rx = t->rx_buf; 334 335 reinit_completion(&mpc8xxx_spi->done); 336 337 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 338 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); 339 else 340 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); 341 if (ret) 342 return ret; 343 344 wait_for_completion(&mpc8xxx_spi->done); 345 346 /* disable rx ints */ 347 mpc8xxx_spi_write_reg(®_base->mask, 0); 348 349 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 350 fsl_spi_cpm_bufs_complete(mpc8xxx_spi); 351 352 return mpc8xxx_spi->count; 353 } 354 355 static int fsl_spi_do_one_msg(struct spi_master *master, 356 struct spi_message *m) 357 { 358 struct spi_device *spi = m->spi; 359 struct spi_transfer *t, *first; 360 unsigned int cs_change; 361 const int nsecs = 50; 362 int status; 363 364 /* Don't allow changes if CS is active */ 365 first = list_first_entry(&m->transfers, struct spi_transfer, 366 transfer_list); 367 list_for_each_entry(t, &m->transfers, transfer_list) { 368 if ((first->bits_per_word != t->bits_per_word) || 369 (first->speed_hz != t->speed_hz)) { 370 dev_err(&spi->dev, 371 "bits_per_word/speed_hz should be same for the same SPI transfer\n"); 372 return -EINVAL; 373 } 374 } 375 376 cs_change = 1; 377 status = -EINVAL; 378 list_for_each_entry(t, &m->transfers, transfer_list) { 379 if (t->bits_per_word || t->speed_hz) { 380 if (cs_change) 381 status = fsl_spi_setup_transfer(spi, t); 382 if (status < 0) 383 break; 384 } 385 386 if (cs_change) { 387 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); 388 ndelay(nsecs); 389 } 390 cs_change = t->cs_change; 391 if (t->len) 392 status = fsl_spi_bufs(spi, t, m->is_dma_mapped); 393 if (status) { 394 status = -EMSGSIZE; 395 break; 396 } 397 m->actual_length += t->len; 398 399 if (t->delay_usecs) 400 udelay(t->delay_usecs); 401 402 if (cs_change) { 403 ndelay(nsecs); 404 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 405 ndelay(nsecs); 406 } 407 } 408 409 m->status = status; 410 spi_finalize_current_message(master); 411 412 if (status || !cs_change) { 413 ndelay(nsecs); 414 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 415 } 416 417 fsl_spi_setup_transfer(spi, NULL); 418 return 0; 419 } 420 421 static int fsl_spi_setup(struct spi_device *spi) 422 { 423 struct mpc8xxx_spi *mpc8xxx_spi; 424 struct fsl_spi_reg *reg_base; 425 int retval; 426 u32 hw_mode; 427 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 428 429 if (!spi->max_speed_hz) 430 return -EINVAL; 431 432 if (!cs) { 433 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 434 if (!cs) 435 return -ENOMEM; 436 spi_set_ctldata(spi, cs); 437 } 438 mpc8xxx_spi = spi_master_get_devdata(spi->master); 439 440 reg_base = mpc8xxx_spi->reg_base; 441 442 hw_mode = cs->hw_mode; /* Save original settings */ 443 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); 444 /* mask out bits we are going to set */ 445 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH 446 | SPMODE_REV | SPMODE_LOOP); 447 448 if (spi->mode & SPI_CPHA) 449 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; 450 if (spi->mode & SPI_CPOL) 451 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; 452 if (!(spi->mode & SPI_LSB_FIRST)) 453 cs->hw_mode |= SPMODE_REV; 454 if (spi->mode & SPI_LOOP) 455 cs->hw_mode |= SPMODE_LOOP; 456 457 retval = fsl_spi_setup_transfer(spi, NULL); 458 if (retval < 0) { 459 cs->hw_mode = hw_mode; /* Restore settings */ 460 return retval; 461 } 462 463 if (mpc8xxx_spi->type == TYPE_GRLIB) { 464 if (gpio_is_valid(spi->cs_gpio)) { 465 int desel; 466 467 retval = gpio_request(spi->cs_gpio, 468 dev_name(&spi->dev)); 469 if (retval) 470 return retval; 471 472 desel = !(spi->mode & SPI_CS_HIGH); 473 retval = gpio_direction_output(spi->cs_gpio, desel); 474 if (retval) { 475 gpio_free(spi->cs_gpio); 476 return retval; 477 } 478 } else if (spi->cs_gpio != -ENOENT) { 479 if (spi->cs_gpio < 0) 480 return spi->cs_gpio; 481 return -EINVAL; 482 } 483 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list 484 * indicates to use native chipselect if present, or allow for 485 * an always selected chip 486 */ 487 } 488 489 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ 490 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 491 492 return 0; 493 } 494 495 static void fsl_spi_cleanup(struct spi_device *spi) 496 { 497 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 498 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); 499 500 if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio)) 501 gpio_free(spi->cs_gpio); 502 503 kfree(cs); 504 spi_set_ctldata(spi, NULL); 505 } 506 507 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 508 { 509 struct fsl_spi_reg *reg_base = mspi->reg_base; 510 511 /* We need handle RX first */ 512 if (events & SPIE_NE) { 513 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); 514 515 if (mspi->rx) 516 mspi->get_rx(rx_data, mspi); 517 } 518 519 if ((events & SPIE_NF) == 0) 520 /* spin until TX is done */ 521 while (((events = 522 mpc8xxx_spi_read_reg(®_base->event)) & 523 SPIE_NF) == 0) 524 cpu_relax(); 525 526 /* Clear the events */ 527 mpc8xxx_spi_write_reg(®_base->event, events); 528 529 mspi->count -= 1; 530 if (mspi->count) { 531 u32 word = mspi->get_tx(mspi); 532 533 mpc8xxx_spi_write_reg(®_base->transmit, word); 534 } else { 535 complete(&mspi->done); 536 } 537 } 538 539 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) 540 { 541 struct mpc8xxx_spi *mspi = context_data; 542 irqreturn_t ret = IRQ_NONE; 543 u32 events; 544 struct fsl_spi_reg *reg_base = mspi->reg_base; 545 546 /* Get interrupt events(tx/rx) */ 547 events = mpc8xxx_spi_read_reg(®_base->event); 548 if (events) 549 ret = IRQ_HANDLED; 550 551 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); 552 553 if (mspi->flags & SPI_CPM_MODE) 554 fsl_spi_cpm_irq(mspi, events); 555 else 556 fsl_spi_cpu_irq(mspi, events); 557 558 return ret; 559 } 560 561 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) 562 { 563 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 564 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; 565 u32 slvsel; 566 u16 cs = spi->chip_select; 567 568 if (gpio_is_valid(spi->cs_gpio)) { 569 gpio_set_value(spi->cs_gpio, on); 570 } else if (cs < mpc8xxx_spi->native_chipselects) { 571 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); 572 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); 573 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); 574 } 575 } 576 577 static void fsl_spi_grlib_probe(struct device *dev) 578 { 579 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 580 struct spi_master *master = dev_get_drvdata(dev); 581 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 582 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; 583 int mbits; 584 u32 capabilities; 585 586 capabilities = mpc8xxx_spi_read_reg(®_base->cap); 587 588 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; 589 mbits = SPCAP_MAXWLEN(capabilities); 590 if (mbits) 591 mpc8xxx_spi->max_bits_per_word = mbits + 1; 592 593 mpc8xxx_spi->native_chipselects = 0; 594 if (SPCAP_SSEN(capabilities)) { 595 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); 596 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); 597 } 598 master->num_chipselect = mpc8xxx_spi->native_chipselects; 599 pdata->cs_control = fsl_spi_grlib_cs_control; 600 } 601 602 static struct spi_master * fsl_spi_probe(struct device *dev, 603 struct resource *mem, unsigned int irq) 604 { 605 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 606 struct spi_master *master; 607 struct mpc8xxx_spi *mpc8xxx_spi; 608 struct fsl_spi_reg *reg_base; 609 u32 regval; 610 int ret = 0; 611 612 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); 613 if (master == NULL) { 614 ret = -ENOMEM; 615 goto err; 616 } 617 618 dev_set_drvdata(dev, master); 619 620 mpc8xxx_spi_probe(dev, mem, irq); 621 622 master->setup = fsl_spi_setup; 623 master->cleanup = fsl_spi_cleanup; 624 master->transfer_one_message = fsl_spi_do_one_msg; 625 626 mpc8xxx_spi = spi_master_get_devdata(master); 627 mpc8xxx_spi->max_bits_per_word = 32; 628 mpc8xxx_spi->type = fsl_spi_get_type(dev); 629 630 ret = fsl_spi_cpm_init(mpc8xxx_spi); 631 if (ret) 632 goto err_cpm_init; 633 634 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); 635 if (IS_ERR(mpc8xxx_spi->reg_base)) { 636 ret = PTR_ERR(mpc8xxx_spi->reg_base); 637 goto err_probe; 638 } 639 640 if (mpc8xxx_spi->type == TYPE_GRLIB) 641 fsl_spi_grlib_probe(dev); 642 643 master->bits_per_word_mask = 644 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) & 645 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); 646 647 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 648 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; 649 650 if (mpc8xxx_spi->set_shifts) 651 /* 8 bits per word and MSB first */ 652 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, 653 &mpc8xxx_spi->tx_shift, 8, 1); 654 655 /* Register for SPI Interrupt */ 656 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq, 657 0, "fsl_spi", mpc8xxx_spi); 658 659 if (ret != 0) 660 goto err_probe; 661 662 reg_base = mpc8xxx_spi->reg_base; 663 664 /* SPI controller initializations */ 665 mpc8xxx_spi_write_reg(®_base->mode, 0); 666 mpc8xxx_spi_write_reg(®_base->mask, 0); 667 mpc8xxx_spi_write_reg(®_base->command, 0); 668 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 669 670 /* Enable SPI interface */ 671 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 672 if (mpc8xxx_spi->max_bits_per_word < 8) { 673 regval &= ~SPMODE_LEN(0xF); 674 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); 675 } 676 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 677 regval |= SPMODE_OP; 678 679 mpc8xxx_spi_write_reg(®_base->mode, regval); 680 681 ret = devm_spi_register_master(dev, master); 682 if (ret < 0) 683 goto err_probe; 684 685 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, 686 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); 687 688 return master; 689 690 err_probe: 691 fsl_spi_cpm_free(mpc8xxx_spi); 692 err_cpm_init: 693 spi_master_put(master); 694 err: 695 return ERR_PTR(ret); 696 } 697 698 static void fsl_spi_cs_control(struct spi_device *spi, bool on) 699 { 700 struct device *dev = spi->dev.parent->parent; 701 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 702 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 703 u16 cs = spi->chip_select; 704 int gpio = pinfo->gpios[cs]; 705 bool alow = pinfo->alow_flags[cs]; 706 707 gpio_set_value(gpio, on ^ alow); 708 } 709 710 static int of_fsl_spi_get_chipselects(struct device *dev) 711 { 712 struct device_node *np = dev->of_node; 713 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 714 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 715 int ngpios; 716 int i = 0; 717 int ret; 718 719 ngpios = of_gpio_count(np); 720 if (ngpios <= 0) { 721 /* 722 * SPI w/o chip-select line. One SPI device is still permitted 723 * though. 724 */ 725 pdata->max_chipselect = 1; 726 return 0; 727 } 728 729 pinfo->gpios = kmalloc_array(ngpios, sizeof(*pinfo->gpios), 730 GFP_KERNEL); 731 if (!pinfo->gpios) 732 return -ENOMEM; 733 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); 734 735 pinfo->alow_flags = kcalloc(ngpios, sizeof(*pinfo->alow_flags), 736 GFP_KERNEL); 737 if (!pinfo->alow_flags) { 738 ret = -ENOMEM; 739 goto err_alloc_flags; 740 } 741 742 for (; i < ngpios; i++) { 743 int gpio; 744 enum of_gpio_flags flags; 745 746 gpio = of_get_gpio_flags(np, i, &flags); 747 if (!gpio_is_valid(gpio)) { 748 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); 749 ret = gpio; 750 goto err_loop; 751 } 752 753 ret = gpio_request(gpio, dev_name(dev)); 754 if (ret) { 755 dev_err(dev, "can't request gpio #%d: %d\n", i, ret); 756 goto err_loop; 757 } 758 759 pinfo->gpios[i] = gpio; 760 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; 761 762 ret = gpio_direction_output(pinfo->gpios[i], 763 pinfo->alow_flags[i]); 764 if (ret) { 765 dev_err(dev, 766 "can't set output direction for gpio #%d: %d\n", 767 i, ret); 768 goto err_loop; 769 } 770 } 771 772 pdata->max_chipselect = ngpios; 773 pdata->cs_control = fsl_spi_cs_control; 774 775 return 0; 776 777 err_loop: 778 while (i >= 0) { 779 if (gpio_is_valid(pinfo->gpios[i])) 780 gpio_free(pinfo->gpios[i]); 781 i--; 782 } 783 784 kfree(pinfo->alow_flags); 785 pinfo->alow_flags = NULL; 786 err_alloc_flags: 787 kfree(pinfo->gpios); 788 pinfo->gpios = NULL; 789 return ret; 790 } 791 792 static int of_fsl_spi_free_chipselects(struct device *dev) 793 { 794 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 795 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 796 int i; 797 798 if (!pinfo->gpios) 799 return 0; 800 801 for (i = 0; i < pdata->max_chipselect; i++) { 802 if (gpio_is_valid(pinfo->gpios[i])) 803 gpio_free(pinfo->gpios[i]); 804 } 805 806 kfree(pinfo->gpios); 807 kfree(pinfo->alow_flags); 808 return 0; 809 } 810 811 static int of_fsl_spi_probe(struct platform_device *ofdev) 812 { 813 struct device *dev = &ofdev->dev; 814 struct device_node *np = ofdev->dev.of_node; 815 struct spi_master *master; 816 struct resource mem; 817 int irq = 0, type; 818 int ret = -ENOMEM; 819 820 ret = of_mpc8xxx_spi_probe(ofdev); 821 if (ret) 822 return ret; 823 824 type = fsl_spi_get_type(&ofdev->dev); 825 if (type == TYPE_FSL) { 826 ret = of_fsl_spi_get_chipselects(dev); 827 if (ret) 828 goto err; 829 } 830 831 ret = of_address_to_resource(np, 0, &mem); 832 if (ret) 833 goto err; 834 835 irq = irq_of_parse_and_map(np, 0); 836 if (!irq) { 837 ret = -EINVAL; 838 goto err; 839 } 840 841 master = fsl_spi_probe(dev, &mem, irq); 842 if (IS_ERR(master)) { 843 ret = PTR_ERR(master); 844 goto err; 845 } 846 847 return 0; 848 849 err: 850 irq_dispose_mapping(irq); 851 if (type == TYPE_FSL) 852 of_fsl_spi_free_chipselects(dev); 853 return ret; 854 } 855 856 static int of_fsl_spi_remove(struct platform_device *ofdev) 857 { 858 struct spi_master *master = platform_get_drvdata(ofdev); 859 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 860 861 fsl_spi_cpm_free(mpc8xxx_spi); 862 if (mpc8xxx_spi->type == TYPE_FSL) 863 of_fsl_spi_free_chipselects(&ofdev->dev); 864 return 0; 865 } 866 867 static struct platform_driver of_fsl_spi_driver = { 868 .driver = { 869 .name = "fsl_spi", 870 .of_match_table = of_fsl_spi_match, 871 }, 872 .probe = of_fsl_spi_probe, 873 .remove = of_fsl_spi_remove, 874 }; 875 876 #ifdef CONFIG_MPC832x_RDB 877 /* 878 * XXX XXX XXX 879 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards 880 * only. The driver should go away soon, since newer MPC8323E-RDB's device 881 * tree can work with OpenFirmware driver. But for now we support old trees 882 * as well. 883 */ 884 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) 885 { 886 struct resource *mem; 887 int irq; 888 struct spi_master *master; 889 890 if (!dev_get_platdata(&pdev->dev)) 891 return -EINVAL; 892 893 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 894 if (!mem) 895 return -EINVAL; 896 897 irq = platform_get_irq(pdev, 0); 898 if (irq <= 0) 899 return -EINVAL; 900 901 master = fsl_spi_probe(&pdev->dev, mem, irq); 902 return PTR_ERR_OR_ZERO(master); 903 } 904 905 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) 906 { 907 struct spi_master *master = platform_get_drvdata(pdev); 908 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 909 910 fsl_spi_cpm_free(mpc8xxx_spi); 911 912 return 0; 913 } 914 915 MODULE_ALIAS("platform:mpc8xxx_spi"); 916 static struct platform_driver mpc8xxx_spi_driver = { 917 .probe = plat_mpc8xxx_spi_probe, 918 .remove = plat_mpc8xxx_spi_remove, 919 .driver = { 920 .name = "mpc8xxx_spi", 921 }, 922 }; 923 924 static bool legacy_driver_failed; 925 926 static void __init legacy_driver_register(void) 927 { 928 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); 929 } 930 931 static void __exit legacy_driver_unregister(void) 932 { 933 if (legacy_driver_failed) 934 return; 935 platform_driver_unregister(&mpc8xxx_spi_driver); 936 } 937 #else 938 static void __init legacy_driver_register(void) {} 939 static void __exit legacy_driver_unregister(void) {} 940 #endif /* CONFIG_MPC832x_RDB */ 941 942 static int __init fsl_spi_init(void) 943 { 944 legacy_driver_register(); 945 return platform_driver_register(&of_fsl_spi_driver); 946 } 947 module_init(fsl_spi_init); 948 949 static void __exit fsl_spi_exit(void) 950 { 951 platform_driver_unregister(&of_fsl_spi_driver); 952 legacy_driver_unregister(); 953 } 954 module_exit(fsl_spi_exit); 955 956 MODULE_AUTHOR("Kumar Gala"); 957 MODULE_DESCRIPTION("Simple Freescale SPI Driver"); 958 MODULE_LICENSE("GPL"); 959