1 /* 2 * Freescale SPI controller driver. 3 * 4 * Maintainer: Kumar Gala 5 * 6 * Copyright (C) 2006 Polycom, Inc. 7 * Copyright 2010 Freescale Semiconductor, Inc. 8 * 9 * CPM SPI and QE buffer descriptors mode support: 10 * Copyright (c) 2009 MontaVista Software, Inc. 11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18 #include <linux/module.h> 19 #include <linux/types.h> 20 #include <linux/kernel.h> 21 #include <linux/interrupt.h> 22 #include <linux/delay.h> 23 #include <linux/irq.h> 24 #include <linux/spi/spi.h> 25 #include <linux/spi/spi_bitbang.h> 26 #include <linux/platform_device.h> 27 #include <linux/fsl_devices.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/mm.h> 30 #include <linux/mutex.h> 31 #include <linux/of.h> 32 #include <linux/of_platform.h> 33 #include <linux/of_address.h> 34 #include <linux/of_irq.h> 35 #include <linux/gpio.h> 36 #include <linux/of_gpio.h> 37 38 #include "spi-fsl-lib.h" 39 #include "spi-fsl-cpm.h" 40 #include "spi-fsl-spi.h" 41 42 #define TYPE_FSL 0 43 44 struct fsl_spi_match_data { 45 int type; 46 }; 47 48 static struct fsl_spi_match_data of_fsl_spi_fsl_config = { 49 .type = TYPE_FSL, 50 }; 51 52 static struct of_device_id of_fsl_spi_match[] = { 53 { 54 .compatible = "fsl,spi", 55 .data = &of_fsl_spi_fsl_config, 56 }, 57 {} 58 }; 59 MODULE_DEVICE_TABLE(of, of_fsl_spi_match); 60 61 static int fsl_spi_get_type(struct device *dev) 62 { 63 const struct of_device_id *match; 64 65 if (dev->of_node) { 66 match = of_match_node(of_fsl_spi_match, dev->of_node); 67 if (match && match->data) 68 return ((struct fsl_spi_match_data *)match->data)->type; 69 } 70 return TYPE_FSL; 71 } 72 73 static void fsl_spi_change_mode(struct spi_device *spi) 74 { 75 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 76 struct spi_mpc8xxx_cs *cs = spi->controller_state; 77 struct fsl_spi_reg *reg_base = mspi->reg_base; 78 __be32 __iomem *mode = ®_base->mode; 79 unsigned long flags; 80 81 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) 82 return; 83 84 /* Turn off IRQs locally to minimize time that SPI is disabled. */ 85 local_irq_save(flags); 86 87 /* Turn off SPI unit prior changing mode */ 88 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); 89 90 /* When in CPM mode, we need to reinit tx and rx. */ 91 if (mspi->flags & SPI_CPM_MODE) { 92 fsl_spi_cpm_reinit_txrx(mspi); 93 } 94 mpc8xxx_spi_write_reg(mode, cs->hw_mode); 95 local_irq_restore(flags); 96 } 97 98 static void fsl_spi_chipselect(struct spi_device *spi, int value) 99 { 100 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 101 struct fsl_spi_platform_data *pdata; 102 bool pol = spi->mode & SPI_CS_HIGH; 103 struct spi_mpc8xxx_cs *cs = spi->controller_state; 104 105 pdata = spi->dev.parent->parent->platform_data; 106 107 if (value == BITBANG_CS_INACTIVE) { 108 if (pdata->cs_control) 109 pdata->cs_control(spi, !pol); 110 } 111 112 if (value == BITBANG_CS_ACTIVE) { 113 mpc8xxx_spi->rx_shift = cs->rx_shift; 114 mpc8xxx_spi->tx_shift = cs->tx_shift; 115 mpc8xxx_spi->get_rx = cs->get_rx; 116 mpc8xxx_spi->get_tx = cs->get_tx; 117 118 fsl_spi_change_mode(spi); 119 120 if (pdata->cs_control) 121 pdata->cs_control(spi, pol); 122 } 123 } 124 125 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, 126 int bits_per_word, int msb_first) 127 { 128 *rx_shift = 0; 129 *tx_shift = 0; 130 if (msb_first) { 131 if (bits_per_word <= 8) { 132 *rx_shift = 16; 133 *tx_shift = 24; 134 } else if (bits_per_word <= 16) { 135 *rx_shift = 16; 136 *tx_shift = 16; 137 } 138 } else { 139 if (bits_per_word <= 8) 140 *rx_shift = 8; 141 } 142 } 143 144 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, 145 struct spi_device *spi, 146 struct mpc8xxx_spi *mpc8xxx_spi, 147 int bits_per_word) 148 { 149 cs->rx_shift = 0; 150 cs->tx_shift = 0; 151 if (bits_per_word <= 8) { 152 cs->get_rx = mpc8xxx_spi_rx_buf_u8; 153 cs->get_tx = mpc8xxx_spi_tx_buf_u8; 154 } else if (bits_per_word <= 16) { 155 cs->get_rx = mpc8xxx_spi_rx_buf_u16; 156 cs->get_tx = mpc8xxx_spi_tx_buf_u16; 157 } else if (bits_per_word <= 32) { 158 cs->get_rx = mpc8xxx_spi_rx_buf_u32; 159 cs->get_tx = mpc8xxx_spi_tx_buf_u32; 160 } else 161 return -EINVAL; 162 163 if (mpc8xxx_spi->set_shifts) 164 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, 165 bits_per_word, 166 !(spi->mode & SPI_LSB_FIRST)); 167 168 mpc8xxx_spi->rx_shift = cs->rx_shift; 169 mpc8xxx_spi->tx_shift = cs->tx_shift; 170 mpc8xxx_spi->get_rx = cs->get_rx; 171 mpc8xxx_spi->get_tx = cs->get_tx; 172 173 return bits_per_word; 174 } 175 176 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, 177 struct spi_device *spi, 178 int bits_per_word) 179 { 180 /* QE uses Little Endian for words > 8 181 * so transform all words > 8 into 8 bits 182 * Unfortnatly that doesn't work for LSB so 183 * reject these for now */ 184 /* Note: 32 bits word, LSB works iff 185 * tfcr/rfcr is set to CPMFCR_GBL */ 186 if (spi->mode & SPI_LSB_FIRST && 187 bits_per_word > 8) 188 return -EINVAL; 189 if (bits_per_word > 8) 190 return 8; /* pretend its 8 bits */ 191 return bits_per_word; 192 } 193 194 static int fsl_spi_setup_transfer(struct spi_device *spi, 195 struct spi_transfer *t) 196 { 197 struct mpc8xxx_spi *mpc8xxx_spi; 198 int bits_per_word = 0; 199 u8 pm; 200 u32 hz = 0; 201 struct spi_mpc8xxx_cs *cs = spi->controller_state; 202 203 mpc8xxx_spi = spi_master_get_devdata(spi->master); 204 205 if (t) { 206 bits_per_word = t->bits_per_word; 207 hz = t->speed_hz; 208 } 209 210 /* spi_transfer level calls that work per-word */ 211 if (!bits_per_word) 212 bits_per_word = spi->bits_per_word; 213 214 /* Make sure its a bit width we support [4..16, 32] */ 215 if ((bits_per_word < 4) 216 || ((bits_per_word > 16) && (bits_per_word != 32)) 217 || (bits_per_word > mpc8xxx_spi->max_bits_per_word)) 218 return -EINVAL; 219 220 if (!hz) 221 hz = spi->max_speed_hz; 222 223 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) 224 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, 225 mpc8xxx_spi, 226 bits_per_word); 227 else if (mpc8xxx_spi->flags & SPI_QE) 228 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, 229 bits_per_word); 230 231 if (bits_per_word < 0) 232 return bits_per_word; 233 234 if (bits_per_word == 32) 235 bits_per_word = 0; 236 else 237 bits_per_word = bits_per_word - 1; 238 239 /* mask out bits we are going to set */ 240 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 241 | SPMODE_PM(0xF)); 242 243 cs->hw_mode |= SPMODE_LEN(bits_per_word); 244 245 if ((mpc8xxx_spi->spibrg / hz) > 64) { 246 cs->hw_mode |= SPMODE_DIV16; 247 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; 248 249 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " 250 "Will use %d Hz instead.\n", dev_name(&spi->dev), 251 hz, mpc8xxx_spi->spibrg / 1024); 252 if (pm > 16) 253 pm = 16; 254 } else { 255 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; 256 } 257 if (pm) 258 pm--; 259 260 cs->hw_mode |= SPMODE_PM(pm); 261 262 fsl_spi_change_mode(spi); 263 return 0; 264 } 265 266 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, 267 struct spi_transfer *t, unsigned int len) 268 { 269 u32 word; 270 struct fsl_spi_reg *reg_base = mspi->reg_base; 271 272 mspi->count = len; 273 274 /* enable rx ints */ 275 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 276 277 /* transmit word */ 278 word = mspi->get_tx(mspi); 279 mpc8xxx_spi_write_reg(®_base->transmit, word); 280 281 return 0; 282 } 283 284 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, 285 bool is_dma_mapped) 286 { 287 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 288 struct fsl_spi_reg *reg_base; 289 unsigned int len = t->len; 290 u8 bits_per_word; 291 int ret; 292 293 reg_base = mpc8xxx_spi->reg_base; 294 bits_per_word = spi->bits_per_word; 295 if (t->bits_per_word) 296 bits_per_word = t->bits_per_word; 297 298 if (bits_per_word > 8) { 299 /* invalid length? */ 300 if (len & 1) 301 return -EINVAL; 302 len /= 2; 303 } 304 if (bits_per_word > 16) { 305 /* invalid length? */ 306 if (len & 1) 307 return -EINVAL; 308 len /= 2; 309 } 310 311 mpc8xxx_spi->tx = t->tx_buf; 312 mpc8xxx_spi->rx = t->rx_buf; 313 314 INIT_COMPLETION(mpc8xxx_spi->done); 315 316 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 317 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); 318 else 319 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); 320 if (ret) 321 return ret; 322 323 wait_for_completion(&mpc8xxx_spi->done); 324 325 /* disable rx ints */ 326 mpc8xxx_spi_write_reg(®_base->mask, 0); 327 328 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 329 fsl_spi_cpm_bufs_complete(mpc8xxx_spi); 330 331 return mpc8xxx_spi->count; 332 } 333 334 static void fsl_spi_do_one_msg(struct spi_message *m) 335 { 336 struct spi_device *spi = m->spi; 337 struct spi_transfer *t; 338 unsigned int cs_change; 339 const int nsecs = 50; 340 int status; 341 342 cs_change = 1; 343 status = 0; 344 list_for_each_entry(t, &m->transfers, transfer_list) { 345 if (t->bits_per_word || t->speed_hz) { 346 /* Don't allow changes if CS is active */ 347 status = -EINVAL; 348 349 if (cs_change) 350 status = fsl_spi_setup_transfer(spi, t); 351 if (status < 0) 352 break; 353 } 354 355 if (cs_change) { 356 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); 357 ndelay(nsecs); 358 } 359 cs_change = t->cs_change; 360 if (t->len) 361 status = fsl_spi_bufs(spi, t, m->is_dma_mapped); 362 if (status) { 363 status = -EMSGSIZE; 364 break; 365 } 366 m->actual_length += t->len; 367 368 if (t->delay_usecs) 369 udelay(t->delay_usecs); 370 371 if (cs_change) { 372 ndelay(nsecs); 373 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 374 ndelay(nsecs); 375 } 376 } 377 378 m->status = status; 379 m->complete(m->context); 380 381 if (status || !cs_change) { 382 ndelay(nsecs); 383 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 384 } 385 386 fsl_spi_setup_transfer(spi, NULL); 387 } 388 389 static int fsl_spi_setup(struct spi_device *spi) 390 { 391 struct mpc8xxx_spi *mpc8xxx_spi; 392 struct fsl_spi_reg *reg_base; 393 int retval; 394 u32 hw_mode; 395 struct spi_mpc8xxx_cs *cs = spi->controller_state; 396 397 if (!spi->max_speed_hz) 398 return -EINVAL; 399 400 if (!cs) { 401 cs = kzalloc(sizeof *cs, GFP_KERNEL); 402 if (!cs) 403 return -ENOMEM; 404 spi->controller_state = cs; 405 } 406 mpc8xxx_spi = spi_master_get_devdata(spi->master); 407 408 reg_base = mpc8xxx_spi->reg_base; 409 410 hw_mode = cs->hw_mode; /* Save original settings */ 411 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); 412 /* mask out bits we are going to set */ 413 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH 414 | SPMODE_REV | SPMODE_LOOP); 415 416 if (spi->mode & SPI_CPHA) 417 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; 418 if (spi->mode & SPI_CPOL) 419 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; 420 if (!(spi->mode & SPI_LSB_FIRST)) 421 cs->hw_mode |= SPMODE_REV; 422 if (spi->mode & SPI_LOOP) 423 cs->hw_mode |= SPMODE_LOOP; 424 425 retval = fsl_spi_setup_transfer(spi, NULL); 426 if (retval < 0) { 427 cs->hw_mode = hw_mode; /* Restore settings */ 428 return retval; 429 } 430 431 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ 432 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 433 434 return 0; 435 } 436 437 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 438 { 439 struct fsl_spi_reg *reg_base = mspi->reg_base; 440 441 /* We need handle RX first */ 442 if (events & SPIE_NE) { 443 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); 444 445 if (mspi->rx) 446 mspi->get_rx(rx_data, mspi); 447 } 448 449 if ((events & SPIE_NF) == 0) 450 /* spin until TX is done */ 451 while (((events = 452 mpc8xxx_spi_read_reg(®_base->event)) & 453 SPIE_NF) == 0) 454 cpu_relax(); 455 456 /* Clear the events */ 457 mpc8xxx_spi_write_reg(®_base->event, events); 458 459 mspi->count -= 1; 460 if (mspi->count) { 461 u32 word = mspi->get_tx(mspi); 462 463 mpc8xxx_spi_write_reg(®_base->transmit, word); 464 } else { 465 complete(&mspi->done); 466 } 467 } 468 469 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) 470 { 471 struct mpc8xxx_spi *mspi = context_data; 472 irqreturn_t ret = IRQ_NONE; 473 u32 events; 474 struct fsl_spi_reg *reg_base = mspi->reg_base; 475 476 /* Get interrupt events(tx/rx) */ 477 events = mpc8xxx_spi_read_reg(®_base->event); 478 if (events) 479 ret = IRQ_HANDLED; 480 481 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); 482 483 if (mspi->flags & SPI_CPM_MODE) 484 fsl_spi_cpm_irq(mspi, events); 485 else 486 fsl_spi_cpu_irq(mspi, events); 487 488 return ret; 489 } 490 491 static void fsl_spi_remove(struct mpc8xxx_spi *mspi) 492 { 493 iounmap(mspi->reg_base); 494 fsl_spi_cpm_free(mspi); 495 } 496 497 static struct spi_master * fsl_spi_probe(struct device *dev, 498 struct resource *mem, unsigned int irq) 499 { 500 struct fsl_spi_platform_data *pdata = dev->platform_data; 501 struct spi_master *master; 502 struct mpc8xxx_spi *mpc8xxx_spi; 503 struct fsl_spi_reg *reg_base; 504 u32 regval; 505 int ret = 0; 506 507 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); 508 if (master == NULL) { 509 ret = -ENOMEM; 510 goto err; 511 } 512 513 dev_set_drvdata(dev, master); 514 515 ret = mpc8xxx_spi_probe(dev, mem, irq); 516 if (ret) 517 goto err_probe; 518 519 master->setup = fsl_spi_setup; 520 521 mpc8xxx_spi = spi_master_get_devdata(master); 522 mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg; 523 mpc8xxx_spi->spi_remove = fsl_spi_remove; 524 mpc8xxx_spi->max_bits_per_word = 32; 525 mpc8xxx_spi->type = fsl_spi_get_type(dev); 526 527 ret = fsl_spi_cpm_init(mpc8xxx_spi); 528 if (ret) 529 goto err_cpm_init; 530 531 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 532 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; 533 534 if (mpc8xxx_spi->set_shifts) 535 /* 8 bits per word and MSB first */ 536 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, 537 &mpc8xxx_spi->tx_shift, 8, 1); 538 539 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); 540 if (mpc8xxx_spi->reg_base == NULL) { 541 ret = -ENOMEM; 542 goto err_ioremap; 543 } 544 545 /* Register for SPI Interrupt */ 546 ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq, 547 0, "fsl_spi", mpc8xxx_spi); 548 549 if (ret != 0) 550 goto free_irq; 551 552 reg_base = mpc8xxx_spi->reg_base; 553 554 /* SPI controller initializations */ 555 mpc8xxx_spi_write_reg(®_base->mode, 0); 556 mpc8xxx_spi_write_reg(®_base->mask, 0); 557 mpc8xxx_spi_write_reg(®_base->command, 0); 558 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 559 560 /* Enable SPI interface */ 561 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 562 if (mpc8xxx_spi->max_bits_per_word < 8) { 563 regval &= ~SPMODE_LEN(0xF); 564 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); 565 } 566 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 567 regval |= SPMODE_OP; 568 569 mpc8xxx_spi_write_reg(®_base->mode, regval); 570 571 ret = spi_register_master(master); 572 if (ret < 0) 573 goto unreg_master; 574 575 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, 576 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); 577 578 return master; 579 580 unreg_master: 581 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); 582 free_irq: 583 iounmap(mpc8xxx_spi->reg_base); 584 err_ioremap: 585 fsl_spi_cpm_free(mpc8xxx_spi); 586 err_cpm_init: 587 err_probe: 588 spi_master_put(master); 589 err: 590 return ERR_PTR(ret); 591 } 592 593 static void fsl_spi_cs_control(struct spi_device *spi, bool on) 594 { 595 struct device *dev = spi->dev.parent->parent; 596 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); 597 u16 cs = spi->chip_select; 598 int gpio = pinfo->gpios[cs]; 599 bool alow = pinfo->alow_flags[cs]; 600 601 gpio_set_value(gpio, on ^ alow); 602 } 603 604 static int of_fsl_spi_get_chipselects(struct device *dev) 605 { 606 struct device_node *np = dev->of_node; 607 struct fsl_spi_platform_data *pdata = dev->platform_data; 608 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 609 int ngpios; 610 int i = 0; 611 int ret; 612 613 ngpios = of_gpio_count(np); 614 if (ngpios <= 0) { 615 /* 616 * SPI w/o chip-select line. One SPI device is still permitted 617 * though. 618 */ 619 pdata->max_chipselect = 1; 620 return 0; 621 } 622 623 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); 624 if (!pinfo->gpios) 625 return -ENOMEM; 626 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); 627 628 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), 629 GFP_KERNEL); 630 if (!pinfo->alow_flags) { 631 ret = -ENOMEM; 632 goto err_alloc_flags; 633 } 634 635 for (; i < ngpios; i++) { 636 int gpio; 637 enum of_gpio_flags flags; 638 639 gpio = of_get_gpio_flags(np, i, &flags); 640 if (!gpio_is_valid(gpio)) { 641 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); 642 ret = gpio; 643 goto err_loop; 644 } 645 646 ret = gpio_request(gpio, dev_name(dev)); 647 if (ret) { 648 dev_err(dev, "can't request gpio #%d: %d\n", i, ret); 649 goto err_loop; 650 } 651 652 pinfo->gpios[i] = gpio; 653 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; 654 655 ret = gpio_direction_output(pinfo->gpios[i], 656 pinfo->alow_flags[i]); 657 if (ret) { 658 dev_err(dev, "can't set output direction for gpio " 659 "#%d: %d\n", i, ret); 660 goto err_loop; 661 } 662 } 663 664 pdata->max_chipselect = ngpios; 665 pdata->cs_control = fsl_spi_cs_control; 666 667 return 0; 668 669 err_loop: 670 while (i >= 0) { 671 if (gpio_is_valid(pinfo->gpios[i])) 672 gpio_free(pinfo->gpios[i]); 673 i--; 674 } 675 676 kfree(pinfo->alow_flags); 677 pinfo->alow_flags = NULL; 678 err_alloc_flags: 679 kfree(pinfo->gpios); 680 pinfo->gpios = NULL; 681 return ret; 682 } 683 684 static int of_fsl_spi_free_chipselects(struct device *dev) 685 { 686 struct fsl_spi_platform_data *pdata = dev->platform_data; 687 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 688 int i; 689 690 if (!pinfo->gpios) 691 return 0; 692 693 for (i = 0; i < pdata->max_chipselect; i++) { 694 if (gpio_is_valid(pinfo->gpios[i])) 695 gpio_free(pinfo->gpios[i]); 696 } 697 698 kfree(pinfo->gpios); 699 kfree(pinfo->alow_flags); 700 return 0; 701 } 702 703 static int of_fsl_spi_probe(struct platform_device *ofdev) 704 { 705 struct device *dev = &ofdev->dev; 706 struct device_node *np = ofdev->dev.of_node; 707 struct spi_master *master; 708 struct resource mem; 709 int irq; 710 int ret = -ENOMEM; 711 712 ret = of_mpc8xxx_spi_probe(ofdev); 713 if (ret) 714 return ret; 715 716 ret = of_fsl_spi_get_chipselects(dev); 717 if (ret) 718 goto err; 719 720 ret = of_address_to_resource(np, 0, &mem); 721 if (ret) 722 goto err; 723 724 irq = irq_of_parse_and_map(np, 0); 725 if (!irq) { 726 ret = -EINVAL; 727 goto err; 728 } 729 730 master = fsl_spi_probe(dev, &mem, irq); 731 if (IS_ERR(master)) { 732 ret = PTR_ERR(master); 733 goto err; 734 } 735 736 return 0; 737 738 err: 739 of_fsl_spi_free_chipselects(dev); 740 return ret; 741 } 742 743 static int of_fsl_spi_remove(struct platform_device *ofdev) 744 { 745 int ret; 746 747 ret = mpc8xxx_spi_remove(&ofdev->dev); 748 if (ret) 749 return ret; 750 of_fsl_spi_free_chipselects(&ofdev->dev); 751 return 0; 752 } 753 754 static struct platform_driver of_fsl_spi_driver = { 755 .driver = { 756 .name = "fsl_spi", 757 .owner = THIS_MODULE, 758 .of_match_table = of_fsl_spi_match, 759 }, 760 .probe = of_fsl_spi_probe, 761 .remove = of_fsl_spi_remove, 762 }; 763 764 #ifdef CONFIG_MPC832x_RDB 765 /* 766 * XXX XXX XXX 767 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards 768 * only. The driver should go away soon, since newer MPC8323E-RDB's device 769 * tree can work with OpenFirmware driver. But for now we support old trees 770 * as well. 771 */ 772 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) 773 { 774 struct resource *mem; 775 int irq; 776 struct spi_master *master; 777 778 if (!pdev->dev.platform_data) 779 return -EINVAL; 780 781 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 782 if (!mem) 783 return -EINVAL; 784 785 irq = platform_get_irq(pdev, 0); 786 if (irq <= 0) 787 return -EINVAL; 788 789 master = fsl_spi_probe(&pdev->dev, mem, irq); 790 return PTR_RET(master); 791 } 792 793 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) 794 { 795 return mpc8xxx_spi_remove(&pdev->dev); 796 } 797 798 MODULE_ALIAS("platform:mpc8xxx_spi"); 799 static struct platform_driver mpc8xxx_spi_driver = { 800 .probe = plat_mpc8xxx_spi_probe, 801 .remove = plat_mpc8xxx_spi_remove, 802 .driver = { 803 .name = "mpc8xxx_spi", 804 .owner = THIS_MODULE, 805 }, 806 }; 807 808 static bool legacy_driver_failed; 809 810 static void __init legacy_driver_register(void) 811 { 812 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); 813 } 814 815 static void __exit legacy_driver_unregister(void) 816 { 817 if (legacy_driver_failed) 818 return; 819 platform_driver_unregister(&mpc8xxx_spi_driver); 820 } 821 #else 822 static void __init legacy_driver_register(void) {} 823 static void __exit legacy_driver_unregister(void) {} 824 #endif /* CONFIG_MPC832x_RDB */ 825 826 static int __init fsl_spi_init(void) 827 { 828 legacy_driver_register(); 829 return platform_driver_register(&of_fsl_spi_driver); 830 } 831 module_init(fsl_spi_init); 832 833 static void __exit fsl_spi_exit(void) 834 { 835 platform_driver_unregister(&of_fsl_spi_driver); 836 legacy_driver_unregister(); 837 } 838 module_exit(fsl_spi_exit); 839 840 MODULE_AUTHOR("Kumar Gala"); 841 MODULE_DESCRIPTION("Simple Freescale SPI Driver"); 842 MODULE_LICENSE("GPL"); 843