1 /* 2 * Freescale SPI controller driver. 3 * 4 * Maintainer: Kumar Gala 5 * 6 * Copyright (C) 2006 Polycom, Inc. 7 * Copyright 2010 Freescale Semiconductor, Inc. 8 * 9 * CPM SPI and QE buffer descriptors mode support: 10 * Copyright (c) 2009 MontaVista Software, Inc. 11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com> 12 * 13 * GRLIB support: 14 * Copyright (c) 2012 Aeroflex Gaisler AB. 15 * Author: Andreas Larsson <andreas@gaisler.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the 19 * Free Software Foundation; either version 2 of the License, or (at your 20 * option) any later version. 21 */ 22 #include <linux/module.h> 23 #include <linux/types.h> 24 #include <linux/kernel.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/irq.h> 28 #include <linux/spi/spi.h> 29 #include <linux/spi/spi_bitbang.h> 30 #include <linux/platform_device.h> 31 #include <linux/fsl_devices.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/mm.h> 34 #include <linux/mutex.h> 35 #include <linux/of.h> 36 #include <linux/of_platform.h> 37 #include <linux/of_address.h> 38 #include <linux/of_irq.h> 39 #include <linux/gpio.h> 40 #include <linux/of_gpio.h> 41 42 #include "spi-fsl-lib.h" 43 #include "spi-fsl-cpm.h" 44 #include "spi-fsl-spi.h" 45 46 #define TYPE_FSL 0 47 #define TYPE_GRLIB 1 48 49 struct fsl_spi_match_data { 50 int type; 51 }; 52 53 static struct fsl_spi_match_data of_fsl_spi_fsl_config = { 54 .type = TYPE_FSL, 55 }; 56 57 static struct fsl_spi_match_data of_fsl_spi_grlib_config = { 58 .type = TYPE_GRLIB, 59 }; 60 61 static struct of_device_id of_fsl_spi_match[] = { 62 { 63 .compatible = "fsl,spi", 64 .data = &of_fsl_spi_fsl_config, 65 }, 66 { 67 .compatible = "aeroflexgaisler,spictrl", 68 .data = &of_fsl_spi_grlib_config, 69 }, 70 {} 71 }; 72 MODULE_DEVICE_TABLE(of, of_fsl_spi_match); 73 74 static int fsl_spi_get_type(struct device *dev) 75 { 76 const struct of_device_id *match; 77 78 if (dev->of_node) { 79 match = of_match_node(of_fsl_spi_match, dev->of_node); 80 if (match && match->data) 81 return ((struct fsl_spi_match_data *)match->data)->type; 82 } 83 return TYPE_FSL; 84 } 85 86 static void fsl_spi_change_mode(struct spi_device *spi) 87 { 88 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 89 struct spi_mpc8xxx_cs *cs = spi->controller_state; 90 struct fsl_spi_reg *reg_base = mspi->reg_base; 91 __be32 __iomem *mode = ®_base->mode; 92 unsigned long flags; 93 94 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) 95 return; 96 97 /* Turn off IRQs locally to minimize time that SPI is disabled. */ 98 local_irq_save(flags); 99 100 /* Turn off SPI unit prior changing mode */ 101 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); 102 103 /* When in CPM mode, we need to reinit tx and rx. */ 104 if (mspi->flags & SPI_CPM_MODE) { 105 fsl_spi_cpm_reinit_txrx(mspi); 106 } 107 mpc8xxx_spi_write_reg(mode, cs->hw_mode); 108 local_irq_restore(flags); 109 } 110 111 static void fsl_spi_chipselect(struct spi_device *spi, int value) 112 { 113 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 114 struct fsl_spi_platform_data *pdata; 115 bool pol = spi->mode & SPI_CS_HIGH; 116 struct spi_mpc8xxx_cs *cs = spi->controller_state; 117 118 pdata = spi->dev.parent->parent->platform_data; 119 120 if (value == BITBANG_CS_INACTIVE) { 121 if (pdata->cs_control) 122 pdata->cs_control(spi, !pol); 123 } 124 125 if (value == BITBANG_CS_ACTIVE) { 126 mpc8xxx_spi->rx_shift = cs->rx_shift; 127 mpc8xxx_spi->tx_shift = cs->tx_shift; 128 mpc8xxx_spi->get_rx = cs->get_rx; 129 mpc8xxx_spi->get_tx = cs->get_tx; 130 131 fsl_spi_change_mode(spi); 132 133 if (pdata->cs_control) 134 pdata->cs_control(spi, pol); 135 } 136 } 137 138 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, 139 int bits_per_word, int msb_first) 140 { 141 *rx_shift = 0; 142 *tx_shift = 0; 143 if (msb_first) { 144 if (bits_per_word <= 8) { 145 *rx_shift = 16; 146 *tx_shift = 24; 147 } else if (bits_per_word <= 16) { 148 *rx_shift = 16; 149 *tx_shift = 16; 150 } 151 } else { 152 if (bits_per_word <= 8) 153 *rx_shift = 8; 154 } 155 } 156 157 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift, 158 int bits_per_word, int msb_first) 159 { 160 *rx_shift = 0; 161 *tx_shift = 0; 162 if (bits_per_word <= 16) { 163 if (msb_first) { 164 *rx_shift = 16; /* LSB in bit 16 */ 165 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ 166 } else { 167 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ 168 } 169 } 170 } 171 172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, 173 struct spi_device *spi, 174 struct mpc8xxx_spi *mpc8xxx_spi, 175 int bits_per_word) 176 { 177 cs->rx_shift = 0; 178 cs->tx_shift = 0; 179 if (bits_per_word <= 8) { 180 cs->get_rx = mpc8xxx_spi_rx_buf_u8; 181 cs->get_tx = mpc8xxx_spi_tx_buf_u8; 182 } else if (bits_per_word <= 16) { 183 cs->get_rx = mpc8xxx_spi_rx_buf_u16; 184 cs->get_tx = mpc8xxx_spi_tx_buf_u16; 185 } else if (bits_per_word <= 32) { 186 cs->get_rx = mpc8xxx_spi_rx_buf_u32; 187 cs->get_tx = mpc8xxx_spi_tx_buf_u32; 188 } else 189 return -EINVAL; 190 191 if (mpc8xxx_spi->set_shifts) 192 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, 193 bits_per_word, 194 !(spi->mode & SPI_LSB_FIRST)); 195 196 mpc8xxx_spi->rx_shift = cs->rx_shift; 197 mpc8xxx_spi->tx_shift = cs->tx_shift; 198 mpc8xxx_spi->get_rx = cs->get_rx; 199 mpc8xxx_spi->get_tx = cs->get_tx; 200 201 return bits_per_word; 202 } 203 204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, 205 struct spi_device *spi, 206 int bits_per_word) 207 { 208 /* QE uses Little Endian for words > 8 209 * so transform all words > 8 into 8 bits 210 * Unfortnatly that doesn't work for LSB so 211 * reject these for now */ 212 /* Note: 32 bits word, LSB works iff 213 * tfcr/rfcr is set to CPMFCR_GBL */ 214 if (spi->mode & SPI_LSB_FIRST && 215 bits_per_word > 8) 216 return -EINVAL; 217 if (bits_per_word > 8) 218 return 8; /* pretend its 8 bits */ 219 return bits_per_word; 220 } 221 222 static int fsl_spi_setup_transfer(struct spi_device *spi, 223 struct spi_transfer *t) 224 { 225 struct mpc8xxx_spi *mpc8xxx_spi; 226 int bits_per_word = 0; 227 u8 pm; 228 u32 hz = 0; 229 struct spi_mpc8xxx_cs *cs = spi->controller_state; 230 231 mpc8xxx_spi = spi_master_get_devdata(spi->master); 232 233 if (t) { 234 bits_per_word = t->bits_per_word; 235 hz = t->speed_hz; 236 } 237 238 /* spi_transfer level calls that work per-word */ 239 if (!bits_per_word) 240 bits_per_word = spi->bits_per_word; 241 242 /* Make sure its a bit width we support [4..16, 32] */ 243 if ((bits_per_word < 4) 244 || ((bits_per_word > 16) && (bits_per_word != 32)) 245 || (bits_per_word > mpc8xxx_spi->max_bits_per_word)) 246 return -EINVAL; 247 248 if (!hz) 249 hz = spi->max_speed_hz; 250 251 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) 252 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, 253 mpc8xxx_spi, 254 bits_per_word); 255 else if (mpc8xxx_spi->flags & SPI_QE) 256 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, 257 bits_per_word); 258 259 if (bits_per_word < 0) 260 return bits_per_word; 261 262 if (bits_per_word == 32) 263 bits_per_word = 0; 264 else 265 bits_per_word = bits_per_word - 1; 266 267 /* mask out bits we are going to set */ 268 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 269 | SPMODE_PM(0xF)); 270 271 cs->hw_mode |= SPMODE_LEN(bits_per_word); 272 273 if ((mpc8xxx_spi->spibrg / hz) > 64) { 274 cs->hw_mode |= SPMODE_DIV16; 275 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; 276 277 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " 278 "Will use %d Hz instead.\n", dev_name(&spi->dev), 279 hz, mpc8xxx_spi->spibrg / 1024); 280 if (pm > 16) 281 pm = 16; 282 } else { 283 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; 284 } 285 if (pm) 286 pm--; 287 288 cs->hw_mode |= SPMODE_PM(pm); 289 290 fsl_spi_change_mode(spi); 291 return 0; 292 } 293 294 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, 295 struct spi_transfer *t, unsigned int len) 296 { 297 u32 word; 298 struct fsl_spi_reg *reg_base = mspi->reg_base; 299 300 mspi->count = len; 301 302 /* enable rx ints */ 303 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 304 305 /* transmit word */ 306 word = mspi->get_tx(mspi); 307 mpc8xxx_spi_write_reg(®_base->transmit, word); 308 309 return 0; 310 } 311 312 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, 313 bool is_dma_mapped) 314 { 315 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 316 struct fsl_spi_reg *reg_base; 317 unsigned int len = t->len; 318 u8 bits_per_word; 319 int ret; 320 321 reg_base = mpc8xxx_spi->reg_base; 322 bits_per_word = spi->bits_per_word; 323 if (t->bits_per_word) 324 bits_per_word = t->bits_per_word; 325 326 if (bits_per_word > 8) { 327 /* invalid length? */ 328 if (len & 1) 329 return -EINVAL; 330 len /= 2; 331 } 332 if (bits_per_word > 16) { 333 /* invalid length? */ 334 if (len & 1) 335 return -EINVAL; 336 len /= 2; 337 } 338 339 mpc8xxx_spi->tx = t->tx_buf; 340 mpc8xxx_spi->rx = t->rx_buf; 341 342 INIT_COMPLETION(mpc8xxx_spi->done); 343 344 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 345 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); 346 else 347 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); 348 if (ret) 349 return ret; 350 351 wait_for_completion(&mpc8xxx_spi->done); 352 353 /* disable rx ints */ 354 mpc8xxx_spi_write_reg(®_base->mask, 0); 355 356 if (mpc8xxx_spi->flags & SPI_CPM_MODE) 357 fsl_spi_cpm_bufs_complete(mpc8xxx_spi); 358 359 return mpc8xxx_spi->count; 360 } 361 362 static void fsl_spi_do_one_msg(struct spi_message *m) 363 { 364 struct spi_device *spi = m->spi; 365 struct spi_transfer *t; 366 unsigned int cs_change; 367 const int nsecs = 50; 368 int status; 369 370 cs_change = 1; 371 status = 0; 372 list_for_each_entry(t, &m->transfers, transfer_list) { 373 if (t->bits_per_word || t->speed_hz) { 374 /* Don't allow changes if CS is active */ 375 status = -EINVAL; 376 377 if (cs_change) 378 status = fsl_spi_setup_transfer(spi, t); 379 if (status < 0) 380 break; 381 } 382 383 if (cs_change) { 384 fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); 385 ndelay(nsecs); 386 } 387 cs_change = t->cs_change; 388 if (t->len) 389 status = fsl_spi_bufs(spi, t, m->is_dma_mapped); 390 if (status) { 391 status = -EMSGSIZE; 392 break; 393 } 394 m->actual_length += t->len; 395 396 if (t->delay_usecs) 397 udelay(t->delay_usecs); 398 399 if (cs_change) { 400 ndelay(nsecs); 401 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 402 ndelay(nsecs); 403 } 404 } 405 406 m->status = status; 407 m->complete(m->context); 408 409 if (status || !cs_change) { 410 ndelay(nsecs); 411 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 412 } 413 414 fsl_spi_setup_transfer(spi, NULL); 415 } 416 417 static int fsl_spi_setup(struct spi_device *spi) 418 { 419 struct mpc8xxx_spi *mpc8xxx_spi; 420 struct fsl_spi_reg *reg_base; 421 int retval; 422 u32 hw_mode; 423 struct spi_mpc8xxx_cs *cs = spi->controller_state; 424 425 if (!spi->max_speed_hz) 426 return -EINVAL; 427 428 if (!cs) { 429 cs = kzalloc(sizeof *cs, GFP_KERNEL); 430 if (!cs) 431 return -ENOMEM; 432 spi->controller_state = cs; 433 } 434 mpc8xxx_spi = spi_master_get_devdata(spi->master); 435 436 reg_base = mpc8xxx_spi->reg_base; 437 438 hw_mode = cs->hw_mode; /* Save original settings */ 439 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); 440 /* mask out bits we are going to set */ 441 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH 442 | SPMODE_REV | SPMODE_LOOP); 443 444 if (spi->mode & SPI_CPHA) 445 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; 446 if (spi->mode & SPI_CPOL) 447 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; 448 if (!(spi->mode & SPI_LSB_FIRST)) 449 cs->hw_mode |= SPMODE_REV; 450 if (spi->mode & SPI_LOOP) 451 cs->hw_mode |= SPMODE_LOOP; 452 453 retval = fsl_spi_setup_transfer(spi, NULL); 454 if (retval < 0) { 455 cs->hw_mode = hw_mode; /* Restore settings */ 456 return retval; 457 } 458 459 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ 460 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); 461 462 return 0; 463 } 464 465 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 466 { 467 struct fsl_spi_reg *reg_base = mspi->reg_base; 468 469 /* We need handle RX first */ 470 if (events & SPIE_NE) { 471 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); 472 473 if (mspi->rx) 474 mspi->get_rx(rx_data, mspi); 475 } 476 477 if ((events & SPIE_NF) == 0) 478 /* spin until TX is done */ 479 while (((events = 480 mpc8xxx_spi_read_reg(®_base->event)) & 481 SPIE_NF) == 0) 482 cpu_relax(); 483 484 /* Clear the events */ 485 mpc8xxx_spi_write_reg(®_base->event, events); 486 487 mspi->count -= 1; 488 if (mspi->count) { 489 u32 word = mspi->get_tx(mspi); 490 491 mpc8xxx_spi_write_reg(®_base->transmit, word); 492 } else { 493 complete(&mspi->done); 494 } 495 } 496 497 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) 498 { 499 struct mpc8xxx_spi *mspi = context_data; 500 irqreturn_t ret = IRQ_NONE; 501 u32 events; 502 struct fsl_spi_reg *reg_base = mspi->reg_base; 503 504 /* Get interrupt events(tx/rx) */ 505 events = mpc8xxx_spi_read_reg(®_base->event); 506 if (events) 507 ret = IRQ_HANDLED; 508 509 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); 510 511 if (mspi->flags & SPI_CPM_MODE) 512 fsl_spi_cpm_irq(mspi, events); 513 else 514 fsl_spi_cpu_irq(mspi, events); 515 516 return ret; 517 } 518 519 static void fsl_spi_remove(struct mpc8xxx_spi *mspi) 520 { 521 iounmap(mspi->reg_base); 522 fsl_spi_cpm_free(mspi); 523 } 524 525 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) 526 { 527 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 528 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; 529 u32 slvsel; 530 u16 cs = spi->chip_select; 531 532 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); 533 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); 534 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); 535 } 536 537 static void fsl_spi_grlib_probe(struct device *dev) 538 { 539 struct fsl_spi_platform_data *pdata = dev->platform_data; 540 struct spi_master *master = dev_get_drvdata(dev); 541 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 542 struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base; 543 int mbits; 544 u32 capabilities; 545 546 capabilities = mpc8xxx_spi_read_reg(®_base->cap); 547 548 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; 549 mbits = SPCAP_MAXWLEN(capabilities); 550 if (mbits) 551 mpc8xxx_spi->max_bits_per_word = mbits + 1; 552 553 master->num_chipselect = 1; /* Allow for an always selected chip */ 554 if (SPCAP_SSEN(capabilities)) { 555 master->num_chipselect = SPCAP_SSSZ(capabilities); 556 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); 557 } 558 pdata->cs_control = fsl_spi_grlib_cs_control; 559 } 560 561 static struct spi_master * fsl_spi_probe(struct device *dev, 562 struct resource *mem, unsigned int irq) 563 { 564 struct fsl_spi_platform_data *pdata = dev->platform_data; 565 struct spi_master *master; 566 struct mpc8xxx_spi *mpc8xxx_spi; 567 struct fsl_spi_reg *reg_base; 568 u32 regval; 569 int ret = 0; 570 571 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); 572 if (master == NULL) { 573 ret = -ENOMEM; 574 goto err; 575 } 576 577 dev_set_drvdata(dev, master); 578 579 ret = mpc8xxx_spi_probe(dev, mem, irq); 580 if (ret) 581 goto err_probe; 582 583 master->setup = fsl_spi_setup; 584 585 mpc8xxx_spi = spi_master_get_devdata(master); 586 mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg; 587 mpc8xxx_spi->spi_remove = fsl_spi_remove; 588 mpc8xxx_spi->max_bits_per_word = 32; 589 mpc8xxx_spi->type = fsl_spi_get_type(dev); 590 591 ret = fsl_spi_cpm_init(mpc8xxx_spi); 592 if (ret) 593 goto err_cpm_init; 594 595 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); 596 if (mpc8xxx_spi->reg_base == NULL) { 597 ret = -ENOMEM; 598 goto err_ioremap; 599 } 600 601 if (mpc8xxx_spi->type == TYPE_GRLIB) 602 fsl_spi_grlib_probe(dev); 603 604 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 605 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; 606 607 if (mpc8xxx_spi->set_shifts) 608 /* 8 bits per word and MSB first */ 609 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, 610 &mpc8xxx_spi->tx_shift, 8, 1); 611 612 /* Register for SPI Interrupt */ 613 ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq, 614 0, "fsl_spi", mpc8xxx_spi); 615 616 if (ret != 0) 617 goto free_irq; 618 619 reg_base = mpc8xxx_spi->reg_base; 620 621 /* SPI controller initializations */ 622 mpc8xxx_spi_write_reg(®_base->mode, 0); 623 mpc8xxx_spi_write_reg(®_base->mask, 0); 624 mpc8xxx_spi_write_reg(®_base->command, 0); 625 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 626 627 /* Enable SPI interface */ 628 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 629 if (mpc8xxx_spi->max_bits_per_word < 8) { 630 regval &= ~SPMODE_LEN(0xF); 631 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); 632 } 633 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) 634 regval |= SPMODE_OP; 635 636 mpc8xxx_spi_write_reg(®_base->mode, regval); 637 638 ret = spi_register_master(master); 639 if (ret < 0) 640 goto unreg_master; 641 642 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, 643 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); 644 645 return master; 646 647 unreg_master: 648 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); 649 free_irq: 650 iounmap(mpc8xxx_spi->reg_base); 651 err_ioremap: 652 fsl_spi_cpm_free(mpc8xxx_spi); 653 err_cpm_init: 654 err_probe: 655 spi_master_put(master); 656 err: 657 return ERR_PTR(ret); 658 } 659 660 static void fsl_spi_cs_control(struct spi_device *spi, bool on) 661 { 662 struct device *dev = spi->dev.parent->parent; 663 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); 664 u16 cs = spi->chip_select; 665 int gpio = pinfo->gpios[cs]; 666 bool alow = pinfo->alow_flags[cs]; 667 668 gpio_set_value(gpio, on ^ alow); 669 } 670 671 static int of_fsl_spi_get_chipselects(struct device *dev) 672 { 673 struct device_node *np = dev->of_node; 674 struct fsl_spi_platform_data *pdata = dev->platform_data; 675 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 676 int ngpios; 677 int i = 0; 678 int ret; 679 680 ngpios = of_gpio_count(np); 681 if (ngpios <= 0) { 682 /* 683 * SPI w/o chip-select line. One SPI device is still permitted 684 * though. 685 */ 686 pdata->max_chipselect = 1; 687 return 0; 688 } 689 690 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); 691 if (!pinfo->gpios) 692 return -ENOMEM; 693 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); 694 695 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), 696 GFP_KERNEL); 697 if (!pinfo->alow_flags) { 698 ret = -ENOMEM; 699 goto err_alloc_flags; 700 } 701 702 for (; i < ngpios; i++) { 703 int gpio; 704 enum of_gpio_flags flags; 705 706 gpio = of_get_gpio_flags(np, i, &flags); 707 if (!gpio_is_valid(gpio)) { 708 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); 709 ret = gpio; 710 goto err_loop; 711 } 712 713 ret = gpio_request(gpio, dev_name(dev)); 714 if (ret) { 715 dev_err(dev, "can't request gpio #%d: %d\n", i, ret); 716 goto err_loop; 717 } 718 719 pinfo->gpios[i] = gpio; 720 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; 721 722 ret = gpio_direction_output(pinfo->gpios[i], 723 pinfo->alow_flags[i]); 724 if (ret) { 725 dev_err(dev, "can't set output direction for gpio " 726 "#%d: %d\n", i, ret); 727 goto err_loop; 728 } 729 } 730 731 pdata->max_chipselect = ngpios; 732 pdata->cs_control = fsl_spi_cs_control; 733 734 return 0; 735 736 err_loop: 737 while (i >= 0) { 738 if (gpio_is_valid(pinfo->gpios[i])) 739 gpio_free(pinfo->gpios[i]); 740 i--; 741 } 742 743 kfree(pinfo->alow_flags); 744 pinfo->alow_flags = NULL; 745 err_alloc_flags: 746 kfree(pinfo->gpios); 747 pinfo->gpios = NULL; 748 return ret; 749 } 750 751 static int of_fsl_spi_free_chipselects(struct device *dev) 752 { 753 struct fsl_spi_platform_data *pdata = dev->platform_data; 754 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); 755 int i; 756 757 if (!pinfo->gpios) 758 return 0; 759 760 for (i = 0; i < pdata->max_chipselect; i++) { 761 if (gpio_is_valid(pinfo->gpios[i])) 762 gpio_free(pinfo->gpios[i]); 763 } 764 765 kfree(pinfo->gpios); 766 kfree(pinfo->alow_flags); 767 return 0; 768 } 769 770 static int of_fsl_spi_probe(struct platform_device *ofdev) 771 { 772 struct device *dev = &ofdev->dev; 773 struct device_node *np = ofdev->dev.of_node; 774 struct spi_master *master; 775 struct resource mem; 776 int irq, type; 777 int ret = -ENOMEM; 778 779 ret = of_mpc8xxx_spi_probe(ofdev); 780 if (ret) 781 return ret; 782 783 type = fsl_spi_get_type(&ofdev->dev); 784 if (type == TYPE_FSL) { 785 ret = of_fsl_spi_get_chipselects(dev); 786 if (ret) 787 goto err; 788 } 789 790 ret = of_address_to_resource(np, 0, &mem); 791 if (ret) 792 goto err; 793 794 irq = irq_of_parse_and_map(np, 0); 795 if (!irq) { 796 ret = -EINVAL; 797 goto err; 798 } 799 800 master = fsl_spi_probe(dev, &mem, irq); 801 if (IS_ERR(master)) { 802 ret = PTR_ERR(master); 803 goto err; 804 } 805 806 return 0; 807 808 err: 809 if (type == TYPE_FSL) 810 of_fsl_spi_free_chipselects(dev); 811 return ret; 812 } 813 814 static int of_fsl_spi_remove(struct platform_device *ofdev) 815 { 816 struct spi_master *master = dev_get_drvdata(&ofdev->dev); 817 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); 818 int ret; 819 820 ret = mpc8xxx_spi_remove(&ofdev->dev); 821 if (ret) 822 return ret; 823 if (mpc8xxx_spi->type == TYPE_FSL) 824 of_fsl_spi_free_chipselects(&ofdev->dev); 825 return 0; 826 } 827 828 static struct platform_driver of_fsl_spi_driver = { 829 .driver = { 830 .name = "fsl_spi", 831 .owner = THIS_MODULE, 832 .of_match_table = of_fsl_spi_match, 833 }, 834 .probe = of_fsl_spi_probe, 835 .remove = of_fsl_spi_remove, 836 }; 837 838 #ifdef CONFIG_MPC832x_RDB 839 /* 840 * XXX XXX XXX 841 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards 842 * only. The driver should go away soon, since newer MPC8323E-RDB's device 843 * tree can work with OpenFirmware driver. But for now we support old trees 844 * as well. 845 */ 846 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) 847 { 848 struct resource *mem; 849 int irq; 850 struct spi_master *master; 851 852 if (!pdev->dev.platform_data) 853 return -EINVAL; 854 855 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 856 if (!mem) 857 return -EINVAL; 858 859 irq = platform_get_irq(pdev, 0); 860 if (irq <= 0) 861 return -EINVAL; 862 863 master = fsl_spi_probe(&pdev->dev, mem, irq); 864 return PTR_RET(master); 865 } 866 867 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) 868 { 869 return mpc8xxx_spi_remove(&pdev->dev); 870 } 871 872 MODULE_ALIAS("platform:mpc8xxx_spi"); 873 static struct platform_driver mpc8xxx_spi_driver = { 874 .probe = plat_mpc8xxx_spi_probe, 875 .remove = plat_mpc8xxx_spi_remove, 876 .driver = { 877 .name = "mpc8xxx_spi", 878 .owner = THIS_MODULE, 879 }, 880 }; 881 882 static bool legacy_driver_failed; 883 884 static void __init legacy_driver_register(void) 885 { 886 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); 887 } 888 889 static void __exit legacy_driver_unregister(void) 890 { 891 if (legacy_driver_failed) 892 return; 893 platform_driver_unregister(&mpc8xxx_spi_driver); 894 } 895 #else 896 static void __init legacy_driver_register(void) {} 897 static void __exit legacy_driver_unregister(void) {} 898 #endif /* CONFIG_MPC832x_RDB */ 899 900 static int __init fsl_spi_init(void) 901 { 902 legacy_driver_register(); 903 return platform_driver_register(&of_fsl_spi_driver); 904 } 905 module_init(fsl_spi_init); 906 907 static void __exit fsl_spi_exit(void) 908 { 909 platform_driver_unregister(&of_fsl_spi_driver); 910 legacy_driver_unregister(); 911 } 912 module_exit(fsl_spi_exit); 913 914 MODULE_AUTHOR("Kumar Gala"); 915 MODULE_DESCRIPTION("Simple Freescale SPI Driver"); 916 MODULE_LICENSE("GPL"); 917