1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale i.MX7ULP LPSPI driver 4 // 5 // Copyright 2016 Freescale Semiconductor, Inc. 6 // Copyright 2018 NXP Semiconductors 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/err.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/platform_device.h> 22 #include <linux/dma/imx-dma.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/slab.h> 25 #include <linux/spi/spi.h> 26 #include <linux/spi/spi_bitbang.h> 27 #include <linux/types.h> 28 29 #define DRIVER_NAME "fsl_lpspi" 30 31 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */ 32 33 /* The maximum bytes that edma can transfer once.*/ 34 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1) 35 36 /* i.MX7ULP LPSPI registers */ 37 #define IMX7ULP_VERID 0x0 38 #define IMX7ULP_PARAM 0x4 39 #define IMX7ULP_CR 0x10 40 #define IMX7ULP_SR 0x14 41 #define IMX7ULP_IER 0x18 42 #define IMX7ULP_DER 0x1c 43 #define IMX7ULP_CFGR0 0x20 44 #define IMX7ULP_CFGR1 0x24 45 #define IMX7ULP_DMR0 0x30 46 #define IMX7ULP_DMR1 0x34 47 #define IMX7ULP_CCR 0x40 48 #define IMX7ULP_FCR 0x58 49 #define IMX7ULP_FSR 0x5c 50 #define IMX7ULP_TCR 0x60 51 #define IMX7ULP_TDR 0x64 52 #define IMX7ULP_RSR 0x70 53 #define IMX7ULP_RDR 0x74 54 55 /* General control register field define */ 56 #define CR_RRF BIT(9) 57 #define CR_RTF BIT(8) 58 #define CR_RST BIT(1) 59 #define CR_MEN BIT(0) 60 #define SR_MBF BIT(24) 61 #define SR_TCF BIT(10) 62 #define SR_FCF BIT(9) 63 #define SR_RDF BIT(1) 64 #define SR_TDF BIT(0) 65 #define IER_TCIE BIT(10) 66 #define IER_FCIE BIT(9) 67 #define IER_RDIE BIT(1) 68 #define IER_TDIE BIT(0) 69 #define DER_RDDE BIT(1) 70 #define DER_TDDE BIT(0) 71 #define CFGR1_PCSCFG BIT(27) 72 #define CFGR1_PINCFG (BIT(24)|BIT(25)) 73 #define CFGR1_PCSPOL BIT(8) 74 #define CFGR1_NOSTALL BIT(3) 75 #define CFGR1_HOST BIT(0) 76 #define FSR_TXCOUNT (0xFF) 77 #define RSR_RXEMPTY BIT(1) 78 #define TCR_CPOL BIT(31) 79 #define TCR_CPHA BIT(30) 80 #define TCR_CONT BIT(21) 81 #define TCR_CONTC BIT(20) 82 #define TCR_RXMSK BIT(19) 83 #define TCR_TXMSK BIT(18) 84 85 struct fsl_lpspi_devtype_data { 86 u8 prescale_max; 87 }; 88 89 struct lpspi_config { 90 u8 bpw; 91 u8 chip_select; 92 u8 prescale; 93 u16 mode; 94 u32 speed_hz; 95 u32 effective_speed_hz; 96 }; 97 98 struct fsl_lpspi_data { 99 struct device *dev; 100 void __iomem *base; 101 unsigned long base_phys; 102 struct clk *clk_ipg; 103 struct clk *clk_per; 104 bool is_target; 105 bool is_only_cs1; 106 bool is_first_byte; 107 108 void *rx_buf; 109 const void *tx_buf; 110 void (*tx)(struct fsl_lpspi_data *); 111 void (*rx)(struct fsl_lpspi_data *); 112 113 u32 remain; 114 u8 watermark; 115 u8 txfifosize; 116 u8 rxfifosize; 117 118 struct lpspi_config config; 119 struct completion xfer_done; 120 121 bool target_aborted; 122 123 /* DMA */ 124 bool usedma; 125 struct completion dma_rx_completion; 126 struct completion dma_tx_completion; 127 128 const struct fsl_lpspi_devtype_data *devtype_data; 129 }; 130 131 /* 132 * ERR051608 fixed or not: 133 * https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf 134 */ 135 static struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = { 136 .prescale_max = 1, 137 }; 138 139 static struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = { 140 .prescale_max = 7, 141 }; 142 143 static const struct of_device_id fsl_lpspi_dt_ids[] = { 144 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,}, 145 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,}, 146 { /* sentinel */ } 147 }; 148 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids); 149 150 #define LPSPI_BUF_RX(type) \ 151 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \ 152 { \ 153 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \ 154 \ 155 if (fsl_lpspi->rx_buf) { \ 156 *(type *)fsl_lpspi->rx_buf = val; \ 157 fsl_lpspi->rx_buf += sizeof(type); \ 158 } \ 159 } 160 161 #define LPSPI_BUF_TX(type) \ 162 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \ 163 { \ 164 type val = 0; \ 165 \ 166 if (fsl_lpspi->tx_buf) { \ 167 val = *(type *)fsl_lpspi->tx_buf; \ 168 fsl_lpspi->tx_buf += sizeof(type); \ 169 } \ 170 \ 171 fsl_lpspi->remain -= sizeof(type); \ 172 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \ 173 } 174 175 LPSPI_BUF_RX(u8) 176 LPSPI_BUF_TX(u8) 177 LPSPI_BUF_RX(u16) 178 LPSPI_BUF_TX(u16) 179 LPSPI_BUF_RX(u32) 180 LPSPI_BUF_TX(u32) 181 182 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi, 183 unsigned int enable) 184 { 185 writel(enable, fsl_lpspi->base + IMX7ULP_IER); 186 } 187 188 static int fsl_lpspi_bytes_per_word(const int bpw) 189 { 190 return DIV_ROUND_UP(bpw, BITS_PER_BYTE); 191 } 192 193 static bool fsl_lpspi_can_dma(struct spi_controller *controller, 194 struct spi_device *spi, 195 struct spi_transfer *transfer) 196 { 197 unsigned int bytes_per_word; 198 199 if (!controller->dma_rx) 200 return false; 201 202 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word); 203 204 switch (bytes_per_word) { 205 case 1: 206 case 2: 207 case 4: 208 break; 209 default: 210 return false; 211 } 212 213 return true; 214 } 215 216 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller) 217 { 218 struct fsl_lpspi_data *fsl_lpspi = 219 spi_controller_get_devdata(controller); 220 int ret; 221 222 ret = pm_runtime_resume_and_get(fsl_lpspi->dev); 223 if (ret < 0) { 224 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); 225 return ret; 226 } 227 228 return 0; 229 } 230 231 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) 232 { 233 struct fsl_lpspi_data *fsl_lpspi = 234 spi_controller_get_devdata(controller); 235 236 pm_runtime_put_autosuspend(fsl_lpspi->dev); 237 238 return 0; 239 } 240 241 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi) 242 { 243 u8 txfifo_cnt; 244 u32 temp; 245 246 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; 247 248 while (txfifo_cnt < fsl_lpspi->txfifosize) { 249 if (!fsl_lpspi->remain) 250 break; 251 fsl_lpspi->tx(fsl_lpspi); 252 txfifo_cnt++; 253 } 254 255 if (txfifo_cnt < fsl_lpspi->txfifosize) { 256 if (!fsl_lpspi->is_target) { 257 temp = readl(fsl_lpspi->base + IMX7ULP_TCR); 258 temp &= ~TCR_CONTC; 259 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); 260 } 261 262 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); 263 } else 264 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE); 265 } 266 267 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi) 268 { 269 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY)) 270 fsl_lpspi->rx(fsl_lpspi); 271 } 272 273 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi) 274 { 275 u32 temp = 0; 276 277 temp |= fsl_lpspi->config.bpw - 1; 278 temp |= (fsl_lpspi->config.mode & 0x3) << 30; 279 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; 280 if (!fsl_lpspi->is_target) { 281 temp |= fsl_lpspi->config.prescale << 27; 282 /* 283 * Set TCR_CONT will keep SS asserted after current transfer. 284 * For the first transfer, clear TCR_CONTC to assert SS. 285 * For subsequent transfer, set TCR_CONTC to keep SS asserted. 286 */ 287 if (!fsl_lpspi->usedma) { 288 temp |= TCR_CONT; 289 if (fsl_lpspi->is_first_byte) 290 temp &= ~TCR_CONTC; 291 else 292 temp |= TCR_CONTC; 293 } 294 } 295 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); 296 297 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp); 298 } 299 300 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi) 301 { 302 u32 temp; 303 304 if (!fsl_lpspi->usedma) 305 temp = fsl_lpspi->watermark >> 1 | 306 (fsl_lpspi->watermark >> 1) << 16; 307 else 308 temp = fsl_lpspi->watermark >> 1; 309 310 writel(temp, fsl_lpspi->base + IMX7ULP_FCR); 311 312 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp); 313 } 314 315 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) 316 { 317 struct lpspi_config config = fsl_lpspi->config; 318 unsigned int perclk_rate, div; 319 u8 prescale_max; 320 u8 prescale; 321 int scldiv; 322 323 perclk_rate = clk_get_rate(fsl_lpspi->clk_per); 324 prescale_max = fsl_lpspi->devtype_data->prescale_max; 325 326 if (!config.speed_hz) { 327 dev_err(fsl_lpspi->dev, 328 "error: the transmission speed provided is 0!\n"); 329 return -EINVAL; 330 } 331 332 if (config.speed_hz > perclk_rate / 2) { 333 div = 2; 334 } else { 335 div = DIV_ROUND_UP(perclk_rate, config.speed_hz); 336 } 337 338 for (prescale = 0; prescale <= prescale_max; prescale++) { 339 scldiv = div / (1 << prescale) - 2; 340 if (scldiv >= 0 && scldiv < 256) { 341 fsl_lpspi->config.prescale = prescale; 342 break; 343 } 344 } 345 346 if (scldiv < 0 || scldiv >= 256) 347 return -EINVAL; 348 349 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16), 350 fsl_lpspi->base + IMX7ULP_CCR); 351 352 fsl_lpspi->config.effective_speed_hz = perclk_rate / (scldiv + 2) * 353 (1 << prescale); 354 355 dev_dbg(fsl_lpspi->dev, "perclk=%u, speed=%u, prescale=%u, scldiv=%d\n", 356 perclk_rate, config.speed_hz, prescale, scldiv); 357 358 return 0; 359 } 360 361 static int fsl_lpspi_dma_configure(struct spi_controller *controller) 362 { 363 int ret; 364 enum dma_slave_buswidth buswidth; 365 struct dma_slave_config rx = {}, tx = {}; 366 struct fsl_lpspi_data *fsl_lpspi = 367 spi_controller_get_devdata(controller); 368 369 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) { 370 case 4: 371 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 372 break; 373 case 2: 374 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 375 break; 376 case 1: 377 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 378 break; 379 default: 380 return -EINVAL; 381 } 382 383 tx.direction = DMA_MEM_TO_DEV; 384 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR; 385 tx.dst_addr_width = buswidth; 386 tx.dst_maxburst = 1; 387 ret = dmaengine_slave_config(controller->dma_tx, &tx); 388 if (ret) { 389 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n", 390 ret); 391 return ret; 392 } 393 394 rx.direction = DMA_DEV_TO_MEM; 395 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR; 396 rx.src_addr_width = buswidth; 397 rx.src_maxburst = 1; 398 ret = dmaengine_slave_config(controller->dma_rx, &rx); 399 if (ret) { 400 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n", 401 ret); 402 return ret; 403 } 404 405 return 0; 406 } 407 408 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) 409 { 410 u32 temp; 411 int ret; 412 413 if (!fsl_lpspi->is_target) { 414 ret = fsl_lpspi_set_bitrate(fsl_lpspi); 415 if (ret) 416 return ret; 417 } 418 419 fsl_lpspi_set_watermark(fsl_lpspi); 420 421 if (!fsl_lpspi->is_target) 422 temp = CFGR1_HOST; 423 else 424 temp = CFGR1_PINCFG; 425 if (fsl_lpspi->config.mode & SPI_CS_HIGH) 426 temp |= CFGR1_PCSPOL; 427 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1); 428 429 temp = readl(fsl_lpspi->base + IMX7ULP_CR); 430 temp |= CR_RRF | CR_RTF | CR_MEN; 431 writel(temp, fsl_lpspi->base + IMX7ULP_CR); 432 433 temp = 0; 434 if (fsl_lpspi->usedma) 435 temp = DER_TDDE | DER_RDDE; 436 writel(temp, fsl_lpspi->base + IMX7ULP_DER); 437 438 return 0; 439 } 440 441 static int fsl_lpspi_setup_transfer(struct spi_controller *controller, 442 struct spi_device *spi, 443 struct spi_transfer *t) 444 { 445 struct fsl_lpspi_data *fsl_lpspi = 446 spi_controller_get_devdata(spi->controller); 447 448 if (t == NULL) 449 return -EINVAL; 450 451 fsl_lpspi->config.mode = spi->mode; 452 fsl_lpspi->config.bpw = t->bits_per_word; 453 fsl_lpspi->config.speed_hz = t->speed_hz; 454 if (fsl_lpspi->is_only_cs1) 455 fsl_lpspi->config.chip_select = 1; 456 else 457 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0); 458 459 if (!fsl_lpspi->config.speed_hz) 460 fsl_lpspi->config.speed_hz = spi->max_speed_hz; 461 if (!fsl_lpspi->config.bpw) 462 fsl_lpspi->config.bpw = spi->bits_per_word; 463 464 /* Initialize the functions for transfer */ 465 if (fsl_lpspi->config.bpw <= 8) { 466 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8; 467 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8; 468 } else if (fsl_lpspi->config.bpw <= 16) { 469 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16; 470 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16; 471 } else { 472 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32; 473 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32; 474 } 475 476 if (t->len <= fsl_lpspi->txfifosize) 477 fsl_lpspi->watermark = t->len; 478 else 479 fsl_lpspi->watermark = fsl_lpspi->txfifosize; 480 481 if (fsl_lpspi_can_dma(controller, spi, t)) 482 fsl_lpspi->usedma = true; 483 else 484 fsl_lpspi->usedma = false; 485 486 return fsl_lpspi_config(fsl_lpspi); 487 } 488 489 static int fsl_lpspi_target_abort(struct spi_controller *controller) 490 { 491 struct fsl_lpspi_data *fsl_lpspi = 492 spi_controller_get_devdata(controller); 493 494 fsl_lpspi->target_aborted = true; 495 if (!fsl_lpspi->usedma) 496 complete(&fsl_lpspi->xfer_done); 497 else { 498 complete(&fsl_lpspi->dma_tx_completion); 499 complete(&fsl_lpspi->dma_rx_completion); 500 } 501 502 return 0; 503 } 504 505 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller) 506 { 507 struct fsl_lpspi_data *fsl_lpspi = 508 spi_controller_get_devdata(controller); 509 510 if (fsl_lpspi->is_target) { 511 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) || 512 fsl_lpspi->target_aborted) { 513 dev_dbg(fsl_lpspi->dev, "interrupted\n"); 514 return -EINTR; 515 } 516 } else { 517 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) { 518 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n"); 519 return -ETIMEDOUT; 520 } 521 } 522 523 return 0; 524 } 525 526 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi) 527 { 528 u32 temp; 529 530 if (!fsl_lpspi->usedma) { 531 /* Disable all interrupt */ 532 fsl_lpspi_intctrl(fsl_lpspi, 0); 533 } 534 535 /* W1C for all flags in SR */ 536 temp = 0x3F << 8; 537 writel(temp, fsl_lpspi->base + IMX7ULP_SR); 538 539 /* Clear FIFO and disable module */ 540 temp = CR_RRF | CR_RTF; 541 writel(temp, fsl_lpspi->base + IMX7ULP_CR); 542 543 return 0; 544 } 545 546 static void fsl_lpspi_dma_rx_callback(void *cookie) 547 { 548 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie; 549 550 complete(&fsl_lpspi->dma_rx_completion); 551 } 552 553 static void fsl_lpspi_dma_tx_callback(void *cookie) 554 { 555 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie; 556 557 complete(&fsl_lpspi->dma_tx_completion); 558 } 559 560 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi, 561 int size) 562 { 563 unsigned long timeout = 0; 564 565 /* Time with actual data transfer and CS change delay related to HW */ 566 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz; 567 568 /* Add extra second for scheduler related activities */ 569 timeout += 1; 570 571 /* Double calculated timeout */ 572 return secs_to_jiffies(2 * timeout); 573 } 574 575 static int fsl_lpspi_dma_transfer(struct spi_controller *controller, 576 struct fsl_lpspi_data *fsl_lpspi, 577 struct spi_transfer *transfer) 578 { 579 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 580 unsigned long transfer_timeout; 581 unsigned long time_left; 582 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 583 int ret; 584 585 ret = fsl_lpspi_dma_configure(controller); 586 if (ret) 587 return ret; 588 589 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, 590 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 591 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 592 if (!desc_rx) 593 return -EINVAL; 594 595 desc_rx->callback = fsl_lpspi_dma_rx_callback; 596 desc_rx->callback_param = (void *)fsl_lpspi; 597 dmaengine_submit(desc_rx); 598 reinit_completion(&fsl_lpspi->dma_rx_completion); 599 dma_async_issue_pending(controller->dma_rx); 600 601 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, 602 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 603 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 604 if (!desc_tx) { 605 dmaengine_terminate_all(controller->dma_tx); 606 return -EINVAL; 607 } 608 609 desc_tx->callback = fsl_lpspi_dma_tx_callback; 610 desc_tx->callback_param = (void *)fsl_lpspi; 611 dmaengine_submit(desc_tx); 612 reinit_completion(&fsl_lpspi->dma_tx_completion); 613 dma_async_issue_pending(controller->dma_tx); 614 615 fsl_lpspi->target_aborted = false; 616 617 if (!fsl_lpspi->is_target) { 618 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi, 619 transfer->len); 620 621 /* Wait eDMA to finish the data transfer.*/ 622 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion, 623 transfer_timeout); 624 if (!time_left) { 625 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n"); 626 dmaengine_terminate_all(controller->dma_tx); 627 dmaengine_terminate_all(controller->dma_rx); 628 fsl_lpspi_reset(fsl_lpspi); 629 return -ETIMEDOUT; 630 } 631 632 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion, 633 transfer_timeout); 634 if (!time_left) { 635 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n"); 636 dmaengine_terminate_all(controller->dma_tx); 637 dmaengine_terminate_all(controller->dma_rx); 638 fsl_lpspi_reset(fsl_lpspi); 639 return -ETIMEDOUT; 640 } 641 } else { 642 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) || 643 fsl_lpspi->target_aborted) { 644 dev_dbg(fsl_lpspi->dev, 645 "I/O Error in DMA TX interrupted\n"); 646 dmaengine_terminate_all(controller->dma_tx); 647 dmaengine_terminate_all(controller->dma_rx); 648 fsl_lpspi_reset(fsl_lpspi); 649 return -EINTR; 650 } 651 652 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) || 653 fsl_lpspi->target_aborted) { 654 dev_dbg(fsl_lpspi->dev, 655 "I/O Error in DMA RX interrupted\n"); 656 dmaengine_terminate_all(controller->dma_tx); 657 dmaengine_terminate_all(controller->dma_rx); 658 fsl_lpspi_reset(fsl_lpspi); 659 return -EINTR; 660 } 661 } 662 663 fsl_lpspi_reset(fsl_lpspi); 664 665 return 0; 666 } 667 668 static void fsl_lpspi_dma_exit(struct spi_controller *controller) 669 { 670 if (controller->dma_rx) { 671 dma_release_channel(controller->dma_rx); 672 controller->dma_rx = NULL; 673 } 674 675 if (controller->dma_tx) { 676 dma_release_channel(controller->dma_tx); 677 controller->dma_tx = NULL; 678 } 679 } 680 681 static int fsl_lpspi_dma_init(struct device *dev, 682 struct fsl_lpspi_data *fsl_lpspi, 683 struct spi_controller *controller) 684 { 685 int ret; 686 687 /* Prepare for TX DMA: */ 688 controller->dma_tx = dma_request_chan(dev, "tx"); 689 if (IS_ERR(controller->dma_tx)) { 690 ret = PTR_ERR(controller->dma_tx); 691 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); 692 controller->dma_tx = NULL; 693 goto err; 694 } 695 696 /* Prepare for RX DMA: */ 697 controller->dma_rx = dma_request_chan(dev, "rx"); 698 if (IS_ERR(controller->dma_rx)) { 699 ret = PTR_ERR(controller->dma_rx); 700 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); 701 controller->dma_rx = NULL; 702 goto err; 703 } 704 705 init_completion(&fsl_lpspi->dma_rx_completion); 706 init_completion(&fsl_lpspi->dma_tx_completion); 707 controller->can_dma = fsl_lpspi_can_dma; 708 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES; 709 710 return 0; 711 err: 712 fsl_lpspi_dma_exit(controller); 713 return ret; 714 } 715 716 static int fsl_lpspi_pio_transfer(struct spi_controller *controller, 717 struct spi_transfer *t) 718 { 719 struct fsl_lpspi_data *fsl_lpspi = 720 spi_controller_get_devdata(controller); 721 int ret; 722 723 fsl_lpspi->tx_buf = t->tx_buf; 724 fsl_lpspi->rx_buf = t->rx_buf; 725 fsl_lpspi->remain = t->len; 726 727 reinit_completion(&fsl_lpspi->xfer_done); 728 fsl_lpspi->target_aborted = false; 729 730 fsl_lpspi_write_tx_fifo(fsl_lpspi); 731 732 ret = fsl_lpspi_wait_for_completion(controller); 733 if (ret) 734 return ret; 735 736 fsl_lpspi_reset(fsl_lpspi); 737 738 return 0; 739 } 740 741 static int fsl_lpspi_transfer_one(struct spi_controller *controller, 742 struct spi_device *spi, 743 struct spi_transfer *t) 744 { 745 struct fsl_lpspi_data *fsl_lpspi = 746 spi_controller_get_devdata(controller); 747 int ret; 748 749 fsl_lpspi->is_first_byte = true; 750 ret = fsl_lpspi_setup_transfer(controller, spi, t); 751 if (ret < 0) 752 return ret; 753 754 t->effective_speed_hz = fsl_lpspi->config.effective_speed_hz; 755 756 fsl_lpspi_set_cmd(fsl_lpspi); 757 fsl_lpspi->is_first_byte = false; 758 759 if (fsl_lpspi->usedma) 760 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t); 761 else 762 ret = fsl_lpspi_pio_transfer(controller, t); 763 if (ret < 0) 764 return ret; 765 766 return 0; 767 } 768 769 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id) 770 { 771 u32 temp_SR, temp_IER; 772 struct fsl_lpspi_data *fsl_lpspi = dev_id; 773 774 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER); 775 fsl_lpspi_intctrl(fsl_lpspi, 0); 776 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR); 777 778 fsl_lpspi_read_rx_fifo(fsl_lpspi); 779 780 if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) { 781 fsl_lpspi_write_tx_fifo(fsl_lpspi); 782 return IRQ_HANDLED; 783 } 784 785 if (temp_SR & SR_MBF || 786 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) { 787 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); 788 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); 789 return IRQ_HANDLED; 790 } 791 792 if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) { 793 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); 794 complete(&fsl_lpspi->xfer_done); 795 return IRQ_HANDLED; 796 } 797 798 return IRQ_NONE; 799 } 800 801 #ifdef CONFIG_PM 802 static int fsl_lpspi_runtime_resume(struct device *dev) 803 { 804 struct spi_controller *controller = dev_get_drvdata(dev); 805 struct fsl_lpspi_data *fsl_lpspi; 806 int ret; 807 808 fsl_lpspi = spi_controller_get_devdata(controller); 809 810 ret = clk_prepare_enable(fsl_lpspi->clk_per); 811 if (ret) 812 return ret; 813 814 ret = clk_prepare_enable(fsl_lpspi->clk_ipg); 815 if (ret) { 816 clk_disable_unprepare(fsl_lpspi->clk_per); 817 return ret; 818 } 819 820 return 0; 821 } 822 823 static int fsl_lpspi_runtime_suspend(struct device *dev) 824 { 825 struct spi_controller *controller = dev_get_drvdata(dev); 826 struct fsl_lpspi_data *fsl_lpspi; 827 828 fsl_lpspi = spi_controller_get_devdata(controller); 829 830 clk_disable_unprepare(fsl_lpspi->clk_per); 831 clk_disable_unprepare(fsl_lpspi->clk_ipg); 832 833 return 0; 834 } 835 #endif 836 837 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi) 838 { 839 struct device *dev = fsl_lpspi->dev; 840 841 pm_runtime_enable(dev); 842 pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT); 843 pm_runtime_use_autosuspend(dev); 844 845 return 0; 846 } 847 848 static int fsl_lpspi_probe(struct platform_device *pdev) 849 { 850 const struct fsl_lpspi_devtype_data *devtype_data; 851 struct fsl_lpspi_data *fsl_lpspi; 852 struct spi_controller *controller; 853 struct resource *res; 854 int ret, irq; 855 u32 num_cs; 856 u32 temp; 857 bool is_target; 858 859 devtype_data = of_device_get_match_data(&pdev->dev); 860 if (!devtype_data) 861 return -ENODEV; 862 863 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave"); 864 if (is_target) 865 controller = devm_spi_alloc_target(&pdev->dev, 866 sizeof(struct fsl_lpspi_data)); 867 else 868 controller = devm_spi_alloc_host(&pdev->dev, 869 sizeof(struct fsl_lpspi_data)); 870 871 if (!controller) 872 return -ENOMEM; 873 874 platform_set_drvdata(pdev, controller); 875 876 fsl_lpspi = spi_controller_get_devdata(controller); 877 fsl_lpspi->dev = &pdev->dev; 878 fsl_lpspi->is_target = is_target; 879 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node, 880 "fsl,spi-only-use-cs1-sel"); 881 fsl_lpspi->devtype_data = devtype_data; 882 883 init_completion(&fsl_lpspi->xfer_done); 884 885 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 886 if (IS_ERR(fsl_lpspi->base)) { 887 ret = PTR_ERR(fsl_lpspi->base); 888 return ret; 889 } 890 fsl_lpspi->base_phys = res->start; 891 892 irq = platform_get_irq(pdev, 0); 893 if (irq < 0) { 894 ret = irq; 895 return ret; 896 } 897 898 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, IRQF_NO_AUTOEN, 899 dev_name(&pdev->dev), fsl_lpspi); 900 if (ret) { 901 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 902 return ret; 903 } 904 905 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per"); 906 if (IS_ERR(fsl_lpspi->clk_per)) { 907 ret = PTR_ERR(fsl_lpspi->clk_per); 908 return ret; 909 } 910 911 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 912 if (IS_ERR(fsl_lpspi->clk_ipg)) { 913 ret = PTR_ERR(fsl_lpspi->clk_ipg); 914 return ret; 915 } 916 917 /* enable the clock */ 918 ret = fsl_lpspi_init_rpm(fsl_lpspi); 919 if (ret) 920 return ret; 921 922 ret = pm_runtime_get_sync(fsl_lpspi->dev); 923 if (ret < 0) { 924 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); 925 goto out_pm_get; 926 } 927 928 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM); 929 fsl_lpspi->txfifosize = 1 << (temp & 0x0f); 930 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f); 931 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs", 932 &num_cs)) { 933 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi")) 934 num_cs = ((temp >> 16) & 0xf); 935 else 936 num_cs = 1; 937 } 938 939 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); 940 controller->transfer_one = fsl_lpspi_transfer_one; 941 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; 942 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; 943 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 944 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; 945 controller->dev.of_node = pdev->dev.of_node; 946 controller->bus_num = pdev->id; 947 controller->num_chipselect = num_cs; 948 controller->target_abort = fsl_lpspi_target_abort; 949 if (!fsl_lpspi->is_target) 950 controller->use_gpio_descriptors = true; 951 952 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller); 953 if (ret == -EPROBE_DEFER) 954 goto out_pm_get; 955 if (ret < 0) { 956 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret); 957 enable_irq(irq); 958 } 959 960 ret = devm_spi_register_controller(&pdev->dev, controller); 961 if (ret < 0) { 962 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n"); 963 goto free_dma; 964 } 965 966 pm_runtime_put_autosuspend(fsl_lpspi->dev); 967 968 return 0; 969 970 free_dma: 971 fsl_lpspi_dma_exit(controller); 972 out_pm_get: 973 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev); 974 pm_runtime_put_sync(fsl_lpspi->dev); 975 pm_runtime_disable(fsl_lpspi->dev); 976 977 return ret; 978 } 979 980 static void fsl_lpspi_remove(struct platform_device *pdev) 981 { 982 struct spi_controller *controller = platform_get_drvdata(pdev); 983 struct fsl_lpspi_data *fsl_lpspi = 984 spi_controller_get_devdata(controller); 985 986 fsl_lpspi_dma_exit(controller); 987 988 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev); 989 pm_runtime_disable(fsl_lpspi->dev); 990 } 991 992 static int fsl_lpspi_suspend(struct device *dev) 993 { 994 pinctrl_pm_select_sleep_state(dev); 995 return pm_runtime_force_suspend(dev); 996 } 997 998 static int fsl_lpspi_resume(struct device *dev) 999 { 1000 int ret; 1001 1002 ret = pm_runtime_force_resume(dev); 1003 if (ret) { 1004 dev_err(dev, "Error in resume: %d\n", ret); 1005 return ret; 1006 } 1007 1008 pinctrl_pm_select_default_state(dev); 1009 1010 return 0; 1011 } 1012 1013 static const struct dev_pm_ops fsl_lpspi_pm_ops = { 1014 SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend, 1015 fsl_lpspi_runtime_resume, NULL) 1016 SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume) 1017 }; 1018 1019 static struct platform_driver fsl_lpspi_driver = { 1020 .driver = { 1021 .name = DRIVER_NAME, 1022 .of_match_table = fsl_lpspi_dt_ids, 1023 .pm = pm_ptr(&fsl_lpspi_pm_ops), 1024 }, 1025 .probe = fsl_lpspi_probe, 1026 .remove = fsl_lpspi_remove, 1027 }; 1028 module_platform_driver(fsl_lpspi_driver); 1029 1030 MODULE_DESCRIPTION("LPSPI Controller driver"); 1031 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>"); 1032 MODULE_LICENSE("GPL"); 1033