1 /* 2 * Freescale eSPI controller driver. 3 * 4 * Copyright 2010 Freescale Semiconductor, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/irq.h> 14 #include <linux/spi/spi.h> 15 #include <linux/platform_device.h> 16 #include <linux/fsl_devices.h> 17 #include <linux/mm.h> 18 #include <linux/of.h> 19 #include <linux/of_platform.h> 20 #include <linux/of_spi.h> 21 #include <linux/interrupt.h> 22 #include <linux/err.h> 23 #include <sysdev/fsl_soc.h> 24 25 #include "spi-fsl-lib.h" 26 27 /* eSPI Controller registers */ 28 struct fsl_espi_reg { 29 __be32 mode; /* 0x000 - eSPI mode register */ 30 __be32 event; /* 0x004 - eSPI event register */ 31 __be32 mask; /* 0x008 - eSPI mask register */ 32 __be32 command; /* 0x00c - eSPI command register */ 33 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/ 34 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/ 35 u8 res[8]; /* 0x018 - 0x01c reserved */ 36 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */ 37 }; 38 39 struct fsl_espi_transfer { 40 const void *tx_buf; 41 void *rx_buf; 42 unsigned len; 43 unsigned n_tx; 44 unsigned n_rx; 45 unsigned actual_length; 46 int status; 47 }; 48 49 /* eSPI Controller mode register definitions */ 50 #define SPMODE_ENABLE (1 << 31) 51 #define SPMODE_LOOP (1 << 30) 52 #define SPMODE_TXTHR(x) ((x) << 8) 53 #define SPMODE_RXTHR(x) ((x) << 0) 54 55 /* eSPI Controller CS mode register definitions */ 56 #define CSMODE_CI_INACTIVEHIGH (1 << 31) 57 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30) 58 #define CSMODE_REV (1 << 29) 59 #define CSMODE_DIV16 (1 << 28) 60 #define CSMODE_PM(x) ((x) << 24) 61 #define CSMODE_POL_1 (1 << 20) 62 #define CSMODE_LEN(x) ((x) << 16) 63 #define CSMODE_BEF(x) ((x) << 12) 64 #define CSMODE_AFT(x) ((x) << 8) 65 #define CSMODE_CG(x) ((x) << 3) 66 67 /* Default mode/csmode for eSPI controller */ 68 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3)) 69 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \ 70 | CSMODE_AFT(0) | CSMODE_CG(1)) 71 72 /* SPIE register values */ 73 #define SPIE_NE 0x00000200 /* Not empty */ 74 #define SPIE_NF 0x00000100 /* Not full */ 75 76 /* SPIM register values */ 77 #define SPIM_NE 0x00000200 /* Not empty */ 78 #define SPIM_NF 0x00000100 /* Not full */ 79 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F) 80 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F) 81 82 /* SPCOM register values */ 83 #define SPCOM_CS(x) ((x) << 30) 84 #define SPCOM_TRANLEN(x) ((x) << 0) 85 #define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */ 86 87 static void fsl_espi_change_mode(struct spi_device *spi) 88 { 89 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 90 struct spi_mpc8xxx_cs *cs = spi->controller_state; 91 struct fsl_espi_reg *reg_base = mspi->reg_base; 92 __be32 __iomem *mode = ®_base->csmode[spi->chip_select]; 93 __be32 __iomem *espi_mode = ®_base->mode; 94 u32 tmp; 95 unsigned long flags; 96 97 /* Turn off IRQs locally to minimize time that SPI is disabled. */ 98 local_irq_save(flags); 99 100 /* Turn off SPI unit prior changing mode */ 101 tmp = mpc8xxx_spi_read_reg(espi_mode); 102 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE); 103 mpc8xxx_spi_write_reg(mode, cs->hw_mode); 104 mpc8xxx_spi_write_reg(espi_mode, tmp); 105 106 local_irq_restore(flags); 107 } 108 109 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi) 110 { 111 u32 data; 112 u16 data_h; 113 u16 data_l; 114 const u32 *tx = mpc8xxx_spi->tx; 115 116 if (!tx) 117 return 0; 118 119 data = *tx++ << mpc8xxx_spi->tx_shift; 120 data_l = data & 0xffff; 121 data_h = (data >> 16) & 0xffff; 122 swab16s(&data_l); 123 swab16s(&data_h); 124 data = data_h | data_l; 125 126 mpc8xxx_spi->tx = tx; 127 return data; 128 } 129 130 static int fsl_espi_setup_transfer(struct spi_device *spi, 131 struct spi_transfer *t) 132 { 133 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 134 int bits_per_word = 0; 135 u8 pm; 136 u32 hz = 0; 137 struct spi_mpc8xxx_cs *cs = spi->controller_state; 138 139 if (t) { 140 bits_per_word = t->bits_per_word; 141 hz = t->speed_hz; 142 } 143 144 /* spi_transfer level calls that work per-word */ 145 if (!bits_per_word) 146 bits_per_word = spi->bits_per_word; 147 148 /* Make sure its a bit width we support [4..16] */ 149 if ((bits_per_word < 4) || (bits_per_word > 16)) 150 return -EINVAL; 151 152 if (!hz) 153 hz = spi->max_speed_hz; 154 155 cs->rx_shift = 0; 156 cs->tx_shift = 0; 157 cs->get_rx = mpc8xxx_spi_rx_buf_u32; 158 cs->get_tx = mpc8xxx_spi_tx_buf_u32; 159 if (bits_per_word <= 8) { 160 cs->rx_shift = 8 - bits_per_word; 161 } else if (bits_per_word <= 16) { 162 cs->rx_shift = 16 - bits_per_word; 163 if (spi->mode & SPI_LSB_FIRST) 164 cs->get_tx = fsl_espi_tx_buf_lsb; 165 } else { 166 return -EINVAL; 167 } 168 169 mpc8xxx_spi->rx_shift = cs->rx_shift; 170 mpc8xxx_spi->tx_shift = cs->tx_shift; 171 mpc8xxx_spi->get_rx = cs->get_rx; 172 mpc8xxx_spi->get_tx = cs->get_tx; 173 174 bits_per_word = bits_per_word - 1; 175 176 /* mask out bits we are going to set */ 177 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); 178 179 cs->hw_mode |= CSMODE_LEN(bits_per_word); 180 181 if ((mpc8xxx_spi->spibrg / hz) > 64) { 182 cs->hw_mode |= CSMODE_DIV16; 183 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; 184 185 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " 186 "Will use %d Hz instead.\n", dev_name(&spi->dev), 187 hz, mpc8xxx_spi->spibrg / 1024); 188 if (pm > 16) 189 pm = 16; 190 } else { 191 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; 192 } 193 if (pm) 194 pm--; 195 196 cs->hw_mode |= CSMODE_PM(pm); 197 198 fsl_espi_change_mode(spi); 199 return 0; 200 } 201 202 static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t, 203 unsigned int len) 204 { 205 u32 word; 206 struct fsl_espi_reg *reg_base = mspi->reg_base; 207 208 mspi->count = len; 209 210 /* enable rx ints */ 211 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); 212 213 /* transmit word */ 214 word = mspi->get_tx(mspi); 215 mpc8xxx_spi_write_reg(®_base->transmit, word); 216 217 return 0; 218 } 219 220 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t) 221 { 222 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); 223 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; 224 unsigned int len = t->len; 225 u8 bits_per_word; 226 int ret; 227 228 bits_per_word = spi->bits_per_word; 229 if (t->bits_per_word) 230 bits_per_word = t->bits_per_word; 231 232 mpc8xxx_spi->len = t->len; 233 len = roundup(len, 4) / 4; 234 235 mpc8xxx_spi->tx = t->tx_buf; 236 mpc8xxx_spi->rx = t->rx_buf; 237 238 INIT_COMPLETION(mpc8xxx_spi->done); 239 240 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ 241 if ((t->len - 1) > SPCOM_TRANLEN_MAX) { 242 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)" 243 " beyond the SPCOM[TRANLEN] field\n", t->len); 244 return -EINVAL; 245 } 246 mpc8xxx_spi_write_reg(®_base->command, 247 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1))); 248 249 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len); 250 if (ret) 251 return ret; 252 253 wait_for_completion(&mpc8xxx_spi->done); 254 255 /* disable rx ints */ 256 mpc8xxx_spi_write_reg(®_base->mask, 0); 257 258 return mpc8xxx_spi->count; 259 } 260 261 static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd) 262 { 263 if (cmd) { 264 cmd[1] = (u8)(addr >> 16); 265 cmd[2] = (u8)(addr >> 8); 266 cmd[3] = (u8)(addr >> 0); 267 } 268 } 269 270 static inline unsigned int fsl_espi_cmd2addr(u8 *cmd) 271 { 272 if (cmd) 273 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0; 274 275 return 0; 276 } 277 278 static void fsl_espi_do_trans(struct spi_message *m, 279 struct fsl_espi_transfer *tr) 280 { 281 struct spi_device *spi = m->spi; 282 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); 283 struct fsl_espi_transfer *espi_trans = tr; 284 struct spi_message message; 285 struct spi_transfer *t, *first, trans; 286 int status = 0; 287 288 spi_message_init(&message); 289 memset(&trans, 0, sizeof(trans)); 290 291 first = list_first_entry(&m->transfers, struct spi_transfer, 292 transfer_list); 293 list_for_each_entry(t, &m->transfers, transfer_list) { 294 if ((first->bits_per_word != t->bits_per_word) || 295 (first->speed_hz != t->speed_hz)) { 296 espi_trans->status = -EINVAL; 297 dev_err(mspi->dev, "bits_per_word/speed_hz should be" 298 " same for the same SPI transfer\n"); 299 return; 300 } 301 302 trans.speed_hz = t->speed_hz; 303 trans.bits_per_word = t->bits_per_word; 304 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs); 305 } 306 307 trans.len = espi_trans->len; 308 trans.tx_buf = espi_trans->tx_buf; 309 trans.rx_buf = espi_trans->rx_buf; 310 spi_message_add_tail(&trans, &message); 311 312 list_for_each_entry(t, &message.transfers, transfer_list) { 313 if (t->bits_per_word || t->speed_hz) { 314 status = -EINVAL; 315 316 status = fsl_espi_setup_transfer(spi, t); 317 if (status < 0) 318 break; 319 } 320 321 if (t->len) 322 status = fsl_espi_bufs(spi, t); 323 324 if (status) { 325 status = -EMSGSIZE; 326 break; 327 } 328 329 if (t->delay_usecs) 330 udelay(t->delay_usecs); 331 } 332 333 espi_trans->status = status; 334 fsl_espi_setup_transfer(spi, NULL); 335 } 336 337 static void fsl_espi_cmd_trans(struct spi_message *m, 338 struct fsl_espi_transfer *trans, u8 *rx_buff) 339 { 340 struct spi_transfer *t; 341 u8 *local_buf; 342 int i = 0; 343 struct fsl_espi_transfer *espi_trans = trans; 344 345 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL); 346 if (!local_buf) { 347 espi_trans->status = -ENOMEM; 348 return; 349 } 350 351 list_for_each_entry(t, &m->transfers, transfer_list) { 352 if (t->tx_buf) { 353 memcpy(local_buf + i, t->tx_buf, t->len); 354 i += t->len; 355 } 356 } 357 358 espi_trans->tx_buf = local_buf; 359 espi_trans->rx_buf = local_buf + espi_trans->n_tx; 360 fsl_espi_do_trans(m, espi_trans); 361 362 espi_trans->actual_length = espi_trans->len; 363 kfree(local_buf); 364 } 365 366 static void fsl_espi_rw_trans(struct spi_message *m, 367 struct fsl_espi_transfer *trans, u8 *rx_buff) 368 { 369 struct fsl_espi_transfer *espi_trans = trans; 370 unsigned int n_tx = espi_trans->n_tx; 371 unsigned int n_rx = espi_trans->n_rx; 372 struct spi_transfer *t; 373 u8 *local_buf; 374 u8 *rx_buf = rx_buff; 375 unsigned int trans_len; 376 unsigned int addr; 377 int i, pos, loop; 378 379 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL); 380 if (!local_buf) { 381 espi_trans->status = -ENOMEM; 382 return; 383 } 384 385 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) { 386 trans_len = n_rx - pos; 387 if (trans_len > SPCOM_TRANLEN_MAX - n_tx) 388 trans_len = SPCOM_TRANLEN_MAX - n_tx; 389 390 i = 0; 391 list_for_each_entry(t, &m->transfers, transfer_list) { 392 if (t->tx_buf) { 393 memcpy(local_buf + i, t->tx_buf, t->len); 394 i += t->len; 395 } 396 } 397 398 if (pos > 0) { 399 addr = fsl_espi_cmd2addr(local_buf); 400 addr += pos; 401 fsl_espi_addr2cmd(addr, local_buf); 402 } 403 404 espi_trans->n_tx = n_tx; 405 espi_trans->n_rx = trans_len; 406 espi_trans->len = trans_len + n_tx; 407 espi_trans->tx_buf = local_buf; 408 espi_trans->rx_buf = local_buf + n_tx; 409 fsl_espi_do_trans(m, espi_trans); 410 411 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len); 412 413 if (loop > 0) 414 espi_trans->actual_length += espi_trans->len - n_tx; 415 else 416 espi_trans->actual_length += espi_trans->len; 417 } 418 419 kfree(local_buf); 420 } 421 422 static void fsl_espi_do_one_msg(struct spi_message *m) 423 { 424 struct spi_transfer *t; 425 u8 *rx_buf = NULL; 426 unsigned int n_tx = 0; 427 unsigned int n_rx = 0; 428 struct fsl_espi_transfer espi_trans; 429 430 list_for_each_entry(t, &m->transfers, transfer_list) { 431 if (t->tx_buf) 432 n_tx += t->len; 433 if (t->rx_buf) { 434 n_rx += t->len; 435 rx_buf = t->rx_buf; 436 } 437 } 438 439 espi_trans.n_tx = n_tx; 440 espi_trans.n_rx = n_rx; 441 espi_trans.len = n_tx + n_rx; 442 espi_trans.actual_length = 0; 443 espi_trans.status = 0; 444 445 if (!rx_buf) 446 fsl_espi_cmd_trans(m, &espi_trans, NULL); 447 else 448 fsl_espi_rw_trans(m, &espi_trans, rx_buf); 449 450 m->actual_length = espi_trans.actual_length; 451 m->status = espi_trans.status; 452 m->complete(m->context); 453 } 454 455 static int fsl_espi_setup(struct spi_device *spi) 456 { 457 struct mpc8xxx_spi *mpc8xxx_spi; 458 struct fsl_espi_reg *reg_base; 459 int retval; 460 u32 hw_mode; 461 u32 loop_mode; 462 struct spi_mpc8xxx_cs *cs = spi->controller_state; 463 464 if (!spi->max_speed_hz) 465 return -EINVAL; 466 467 if (!cs) { 468 cs = kzalloc(sizeof *cs, GFP_KERNEL); 469 if (!cs) 470 return -ENOMEM; 471 spi->controller_state = cs; 472 } 473 474 mpc8xxx_spi = spi_master_get_devdata(spi->master); 475 reg_base = mpc8xxx_spi->reg_base; 476 477 hw_mode = cs->hw_mode; /* Save original settings */ 478 cs->hw_mode = mpc8xxx_spi_read_reg( 479 ®_base->csmode[spi->chip_select]); 480 /* mask out bits we are going to set */ 481 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH 482 | CSMODE_REV); 483 484 if (spi->mode & SPI_CPHA) 485 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; 486 if (spi->mode & SPI_CPOL) 487 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; 488 if (!(spi->mode & SPI_LSB_FIRST)) 489 cs->hw_mode |= CSMODE_REV; 490 491 /* Handle the loop mode */ 492 loop_mode = mpc8xxx_spi_read_reg(®_base->mode); 493 loop_mode &= ~SPMODE_LOOP; 494 if (spi->mode & SPI_LOOP) 495 loop_mode |= SPMODE_LOOP; 496 mpc8xxx_spi_write_reg(®_base->mode, loop_mode); 497 498 retval = fsl_espi_setup_transfer(spi, NULL); 499 if (retval < 0) { 500 cs->hw_mode = hw_mode; /* Restore settings */ 501 return retval; 502 } 503 return 0; 504 } 505 506 void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 507 { 508 struct fsl_espi_reg *reg_base = mspi->reg_base; 509 510 /* We need handle RX first */ 511 if (events & SPIE_NE) { 512 u32 rx_data, tmp; 513 u8 rx_data_8; 514 515 /* Spin until RX is done */ 516 while (SPIE_RXCNT(events) < min(4, mspi->len)) { 517 cpu_relax(); 518 events = mpc8xxx_spi_read_reg(®_base->event); 519 } 520 521 if (mspi->len >= 4) { 522 rx_data = mpc8xxx_spi_read_reg(®_base->receive); 523 } else { 524 tmp = mspi->len; 525 rx_data = 0; 526 while (tmp--) { 527 rx_data_8 = in_8((u8 *)®_base->receive); 528 rx_data |= (rx_data_8 << (tmp * 8)); 529 } 530 531 rx_data <<= (4 - mspi->len) * 8; 532 } 533 534 mspi->len -= 4; 535 536 if (mspi->rx) 537 mspi->get_rx(rx_data, mspi); 538 } 539 540 if (!(events & SPIE_NF)) { 541 int ret; 542 543 /* spin until TX is done */ 544 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg( 545 ®_base->event)) & SPIE_NF) == 0, 1000, 0); 546 if (!ret) { 547 dev_err(mspi->dev, "tired waiting for SPIE_NF\n"); 548 return; 549 } 550 } 551 552 /* Clear the events */ 553 mpc8xxx_spi_write_reg(®_base->event, events); 554 555 mspi->count -= 1; 556 if (mspi->count) { 557 u32 word = mspi->get_tx(mspi); 558 559 mpc8xxx_spi_write_reg(®_base->transmit, word); 560 } else { 561 complete(&mspi->done); 562 } 563 } 564 565 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data) 566 { 567 struct mpc8xxx_spi *mspi = context_data; 568 struct fsl_espi_reg *reg_base = mspi->reg_base; 569 irqreturn_t ret = IRQ_NONE; 570 u32 events; 571 572 /* Get interrupt events(tx/rx) */ 573 events = mpc8xxx_spi_read_reg(®_base->event); 574 if (events) 575 ret = IRQ_HANDLED; 576 577 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events); 578 579 fsl_espi_cpu_irq(mspi, events); 580 581 return ret; 582 } 583 584 static void fsl_espi_remove(struct mpc8xxx_spi *mspi) 585 { 586 iounmap(mspi->reg_base); 587 } 588 589 static struct spi_master * __devinit fsl_espi_probe(struct device *dev, 590 struct resource *mem, unsigned int irq) 591 { 592 struct fsl_spi_platform_data *pdata = dev->platform_data; 593 struct spi_master *master; 594 struct mpc8xxx_spi *mpc8xxx_spi; 595 struct fsl_espi_reg *reg_base; 596 u32 regval; 597 int i, ret = 0; 598 599 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); 600 if (!master) { 601 ret = -ENOMEM; 602 goto err; 603 } 604 605 dev_set_drvdata(dev, master); 606 607 ret = mpc8xxx_spi_probe(dev, mem, irq); 608 if (ret) 609 goto err_probe; 610 611 master->setup = fsl_espi_setup; 612 613 mpc8xxx_spi = spi_master_get_devdata(master); 614 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg; 615 mpc8xxx_spi->spi_remove = fsl_espi_remove; 616 617 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); 618 if (!mpc8xxx_spi->reg_base) { 619 ret = -ENOMEM; 620 goto err_probe; 621 } 622 623 reg_base = mpc8xxx_spi->reg_base; 624 625 /* Register for SPI Interrupt */ 626 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq, 627 0, "fsl_espi", mpc8xxx_spi); 628 if (ret) 629 goto free_irq; 630 631 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { 632 mpc8xxx_spi->rx_shift = 16; 633 mpc8xxx_spi->tx_shift = 24; 634 } 635 636 /* SPI controller initializations */ 637 mpc8xxx_spi_write_reg(®_base->mode, 0); 638 mpc8xxx_spi_write_reg(®_base->mask, 0); 639 mpc8xxx_spi_write_reg(®_base->command, 0); 640 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); 641 642 /* Init eSPI CS mode register */ 643 for (i = 0; i < pdata->max_chipselect; i++) 644 mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL); 645 646 /* Enable SPI interface */ 647 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; 648 649 mpc8xxx_spi_write_reg(®_base->mode, regval); 650 651 ret = spi_register_master(master); 652 if (ret < 0) 653 goto unreg_master; 654 655 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq); 656 657 return master; 658 659 unreg_master: 660 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); 661 free_irq: 662 iounmap(mpc8xxx_spi->reg_base); 663 err_probe: 664 spi_master_put(master); 665 err: 666 return ERR_PTR(ret); 667 } 668 669 static int of_fsl_espi_get_chipselects(struct device *dev) 670 { 671 struct device_node *np = dev->of_node; 672 struct fsl_spi_platform_data *pdata = dev->platform_data; 673 const u32 *prop; 674 int len; 675 676 prop = of_get_property(np, "fsl,espi-num-chipselects", &len); 677 if (!prop || len < sizeof(*prop)) { 678 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); 679 return -EINVAL; 680 } 681 682 pdata->max_chipselect = *prop; 683 pdata->cs_control = NULL; 684 685 return 0; 686 } 687 688 static int __devinit of_fsl_espi_probe(struct platform_device *ofdev) 689 { 690 struct device *dev = &ofdev->dev; 691 struct device_node *np = ofdev->dev.of_node; 692 struct spi_master *master; 693 struct resource mem; 694 struct resource irq; 695 int ret = -ENOMEM; 696 697 ret = of_mpc8xxx_spi_probe(ofdev); 698 if (ret) 699 return ret; 700 701 ret = of_fsl_espi_get_chipselects(dev); 702 if (ret) 703 goto err; 704 705 ret = of_address_to_resource(np, 0, &mem); 706 if (ret) 707 goto err; 708 709 ret = of_irq_to_resource(np, 0, &irq); 710 if (!ret) { 711 ret = -EINVAL; 712 goto err; 713 } 714 715 master = fsl_espi_probe(dev, &mem, irq.start); 716 if (IS_ERR(master)) { 717 ret = PTR_ERR(master); 718 goto err; 719 } 720 721 return 0; 722 723 err: 724 return ret; 725 } 726 727 static int __devexit of_fsl_espi_remove(struct platform_device *dev) 728 { 729 return mpc8xxx_spi_remove(&dev->dev); 730 } 731 732 static const struct of_device_id of_fsl_espi_match[] = { 733 { .compatible = "fsl,mpc8536-espi" }, 734 {} 735 }; 736 MODULE_DEVICE_TABLE(of, of_fsl_espi_match); 737 738 static struct platform_driver fsl_espi_driver = { 739 .driver = { 740 .name = "fsl_espi", 741 .owner = THIS_MODULE, 742 .of_match_table = of_fsl_espi_match, 743 }, 744 .probe = of_fsl_espi_probe, 745 .remove = __devexit_p(of_fsl_espi_remove), 746 }; 747 module_platform_driver(fsl_espi_driver); 748 749 MODULE_AUTHOR("Mingkai Hu"); 750 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver"); 751 MODULE_LICENSE("GPL"); 752