1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright 2013 Freescale Semiconductor, Inc. 4 // Copyright 2020 NXP 5 // 6 // Freescale DSPI driver 7 // This file contains a driver for the Freescale DSPI 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/spi/spi.h> 20 #include <linux/spi/spi-fsl-dspi.h> 21 22 #define DRIVER_NAME "fsl-dspi" 23 24 #define SPI_MCR 0x00 25 #define SPI_MCR_MASTER BIT(31) 26 #define SPI_MCR_PCSIS(x) ((x) << 16) 27 #define SPI_MCR_CLR_TXF BIT(11) 28 #define SPI_MCR_CLR_RXF BIT(10) 29 #define SPI_MCR_XSPI BIT(3) 30 #define SPI_MCR_DIS_TXF BIT(13) 31 #define SPI_MCR_DIS_RXF BIT(12) 32 #define SPI_MCR_HALT BIT(0) 33 34 #define SPI_TCR 0x08 35 #define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16) 36 37 #define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4)) 38 #define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27)) 39 #define SPI_CTAR_CPOL BIT(26) 40 #define SPI_CTAR_CPHA BIT(25) 41 #define SPI_CTAR_LSBFE BIT(24) 42 #define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22)) 43 #define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20)) 44 #define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18)) 45 #define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16)) 46 #define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12)) 47 #define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8)) 48 #define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4)) 49 #define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0)) 50 #define SPI_CTAR_SCALE_BITS 0xf 51 52 #define SPI_CTAR0_SLAVE 0x0c 53 54 #define SPI_SR 0x2c 55 #define SPI_SR_TCFQF BIT(31) 56 #define SPI_SR_TFUF BIT(27) 57 #define SPI_SR_TFFF BIT(25) 58 #define SPI_SR_CMDTCF BIT(23) 59 #define SPI_SR_SPEF BIT(21) 60 #define SPI_SR_RFOF BIT(19) 61 #define SPI_SR_TFIWF BIT(18) 62 #define SPI_SR_RFDF BIT(17) 63 #define SPI_SR_CMDFFF BIT(16) 64 #define SPI_SR_CLEAR (SPI_SR_TCFQF | \ 65 SPI_SR_TFUF | SPI_SR_TFFF | \ 66 SPI_SR_CMDTCF | SPI_SR_SPEF | \ 67 SPI_SR_RFOF | SPI_SR_TFIWF | \ 68 SPI_SR_RFDF | SPI_SR_CMDFFF) 69 70 #define SPI_RSER_TFFFE BIT(25) 71 #define SPI_RSER_TFFFD BIT(24) 72 #define SPI_RSER_RFDFE BIT(17) 73 #define SPI_RSER_RFDFD BIT(16) 74 75 #define SPI_RSER 0x30 76 #define SPI_RSER_TCFQE BIT(31) 77 #define SPI_RSER_CMDTCFE BIT(23) 78 79 #define SPI_PUSHR 0x34 80 #define SPI_PUSHR_CMD_CONT BIT(15) 81 #define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12))) 82 #define SPI_PUSHR_CMD_EOQ BIT(11) 83 #define SPI_PUSHR_CMD_CTCNT BIT(10) 84 #define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0)) 85 86 #define SPI_PUSHR_SLAVE 0x34 87 88 #define SPI_POPR 0x38 89 90 #define SPI_TXFR0 0x3c 91 #define SPI_TXFR1 0x40 92 #define SPI_TXFR2 0x44 93 #define SPI_TXFR3 0x48 94 #define SPI_RXFR0 0x7c 95 #define SPI_RXFR1 0x80 96 #define SPI_RXFR2 0x84 97 #define SPI_RXFR3 0x88 98 99 #define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4)) 100 #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16) 101 #define SPI_CTARE_DTCP(x) ((x) & 0x7ff) 102 103 #define SPI_SREX 0x13c 104 105 #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) 106 #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) 107 108 #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) 109 110 struct chip_data { 111 u32 ctar_val; 112 }; 113 114 enum dspi_trans_mode { 115 DSPI_XSPI_MODE, 116 DSPI_DMA_MODE, 117 }; 118 119 struct fsl_dspi_devtype_data { 120 enum dspi_trans_mode trans_mode; 121 u8 max_clock_factor; 122 int fifo_size; 123 }; 124 125 enum { 126 LS1021A, 127 LS1012A, 128 LS1028A, 129 LS1043A, 130 LS1046A, 131 LS2080A, 132 LS2085A, 133 LX2160A, 134 MCF5441X, 135 VF610, 136 }; 137 138 static const struct fsl_dspi_devtype_data devtype_data[] = { 139 [VF610] = { 140 .trans_mode = DSPI_DMA_MODE, 141 .max_clock_factor = 2, 142 .fifo_size = 4, 143 }, 144 [LS1021A] = { 145 /* Has A-011218 DMA erratum */ 146 .trans_mode = DSPI_XSPI_MODE, 147 .max_clock_factor = 8, 148 .fifo_size = 4, 149 }, 150 [LS1012A] = { 151 /* Has A-011218 DMA erratum */ 152 .trans_mode = DSPI_XSPI_MODE, 153 .max_clock_factor = 8, 154 .fifo_size = 16, 155 }, 156 [LS1028A] = { 157 .trans_mode = DSPI_XSPI_MODE, 158 .max_clock_factor = 8, 159 .fifo_size = 4, 160 }, 161 [LS1043A] = { 162 /* Has A-011218 DMA erratum */ 163 .trans_mode = DSPI_XSPI_MODE, 164 .max_clock_factor = 8, 165 .fifo_size = 16, 166 }, 167 [LS1046A] = { 168 /* Has A-011218 DMA erratum */ 169 .trans_mode = DSPI_XSPI_MODE, 170 .max_clock_factor = 8, 171 .fifo_size = 16, 172 }, 173 [LS2080A] = { 174 .trans_mode = DSPI_XSPI_MODE, 175 .max_clock_factor = 8, 176 .fifo_size = 4, 177 }, 178 [LS2085A] = { 179 .trans_mode = DSPI_XSPI_MODE, 180 .max_clock_factor = 8, 181 .fifo_size = 4, 182 }, 183 [LX2160A] = { 184 .trans_mode = DSPI_XSPI_MODE, 185 .max_clock_factor = 8, 186 .fifo_size = 4, 187 }, 188 [MCF5441X] = { 189 .trans_mode = DSPI_DMA_MODE, 190 .max_clock_factor = 8, 191 .fifo_size = 16, 192 }, 193 }; 194 195 struct fsl_dspi_dma { 196 u32 *tx_dma_buf; 197 struct dma_chan *chan_tx; 198 dma_addr_t tx_dma_phys; 199 struct completion cmd_tx_complete; 200 struct dma_async_tx_descriptor *tx_desc; 201 202 u32 *rx_dma_buf; 203 struct dma_chan *chan_rx; 204 dma_addr_t rx_dma_phys; 205 struct completion cmd_rx_complete; 206 struct dma_async_tx_descriptor *rx_desc; 207 }; 208 209 struct fsl_dspi { 210 struct spi_controller *ctlr; 211 struct platform_device *pdev; 212 213 struct regmap *regmap; 214 struct regmap *regmap_pushr; 215 int irq; 216 struct clk *clk; 217 218 struct spi_transfer *cur_transfer; 219 struct spi_message *cur_msg; 220 struct chip_data *cur_chip; 221 size_t progress; 222 size_t len; 223 const void *tx; 224 void *rx; 225 u16 tx_cmd; 226 const struct fsl_dspi_devtype_data *devtype_data; 227 228 struct completion xfer_done; 229 230 struct fsl_dspi_dma *dma; 231 232 int oper_word_size; 233 int oper_bits_per_word; 234 235 int words_in_flight; 236 237 /* 238 * Offsets for CMD and TXDATA within SPI_PUSHR when accessed 239 * individually (in XSPI mode) 240 */ 241 int pushr_cmd; 242 int pushr_tx; 243 244 void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata); 245 void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata); 246 }; 247 248 static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) 249 { 250 switch (dspi->oper_word_size) { 251 case 1: 252 *txdata = *(u8 *)dspi->tx; 253 break; 254 case 2: 255 *txdata = *(u16 *)dspi->tx; 256 break; 257 case 4: 258 *txdata = *(u32 *)dspi->tx; 259 break; 260 } 261 dspi->tx += dspi->oper_word_size; 262 } 263 264 static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) 265 { 266 switch (dspi->oper_word_size) { 267 case 1: 268 *(u8 *)dspi->rx = rxdata; 269 break; 270 case 2: 271 *(u16 *)dspi->rx = rxdata; 272 break; 273 case 4: 274 *(u32 *)dspi->rx = rxdata; 275 break; 276 } 277 dspi->rx += dspi->oper_word_size; 278 } 279 280 static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) 281 { 282 *txdata = cpu_to_be32(*(u32 *)dspi->tx); 283 dspi->tx += sizeof(u32); 284 } 285 286 static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) 287 { 288 *(u32 *)dspi->rx = be32_to_cpu(rxdata); 289 dspi->rx += sizeof(u32); 290 } 291 292 static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) 293 { 294 *txdata = cpu_to_be16(*(u16 *)dspi->tx); 295 dspi->tx += sizeof(u16); 296 } 297 298 static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) 299 { 300 *(u16 *)dspi->rx = be16_to_cpu(rxdata); 301 dspi->rx += sizeof(u16); 302 } 303 304 static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) 305 { 306 u16 hi = *(u16 *)dspi->tx; 307 u16 lo = *(u16 *)(dspi->tx + 2); 308 309 *txdata = (u32)hi << 16 | lo; 310 dspi->tx += sizeof(u32); 311 } 312 313 static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) 314 { 315 u16 hi = rxdata & 0xffff; 316 u16 lo = rxdata >> 16; 317 318 *(u16 *)dspi->rx = lo; 319 *(u16 *)(dspi->rx + 2) = hi; 320 dspi->rx += sizeof(u32); 321 } 322 323 /* 324 * Pop one word from the TX buffer for pushing into the 325 * PUSHR register (TX FIFO) 326 */ 327 static u32 dspi_pop_tx(struct fsl_dspi *dspi) 328 { 329 u32 txdata = 0; 330 331 if (dspi->tx) 332 dspi->host_to_dev(dspi, &txdata); 333 dspi->len -= dspi->oper_word_size; 334 return txdata; 335 } 336 337 /* Prepare one TX FIFO entry (txdata plus cmd) */ 338 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) 339 { 340 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi); 341 342 if (spi_controller_is_slave(dspi->ctlr)) 343 return data; 344 345 if (dspi->len > 0) 346 cmd |= SPI_PUSHR_CMD_CONT; 347 return cmd << 16 | data; 348 } 349 350 /* Push one word to the RX buffer from the POPR register (RX FIFO) */ 351 static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) 352 { 353 if (!dspi->rx) 354 return; 355 dspi->dev_to_host(dspi, rxdata); 356 } 357 358 static void dspi_tx_dma_callback(void *arg) 359 { 360 struct fsl_dspi *dspi = arg; 361 struct fsl_dspi_dma *dma = dspi->dma; 362 363 complete(&dma->cmd_tx_complete); 364 } 365 366 static void dspi_rx_dma_callback(void *arg) 367 { 368 struct fsl_dspi *dspi = arg; 369 struct fsl_dspi_dma *dma = dspi->dma; 370 int i; 371 372 if (dspi->rx) { 373 for (i = 0; i < dspi->words_in_flight; i++) 374 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]); 375 } 376 377 complete(&dma->cmd_rx_complete); 378 } 379 380 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) 381 { 382 struct device *dev = &dspi->pdev->dev; 383 struct fsl_dspi_dma *dma = dspi->dma; 384 int time_left; 385 int i; 386 387 for (i = 0; i < dspi->words_in_flight; i++) 388 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi); 389 390 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx, 391 dma->tx_dma_phys, 392 dspi->words_in_flight * 393 DMA_SLAVE_BUSWIDTH_4_BYTES, 394 DMA_MEM_TO_DEV, 395 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 396 if (!dma->tx_desc) { 397 dev_err(dev, "Not able to get desc for DMA xfer\n"); 398 return -EIO; 399 } 400 401 dma->tx_desc->callback = dspi_tx_dma_callback; 402 dma->tx_desc->callback_param = dspi; 403 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) { 404 dev_err(dev, "DMA submit failed\n"); 405 return -EINVAL; 406 } 407 408 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx, 409 dma->rx_dma_phys, 410 dspi->words_in_flight * 411 DMA_SLAVE_BUSWIDTH_4_BYTES, 412 DMA_DEV_TO_MEM, 413 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 414 if (!dma->rx_desc) { 415 dev_err(dev, "Not able to get desc for DMA xfer\n"); 416 return -EIO; 417 } 418 419 dma->rx_desc->callback = dspi_rx_dma_callback; 420 dma->rx_desc->callback_param = dspi; 421 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) { 422 dev_err(dev, "DMA submit failed\n"); 423 return -EINVAL; 424 } 425 426 reinit_completion(&dspi->dma->cmd_rx_complete); 427 reinit_completion(&dspi->dma->cmd_tx_complete); 428 429 dma_async_issue_pending(dma->chan_rx); 430 dma_async_issue_pending(dma->chan_tx); 431 432 if (spi_controller_is_slave(dspi->ctlr)) { 433 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete); 434 return 0; 435 } 436 437 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, 438 DMA_COMPLETION_TIMEOUT); 439 if (time_left == 0) { 440 dev_err(dev, "DMA tx timeout\n"); 441 dmaengine_terminate_all(dma->chan_tx); 442 dmaengine_terminate_all(dma->chan_rx); 443 return -ETIMEDOUT; 444 } 445 446 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete, 447 DMA_COMPLETION_TIMEOUT); 448 if (time_left == 0) { 449 dev_err(dev, "DMA rx timeout\n"); 450 dmaengine_terminate_all(dma->chan_tx); 451 dmaengine_terminate_all(dma->chan_rx); 452 return -ETIMEDOUT; 453 } 454 455 return 0; 456 } 457 458 static void dspi_setup_accel(struct fsl_dspi *dspi); 459 460 static int dspi_dma_xfer(struct fsl_dspi *dspi) 461 { 462 struct spi_message *message = dspi->cur_msg; 463 struct device *dev = &dspi->pdev->dev; 464 int ret = 0; 465 466 /* 467 * dspi->len gets decremented by dspi_pop_tx_pushr in 468 * dspi_next_xfer_dma_submit 469 */ 470 while (dspi->len) { 471 /* Figure out operational bits-per-word for this chunk */ 472 dspi_setup_accel(dspi); 473 474 dspi->words_in_flight = dspi->len / dspi->oper_word_size; 475 if (dspi->words_in_flight > dspi->devtype_data->fifo_size) 476 dspi->words_in_flight = dspi->devtype_data->fifo_size; 477 478 message->actual_length += dspi->words_in_flight * 479 dspi->oper_word_size; 480 481 ret = dspi_next_xfer_dma_submit(dspi); 482 if (ret) { 483 dev_err(dev, "DMA transfer failed\n"); 484 break; 485 } 486 } 487 488 return ret; 489 } 490 491 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) 492 { 493 int dma_bufsize = dspi->devtype_data->fifo_size * 2; 494 struct device *dev = &dspi->pdev->dev; 495 struct dma_slave_config cfg; 496 struct fsl_dspi_dma *dma; 497 int ret; 498 499 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 500 if (!dma) 501 return -ENOMEM; 502 503 dma->chan_rx = dma_request_chan(dev, "rx"); 504 if (IS_ERR(dma->chan_rx)) { 505 dev_err(dev, "rx dma channel not available\n"); 506 ret = PTR_ERR(dma->chan_rx); 507 return ret; 508 } 509 510 dma->chan_tx = dma_request_chan(dev, "tx"); 511 if (IS_ERR(dma->chan_tx)) { 512 dev_err(dev, "tx dma channel not available\n"); 513 ret = PTR_ERR(dma->chan_tx); 514 goto err_tx_channel; 515 } 516 517 dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev, 518 dma_bufsize, &dma->tx_dma_phys, 519 GFP_KERNEL); 520 if (!dma->tx_dma_buf) { 521 ret = -ENOMEM; 522 goto err_tx_dma_buf; 523 } 524 525 dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev, 526 dma_bufsize, &dma->rx_dma_phys, 527 GFP_KERNEL); 528 if (!dma->rx_dma_buf) { 529 ret = -ENOMEM; 530 goto err_rx_dma_buf; 531 } 532 533 memset(&cfg, 0, sizeof(cfg)); 534 cfg.src_addr = phy_addr + SPI_POPR; 535 cfg.dst_addr = phy_addr + SPI_PUSHR; 536 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 537 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 538 cfg.src_maxburst = 1; 539 cfg.dst_maxburst = 1; 540 541 cfg.direction = DMA_DEV_TO_MEM; 542 ret = dmaengine_slave_config(dma->chan_rx, &cfg); 543 if (ret) { 544 dev_err(dev, "can't configure rx dma channel\n"); 545 ret = -EINVAL; 546 goto err_slave_config; 547 } 548 549 cfg.direction = DMA_MEM_TO_DEV; 550 ret = dmaengine_slave_config(dma->chan_tx, &cfg); 551 if (ret) { 552 dev_err(dev, "can't configure tx dma channel\n"); 553 ret = -EINVAL; 554 goto err_slave_config; 555 } 556 557 dspi->dma = dma; 558 init_completion(&dma->cmd_tx_complete); 559 init_completion(&dma->cmd_rx_complete); 560 561 return 0; 562 563 err_slave_config: 564 dma_free_coherent(dma->chan_rx->device->dev, 565 dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys); 566 err_rx_dma_buf: 567 dma_free_coherent(dma->chan_tx->device->dev, 568 dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys); 569 err_tx_dma_buf: 570 dma_release_channel(dma->chan_tx); 571 err_tx_channel: 572 dma_release_channel(dma->chan_rx); 573 574 devm_kfree(dev, dma); 575 dspi->dma = NULL; 576 577 return ret; 578 } 579 580 static void dspi_release_dma(struct fsl_dspi *dspi) 581 { 582 int dma_bufsize = dspi->devtype_data->fifo_size * 2; 583 struct fsl_dspi_dma *dma = dspi->dma; 584 585 if (!dma) 586 return; 587 588 if (dma->chan_tx) { 589 dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize, 590 dma->tx_dma_buf, dma->tx_dma_phys); 591 dma_release_channel(dma->chan_tx); 592 } 593 594 if (dma->chan_rx) { 595 dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize, 596 dma->rx_dma_buf, dma->rx_dma_phys); 597 dma_release_channel(dma->chan_rx); 598 } 599 } 600 601 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, 602 unsigned long clkrate) 603 { 604 /* Valid baud rate pre-scaler values */ 605 int pbr_tbl[4] = {2, 3, 5, 7}; 606 int brs[16] = { 2, 4, 6, 8, 607 16, 32, 64, 128, 608 256, 512, 1024, 2048, 609 4096, 8192, 16384, 32768 }; 610 int scale_needed, scale, minscale = INT_MAX; 611 int i, j; 612 613 scale_needed = clkrate / speed_hz; 614 if (clkrate % speed_hz) 615 scale_needed++; 616 617 for (i = 0; i < ARRAY_SIZE(brs); i++) 618 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { 619 scale = brs[i] * pbr_tbl[j]; 620 if (scale >= scale_needed) { 621 if (scale < minscale) { 622 minscale = scale; 623 *br = i; 624 *pbr = j; 625 } 626 break; 627 } 628 } 629 630 if (minscale == INT_MAX) { 631 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", 632 speed_hz, clkrate); 633 *pbr = ARRAY_SIZE(pbr_tbl) - 1; 634 *br = ARRAY_SIZE(brs) - 1; 635 } 636 } 637 638 static void ns_delay_scale(char *psc, char *sc, int delay_ns, 639 unsigned long clkrate) 640 { 641 int scale_needed, scale, minscale = INT_MAX; 642 int pscale_tbl[4] = {1, 3, 5, 7}; 643 u32 remainder; 644 int i, j; 645 646 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, 647 &remainder); 648 if (remainder) 649 scale_needed++; 650 651 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) 652 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { 653 scale = pscale_tbl[i] * (2 << j); 654 if (scale >= scale_needed) { 655 if (scale < minscale) { 656 minscale = scale; 657 *psc = i; 658 *sc = j; 659 } 660 break; 661 } 662 } 663 664 if (minscale == INT_MAX) { 665 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", 666 delay_ns, clkrate); 667 *psc = ARRAY_SIZE(pscale_tbl) - 1; 668 *sc = SPI_CTAR_SCALE_BITS; 669 } 670 } 671 672 static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd) 673 { 674 /* 675 * The only time when the PCS doesn't need continuation after this word 676 * is when it's last. We need to look ahead, because we actually call 677 * dspi_pop_tx (the function that decrements dspi->len) _after_ 678 * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One 679 * word is enough. If there's more to transmit than that, 680 * dspi_xspi_write will know to split the FIFO writes in 2, and 681 * generate a new PUSHR command with the final word that will have PCS 682 * deasserted (not continued) here. 683 */ 684 if (dspi->len > dspi->oper_word_size) 685 cmd |= SPI_PUSHR_CMD_CONT; 686 regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd); 687 } 688 689 static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) 690 { 691 regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata); 692 } 693 694 static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words) 695 { 696 int num_bytes = num_words * dspi->oper_word_size; 697 u16 tx_cmd = dspi->tx_cmd; 698 699 /* 700 * If the PCS needs to de-assert (i.e. we're at the end of the buffer 701 * and cs_change does not want the PCS to stay on), then we need a new 702 * PUSHR command, since this one (for the body of the buffer) 703 * necessarily has the CONT bit set. 704 * So send one word less during this go, to force a split and a command 705 * with a single word next time, when CONT will be unset. 706 */ 707 if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len) 708 tx_cmd |= SPI_PUSHR_CMD_EOQ; 709 710 /* Update CTARE */ 711 regmap_write(dspi->regmap, SPI_CTARE(0), 712 SPI_FRAME_EBITS(dspi->oper_bits_per_word) | 713 SPI_CTARE_DTCP(num_words)); 714 715 /* 716 * Write the CMD FIFO entry first, and then the two 717 * corresponding TX FIFO entries (or one...). 718 */ 719 dspi_pushr_cmd_write(dspi, tx_cmd); 720 721 /* Fill TX FIFO with as many transfers as possible */ 722 while (num_words--) { 723 u32 data = dspi_pop_tx(dspi); 724 725 dspi_pushr_txdata_write(dspi, data & 0xFFFF); 726 if (dspi->oper_bits_per_word > 16) 727 dspi_pushr_txdata_write(dspi, data >> 16); 728 } 729 } 730 731 static u32 dspi_popr_read(struct fsl_dspi *dspi) 732 { 733 u32 rxdata = 0; 734 735 regmap_read(dspi->regmap, SPI_POPR, &rxdata); 736 return rxdata; 737 } 738 739 static void dspi_fifo_read(struct fsl_dspi *dspi) 740 { 741 int num_fifo_entries = dspi->words_in_flight; 742 743 /* Read one FIFO entry and push to rx buffer */ 744 while (num_fifo_entries--) 745 dspi_push_rx(dspi, dspi_popr_read(dspi)); 746 } 747 748 static void dspi_setup_accel(struct fsl_dspi *dspi) 749 { 750 struct spi_transfer *xfer = dspi->cur_transfer; 751 bool odd = !!(dspi->len & 1); 752 753 /* No accel for frames not multiple of 8 bits at the moment */ 754 if (xfer->bits_per_word % 8) 755 goto no_accel; 756 757 if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) { 758 dspi->oper_bits_per_word = 16; 759 } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) { 760 dspi->oper_bits_per_word = 8; 761 } else { 762 /* Start off with maximum supported by hardware */ 763 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) 764 dspi->oper_bits_per_word = 32; 765 else 766 dspi->oper_bits_per_word = 16; 767 768 /* 769 * And go down only if the buffer can't be sent with 770 * words this big 771 */ 772 do { 773 if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8)) 774 break; 775 776 dspi->oper_bits_per_word /= 2; 777 } while (dspi->oper_bits_per_word > 8); 778 } 779 780 if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) { 781 dspi->dev_to_host = dspi_8on32_dev_to_host; 782 dspi->host_to_dev = dspi_8on32_host_to_dev; 783 } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) { 784 dspi->dev_to_host = dspi_8on16_dev_to_host; 785 dspi->host_to_dev = dspi_8on16_host_to_dev; 786 } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) { 787 dspi->dev_to_host = dspi_16on32_dev_to_host; 788 dspi->host_to_dev = dspi_16on32_host_to_dev; 789 } else { 790 no_accel: 791 dspi->dev_to_host = dspi_native_dev_to_host; 792 dspi->host_to_dev = dspi_native_host_to_dev; 793 dspi->oper_bits_per_word = xfer->bits_per_word; 794 } 795 796 dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8); 797 798 /* 799 * Update CTAR here (code is common for XSPI and DMA modes). 800 * We will update CTARE in the portion specific to XSPI, when we 801 * also know the preload value (DTCP). 802 */ 803 regmap_write(dspi->regmap, SPI_CTAR(0), 804 dspi->cur_chip->ctar_val | 805 SPI_FRAME_BITS(dspi->oper_bits_per_word)); 806 } 807 808 static void dspi_fifo_write(struct fsl_dspi *dspi) 809 { 810 int num_fifo_entries = dspi->devtype_data->fifo_size; 811 struct spi_transfer *xfer = dspi->cur_transfer; 812 struct spi_message *msg = dspi->cur_msg; 813 int num_words, num_bytes; 814 815 dspi_setup_accel(dspi); 816 817 /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ 818 if (dspi->oper_word_size == 4) 819 num_fifo_entries /= 2; 820 821 /* 822 * Integer division intentionally trims off odd (or non-multiple of 4) 823 * numbers of bytes at the end of the buffer, which will be sent next 824 * time using a smaller oper_word_size. 825 */ 826 num_words = dspi->len / dspi->oper_word_size; 827 if (num_words > num_fifo_entries) 828 num_words = num_fifo_entries; 829 830 /* Update total number of bytes that were transferred */ 831 num_bytes = num_words * dspi->oper_word_size; 832 msg->actual_length += num_bytes; 833 dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8); 834 835 /* 836 * Update shared variable for use in the next interrupt (both in 837 * dspi_fifo_read and in dspi_fifo_write). 838 */ 839 dspi->words_in_flight = num_words; 840 841 spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq); 842 843 dspi_xspi_fifo_write(dspi, num_words); 844 /* 845 * Everything after this point is in a potential race with the next 846 * interrupt, so we must never use dspi->words_in_flight again since it 847 * might already be modified by the next dspi_fifo_write. 848 */ 849 850 spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer, 851 dspi->progress, !dspi->irq); 852 } 853 854 static int dspi_rxtx(struct fsl_dspi *dspi) 855 { 856 dspi_fifo_read(dspi); 857 858 if (!dspi->len) 859 /* Success! */ 860 return 0; 861 862 dspi_fifo_write(dspi); 863 864 return -EINPROGRESS; 865 } 866 867 static int dspi_poll(struct fsl_dspi *dspi) 868 { 869 int tries = 1000; 870 u32 spi_sr; 871 872 do { 873 regmap_read(dspi->regmap, SPI_SR, &spi_sr); 874 regmap_write(dspi->regmap, SPI_SR, spi_sr); 875 876 if (spi_sr & SPI_SR_CMDTCF) 877 break; 878 } while (--tries); 879 880 if (!tries) 881 return -ETIMEDOUT; 882 883 return dspi_rxtx(dspi); 884 } 885 886 static irqreturn_t dspi_interrupt(int irq, void *dev_id) 887 { 888 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; 889 u32 spi_sr; 890 891 regmap_read(dspi->regmap, SPI_SR, &spi_sr); 892 regmap_write(dspi->regmap, SPI_SR, spi_sr); 893 894 if (!(spi_sr & SPI_SR_CMDTCF)) 895 return IRQ_NONE; 896 897 if (dspi_rxtx(dspi) == 0) 898 complete(&dspi->xfer_done); 899 900 return IRQ_HANDLED; 901 } 902 903 static int dspi_transfer_one_message(struct spi_controller *ctlr, 904 struct spi_message *message) 905 { 906 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); 907 struct spi_device *spi = message->spi; 908 struct spi_transfer *transfer; 909 int status = 0; 910 911 message->actual_length = 0; 912 913 list_for_each_entry(transfer, &message->transfers, transfer_list) { 914 dspi->cur_transfer = transfer; 915 dspi->cur_msg = message; 916 dspi->cur_chip = spi_get_ctldata(spi); 917 /* Prepare command word for CMD FIFO */ 918 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) | 919 SPI_PUSHR_CMD_PCS(spi->chip_select); 920 if (list_is_last(&dspi->cur_transfer->transfer_list, 921 &dspi->cur_msg->transfers)) { 922 /* Leave PCS activated after last transfer when 923 * cs_change is set. 924 */ 925 if (transfer->cs_change) 926 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; 927 } else { 928 /* Keep PCS active between transfers in same message 929 * when cs_change is not set, and de-activate PCS 930 * between transfers in the same message when 931 * cs_change is set. 932 */ 933 if (!transfer->cs_change) 934 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; 935 } 936 937 dspi->tx = transfer->tx_buf; 938 dspi->rx = transfer->rx_buf; 939 dspi->len = transfer->len; 940 dspi->progress = 0; 941 942 regmap_update_bits(dspi->regmap, SPI_MCR, 943 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, 944 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); 945 946 spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, 947 dspi->progress, !dspi->irq); 948 949 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { 950 status = dspi_dma_xfer(dspi); 951 } else { 952 dspi_fifo_write(dspi); 953 954 if (dspi->irq) { 955 wait_for_completion(&dspi->xfer_done); 956 reinit_completion(&dspi->xfer_done); 957 } else { 958 do { 959 status = dspi_poll(dspi); 960 } while (status == -EINPROGRESS); 961 } 962 } 963 if (status) 964 break; 965 966 spi_transfer_delay_exec(transfer); 967 } 968 969 message->status = status; 970 spi_finalize_current_message(ctlr); 971 972 return status; 973 } 974 975 static int dspi_setup(struct spi_device *spi) 976 { 977 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller); 978 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; 979 u32 cs_sck_delay = 0, sck_cs_delay = 0; 980 struct fsl_dspi_platform_data *pdata; 981 unsigned char pasc = 0, asc = 0; 982 struct chip_data *chip; 983 unsigned long clkrate; 984 985 /* Only alloc on first setup */ 986 chip = spi_get_ctldata(spi); 987 if (chip == NULL) { 988 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 989 if (!chip) 990 return -ENOMEM; 991 } 992 993 pdata = dev_get_platdata(&dspi->pdev->dev); 994 995 if (!pdata) { 996 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", 997 &cs_sck_delay); 998 999 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", 1000 &sck_cs_delay); 1001 } else { 1002 cs_sck_delay = pdata->cs_sck_delay; 1003 sck_cs_delay = pdata->sck_cs_delay; 1004 } 1005 1006 clkrate = clk_get_rate(dspi->clk); 1007 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); 1008 1009 /* Set PCS to SCK delay scale values */ 1010 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); 1011 1012 /* Set After SCK delay scale values */ 1013 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); 1014 1015 chip->ctar_val = 0; 1016 if (spi->mode & SPI_CPOL) 1017 chip->ctar_val |= SPI_CTAR_CPOL; 1018 if (spi->mode & SPI_CPHA) 1019 chip->ctar_val |= SPI_CTAR_CPHA; 1020 1021 if (!spi_controller_is_slave(dspi->ctlr)) { 1022 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) | 1023 SPI_CTAR_CSSCK(cssck) | 1024 SPI_CTAR_PASC(pasc) | 1025 SPI_CTAR_ASC(asc) | 1026 SPI_CTAR_PBR(pbr) | 1027 SPI_CTAR_BR(br); 1028 1029 if (spi->mode & SPI_LSB_FIRST) 1030 chip->ctar_val |= SPI_CTAR_LSBFE; 1031 } 1032 1033 spi_set_ctldata(spi, chip); 1034 1035 return 0; 1036 } 1037 1038 static void dspi_cleanup(struct spi_device *spi) 1039 { 1040 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); 1041 1042 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", 1043 spi->controller->bus_num, spi->chip_select); 1044 1045 kfree(chip); 1046 } 1047 1048 static const struct of_device_id fsl_dspi_dt_ids[] = { 1049 { 1050 .compatible = "fsl,vf610-dspi", 1051 .data = &devtype_data[VF610], 1052 }, { 1053 .compatible = "fsl,ls1021a-v1.0-dspi", 1054 .data = &devtype_data[LS1021A], 1055 }, { 1056 .compatible = "fsl,ls1012a-dspi", 1057 .data = &devtype_data[LS1012A], 1058 }, { 1059 .compatible = "fsl,ls1028a-dspi", 1060 .data = &devtype_data[LS1028A], 1061 }, { 1062 .compatible = "fsl,ls1043a-dspi", 1063 .data = &devtype_data[LS1043A], 1064 }, { 1065 .compatible = "fsl,ls1046a-dspi", 1066 .data = &devtype_data[LS1046A], 1067 }, { 1068 .compatible = "fsl,ls2080a-dspi", 1069 .data = &devtype_data[LS2080A], 1070 }, { 1071 .compatible = "fsl,ls2085a-dspi", 1072 .data = &devtype_data[LS2085A], 1073 }, { 1074 .compatible = "fsl,lx2160a-dspi", 1075 .data = &devtype_data[LX2160A], 1076 }, 1077 { /* sentinel */ } 1078 }; 1079 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); 1080 1081 #ifdef CONFIG_PM_SLEEP 1082 static int dspi_suspend(struct device *dev) 1083 { 1084 struct fsl_dspi *dspi = dev_get_drvdata(dev); 1085 1086 if (dspi->irq) 1087 disable_irq(dspi->irq); 1088 spi_controller_suspend(dspi->ctlr); 1089 clk_disable_unprepare(dspi->clk); 1090 1091 pinctrl_pm_select_sleep_state(dev); 1092 1093 return 0; 1094 } 1095 1096 static int dspi_resume(struct device *dev) 1097 { 1098 struct fsl_dspi *dspi = dev_get_drvdata(dev); 1099 int ret; 1100 1101 pinctrl_pm_select_default_state(dev); 1102 1103 ret = clk_prepare_enable(dspi->clk); 1104 if (ret) 1105 return ret; 1106 spi_controller_resume(dspi->ctlr); 1107 if (dspi->irq) 1108 enable_irq(dspi->irq); 1109 1110 return 0; 1111 } 1112 #endif /* CONFIG_PM_SLEEP */ 1113 1114 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); 1115 1116 static const struct regmap_range dspi_volatile_ranges[] = { 1117 regmap_reg_range(SPI_MCR, SPI_TCR), 1118 regmap_reg_range(SPI_SR, SPI_SR), 1119 regmap_reg_range(SPI_PUSHR, SPI_RXFR3), 1120 }; 1121 1122 static const struct regmap_access_table dspi_volatile_table = { 1123 .yes_ranges = dspi_volatile_ranges, 1124 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges), 1125 }; 1126 1127 static const struct regmap_config dspi_regmap_config = { 1128 .reg_bits = 32, 1129 .val_bits = 32, 1130 .reg_stride = 4, 1131 .max_register = 0x88, 1132 .volatile_table = &dspi_volatile_table, 1133 }; 1134 1135 static const struct regmap_range dspi_xspi_volatile_ranges[] = { 1136 regmap_reg_range(SPI_MCR, SPI_TCR), 1137 regmap_reg_range(SPI_SR, SPI_SR), 1138 regmap_reg_range(SPI_PUSHR, SPI_RXFR3), 1139 regmap_reg_range(SPI_SREX, SPI_SREX), 1140 }; 1141 1142 static const struct regmap_access_table dspi_xspi_volatile_table = { 1143 .yes_ranges = dspi_xspi_volatile_ranges, 1144 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges), 1145 }; 1146 1147 static const struct regmap_config dspi_xspi_regmap_config[] = { 1148 { 1149 .reg_bits = 32, 1150 .val_bits = 32, 1151 .reg_stride = 4, 1152 .max_register = 0x13c, 1153 .volatile_table = &dspi_xspi_volatile_table, 1154 }, 1155 { 1156 .name = "pushr", 1157 .reg_bits = 16, 1158 .val_bits = 16, 1159 .reg_stride = 2, 1160 .max_register = 0x2, 1161 }, 1162 }; 1163 1164 static int dspi_init(struct fsl_dspi *dspi) 1165 { 1166 unsigned int mcr; 1167 1168 /* Set idle states for all chip select signals to high */ 1169 mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0)); 1170 1171 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) 1172 mcr |= SPI_MCR_XSPI; 1173 if (!spi_controller_is_slave(dspi->ctlr)) 1174 mcr |= SPI_MCR_MASTER; 1175 1176 regmap_write(dspi->regmap, SPI_MCR, mcr); 1177 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); 1178 1179 switch (dspi->devtype_data->trans_mode) { 1180 case DSPI_XSPI_MODE: 1181 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); 1182 break; 1183 case DSPI_DMA_MODE: 1184 regmap_write(dspi->regmap, SPI_RSER, 1185 SPI_RSER_TFFFE | SPI_RSER_TFFFD | 1186 SPI_RSER_RFDFE | SPI_RSER_RFDFD); 1187 break; 1188 default: 1189 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", 1190 dspi->devtype_data->trans_mode); 1191 return -EINVAL; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int dspi_slave_abort(struct spi_master *master) 1198 { 1199 struct fsl_dspi *dspi = spi_master_get_devdata(master); 1200 1201 /* 1202 * Terminate all pending DMA transactions for the SPI working 1203 * in SLAVE mode. 1204 */ 1205 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { 1206 dmaengine_terminate_sync(dspi->dma->chan_rx); 1207 dmaengine_terminate_sync(dspi->dma->chan_tx); 1208 } 1209 1210 /* Clear the internal DSPI RX and TX FIFO buffers */ 1211 regmap_update_bits(dspi->regmap, SPI_MCR, 1212 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, 1213 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); 1214 1215 return 0; 1216 } 1217 1218 static int dspi_probe(struct platform_device *pdev) 1219 { 1220 struct device_node *np = pdev->dev.of_node; 1221 const struct regmap_config *regmap_config; 1222 struct fsl_dspi_platform_data *pdata; 1223 struct spi_controller *ctlr; 1224 int ret, cs_num, bus_num = -1; 1225 struct fsl_dspi *dspi; 1226 struct resource *res; 1227 void __iomem *base; 1228 bool big_endian; 1229 1230 dspi = devm_kzalloc(&pdev->dev, sizeof(*dspi), GFP_KERNEL); 1231 if (!dspi) 1232 return -ENOMEM; 1233 1234 ctlr = spi_alloc_master(&pdev->dev, 0); 1235 if (!ctlr) 1236 return -ENOMEM; 1237 1238 spi_controller_set_devdata(ctlr, dspi); 1239 platform_set_drvdata(pdev, dspi); 1240 1241 dspi->pdev = pdev; 1242 dspi->ctlr = ctlr; 1243 1244 ctlr->setup = dspi_setup; 1245 ctlr->transfer_one_message = dspi_transfer_one_message; 1246 ctlr->dev.of_node = pdev->dev.of_node; 1247 1248 ctlr->cleanup = dspi_cleanup; 1249 ctlr->slave_abort = dspi_slave_abort; 1250 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 1251 1252 pdata = dev_get_platdata(&pdev->dev); 1253 if (pdata) { 1254 ctlr->num_chipselect = ctlr->max_native_cs = pdata->cs_num; 1255 ctlr->bus_num = pdata->bus_num; 1256 1257 /* Only Coldfire uses platform data */ 1258 dspi->devtype_data = &devtype_data[MCF5441X]; 1259 big_endian = true; 1260 } else { 1261 1262 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); 1263 if (ret < 0) { 1264 dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); 1265 goto out_ctlr_put; 1266 } 1267 ctlr->num_chipselect = ctlr->max_native_cs = cs_num; 1268 1269 of_property_read_u32(np, "bus-num", &bus_num); 1270 ctlr->bus_num = bus_num; 1271 1272 if (of_property_read_bool(np, "spi-slave")) 1273 ctlr->slave = true; 1274 1275 dspi->devtype_data = of_device_get_match_data(&pdev->dev); 1276 if (!dspi->devtype_data) { 1277 dev_err(&pdev->dev, "can't get devtype_data\n"); 1278 ret = -EFAULT; 1279 goto out_ctlr_put; 1280 } 1281 1282 big_endian = of_device_is_big_endian(np); 1283 } 1284 if (big_endian) { 1285 dspi->pushr_cmd = 0; 1286 dspi->pushr_tx = 2; 1287 } else { 1288 dspi->pushr_cmd = 2; 1289 dspi->pushr_tx = 0; 1290 } 1291 1292 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) 1293 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1294 else 1295 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1296 1297 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1298 base = devm_ioremap_resource(&pdev->dev, res); 1299 if (IS_ERR(base)) { 1300 ret = PTR_ERR(base); 1301 goto out_ctlr_put; 1302 } 1303 1304 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) 1305 regmap_config = &dspi_xspi_regmap_config[0]; 1306 else 1307 regmap_config = &dspi_regmap_config; 1308 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config); 1309 if (IS_ERR(dspi->regmap)) { 1310 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 1311 PTR_ERR(dspi->regmap)); 1312 ret = PTR_ERR(dspi->regmap); 1313 goto out_ctlr_put; 1314 } 1315 1316 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) { 1317 dspi->regmap_pushr = devm_regmap_init_mmio( 1318 &pdev->dev, base + SPI_PUSHR, 1319 &dspi_xspi_regmap_config[1]); 1320 if (IS_ERR(dspi->regmap_pushr)) { 1321 dev_err(&pdev->dev, 1322 "failed to init pushr regmap: %ld\n", 1323 PTR_ERR(dspi->regmap_pushr)); 1324 ret = PTR_ERR(dspi->regmap_pushr); 1325 goto out_ctlr_put; 1326 } 1327 } 1328 1329 dspi->clk = devm_clk_get(&pdev->dev, "dspi"); 1330 if (IS_ERR(dspi->clk)) { 1331 ret = PTR_ERR(dspi->clk); 1332 dev_err(&pdev->dev, "unable to get clock\n"); 1333 goto out_ctlr_put; 1334 } 1335 ret = clk_prepare_enable(dspi->clk); 1336 if (ret) 1337 goto out_ctlr_put; 1338 1339 ret = dspi_init(dspi); 1340 if (ret) 1341 goto out_clk_put; 1342 1343 dspi->irq = platform_get_irq(pdev, 0); 1344 if (dspi->irq <= 0) { 1345 dev_info(&pdev->dev, 1346 "can't get platform irq, using poll mode\n"); 1347 dspi->irq = 0; 1348 goto poll_mode; 1349 } 1350 1351 init_completion(&dspi->xfer_done); 1352 1353 ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL, 1354 IRQF_SHARED, pdev->name, dspi); 1355 if (ret < 0) { 1356 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); 1357 goto out_clk_put; 1358 } 1359 1360 poll_mode: 1361 1362 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { 1363 ret = dspi_request_dma(dspi, res->start); 1364 if (ret < 0) { 1365 dev_err(&pdev->dev, "can't get dma channels\n"); 1366 goto out_free_irq; 1367 } 1368 } 1369 1370 ctlr->max_speed_hz = 1371 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; 1372 1373 if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE) 1374 ctlr->ptp_sts_supported = true; 1375 1376 ret = spi_register_controller(ctlr); 1377 if (ret != 0) { 1378 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n"); 1379 goto out_release_dma; 1380 } 1381 1382 return ret; 1383 1384 out_release_dma: 1385 dspi_release_dma(dspi); 1386 out_free_irq: 1387 if (dspi->irq) 1388 free_irq(dspi->irq, dspi); 1389 out_clk_put: 1390 clk_disable_unprepare(dspi->clk); 1391 out_ctlr_put: 1392 spi_controller_put(ctlr); 1393 1394 return ret; 1395 } 1396 1397 static int dspi_remove(struct platform_device *pdev) 1398 { 1399 struct fsl_dspi *dspi = platform_get_drvdata(pdev); 1400 1401 /* Disconnect from the SPI framework */ 1402 spi_unregister_controller(dspi->ctlr); 1403 1404 /* Disable RX and TX */ 1405 regmap_update_bits(dspi->regmap, SPI_MCR, 1406 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF, 1407 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF); 1408 1409 /* Stop Running */ 1410 regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT); 1411 1412 dspi_release_dma(dspi); 1413 if (dspi->irq) 1414 free_irq(dspi->irq, dspi); 1415 clk_disable_unprepare(dspi->clk); 1416 1417 return 0; 1418 } 1419 1420 static void dspi_shutdown(struct platform_device *pdev) 1421 { 1422 dspi_remove(pdev); 1423 } 1424 1425 static struct platform_driver fsl_dspi_driver = { 1426 .driver.name = DRIVER_NAME, 1427 .driver.of_match_table = fsl_dspi_dt_ids, 1428 .driver.owner = THIS_MODULE, 1429 .driver.pm = &dspi_pm, 1430 .probe = dspi_probe, 1431 .remove = dspi_remove, 1432 .shutdown = dspi_shutdown, 1433 }; 1434 module_platform_driver(fsl_dspi_driver); 1435 1436 MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); 1437 MODULE_LICENSE("GPL"); 1438 MODULE_ALIAS("platform:" DRIVER_NAME); 1439