1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2ca632f55SGrant Likely #ifndef DW_SPI_HEADER_H 3ca632f55SGrant Likely #define DW_SPI_HEADER_H 4ca632f55SGrant Likely 5ca632f55SGrant Likely #include <linux/io.h> 6ca632f55SGrant Likely #include <linux/scatterlist.h> 7ca632f55SGrant Likely 87eb187b3SH Hartley Sweeten /* Register offsets */ 9299cb65cSWan Ahmad Zainie #define DW_SPI_CTRLR0 0x00 10299cb65cSWan Ahmad Zainie #define DW_SPI_CTRLR1 0x04 117eb187b3SH Hartley Sweeten #define DW_SPI_SSIENR 0x08 127eb187b3SH Hartley Sweeten #define DW_SPI_MWCR 0x0c 137eb187b3SH Hartley Sweeten #define DW_SPI_SER 0x10 147eb187b3SH Hartley Sweeten #define DW_SPI_BAUDR 0x14 15299cb65cSWan Ahmad Zainie #define DW_SPI_TXFTLR 0x18 16299cb65cSWan Ahmad Zainie #define DW_SPI_RXFTLR 0x1c 177eb187b3SH Hartley Sweeten #define DW_SPI_TXFLR 0x20 187eb187b3SH Hartley Sweeten #define DW_SPI_RXFLR 0x24 197eb187b3SH Hartley Sweeten #define DW_SPI_SR 0x28 207eb187b3SH Hartley Sweeten #define DW_SPI_IMR 0x2c 217eb187b3SH Hartley Sweeten #define DW_SPI_ISR 0x30 227eb187b3SH Hartley Sweeten #define DW_SPI_RISR 0x34 237eb187b3SH Hartley Sweeten #define DW_SPI_TXOICR 0x38 247eb187b3SH Hartley Sweeten #define DW_SPI_RXOICR 0x3c 257eb187b3SH Hartley Sweeten #define DW_SPI_RXUICR 0x40 267eb187b3SH Hartley Sweeten #define DW_SPI_MSTICR 0x44 277eb187b3SH Hartley Sweeten #define DW_SPI_ICR 0x48 287eb187b3SH Hartley Sweeten #define DW_SPI_DMACR 0x4c 297eb187b3SH Hartley Sweeten #define DW_SPI_DMATDLR 0x50 307eb187b3SH Hartley Sweeten #define DW_SPI_DMARDLR 0x54 317eb187b3SH Hartley Sweeten #define DW_SPI_IDR 0x58 327eb187b3SH Hartley Sweeten #define DW_SPI_VERSION 0x5c 337eb187b3SH Hartley Sweeten #define DW_SPI_DR 0x60 34f2d70479STalel Shenhar #define DW_SPI_CS_OVERRIDE 0xf4 357eb187b3SH Hartley Sweeten 36ca632f55SGrant Likely /* Bit fields in CTRLR0 */ 37ca632f55SGrant Likely #define SPI_DFS_OFFSET 0 38ca632f55SGrant Likely 39ca632f55SGrant Likely #define SPI_FRF_OFFSET 4 40ca632f55SGrant Likely #define SPI_FRF_SPI 0x0 41ca632f55SGrant Likely #define SPI_FRF_SSP 0x1 42ca632f55SGrant Likely #define SPI_FRF_MICROWIRE 0x2 43ca632f55SGrant Likely #define SPI_FRF_RESV 0x3 44ca632f55SGrant Likely 45ca632f55SGrant Likely #define SPI_MODE_OFFSET 6 46ca632f55SGrant Likely #define SPI_SCPH_OFFSET 6 47ca632f55SGrant Likely #define SPI_SCOL_OFFSET 7 48ca632f55SGrant Likely 49ca632f55SGrant Likely #define SPI_TMOD_OFFSET 8 50ca632f55SGrant Likely #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) 51ca632f55SGrant Likely #define SPI_TMOD_TR 0x0 /* xmit & recv */ 52ca632f55SGrant Likely #define SPI_TMOD_TO 0x1 /* xmit only */ 53ca632f55SGrant Likely #define SPI_TMOD_RO 0x2 /* recv only */ 54ca632f55SGrant Likely #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ 55ca632f55SGrant Likely 56ca632f55SGrant Likely #define SPI_SLVOE_OFFSET 10 57ca632f55SGrant Likely #define SPI_SRL_OFFSET 11 58ca632f55SGrant Likely #define SPI_CFS_OFFSET 12 59ca632f55SGrant Likely 60ca632f55SGrant Likely /* Bit fields in SR, 7 bits */ 61ca632f55SGrant Likely #define SR_MASK 0x7f /* cover 7 bits */ 62ca632f55SGrant Likely #define SR_BUSY (1 << 0) 63ca632f55SGrant Likely #define SR_TF_NOT_FULL (1 << 1) 64ca632f55SGrant Likely #define SR_TF_EMPT (1 << 2) 65ca632f55SGrant Likely #define SR_RF_NOT_EMPT (1 << 3) 66ca632f55SGrant Likely #define SR_RF_FULL (1 << 4) 67ca632f55SGrant Likely #define SR_TX_ERR (1 << 5) 68ca632f55SGrant Likely #define SR_DCOL (1 << 6) 69ca632f55SGrant Likely 70ca632f55SGrant Likely /* Bit fields in ISR, IMR, RISR, 7 bits */ 71ca632f55SGrant Likely #define SPI_INT_TXEI (1 << 0) 72ca632f55SGrant Likely #define SPI_INT_TXOI (1 << 1) 73ca632f55SGrant Likely #define SPI_INT_RXUI (1 << 2) 74ca632f55SGrant Likely #define SPI_INT_RXOI (1 << 3) 75ca632f55SGrant Likely #define SPI_INT_RXFI (1 << 4) 76ca632f55SGrant Likely #define SPI_INT_MSTI (1 << 5) 77ca632f55SGrant Likely 7815ee3be7SAndy Shevchenko /* Bit fields in DMACR */ 7915ee3be7SAndy Shevchenko #define SPI_DMA_RDMAE (1 << 0) 8015ee3be7SAndy Shevchenko #define SPI_DMA_TDMAE (1 << 1) 8115ee3be7SAndy Shevchenko 82ca632f55SGrant Likely /* TX RX interrupt level threshold, max can be 256 */ 83ca632f55SGrant Likely #define SPI_INT_THRESHOLD 32 84ca632f55SGrant Likely 85ca632f55SGrant Likely enum dw_ssi_type { 86ca632f55SGrant Likely SSI_MOTO_SPI = 0, 87ca632f55SGrant Likely SSI_TI_SSP, 88ca632f55SGrant Likely SSI_NS_MICROWIRE, 89ca632f55SGrant Likely }; 90ca632f55SGrant Likely 91ca632f55SGrant Likely struct dw_spi; 92ca632f55SGrant Likely struct dw_spi_dma_ops { 93ca632f55SGrant Likely int (*dma_init)(struct dw_spi *dws); 94ca632f55SGrant Likely void (*dma_exit)(struct dw_spi *dws); 95f89a6d8fSAndy Shevchenko int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer); 96721483e2SJarkko Nikula bool (*can_dma)(struct spi_controller *master, struct spi_device *spi, 97f89a6d8fSAndy Shevchenko struct spi_transfer *xfer); 98f89a6d8fSAndy Shevchenko int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer); 994d5ac1edSAndy Shevchenko void (*dma_stop)(struct dw_spi *dws); 100ca632f55SGrant Likely }; 101ca632f55SGrant Likely 102ca632f55SGrant Likely struct dw_spi { 103721483e2SJarkko Nikula struct spi_controller *master; 104ca632f55SGrant Likely enum dw_ssi_type type; 105ca632f55SGrant Likely 106ca632f55SGrant Likely void __iomem *regs; 107ca632f55SGrant Likely unsigned long paddr; 108ca632f55SGrant Likely int irq; 109ca632f55SGrant Likely u32 fifo_len; /* depth of the FIFO buffer */ 110ca632f55SGrant Likely u32 max_freq; /* max bus freq supported */ 111ca632f55SGrant Likely 112f2d70479STalel Shenhar int cs_override; 113c4fe57f7SMichael van der Westhuizen u32 reg_io_width; /* DR I/O width in bytes */ 114ca632f55SGrant Likely u16 bus_num; 115ca632f55SGrant Likely u16 num_cs; /* supported slave numbers */ 11662dbbae4SAlexandre Belloni void (*set_cs)(struct spi_device *spi, bool enable); 117*c4eadee2SWan Ahmad Zainie u32 (*update_cr0)(struct spi_controller *master, struct spi_device *spi, 118*c4eadee2SWan Ahmad Zainie struct spi_transfer *transfer); 119ca632f55SGrant Likely 120ca632f55SGrant Likely /* Current message transfer state info */ 121ca632f55SGrant Likely size_t len; 122ca632f55SGrant Likely void *tx; 123ca632f55SGrant Likely void *tx_end; 12419b61392Swuxu.wu spinlock_t buf_lock; 125ca632f55SGrant Likely void *rx; 126ca632f55SGrant Likely void *rx_end; 127ca632f55SGrant Likely int dma_mapped; 128ca632f55SGrant Likely u8 n_bytes; /* current is a 1/2 bytes op */ 129ca632f55SGrant Likely u32 dma_width; 130ca632f55SGrant Likely irqreturn_t (*transfer_handler)(struct dw_spi *dws); 13113b10301SMatthias Seidel u32 current_freq; /* frequency in hz */ 132ca632f55SGrant Likely 133f89a6d8fSAndy Shevchenko /* DMA info */ 134ca632f55SGrant Likely int dma_inited; 135ca632f55SGrant Likely struct dma_chan *txchan; 136ca632f55SGrant Likely struct dma_chan *rxchan; 13730c8eb52SAndy Shevchenko unsigned long dma_chan_busy; 138ca632f55SGrant Likely dma_addr_t dma_addr; /* phy address of the Data register */ 1394fe338c9SJulia Lawall const struct dw_spi_dma_ops *dma_ops; 140d744f826SAndy Shevchenko void *dma_tx; 141d744f826SAndy Shevchenko void *dma_rx; 142ca632f55SGrant Likely 143ca632f55SGrant Likely /* Bus interface info */ 144ca632f55SGrant Likely void *priv; 145ca632f55SGrant Likely #ifdef CONFIG_DEBUG_FS 146ca632f55SGrant Likely struct dentry *debugfs; 147ca632f55SGrant Likely #endif 148ca632f55SGrant Likely }; 149ca632f55SGrant Likely 1507eb187b3SH Hartley Sweeten static inline u32 dw_readl(struct dw_spi *dws, u32 offset) 1517eb187b3SH Hartley Sweeten { 1527eb187b3SH Hartley Sweeten return __raw_readl(dws->regs + offset); 1537eb187b3SH Hartley Sweeten } 1547eb187b3SH Hartley Sweeten 155c4fe57f7SMichael van der Westhuizen static inline u16 dw_readw(struct dw_spi *dws, u32 offset) 156c4fe57f7SMichael van der Westhuizen { 157c4fe57f7SMichael van der Westhuizen return __raw_readw(dws->regs + offset); 158c4fe57f7SMichael van der Westhuizen } 159c4fe57f7SMichael van der Westhuizen 1607eb187b3SH Hartley Sweeten static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) 1617eb187b3SH Hartley Sweeten { 1627eb187b3SH Hartley Sweeten __raw_writel(val, dws->regs + offset); 1637eb187b3SH Hartley Sweeten } 1647eb187b3SH Hartley Sweeten 165c4fe57f7SMichael van der Westhuizen static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) 166c4fe57f7SMichael van der Westhuizen { 167c4fe57f7SMichael van der Westhuizen __raw_writew(val, dws->regs + offset); 168c4fe57f7SMichael van der Westhuizen } 169c4fe57f7SMichael van der Westhuizen 170c4fe57f7SMichael van der Westhuizen static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) 171c4fe57f7SMichael van der Westhuizen { 172c4fe57f7SMichael van der Westhuizen switch (dws->reg_io_width) { 173c4fe57f7SMichael van der Westhuizen case 2: 174c4fe57f7SMichael van der Westhuizen return dw_readw(dws, offset); 175c4fe57f7SMichael van der Westhuizen case 4: 176c4fe57f7SMichael van der Westhuizen default: 177c4fe57f7SMichael van der Westhuizen return dw_readl(dws, offset); 178c4fe57f7SMichael van der Westhuizen } 179c4fe57f7SMichael van der Westhuizen } 180c4fe57f7SMichael van der Westhuizen 181c4fe57f7SMichael van der Westhuizen static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) 182c4fe57f7SMichael van der Westhuizen { 183c4fe57f7SMichael van der Westhuizen switch (dws->reg_io_width) { 184c4fe57f7SMichael van der Westhuizen case 2: 185c4fe57f7SMichael van der Westhuizen dw_writew(dws, offset, val); 186c4fe57f7SMichael van der Westhuizen break; 187c4fe57f7SMichael van der Westhuizen case 4: 188c4fe57f7SMichael van der Westhuizen default: 189c4fe57f7SMichael van der Westhuizen dw_writel(dws, offset, val); 190c4fe57f7SMichael van der Westhuizen break; 191c4fe57f7SMichael van der Westhuizen } 192c4fe57f7SMichael van der Westhuizen } 193c4fe57f7SMichael van der Westhuizen 194ca632f55SGrant Likely static inline void spi_enable_chip(struct dw_spi *dws, int enable) 195ca632f55SGrant Likely { 1967eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); 197ca632f55SGrant Likely } 198ca632f55SGrant Likely 199ca632f55SGrant Likely static inline void spi_set_clk(struct dw_spi *dws, u16 div) 200ca632f55SGrant Likely { 2017eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_BAUDR, div); 202ca632f55SGrant Likely } 203ca632f55SGrant Likely 204ca632f55SGrant Likely /* Disable IRQ bits */ 205ca632f55SGrant Likely static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) 206ca632f55SGrant Likely { 207ca632f55SGrant Likely u32 new_mask; 208ca632f55SGrant Likely 2097eb187b3SH Hartley Sweeten new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; 2107eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_IMR, new_mask); 211ca632f55SGrant Likely } 212ca632f55SGrant Likely 213ca632f55SGrant Likely /* Enable IRQ bits */ 214ca632f55SGrant Likely static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) 215ca632f55SGrant Likely { 216ca632f55SGrant Likely u32 new_mask; 217ca632f55SGrant Likely 2187eb187b3SH Hartley Sweeten new_mask = dw_readl(dws, DW_SPI_IMR) | mask; 2197eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_IMR, new_mask); 220ca632f55SGrant Likely } 221ca632f55SGrant Likely 222ca632f55SGrant Likely /* 22345746e82SAndy Shevchenko * This does disable the SPI controller, interrupts, and re-enable the 22445746e82SAndy Shevchenko * controller back. Transmit and receive FIFO buffers are cleared when the 22545746e82SAndy Shevchenko * device is disabled. 22645746e82SAndy Shevchenko */ 22745746e82SAndy Shevchenko static inline void spi_reset_chip(struct dw_spi *dws) 22845746e82SAndy Shevchenko { 22945746e82SAndy Shevchenko spi_enable_chip(dws, 0); 23045746e82SAndy Shevchenko spi_mask_intr(dws, 0xff); 23145746e82SAndy Shevchenko spi_enable_chip(dws, 1); 23245746e82SAndy Shevchenko } 23345746e82SAndy Shevchenko 2341cc3f141SAndy Shevchenko static inline void spi_shutdown_chip(struct dw_spi *dws) 2351cc3f141SAndy Shevchenko { 2361cc3f141SAndy Shevchenko spi_enable_chip(dws, 0); 2371cc3f141SAndy Shevchenko spi_set_clk(dws, 0); 2381cc3f141SAndy Shevchenko } 2391cc3f141SAndy Shevchenko 240c79bdbb4SAlexandre Belloni extern void dw_spi_set_cs(struct spi_device *spi, bool enable); 24104f421e7SBaruch Siach extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); 242ca632f55SGrant Likely extern void dw_spi_remove_host(struct dw_spi *dws); 243ca632f55SGrant Likely extern int dw_spi_suspend_host(struct dw_spi *dws); 244ca632f55SGrant Likely extern int dw_spi_resume_host(struct dw_spi *dws); 245*c4eadee2SWan Ahmad Zainie extern u32 dw_spi_update_cr0(struct spi_controller *master, 246*c4eadee2SWan Ahmad Zainie struct spi_device *spi, 247*c4eadee2SWan Ahmad Zainie struct spi_transfer *transfer); 248ca632f55SGrant Likely 249ca632f55SGrant Likely /* platform related setup */ 250ca632f55SGrant Likely extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ 251ca632f55SGrant Likely #endif /* DW_SPI_HEADER_H */ 252