1ca632f55SGrant Likely #ifndef DW_SPI_HEADER_H 2ca632f55SGrant Likely #define DW_SPI_HEADER_H 3ca632f55SGrant Likely 4ca632f55SGrant Likely #include <linux/io.h> 5ca632f55SGrant Likely #include <linux/scatterlist.h> 6d9c73bb8SBaruch Siach #include <linux/gpio.h> 7ca632f55SGrant Likely 87eb187b3SH Hartley Sweeten /* Register offsets */ 97eb187b3SH Hartley Sweeten #define DW_SPI_CTRL0 0x00 107eb187b3SH Hartley Sweeten #define DW_SPI_CTRL1 0x04 117eb187b3SH Hartley Sweeten #define DW_SPI_SSIENR 0x08 127eb187b3SH Hartley Sweeten #define DW_SPI_MWCR 0x0c 137eb187b3SH Hartley Sweeten #define DW_SPI_SER 0x10 147eb187b3SH Hartley Sweeten #define DW_SPI_BAUDR 0x14 157eb187b3SH Hartley Sweeten #define DW_SPI_TXFLTR 0x18 167eb187b3SH Hartley Sweeten #define DW_SPI_RXFLTR 0x1c 177eb187b3SH Hartley Sweeten #define DW_SPI_TXFLR 0x20 187eb187b3SH Hartley Sweeten #define DW_SPI_RXFLR 0x24 197eb187b3SH Hartley Sweeten #define DW_SPI_SR 0x28 207eb187b3SH Hartley Sweeten #define DW_SPI_IMR 0x2c 217eb187b3SH Hartley Sweeten #define DW_SPI_ISR 0x30 227eb187b3SH Hartley Sweeten #define DW_SPI_RISR 0x34 237eb187b3SH Hartley Sweeten #define DW_SPI_TXOICR 0x38 247eb187b3SH Hartley Sweeten #define DW_SPI_RXOICR 0x3c 257eb187b3SH Hartley Sweeten #define DW_SPI_RXUICR 0x40 267eb187b3SH Hartley Sweeten #define DW_SPI_MSTICR 0x44 277eb187b3SH Hartley Sweeten #define DW_SPI_ICR 0x48 287eb187b3SH Hartley Sweeten #define DW_SPI_DMACR 0x4c 297eb187b3SH Hartley Sweeten #define DW_SPI_DMATDLR 0x50 307eb187b3SH Hartley Sweeten #define DW_SPI_DMARDLR 0x54 317eb187b3SH Hartley Sweeten #define DW_SPI_IDR 0x58 327eb187b3SH Hartley Sweeten #define DW_SPI_VERSION 0x5c 337eb187b3SH Hartley Sweeten #define DW_SPI_DR 0x60 347eb187b3SH Hartley Sweeten 35ca632f55SGrant Likely /* Bit fields in CTRLR0 */ 36ca632f55SGrant Likely #define SPI_DFS_OFFSET 0 37ca632f55SGrant Likely 38ca632f55SGrant Likely #define SPI_FRF_OFFSET 4 39ca632f55SGrant Likely #define SPI_FRF_SPI 0x0 40ca632f55SGrant Likely #define SPI_FRF_SSP 0x1 41ca632f55SGrant Likely #define SPI_FRF_MICROWIRE 0x2 42ca632f55SGrant Likely #define SPI_FRF_RESV 0x3 43ca632f55SGrant Likely 44ca632f55SGrant Likely #define SPI_MODE_OFFSET 6 45ca632f55SGrant Likely #define SPI_SCPH_OFFSET 6 46ca632f55SGrant Likely #define SPI_SCOL_OFFSET 7 47ca632f55SGrant Likely 48ca632f55SGrant Likely #define SPI_TMOD_OFFSET 8 49ca632f55SGrant Likely #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) 50ca632f55SGrant Likely #define SPI_TMOD_TR 0x0 /* xmit & recv */ 51ca632f55SGrant Likely #define SPI_TMOD_TO 0x1 /* xmit only */ 52ca632f55SGrant Likely #define SPI_TMOD_RO 0x2 /* recv only */ 53ca632f55SGrant Likely #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ 54ca632f55SGrant Likely 55ca632f55SGrant Likely #define SPI_SLVOE_OFFSET 10 56ca632f55SGrant Likely #define SPI_SRL_OFFSET 11 57ca632f55SGrant Likely #define SPI_CFS_OFFSET 12 58ca632f55SGrant Likely 59ca632f55SGrant Likely /* Bit fields in SR, 7 bits */ 60ca632f55SGrant Likely #define SR_MASK 0x7f /* cover 7 bits */ 61ca632f55SGrant Likely #define SR_BUSY (1 << 0) 62ca632f55SGrant Likely #define SR_TF_NOT_FULL (1 << 1) 63ca632f55SGrant Likely #define SR_TF_EMPT (1 << 2) 64ca632f55SGrant Likely #define SR_RF_NOT_EMPT (1 << 3) 65ca632f55SGrant Likely #define SR_RF_FULL (1 << 4) 66ca632f55SGrant Likely #define SR_TX_ERR (1 << 5) 67ca632f55SGrant Likely #define SR_DCOL (1 << 6) 68ca632f55SGrant Likely 69ca632f55SGrant Likely /* Bit fields in ISR, IMR, RISR, 7 bits */ 70ca632f55SGrant Likely #define SPI_INT_TXEI (1 << 0) 71ca632f55SGrant Likely #define SPI_INT_TXOI (1 << 1) 72ca632f55SGrant Likely #define SPI_INT_RXUI (1 << 2) 73ca632f55SGrant Likely #define SPI_INT_RXOI (1 << 3) 74ca632f55SGrant Likely #define SPI_INT_RXFI (1 << 4) 75ca632f55SGrant Likely #define SPI_INT_MSTI (1 << 5) 76ca632f55SGrant Likely 7715ee3be7SAndy Shevchenko /* Bit fields in DMACR */ 7815ee3be7SAndy Shevchenko #define SPI_DMA_RDMAE (1 << 0) 7915ee3be7SAndy Shevchenko #define SPI_DMA_TDMAE (1 << 1) 8015ee3be7SAndy Shevchenko 81ca632f55SGrant Likely /* TX RX interrupt level threshold, max can be 256 */ 82ca632f55SGrant Likely #define SPI_INT_THRESHOLD 32 83ca632f55SGrant Likely 84ca632f55SGrant Likely enum dw_ssi_type { 85ca632f55SGrant Likely SSI_MOTO_SPI = 0, 86ca632f55SGrant Likely SSI_TI_SSP, 87ca632f55SGrant Likely SSI_NS_MICROWIRE, 88ca632f55SGrant Likely }; 89ca632f55SGrant Likely 90ca632f55SGrant Likely struct dw_spi; 91ca632f55SGrant Likely struct dw_spi_dma_ops { 92ca632f55SGrant Likely int (*dma_init)(struct dw_spi *dws); 93ca632f55SGrant Likely void (*dma_exit)(struct dw_spi *dws); 949f14538eSAndy Shevchenko int (*dma_setup)(struct dw_spi *dws); 959f14538eSAndy Shevchenko int (*dma_transfer)(struct dw_spi *dws); 96*4d5ac1edSAndy Shevchenko void (*dma_stop)(struct dw_spi *dws); 97ca632f55SGrant Likely }; 98ca632f55SGrant Likely 99ca632f55SGrant Likely struct dw_spi { 100ca632f55SGrant Likely struct spi_master *master; 101ca632f55SGrant Likely enum dw_ssi_type type; 10240bfff85SLiu, ShuoX char name[16]; 103ca632f55SGrant Likely 104ca632f55SGrant Likely void __iomem *regs; 105ca632f55SGrant Likely unsigned long paddr; 106ca632f55SGrant Likely int irq; 107ca632f55SGrant Likely u32 fifo_len; /* depth of the FIFO buffer */ 108ca632f55SGrant Likely u32 max_freq; /* max bus freq supported */ 109ca632f55SGrant Likely 110ca632f55SGrant Likely u16 bus_num; 111ca632f55SGrant Likely u16 num_cs; /* supported slave numbers */ 112ca632f55SGrant Likely 113ca632f55SGrant Likely /* Current message transfer state info */ 114ca632f55SGrant Likely size_t len; 115ca632f55SGrant Likely void *tx; 116ca632f55SGrant Likely void *tx_end; 117ca632f55SGrant Likely void *rx; 118ca632f55SGrant Likely void *rx_end; 119ca632f55SGrant Likely int dma_mapped; 120ca632f55SGrant Likely dma_addr_t rx_dma; 121ca632f55SGrant Likely dma_addr_t tx_dma; 122ca632f55SGrant Likely size_t rx_map_len; 123ca632f55SGrant Likely size_t tx_map_len; 124ca632f55SGrant Likely u8 n_bytes; /* current is a 1/2 bytes op */ 125ca632f55SGrant Likely u32 dma_width; 126ca632f55SGrant Likely irqreturn_t (*transfer_handler)(struct dw_spi *dws); 127ca632f55SGrant Likely 128ca632f55SGrant Likely /* Dma info */ 129ca632f55SGrant Likely int dma_inited; 130ca632f55SGrant Likely struct dma_chan *txchan; 131ca632f55SGrant Likely struct scatterlist tx_sgl; 132ca632f55SGrant Likely struct dma_chan *rxchan; 133ca632f55SGrant Likely struct scatterlist rx_sgl; 13430c8eb52SAndy Shevchenko unsigned long dma_chan_busy; 135ca632f55SGrant Likely struct device *dma_dev; 136ca632f55SGrant Likely dma_addr_t dma_addr; /* phy address of the Data register */ 137ca632f55SGrant Likely struct dw_spi_dma_ops *dma_ops; 138ca632f55SGrant Likely void *dma_priv; /* platform relate info */ 139ca632f55SGrant Likely 140ca632f55SGrant Likely /* Bus interface info */ 141ca632f55SGrant Likely void *priv; 142ca632f55SGrant Likely #ifdef CONFIG_DEBUG_FS 143ca632f55SGrant Likely struct dentry *debugfs; 144ca632f55SGrant Likely #endif 145ca632f55SGrant Likely }; 146ca632f55SGrant Likely 1477eb187b3SH Hartley Sweeten static inline u32 dw_readl(struct dw_spi *dws, u32 offset) 1487eb187b3SH Hartley Sweeten { 1497eb187b3SH Hartley Sweeten return __raw_readl(dws->regs + offset); 1507eb187b3SH Hartley Sweeten } 1517eb187b3SH Hartley Sweeten 1527eb187b3SH Hartley Sweeten static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) 1537eb187b3SH Hartley Sweeten { 1547eb187b3SH Hartley Sweeten __raw_writel(val, dws->regs + offset); 1557eb187b3SH Hartley Sweeten } 1567eb187b3SH Hartley Sweeten 1577eb187b3SH Hartley Sweeten static inline u16 dw_readw(struct dw_spi *dws, u32 offset) 1587eb187b3SH Hartley Sweeten { 1597eb187b3SH Hartley Sweeten return __raw_readw(dws->regs + offset); 1607eb187b3SH Hartley Sweeten } 1617eb187b3SH Hartley Sweeten 1627eb187b3SH Hartley Sweeten static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) 1637eb187b3SH Hartley Sweeten { 1647eb187b3SH Hartley Sweeten __raw_writew(val, dws->regs + offset); 1657eb187b3SH Hartley Sweeten } 166ca632f55SGrant Likely 167ca632f55SGrant Likely static inline void spi_enable_chip(struct dw_spi *dws, int enable) 168ca632f55SGrant Likely { 1697eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); 170ca632f55SGrant Likely } 171ca632f55SGrant Likely 172ca632f55SGrant Likely static inline void spi_set_clk(struct dw_spi *dws, u16 div) 173ca632f55SGrant Likely { 1747eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_BAUDR, div); 175ca632f55SGrant Likely } 176ca632f55SGrant Likely 177ca632f55SGrant Likely /* Disable IRQ bits */ 178ca632f55SGrant Likely static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) 179ca632f55SGrant Likely { 180ca632f55SGrant Likely u32 new_mask; 181ca632f55SGrant Likely 1827eb187b3SH Hartley Sweeten new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; 1837eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_IMR, new_mask); 184ca632f55SGrant Likely } 185ca632f55SGrant Likely 186ca632f55SGrant Likely /* Enable IRQ bits */ 187ca632f55SGrant Likely static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) 188ca632f55SGrant Likely { 189ca632f55SGrant Likely u32 new_mask; 190ca632f55SGrant Likely 1917eb187b3SH Hartley Sweeten new_mask = dw_readl(dws, DW_SPI_IMR) | mask; 1927eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_IMR, new_mask); 193ca632f55SGrant Likely } 194ca632f55SGrant Likely 195ca632f55SGrant Likely /* 19645746e82SAndy Shevchenko * This does disable the SPI controller, interrupts, and re-enable the 19745746e82SAndy Shevchenko * controller back. Transmit and receive FIFO buffers are cleared when the 19845746e82SAndy Shevchenko * device is disabled. 19945746e82SAndy Shevchenko */ 20045746e82SAndy Shevchenko static inline void spi_reset_chip(struct dw_spi *dws) 20145746e82SAndy Shevchenko { 20245746e82SAndy Shevchenko spi_enable_chip(dws, 0); 20345746e82SAndy Shevchenko spi_mask_intr(dws, 0xff); 20445746e82SAndy Shevchenko spi_enable_chip(dws, 1); 20545746e82SAndy Shevchenko } 20645746e82SAndy Shevchenko 20745746e82SAndy Shevchenko /* 208ca632f55SGrant Likely * Each SPI slave device to work with dw_api controller should 209ca632f55SGrant Likely * has such a structure claiming its working mode (PIO/DMA etc), 210ca632f55SGrant Likely * which can be save in the "controller_data" member of the 21105ed2aeeSAndy Shevchenko * struct spi_device. 212ca632f55SGrant Likely */ 213ca632f55SGrant Likely struct dw_spi_chip { 21405ed2aeeSAndy Shevchenko u8 poll_mode; /* 1 for controller polling mode */ 21505ed2aeeSAndy Shevchenko u8 type; /* SPI/SSP/MicroWire */ 216ca632f55SGrant Likely u8 enable_dma; 217ca632f55SGrant Likely void (*cs_control)(u32 command); 218ca632f55SGrant Likely }; 219ca632f55SGrant Likely 22004f421e7SBaruch Siach extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); 221ca632f55SGrant Likely extern void dw_spi_remove_host(struct dw_spi *dws); 222ca632f55SGrant Likely extern int dw_spi_suspend_host(struct dw_spi *dws); 223ca632f55SGrant Likely extern int dw_spi_resume_host(struct dw_spi *dws); 224ca632f55SGrant Likely 225ca632f55SGrant Likely /* platform related setup */ 226ca632f55SGrant Likely extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ 227ca632f55SGrant Likely #endif /* DW_SPI_HEADER_H */ 228