1ca632f55SGrant Likely #ifndef DW_SPI_HEADER_H 2ca632f55SGrant Likely #define DW_SPI_HEADER_H 3ca632f55SGrant Likely 4ca632f55SGrant Likely #include <linux/io.h> 5ca632f55SGrant Likely #include <linux/scatterlist.h> 6d9c73bb8SBaruch Siach #include <linux/gpio.h> 7ca632f55SGrant Likely 87eb187b3SH Hartley Sweeten /* Register offsets */ 97eb187b3SH Hartley Sweeten #define DW_SPI_CTRL0 0x00 107eb187b3SH Hartley Sweeten #define DW_SPI_CTRL1 0x04 117eb187b3SH Hartley Sweeten #define DW_SPI_SSIENR 0x08 127eb187b3SH Hartley Sweeten #define DW_SPI_MWCR 0x0c 137eb187b3SH Hartley Sweeten #define DW_SPI_SER 0x10 147eb187b3SH Hartley Sweeten #define DW_SPI_BAUDR 0x14 157eb187b3SH Hartley Sweeten #define DW_SPI_TXFLTR 0x18 167eb187b3SH Hartley Sweeten #define DW_SPI_RXFLTR 0x1c 177eb187b3SH Hartley Sweeten #define DW_SPI_TXFLR 0x20 187eb187b3SH Hartley Sweeten #define DW_SPI_RXFLR 0x24 197eb187b3SH Hartley Sweeten #define DW_SPI_SR 0x28 207eb187b3SH Hartley Sweeten #define DW_SPI_IMR 0x2c 217eb187b3SH Hartley Sweeten #define DW_SPI_ISR 0x30 227eb187b3SH Hartley Sweeten #define DW_SPI_RISR 0x34 237eb187b3SH Hartley Sweeten #define DW_SPI_TXOICR 0x38 247eb187b3SH Hartley Sweeten #define DW_SPI_RXOICR 0x3c 257eb187b3SH Hartley Sweeten #define DW_SPI_RXUICR 0x40 267eb187b3SH Hartley Sweeten #define DW_SPI_MSTICR 0x44 277eb187b3SH Hartley Sweeten #define DW_SPI_ICR 0x48 287eb187b3SH Hartley Sweeten #define DW_SPI_DMACR 0x4c 297eb187b3SH Hartley Sweeten #define DW_SPI_DMATDLR 0x50 307eb187b3SH Hartley Sweeten #define DW_SPI_DMARDLR 0x54 317eb187b3SH Hartley Sweeten #define DW_SPI_IDR 0x58 327eb187b3SH Hartley Sweeten #define DW_SPI_VERSION 0x5c 337eb187b3SH Hartley Sweeten #define DW_SPI_DR 0x60 347eb187b3SH Hartley Sweeten 35ca632f55SGrant Likely /* Bit fields in CTRLR0 */ 36ca632f55SGrant Likely #define SPI_DFS_OFFSET 0 37ca632f55SGrant Likely 38ca632f55SGrant Likely #define SPI_FRF_OFFSET 4 39ca632f55SGrant Likely #define SPI_FRF_SPI 0x0 40ca632f55SGrant Likely #define SPI_FRF_SSP 0x1 41ca632f55SGrant Likely #define SPI_FRF_MICROWIRE 0x2 42ca632f55SGrant Likely #define SPI_FRF_RESV 0x3 43ca632f55SGrant Likely 44ca632f55SGrant Likely #define SPI_MODE_OFFSET 6 45ca632f55SGrant Likely #define SPI_SCPH_OFFSET 6 46ca632f55SGrant Likely #define SPI_SCOL_OFFSET 7 47ca632f55SGrant Likely 48ca632f55SGrant Likely #define SPI_TMOD_OFFSET 8 49ca632f55SGrant Likely #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) 50ca632f55SGrant Likely #define SPI_TMOD_TR 0x0 /* xmit & recv */ 51ca632f55SGrant Likely #define SPI_TMOD_TO 0x1 /* xmit only */ 52ca632f55SGrant Likely #define SPI_TMOD_RO 0x2 /* recv only */ 53ca632f55SGrant Likely #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ 54ca632f55SGrant Likely 55ca632f55SGrant Likely #define SPI_SLVOE_OFFSET 10 56ca632f55SGrant Likely #define SPI_SRL_OFFSET 11 57ca632f55SGrant Likely #define SPI_CFS_OFFSET 12 58ca632f55SGrant Likely 59ca632f55SGrant Likely /* Bit fields in SR, 7 bits */ 60ca632f55SGrant Likely #define SR_MASK 0x7f /* cover 7 bits */ 61ca632f55SGrant Likely #define SR_BUSY (1 << 0) 62ca632f55SGrant Likely #define SR_TF_NOT_FULL (1 << 1) 63ca632f55SGrant Likely #define SR_TF_EMPT (1 << 2) 64ca632f55SGrant Likely #define SR_RF_NOT_EMPT (1 << 3) 65ca632f55SGrant Likely #define SR_RF_FULL (1 << 4) 66ca632f55SGrant Likely #define SR_TX_ERR (1 << 5) 67ca632f55SGrant Likely #define SR_DCOL (1 << 6) 68ca632f55SGrant Likely 69ca632f55SGrant Likely /* Bit fields in ISR, IMR, RISR, 7 bits */ 70ca632f55SGrant Likely #define SPI_INT_TXEI (1 << 0) 71ca632f55SGrant Likely #define SPI_INT_TXOI (1 << 1) 72ca632f55SGrant Likely #define SPI_INT_RXUI (1 << 2) 73ca632f55SGrant Likely #define SPI_INT_RXOI (1 << 3) 74ca632f55SGrant Likely #define SPI_INT_RXFI (1 << 4) 75ca632f55SGrant Likely #define SPI_INT_MSTI (1 << 5) 76ca632f55SGrant Likely 7715ee3be7SAndy Shevchenko /* Bit fields in DMACR */ 7815ee3be7SAndy Shevchenko #define SPI_DMA_RDMAE (1 << 0) 7915ee3be7SAndy Shevchenko #define SPI_DMA_TDMAE (1 << 1) 8015ee3be7SAndy Shevchenko 81ca632f55SGrant Likely /* TX RX interrupt level threshold, max can be 256 */ 82ca632f55SGrant Likely #define SPI_INT_THRESHOLD 32 83ca632f55SGrant Likely 84ca632f55SGrant Likely enum dw_ssi_type { 85ca632f55SGrant Likely SSI_MOTO_SPI = 0, 86ca632f55SGrant Likely SSI_TI_SSP, 87ca632f55SGrant Likely SSI_NS_MICROWIRE, 88ca632f55SGrant Likely }; 89ca632f55SGrant Likely 90ca632f55SGrant Likely struct dw_spi; 91ca632f55SGrant Likely struct dw_spi_dma_ops { 92ca632f55SGrant Likely int (*dma_init)(struct dw_spi *dws); 93ca632f55SGrant Likely void (*dma_exit)(struct dw_spi *dws); 94f89a6d8fSAndy Shevchenko int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer); 95f89a6d8fSAndy Shevchenko bool (*can_dma)(struct spi_master *master, struct spi_device *spi, 96f89a6d8fSAndy Shevchenko struct spi_transfer *xfer); 97f89a6d8fSAndy Shevchenko int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer); 984d5ac1edSAndy Shevchenko void (*dma_stop)(struct dw_spi *dws); 99ca632f55SGrant Likely }; 100ca632f55SGrant Likely 101ca632f55SGrant Likely struct dw_spi { 102ca632f55SGrant Likely struct spi_master *master; 103ca632f55SGrant Likely enum dw_ssi_type type; 10440bfff85SLiu, ShuoX char name[16]; 105ca632f55SGrant Likely 106ca632f55SGrant Likely void __iomem *regs; 107ca632f55SGrant Likely unsigned long paddr; 108ca632f55SGrant Likely int irq; 109ca632f55SGrant Likely u32 fifo_len; /* depth of the FIFO buffer */ 110ca632f55SGrant Likely u32 max_freq; /* max bus freq supported */ 111ca632f55SGrant Likely 112c4fe57f7SMichael van der Westhuizen u32 reg_io_width; /* DR I/O width in bytes */ 113ca632f55SGrant Likely u16 bus_num; 114ca632f55SGrant Likely u16 num_cs; /* supported slave numbers */ 115ca632f55SGrant Likely 116ca632f55SGrant Likely /* Current message transfer state info */ 117ca632f55SGrant Likely size_t len; 118ca632f55SGrant Likely void *tx; 119ca632f55SGrant Likely void *tx_end; 120ca632f55SGrant Likely void *rx; 121ca632f55SGrant Likely void *rx_end; 122ca632f55SGrant Likely int dma_mapped; 123ca632f55SGrant Likely u8 n_bytes; /* current is a 1/2 bytes op */ 124ca632f55SGrant Likely u32 dma_width; 125ca632f55SGrant Likely irqreturn_t (*transfer_handler)(struct dw_spi *dws); 126*13b10301SMatthias Seidel u32 current_freq; /* frequency in hz */ 127ca632f55SGrant Likely 128f89a6d8fSAndy Shevchenko /* DMA info */ 129ca632f55SGrant Likely int dma_inited; 130ca632f55SGrant Likely struct dma_chan *txchan; 131ca632f55SGrant Likely struct dma_chan *rxchan; 13230c8eb52SAndy Shevchenko unsigned long dma_chan_busy; 133ca632f55SGrant Likely dma_addr_t dma_addr; /* phy address of the Data register */ 1344fe338c9SJulia Lawall const struct dw_spi_dma_ops *dma_ops; 135d744f826SAndy Shevchenko void *dma_tx; 136d744f826SAndy Shevchenko void *dma_rx; 137ca632f55SGrant Likely 138ca632f55SGrant Likely /* Bus interface info */ 139ca632f55SGrant Likely void *priv; 140ca632f55SGrant Likely #ifdef CONFIG_DEBUG_FS 141ca632f55SGrant Likely struct dentry *debugfs; 142ca632f55SGrant Likely #endif 143ca632f55SGrant Likely }; 144ca632f55SGrant Likely 1457eb187b3SH Hartley Sweeten static inline u32 dw_readl(struct dw_spi *dws, u32 offset) 1467eb187b3SH Hartley Sweeten { 1477eb187b3SH Hartley Sweeten return __raw_readl(dws->regs + offset); 1487eb187b3SH Hartley Sweeten } 1497eb187b3SH Hartley Sweeten 150c4fe57f7SMichael van der Westhuizen static inline u16 dw_readw(struct dw_spi *dws, u32 offset) 151c4fe57f7SMichael van der Westhuizen { 152c4fe57f7SMichael van der Westhuizen return __raw_readw(dws->regs + offset); 153c4fe57f7SMichael van der Westhuizen } 154c4fe57f7SMichael van der Westhuizen 1557eb187b3SH Hartley Sweeten static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) 1567eb187b3SH Hartley Sweeten { 1577eb187b3SH Hartley Sweeten __raw_writel(val, dws->regs + offset); 1587eb187b3SH Hartley Sweeten } 1597eb187b3SH Hartley Sweeten 160c4fe57f7SMichael van der Westhuizen static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) 161c4fe57f7SMichael van der Westhuizen { 162c4fe57f7SMichael van der Westhuizen __raw_writew(val, dws->regs + offset); 163c4fe57f7SMichael van der Westhuizen } 164c4fe57f7SMichael van der Westhuizen 165c4fe57f7SMichael van der Westhuizen static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) 166c4fe57f7SMichael van der Westhuizen { 167c4fe57f7SMichael van der Westhuizen switch (dws->reg_io_width) { 168c4fe57f7SMichael van der Westhuizen case 2: 169c4fe57f7SMichael van der Westhuizen return dw_readw(dws, offset); 170c4fe57f7SMichael van der Westhuizen case 4: 171c4fe57f7SMichael van der Westhuizen default: 172c4fe57f7SMichael van der Westhuizen return dw_readl(dws, offset); 173c4fe57f7SMichael van der Westhuizen } 174c4fe57f7SMichael van der Westhuizen } 175c4fe57f7SMichael van der Westhuizen 176c4fe57f7SMichael van der Westhuizen static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) 177c4fe57f7SMichael van der Westhuizen { 178c4fe57f7SMichael van der Westhuizen switch (dws->reg_io_width) { 179c4fe57f7SMichael van der Westhuizen case 2: 180c4fe57f7SMichael van der Westhuizen dw_writew(dws, offset, val); 181c4fe57f7SMichael van der Westhuizen break; 182c4fe57f7SMichael van der Westhuizen case 4: 183c4fe57f7SMichael van der Westhuizen default: 184c4fe57f7SMichael van der Westhuizen dw_writel(dws, offset, val); 185c4fe57f7SMichael van der Westhuizen break; 186c4fe57f7SMichael van der Westhuizen } 187c4fe57f7SMichael van der Westhuizen } 188c4fe57f7SMichael van der Westhuizen 189ca632f55SGrant Likely static inline void spi_enable_chip(struct dw_spi *dws, int enable) 190ca632f55SGrant Likely { 1917eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); 192ca632f55SGrant Likely } 193ca632f55SGrant Likely 194ca632f55SGrant Likely static inline void spi_set_clk(struct dw_spi *dws, u16 div) 195ca632f55SGrant Likely { 1967eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_BAUDR, div); 197ca632f55SGrant Likely } 198ca632f55SGrant Likely 199ca632f55SGrant Likely /* Disable IRQ bits */ 200ca632f55SGrant Likely static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) 201ca632f55SGrant Likely { 202ca632f55SGrant Likely u32 new_mask; 203ca632f55SGrant Likely 2047eb187b3SH Hartley Sweeten new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; 2057eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_IMR, new_mask); 206ca632f55SGrant Likely } 207ca632f55SGrant Likely 208ca632f55SGrant Likely /* Enable IRQ bits */ 209ca632f55SGrant Likely static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) 210ca632f55SGrant Likely { 211ca632f55SGrant Likely u32 new_mask; 212ca632f55SGrant Likely 2137eb187b3SH Hartley Sweeten new_mask = dw_readl(dws, DW_SPI_IMR) | mask; 2147eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_IMR, new_mask); 215ca632f55SGrant Likely } 216ca632f55SGrant Likely 217ca632f55SGrant Likely /* 21845746e82SAndy Shevchenko * This does disable the SPI controller, interrupts, and re-enable the 21945746e82SAndy Shevchenko * controller back. Transmit and receive FIFO buffers are cleared when the 22045746e82SAndy Shevchenko * device is disabled. 22145746e82SAndy Shevchenko */ 22245746e82SAndy Shevchenko static inline void spi_reset_chip(struct dw_spi *dws) 22345746e82SAndy Shevchenko { 22445746e82SAndy Shevchenko spi_enable_chip(dws, 0); 22545746e82SAndy Shevchenko spi_mask_intr(dws, 0xff); 22645746e82SAndy Shevchenko spi_enable_chip(dws, 1); 22745746e82SAndy Shevchenko } 22845746e82SAndy Shevchenko 2291cc3f141SAndy Shevchenko static inline void spi_shutdown_chip(struct dw_spi *dws) 2301cc3f141SAndy Shevchenko { 2311cc3f141SAndy Shevchenko spi_enable_chip(dws, 0); 2321cc3f141SAndy Shevchenko spi_set_clk(dws, 0); 2331cc3f141SAndy Shevchenko } 2341cc3f141SAndy Shevchenko 23545746e82SAndy Shevchenko /* 236ca632f55SGrant Likely * Each SPI slave device to work with dw_api controller should 237f89a6d8fSAndy Shevchenko * has such a structure claiming its working mode (poll or PIO/DMA), 238ca632f55SGrant Likely * which can be save in the "controller_data" member of the 23905ed2aeeSAndy Shevchenko * struct spi_device. 240ca632f55SGrant Likely */ 241ca632f55SGrant Likely struct dw_spi_chip { 24205ed2aeeSAndy Shevchenko u8 poll_mode; /* 1 for controller polling mode */ 24305ed2aeeSAndy Shevchenko u8 type; /* SPI/SSP/MicroWire */ 244ca632f55SGrant Likely void (*cs_control)(u32 command); 245ca632f55SGrant Likely }; 246ca632f55SGrant Likely 24704f421e7SBaruch Siach extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); 248ca632f55SGrant Likely extern void dw_spi_remove_host(struct dw_spi *dws); 249ca632f55SGrant Likely extern int dw_spi_suspend_host(struct dw_spi *dws); 250ca632f55SGrant Likely extern int dw_spi_resume_host(struct dw_spi *dws); 251ca632f55SGrant Likely 252ca632f55SGrant Likely /* platform related setup */ 253ca632f55SGrant Likely extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ 254ca632f55SGrant Likely #endif /* DW_SPI_HEADER_H */ 255