1ca632f55SGrant Likely #ifndef DW_SPI_HEADER_H 2ca632f55SGrant Likely #define DW_SPI_HEADER_H 3ca632f55SGrant Likely 4ca632f55SGrant Likely #include <linux/io.h> 5ca632f55SGrant Likely #include <linux/scatterlist.h> 6ca632f55SGrant Likely 77eb187b3SH Hartley Sweeten /* Register offsets */ 87eb187b3SH Hartley Sweeten #define DW_SPI_CTRL0 0x00 97eb187b3SH Hartley Sweeten #define DW_SPI_CTRL1 0x04 107eb187b3SH Hartley Sweeten #define DW_SPI_SSIENR 0x08 117eb187b3SH Hartley Sweeten #define DW_SPI_MWCR 0x0c 127eb187b3SH Hartley Sweeten #define DW_SPI_SER 0x10 137eb187b3SH Hartley Sweeten #define DW_SPI_BAUDR 0x14 147eb187b3SH Hartley Sweeten #define DW_SPI_TXFLTR 0x18 157eb187b3SH Hartley Sweeten #define DW_SPI_RXFLTR 0x1c 167eb187b3SH Hartley Sweeten #define DW_SPI_TXFLR 0x20 177eb187b3SH Hartley Sweeten #define DW_SPI_RXFLR 0x24 187eb187b3SH Hartley Sweeten #define DW_SPI_SR 0x28 197eb187b3SH Hartley Sweeten #define DW_SPI_IMR 0x2c 207eb187b3SH Hartley Sweeten #define DW_SPI_ISR 0x30 217eb187b3SH Hartley Sweeten #define DW_SPI_RISR 0x34 227eb187b3SH Hartley Sweeten #define DW_SPI_TXOICR 0x38 237eb187b3SH Hartley Sweeten #define DW_SPI_RXOICR 0x3c 247eb187b3SH Hartley Sweeten #define DW_SPI_RXUICR 0x40 257eb187b3SH Hartley Sweeten #define DW_SPI_MSTICR 0x44 267eb187b3SH Hartley Sweeten #define DW_SPI_ICR 0x48 277eb187b3SH Hartley Sweeten #define DW_SPI_DMACR 0x4c 287eb187b3SH Hartley Sweeten #define DW_SPI_DMATDLR 0x50 297eb187b3SH Hartley Sweeten #define DW_SPI_DMARDLR 0x54 307eb187b3SH Hartley Sweeten #define DW_SPI_IDR 0x58 317eb187b3SH Hartley Sweeten #define DW_SPI_VERSION 0x5c 327eb187b3SH Hartley Sweeten #define DW_SPI_DR 0x60 337eb187b3SH Hartley Sweeten 34ca632f55SGrant Likely /* Bit fields in CTRLR0 */ 35ca632f55SGrant Likely #define SPI_DFS_OFFSET 0 36ca632f55SGrant Likely 37ca632f55SGrant Likely #define SPI_FRF_OFFSET 4 38ca632f55SGrant Likely #define SPI_FRF_SPI 0x0 39ca632f55SGrant Likely #define SPI_FRF_SSP 0x1 40ca632f55SGrant Likely #define SPI_FRF_MICROWIRE 0x2 41ca632f55SGrant Likely #define SPI_FRF_RESV 0x3 42ca632f55SGrant Likely 43ca632f55SGrant Likely #define SPI_MODE_OFFSET 6 44ca632f55SGrant Likely #define SPI_SCPH_OFFSET 6 45ca632f55SGrant Likely #define SPI_SCOL_OFFSET 7 46ca632f55SGrant Likely 47ca632f55SGrant Likely #define SPI_TMOD_OFFSET 8 48ca632f55SGrant Likely #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) 49ca632f55SGrant Likely #define SPI_TMOD_TR 0x0 /* xmit & recv */ 50ca632f55SGrant Likely #define SPI_TMOD_TO 0x1 /* xmit only */ 51ca632f55SGrant Likely #define SPI_TMOD_RO 0x2 /* recv only */ 52ca632f55SGrant Likely #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ 53ca632f55SGrant Likely 54ca632f55SGrant Likely #define SPI_SLVOE_OFFSET 10 55ca632f55SGrant Likely #define SPI_SRL_OFFSET 11 56ca632f55SGrant Likely #define SPI_CFS_OFFSET 12 57ca632f55SGrant Likely 58ca632f55SGrant Likely /* Bit fields in SR, 7 bits */ 59ca632f55SGrant Likely #define SR_MASK 0x7f /* cover 7 bits */ 60ca632f55SGrant Likely #define SR_BUSY (1 << 0) 61ca632f55SGrant Likely #define SR_TF_NOT_FULL (1 << 1) 62ca632f55SGrant Likely #define SR_TF_EMPT (1 << 2) 63ca632f55SGrant Likely #define SR_RF_NOT_EMPT (1 << 3) 64ca632f55SGrant Likely #define SR_RF_FULL (1 << 4) 65ca632f55SGrant Likely #define SR_TX_ERR (1 << 5) 66ca632f55SGrant Likely #define SR_DCOL (1 << 6) 67ca632f55SGrant Likely 68ca632f55SGrant Likely /* Bit fields in ISR, IMR, RISR, 7 bits */ 69ca632f55SGrant Likely #define SPI_INT_TXEI (1 << 0) 70ca632f55SGrant Likely #define SPI_INT_TXOI (1 << 1) 71ca632f55SGrant Likely #define SPI_INT_RXUI (1 << 2) 72ca632f55SGrant Likely #define SPI_INT_RXOI (1 << 3) 73ca632f55SGrant Likely #define SPI_INT_RXFI (1 << 4) 74ca632f55SGrant Likely #define SPI_INT_MSTI (1 << 5) 75ca632f55SGrant Likely 76ca632f55SGrant Likely /* TX RX interrupt level threshold, max can be 256 */ 77ca632f55SGrant Likely #define SPI_INT_THRESHOLD 32 78ca632f55SGrant Likely 79ca632f55SGrant Likely enum dw_ssi_type { 80ca632f55SGrant Likely SSI_MOTO_SPI = 0, 81ca632f55SGrant Likely SSI_TI_SSP, 82ca632f55SGrant Likely SSI_NS_MICROWIRE, 83ca632f55SGrant Likely }; 84ca632f55SGrant Likely 85ca632f55SGrant Likely struct dw_spi; 86ca632f55SGrant Likely struct dw_spi_dma_ops { 87ca632f55SGrant Likely int (*dma_init)(struct dw_spi *dws); 88ca632f55SGrant Likely void (*dma_exit)(struct dw_spi *dws); 89ca632f55SGrant Likely int (*dma_transfer)(struct dw_spi *dws, int cs_change); 90ca632f55SGrant Likely }; 91ca632f55SGrant Likely 92ca632f55SGrant Likely struct dw_spi { 93ca632f55SGrant Likely struct spi_master *master; 94ca632f55SGrant Likely struct spi_device *cur_dev; 95ca632f55SGrant Likely enum dw_ssi_type type; 9640bfff85SLiu, ShuoX char name[16]; 97ca632f55SGrant Likely 98ca632f55SGrant Likely void __iomem *regs; 99ca632f55SGrant Likely unsigned long paddr; 100ca632f55SGrant Likely int irq; 101ca632f55SGrant Likely u32 fifo_len; /* depth of the FIFO buffer */ 102ca632f55SGrant Likely u32 max_freq; /* max bus freq supported */ 103ca632f55SGrant Likely 104ca632f55SGrant Likely u16 bus_num; 105ca632f55SGrant Likely u16 num_cs; /* supported slave numbers */ 106ca632f55SGrant Likely 107ca632f55SGrant Likely /* Driver message queue */ 108ca632f55SGrant Likely struct workqueue_struct *workqueue; 109ca632f55SGrant Likely struct work_struct pump_messages; 110ca632f55SGrant Likely spinlock_t lock; 111ca632f55SGrant Likely struct list_head queue; 112ca632f55SGrant Likely int busy; 113ca632f55SGrant Likely int run; 114ca632f55SGrant Likely 115ca632f55SGrant Likely /* Message Transfer pump */ 116ca632f55SGrant Likely struct tasklet_struct pump_transfers; 117ca632f55SGrant Likely 118ca632f55SGrant Likely /* Current message transfer state info */ 119ca632f55SGrant Likely struct spi_message *cur_msg; 120ca632f55SGrant Likely struct spi_transfer *cur_transfer; 121ca632f55SGrant Likely struct chip_data *cur_chip; 122ca632f55SGrant Likely struct chip_data *prev_chip; 123ca632f55SGrant Likely size_t len; 124ca632f55SGrant Likely void *tx; 125ca632f55SGrant Likely void *tx_end; 126ca632f55SGrant Likely void *rx; 127ca632f55SGrant Likely void *rx_end; 128ca632f55SGrant Likely int dma_mapped; 129ca632f55SGrant Likely dma_addr_t rx_dma; 130ca632f55SGrant Likely dma_addr_t tx_dma; 131ca632f55SGrant Likely size_t rx_map_len; 132ca632f55SGrant Likely size_t tx_map_len; 133ca632f55SGrant Likely u8 n_bytes; /* current is a 1/2 bytes op */ 134ca632f55SGrant Likely u8 max_bits_per_word; /* maxim is 16b */ 135ca632f55SGrant Likely u32 dma_width; 136ca632f55SGrant Likely irqreturn_t (*transfer_handler)(struct dw_spi *dws); 137ca632f55SGrant Likely void (*cs_control)(u32 command); 138ca632f55SGrant Likely 139ca632f55SGrant Likely /* Dma info */ 140ca632f55SGrant Likely int dma_inited; 141ca632f55SGrant Likely struct dma_chan *txchan; 142ca632f55SGrant Likely struct scatterlist tx_sgl; 143ca632f55SGrant Likely struct dma_chan *rxchan; 144ca632f55SGrant Likely struct scatterlist rx_sgl; 145ca632f55SGrant Likely int dma_chan_done; 146ca632f55SGrant Likely struct device *dma_dev; 147ca632f55SGrant Likely dma_addr_t dma_addr; /* phy address of the Data register */ 148ca632f55SGrant Likely struct dw_spi_dma_ops *dma_ops; 149ca632f55SGrant Likely void *dma_priv; /* platform relate info */ 150ca632f55SGrant Likely struct pci_dev *dmac; 151ca632f55SGrant Likely 152ca632f55SGrant Likely /* Bus interface info */ 153ca632f55SGrant Likely void *priv; 154ca632f55SGrant Likely #ifdef CONFIG_DEBUG_FS 155ca632f55SGrant Likely struct dentry *debugfs; 156ca632f55SGrant Likely #endif 157ca632f55SGrant Likely }; 158ca632f55SGrant Likely 1597eb187b3SH Hartley Sweeten static inline u32 dw_readl(struct dw_spi *dws, u32 offset) 1607eb187b3SH Hartley Sweeten { 1617eb187b3SH Hartley Sweeten return __raw_readl(dws->regs + offset); 1627eb187b3SH Hartley Sweeten } 1637eb187b3SH Hartley Sweeten 1647eb187b3SH Hartley Sweeten static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) 1657eb187b3SH Hartley Sweeten { 1667eb187b3SH Hartley Sweeten __raw_writel(val, dws->regs + offset); 1677eb187b3SH Hartley Sweeten } 1687eb187b3SH Hartley Sweeten 1697eb187b3SH Hartley Sweeten static inline u16 dw_readw(struct dw_spi *dws, u32 offset) 1707eb187b3SH Hartley Sweeten { 1717eb187b3SH Hartley Sweeten return __raw_readw(dws->regs + offset); 1727eb187b3SH Hartley Sweeten } 1737eb187b3SH Hartley Sweeten 1747eb187b3SH Hartley Sweeten static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) 1757eb187b3SH Hartley Sweeten { 1767eb187b3SH Hartley Sweeten __raw_writew(val, dws->regs + offset); 1777eb187b3SH Hartley Sweeten } 178ca632f55SGrant Likely 179ca632f55SGrant Likely static inline void spi_enable_chip(struct dw_spi *dws, int enable) 180ca632f55SGrant Likely { 1817eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); 182ca632f55SGrant Likely } 183ca632f55SGrant Likely 184ca632f55SGrant Likely static inline void spi_set_clk(struct dw_spi *dws, u16 div) 185ca632f55SGrant Likely { 1867eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_BAUDR, div); 187ca632f55SGrant Likely } 188ca632f55SGrant Likely 189ca632f55SGrant Likely static inline void spi_chip_sel(struct dw_spi *dws, u16 cs) 190ca632f55SGrant Likely { 191ca632f55SGrant Likely if (cs > dws->num_cs) 192ca632f55SGrant Likely return; 193ca632f55SGrant Likely 194ca632f55SGrant Likely if (dws->cs_control) 195ca632f55SGrant Likely dws->cs_control(1); 196ca632f55SGrant Likely 1977eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_SER, 1 << cs); 198ca632f55SGrant Likely } 199ca632f55SGrant Likely 200ca632f55SGrant Likely /* Disable IRQ bits */ 201ca632f55SGrant Likely static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) 202ca632f55SGrant Likely { 203ca632f55SGrant Likely u32 new_mask; 204ca632f55SGrant Likely 2057eb187b3SH Hartley Sweeten new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; 2067eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_IMR, new_mask); 207ca632f55SGrant Likely } 208ca632f55SGrant Likely 209ca632f55SGrant Likely /* Enable IRQ bits */ 210ca632f55SGrant Likely static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) 211ca632f55SGrant Likely { 212ca632f55SGrant Likely u32 new_mask; 213ca632f55SGrant Likely 2147eb187b3SH Hartley Sweeten new_mask = dw_readl(dws, DW_SPI_IMR) | mask; 2157eb187b3SH Hartley Sweeten dw_writel(dws, DW_SPI_IMR, new_mask); 216ca632f55SGrant Likely } 217ca632f55SGrant Likely 218ca632f55SGrant Likely /* 219ca632f55SGrant Likely * Each SPI slave device to work with dw_api controller should 220ca632f55SGrant Likely * has such a structure claiming its working mode (PIO/DMA etc), 221ca632f55SGrant Likely * which can be save in the "controller_data" member of the 222ca632f55SGrant Likely * struct spi_device 223ca632f55SGrant Likely */ 224ca632f55SGrant Likely struct dw_spi_chip { 225ca632f55SGrant Likely u8 poll_mode; /* 0 for contoller polling mode */ 226ca632f55SGrant Likely u8 type; /* SPI/SSP/Micrwire */ 227ca632f55SGrant Likely u8 enable_dma; 228ca632f55SGrant Likely void (*cs_control)(u32 command); 229ca632f55SGrant Likely }; 230ca632f55SGrant Likely 231*04f421e7SBaruch Siach extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); 232ca632f55SGrant Likely extern void dw_spi_remove_host(struct dw_spi *dws); 233ca632f55SGrant Likely extern int dw_spi_suspend_host(struct dw_spi *dws); 234ca632f55SGrant Likely extern int dw_spi_resume_host(struct dw_spi *dws); 235ca632f55SGrant Likely extern void dw_spi_xfer_done(struct dw_spi *dws); 236ca632f55SGrant Likely 237ca632f55SGrant Likely /* platform related setup */ 238ca632f55SGrant Likely extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */ 239ca632f55SGrant Likely #endif /* DW_SPI_HEADER_H */ 240