1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * PCI interface driver for DW SPI Core
4 *
5 * Copyright (c) 2009, 2014 Intel Corporation.
6 */
7
8 #include <linux/pci.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/slab.h>
11 #include <linux/spi/spi.h>
12 #include <linux/module.h>
13
14 #include "spi-dw.h"
15
16 #define DRIVER_NAME "dw_spi_pci"
17
18 /* HW info for MRST Clk Control Unit, 32b reg per controller */
19 #define MRST_SPI_CLK_BASE 100000000 /* 100m */
20 #define MRST_CLK_SPI_REG 0xff11d86c
21 #define CLK_SPI_BDIV_OFFSET 0
22 #define CLK_SPI_BDIV_MASK 0x00000007
23 #define CLK_SPI_CDIV_OFFSET 9
24 #define CLK_SPI_CDIV_MASK 0x00000e00
25 #define CLK_SPI_DISABLE_OFFSET 8
26
27 struct dw_spi_pci_desc {
28 int (*setup)(struct dw_spi *);
29 u16 num_cs;
30 u16 bus_num;
31 u32 max_freq;
32 };
33
dw_spi_pci_mid_init(struct dw_spi * dws)34 static int dw_spi_pci_mid_init(struct dw_spi *dws)
35 {
36 void __iomem *clk_reg;
37 u32 clk_cdiv;
38
39 clk_reg = ioremap(MRST_CLK_SPI_REG, 16);
40 if (!clk_reg)
41 return -ENOMEM;
42
43 /* Get SPI controller operating freq info */
44 clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
45 clk_cdiv &= CLK_SPI_CDIV_MASK;
46 clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
47 dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
48
49 iounmap(clk_reg);
50
51 dw_spi_dma_setup_mfld(dws);
52
53 return 0;
54 }
55
dw_spi_pci_generic_init(struct dw_spi * dws)56 static int dw_spi_pci_generic_init(struct dw_spi *dws)
57 {
58 dw_spi_dma_setup_generic(dws);
59
60 return 0;
61 }
62
63 static struct dw_spi_pci_desc dw_spi_pci_mid_desc_1 = {
64 .setup = dw_spi_pci_mid_init,
65 .num_cs = 5,
66 .bus_num = 0,
67 };
68
69 static struct dw_spi_pci_desc dw_spi_pci_mid_desc_2 = {
70 .setup = dw_spi_pci_mid_init,
71 .num_cs = 2,
72 .bus_num = 1,
73 };
74
75 static struct dw_spi_pci_desc dw_spi_pci_ehl_desc = {
76 .setup = dw_spi_pci_generic_init,
77 .num_cs = 2,
78 .bus_num = -1,
79 .max_freq = 100000000,
80 };
81
dw_spi_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)82 static int dw_spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
83 {
84 struct dw_spi_pci_desc *desc = (struct dw_spi_pci_desc *)ent->driver_data;
85 struct dw_spi *dws;
86 int pci_bar = 0;
87 int ret;
88
89 ret = pcim_enable_device(pdev);
90 if (ret)
91 return ret;
92
93 dws = devm_kzalloc(&pdev->dev, sizeof(*dws), GFP_KERNEL);
94 if (!dws)
95 return -ENOMEM;
96
97 /* Get basic io resource and map it */
98 dws->paddr = pci_resource_start(pdev, pci_bar);
99 pci_set_master(pdev);
100
101 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
102 if (ret < 0)
103 return ret;
104
105 dws->regs = pcim_iomap_region(pdev, pci_bar, pci_name(pdev));
106 if (IS_ERR(dws->regs))
107 return PTR_ERR(dws->regs);
108
109 dws->irq = pci_irq_vector(pdev, 0);
110
111 /*
112 * Specific handling for platforms, like dma setup,
113 * clock rate, FIFO depth.
114 */
115 if (desc) {
116 dws->num_cs = desc->num_cs;
117 dws->bus_num = desc->bus_num;
118 dws->max_freq = desc->max_freq;
119
120 if (desc->setup) {
121 ret = desc->setup(dws);
122 if (ret)
123 goto err_free_irq_vectors;
124 }
125 } else {
126 ret = -ENODEV;
127 goto err_free_irq_vectors;
128 }
129
130 ret = dw_spi_add_host(&pdev->dev, dws);
131 if (ret)
132 goto err_free_irq_vectors;
133
134 /* PCI hook and SPI hook use the same drv data */
135 pci_set_drvdata(pdev, dws);
136
137 dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n",
138 pdev->vendor, pdev->device);
139
140 pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
141 pm_runtime_use_autosuspend(&pdev->dev);
142 pm_runtime_put_autosuspend(&pdev->dev);
143 pm_runtime_allow(&pdev->dev);
144
145 return 0;
146
147 err_free_irq_vectors:
148 pci_free_irq_vectors(pdev);
149 return ret;
150 }
151
dw_spi_pci_remove(struct pci_dev * pdev)152 static void dw_spi_pci_remove(struct pci_dev *pdev)
153 {
154 struct dw_spi *dws = pci_get_drvdata(pdev);
155
156 pm_runtime_forbid(&pdev->dev);
157 pm_runtime_get_noresume(&pdev->dev);
158
159 dw_spi_remove_host(dws);
160 pci_free_irq_vectors(pdev);
161 }
162
163 #ifdef CONFIG_PM_SLEEP
dw_spi_pci_suspend(struct device * dev)164 static int dw_spi_pci_suspend(struct device *dev)
165 {
166 struct dw_spi *dws = dev_get_drvdata(dev);
167
168 return dw_spi_suspend_host(dws);
169 }
170
dw_spi_pci_resume(struct device * dev)171 static int dw_spi_pci_resume(struct device *dev)
172 {
173 struct dw_spi *dws = dev_get_drvdata(dev);
174
175 return dw_spi_resume_host(dws);
176 }
177 #endif
178
179 static SIMPLE_DEV_PM_OPS(dw_spi_pci_pm_ops, dw_spi_pci_suspend, dw_spi_pci_resume);
180
181 static const struct pci_device_id dw_spi_pci_ids[] = {
182 /* Intel MID platform SPI controller 0 */
183 /*
184 * The access to the device 8086:0801 is disabled by HW, since it's
185 * exclusively used by SCU to communicate with MSIC.
186 */
187 /* Intel MID platform SPI controller 1 */
188 { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&dw_spi_pci_mid_desc_1},
189 /* Intel MID platform SPI controller 2 */
190 { PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&dw_spi_pci_mid_desc_2},
191 /* Intel Elkhart Lake PSE SPI controllers */
192 { PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&dw_spi_pci_ehl_desc},
193 { PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&dw_spi_pci_ehl_desc},
194 { PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&dw_spi_pci_ehl_desc},
195 { PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&dw_spi_pci_ehl_desc},
196 {},
197 };
198 MODULE_DEVICE_TABLE(pci, dw_spi_pci_ids);
199
200 static struct pci_driver dw_spi_pci_driver = {
201 .name = DRIVER_NAME,
202 .id_table = dw_spi_pci_ids,
203 .probe = dw_spi_pci_probe,
204 .remove = dw_spi_pci_remove,
205 .driver = {
206 .pm = &dw_spi_pci_pm_ops,
207 },
208 };
209 module_pci_driver(dw_spi_pci_driver);
210
211 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
212 MODULE_DESCRIPTION("PCI interface driver for DW SPI Core");
213 MODULE_LICENSE("GPL v2");
214 MODULE_IMPORT_NS("SPI_DW_CORE");
215