1 /* 2 * Copyright (C) 2009 Texas Instruments. 3 * Copyright (C) 2010 EF Johnson Technologies 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/gpio.h> 23 #include <linux/module.h> 24 #include <linux/delay.h> 25 #include <linux/platform_device.h> 26 #include <linux/err.h> 27 #include <linux/clk.h> 28 #include <linux/dmaengine.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/edma.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/of_gpio.h> 34 #include <linux/spi/spi.h> 35 #include <linux/spi/spi_bitbang.h> 36 #include <linux/slab.h> 37 38 #include <linux/platform_data/spi-davinci.h> 39 40 #define SPI_NO_RESOURCE ((resource_size_t)-1) 41 42 #define CS_DEFAULT 0xFF 43 44 #define SPIFMT_PHASE_MASK BIT(16) 45 #define SPIFMT_POLARITY_MASK BIT(17) 46 #define SPIFMT_DISTIMER_MASK BIT(18) 47 #define SPIFMT_SHIFTDIR_MASK BIT(20) 48 #define SPIFMT_WAITENA_MASK BIT(21) 49 #define SPIFMT_PARITYENA_MASK BIT(22) 50 #define SPIFMT_ODD_PARITY_MASK BIT(23) 51 #define SPIFMT_WDELAY_MASK 0x3f000000u 52 #define SPIFMT_WDELAY_SHIFT 24 53 #define SPIFMT_PRESCALE_SHIFT 8 54 55 /* SPIPC0 */ 56 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ 57 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ 58 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ 59 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ 60 61 #define SPIINT_MASKALL 0x0101035F 62 #define SPIINT_MASKINT 0x0000015F 63 #define SPI_INTLVL_1 0x000001FF 64 #define SPI_INTLVL_0 0x00000000 65 66 /* SPIDAT1 (upper 16 bit defines) */ 67 #define SPIDAT1_CSHOLD_MASK BIT(12) 68 69 /* SPIGCR1 */ 70 #define SPIGCR1_CLKMOD_MASK BIT(1) 71 #define SPIGCR1_MASTER_MASK BIT(0) 72 #define SPIGCR1_POWERDOWN_MASK BIT(8) 73 #define SPIGCR1_LOOPBACK_MASK BIT(16) 74 #define SPIGCR1_SPIENA_MASK BIT(24) 75 76 /* SPIBUF */ 77 #define SPIBUF_TXFULL_MASK BIT(29) 78 #define SPIBUF_RXEMPTY_MASK BIT(31) 79 80 /* SPIDELAY */ 81 #define SPIDELAY_C2TDELAY_SHIFT 24 82 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) 83 #define SPIDELAY_T2CDELAY_SHIFT 16 84 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) 85 #define SPIDELAY_T2EDELAY_SHIFT 8 86 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) 87 #define SPIDELAY_C2EDELAY_SHIFT 0 88 #define SPIDELAY_C2EDELAY_MASK 0xFF 89 90 /* Error Masks */ 91 #define SPIFLG_DLEN_ERR_MASK BIT(0) 92 #define SPIFLG_TIMEOUT_MASK BIT(1) 93 #define SPIFLG_PARERR_MASK BIT(2) 94 #define SPIFLG_DESYNC_MASK BIT(3) 95 #define SPIFLG_BITERR_MASK BIT(4) 96 #define SPIFLG_OVRRUN_MASK BIT(6) 97 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) 98 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ 99 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ 100 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ 101 | SPIFLG_OVRRUN_MASK) 102 103 #define SPIINT_DMA_REQ_EN BIT(16) 104 105 /* SPI Controller registers */ 106 #define SPIGCR0 0x00 107 #define SPIGCR1 0x04 108 #define SPIINT 0x08 109 #define SPILVL 0x0c 110 #define SPIFLG 0x10 111 #define SPIPC0 0x14 112 #define SPIDAT1 0x3c 113 #define SPIBUF 0x40 114 #define SPIDELAY 0x48 115 #define SPIDEF 0x4c 116 #define SPIFMT0 0x50 117 118 /* SPI Controller driver's private data. */ 119 struct davinci_spi { 120 struct spi_bitbang bitbang; 121 struct clk *clk; 122 123 u8 version; 124 resource_size_t pbase; 125 void __iomem *base; 126 u32 irq; 127 struct completion done; 128 129 const void *tx; 130 void *rx; 131 int rcount; 132 int wcount; 133 134 struct dma_chan *dma_rx; 135 struct dma_chan *dma_tx; 136 int dma_rx_chnum; 137 int dma_tx_chnum; 138 139 struct davinci_spi_platform_data pdata; 140 141 void (*get_rx)(u32 rx_data, struct davinci_spi *); 142 u32 (*get_tx)(struct davinci_spi *); 143 144 u8 *bytes_per_word; 145 }; 146 147 static struct davinci_spi_config davinci_spi_default_cfg; 148 149 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) 150 { 151 if (dspi->rx) { 152 u8 *rx = dspi->rx; 153 *rx++ = (u8)data; 154 dspi->rx = rx; 155 } 156 } 157 158 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) 159 { 160 if (dspi->rx) { 161 u16 *rx = dspi->rx; 162 *rx++ = (u16)data; 163 dspi->rx = rx; 164 } 165 } 166 167 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) 168 { 169 u32 data = 0; 170 if (dspi->tx) { 171 const u8 *tx = dspi->tx; 172 data = *tx++; 173 dspi->tx = tx; 174 } 175 return data; 176 } 177 178 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) 179 { 180 u32 data = 0; 181 if (dspi->tx) { 182 const u16 *tx = dspi->tx; 183 data = *tx++; 184 dspi->tx = tx; 185 } 186 return data; 187 } 188 189 static inline void set_io_bits(void __iomem *addr, u32 bits) 190 { 191 u32 v = ioread32(addr); 192 193 v |= bits; 194 iowrite32(v, addr); 195 } 196 197 static inline void clear_io_bits(void __iomem *addr, u32 bits) 198 { 199 u32 v = ioread32(addr); 200 201 v &= ~bits; 202 iowrite32(v, addr); 203 } 204 205 /* 206 * Interface to control the chip select signal 207 */ 208 static void davinci_spi_chipselect(struct spi_device *spi, int value) 209 { 210 struct davinci_spi *dspi; 211 struct davinci_spi_platform_data *pdata; 212 u8 chip_sel = spi->chip_select; 213 u16 spidat1 = CS_DEFAULT; 214 bool gpio_chipsel = false; 215 int gpio; 216 217 dspi = spi_master_get_devdata(spi->master); 218 pdata = &dspi->pdata; 219 220 if (spi->cs_gpio >= 0) { 221 /* SPI core parse and update master->cs_gpio */ 222 gpio_chipsel = true; 223 gpio = spi->cs_gpio; 224 } 225 226 /* 227 * Board specific chip select logic decides the polarity and cs 228 * line for the controller 229 */ 230 if (gpio_chipsel) { 231 if (value == BITBANG_CS_ACTIVE) 232 gpio_set_value(gpio, spi->mode & SPI_CS_HIGH); 233 else 234 gpio_set_value(gpio, !(spi->mode & SPI_CS_HIGH)); 235 } else { 236 if (value == BITBANG_CS_ACTIVE) { 237 spidat1 |= SPIDAT1_CSHOLD_MASK; 238 spidat1 &= ~(0x1 << chip_sel); 239 } 240 241 iowrite16(spidat1, dspi->base + SPIDAT1 + 2); 242 } 243 } 244 245 /** 246 * davinci_spi_get_prescale - Calculates the correct prescale value 247 * @maxspeed_hz: the maximum rate the SPI clock can run at 248 * 249 * This function calculates the prescale value that generates a clock rate 250 * less than or equal to the specified maximum. 251 * 252 * Returns: calculated prescale - 1 for easy programming into SPI registers 253 * or negative error number if valid prescalar cannot be updated. 254 */ 255 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, 256 u32 max_speed_hz) 257 { 258 int ret; 259 260 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); 261 262 if (ret < 3 || ret > 256) 263 return -EINVAL; 264 265 return ret - 1; 266 } 267 268 /** 269 * davinci_spi_setup_transfer - This functions will determine transfer method 270 * @spi: spi device on which data transfer to be done 271 * @t: spi transfer in which transfer info is filled 272 * 273 * This function determines data transfer method (8/16/32 bit transfer). 274 * It will also set the SPI Clock Control register according to 275 * SPI slave device freq. 276 */ 277 static int davinci_spi_setup_transfer(struct spi_device *spi, 278 struct spi_transfer *t) 279 { 280 281 struct davinci_spi *dspi; 282 struct davinci_spi_config *spicfg; 283 u8 bits_per_word = 0; 284 u32 hz = 0, spifmt = 0; 285 int prescale; 286 287 dspi = spi_master_get_devdata(spi->master); 288 spicfg = (struct davinci_spi_config *)spi->controller_data; 289 if (!spicfg) 290 spicfg = &davinci_spi_default_cfg; 291 292 if (t) { 293 bits_per_word = t->bits_per_word; 294 hz = t->speed_hz; 295 } 296 297 /* if bits_per_word is not set then set it default */ 298 if (!bits_per_word) 299 bits_per_word = spi->bits_per_word; 300 301 /* 302 * Assign function pointer to appropriate transfer method 303 * 8bit, 16bit or 32bit transfer 304 */ 305 if (bits_per_word <= 8) { 306 dspi->get_rx = davinci_spi_rx_buf_u8; 307 dspi->get_tx = davinci_spi_tx_buf_u8; 308 dspi->bytes_per_word[spi->chip_select] = 1; 309 } else { 310 dspi->get_rx = davinci_spi_rx_buf_u16; 311 dspi->get_tx = davinci_spi_tx_buf_u16; 312 dspi->bytes_per_word[spi->chip_select] = 2; 313 } 314 315 if (!hz) 316 hz = spi->max_speed_hz; 317 318 /* Set up SPIFMTn register, unique to this chipselect. */ 319 320 prescale = davinci_spi_get_prescale(dspi, hz); 321 if (prescale < 0) 322 return prescale; 323 324 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); 325 326 if (spi->mode & SPI_LSB_FIRST) 327 spifmt |= SPIFMT_SHIFTDIR_MASK; 328 329 if (spi->mode & SPI_CPOL) 330 spifmt |= SPIFMT_POLARITY_MASK; 331 332 if (!(spi->mode & SPI_CPHA)) 333 spifmt |= SPIFMT_PHASE_MASK; 334 335 /* 336 * Version 1 hardware supports two basic SPI modes: 337 * - Standard SPI mode uses 4 pins, with chipselect 338 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) 339 * (distinct from SPI_3WIRE, with just one data wire; 340 * or similar variants without MOSI or without MISO) 341 * 342 * Version 2 hardware supports an optional handshaking signal, 343 * so it can support two more modes: 344 * - 5 pin SPI variant is standard SPI plus SPI_READY 345 * - 4 pin with enable is (SPI_READY | SPI_NO_CS) 346 */ 347 348 if (dspi->version == SPI_VERSION_2) { 349 350 u32 delay = 0; 351 352 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) 353 & SPIFMT_WDELAY_MASK); 354 355 if (spicfg->odd_parity) 356 spifmt |= SPIFMT_ODD_PARITY_MASK; 357 358 if (spicfg->parity_enable) 359 spifmt |= SPIFMT_PARITYENA_MASK; 360 361 if (spicfg->timer_disable) { 362 spifmt |= SPIFMT_DISTIMER_MASK; 363 } else { 364 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) 365 & SPIDELAY_C2TDELAY_MASK; 366 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) 367 & SPIDELAY_T2CDELAY_MASK; 368 } 369 370 if (spi->mode & SPI_READY) { 371 spifmt |= SPIFMT_WAITENA_MASK; 372 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) 373 & SPIDELAY_T2EDELAY_MASK; 374 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) 375 & SPIDELAY_C2EDELAY_MASK; 376 } 377 378 iowrite32(delay, dspi->base + SPIDELAY); 379 } 380 381 iowrite32(spifmt, dspi->base + SPIFMT0); 382 383 return 0; 384 } 385 386 /** 387 * davinci_spi_setup - This functions will set default transfer method 388 * @spi: spi device on which data transfer to be done 389 * 390 * This functions sets the default transfer method. 391 */ 392 static int davinci_spi_setup(struct spi_device *spi) 393 { 394 int retval = 0; 395 struct davinci_spi *dspi; 396 struct davinci_spi_platform_data *pdata; 397 struct spi_master *master = spi->master; 398 struct device_node *np = spi->dev.of_node; 399 bool internal_cs = true; 400 401 dspi = spi_master_get_devdata(spi->master); 402 pdata = &dspi->pdata; 403 404 if (!(spi->mode & SPI_NO_CS)) { 405 if (np && (master->cs_gpios != NULL) && (spi->cs_gpio >= 0)) { 406 retval = gpio_direction_output( 407 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 408 internal_cs = false; 409 } else if (pdata->chip_sel && 410 spi->chip_select < pdata->num_chipselect && 411 pdata->chip_sel[spi->chip_select] != SPI_INTERN_CS) { 412 spi->cs_gpio = pdata->chip_sel[spi->chip_select]; 413 retval = gpio_direction_output( 414 spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 415 internal_cs = false; 416 } 417 418 if (retval) { 419 dev_err(&spi->dev, "GPIO %d setup failed (%d)\n", 420 spi->cs_gpio, retval); 421 return retval; 422 } 423 424 if (internal_cs) 425 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); 426 } 427 428 if (spi->mode & SPI_READY) 429 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); 430 431 if (spi->mode & SPI_LOOP) 432 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 433 else 434 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); 435 436 return retval; 437 } 438 439 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) 440 { 441 struct device *sdev = dspi->bitbang.master->dev.parent; 442 443 if (int_status & SPIFLG_TIMEOUT_MASK) { 444 dev_dbg(sdev, "SPI Time-out Error\n"); 445 return -ETIMEDOUT; 446 } 447 if (int_status & SPIFLG_DESYNC_MASK) { 448 dev_dbg(sdev, "SPI Desynchronization Error\n"); 449 return -EIO; 450 } 451 if (int_status & SPIFLG_BITERR_MASK) { 452 dev_dbg(sdev, "SPI Bit error\n"); 453 return -EIO; 454 } 455 456 if (dspi->version == SPI_VERSION_2) { 457 if (int_status & SPIFLG_DLEN_ERR_MASK) { 458 dev_dbg(sdev, "SPI Data Length Error\n"); 459 return -EIO; 460 } 461 if (int_status & SPIFLG_PARERR_MASK) { 462 dev_dbg(sdev, "SPI Parity Error\n"); 463 return -EIO; 464 } 465 if (int_status & SPIFLG_OVRRUN_MASK) { 466 dev_dbg(sdev, "SPI Data Overrun error\n"); 467 return -EIO; 468 } 469 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { 470 dev_dbg(sdev, "SPI Buffer Init Active\n"); 471 return -EBUSY; 472 } 473 } 474 475 return 0; 476 } 477 478 /** 479 * davinci_spi_process_events - check for and handle any SPI controller events 480 * @dspi: the controller data 481 * 482 * This function will check the SPIFLG register and handle any events that are 483 * detected there 484 */ 485 static int davinci_spi_process_events(struct davinci_spi *dspi) 486 { 487 u32 buf, status, errors = 0, spidat1; 488 489 buf = ioread32(dspi->base + SPIBUF); 490 491 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { 492 dspi->get_rx(buf & 0xFFFF, dspi); 493 dspi->rcount--; 494 } 495 496 status = ioread32(dspi->base + SPIFLG); 497 498 if (unlikely(status & SPIFLG_ERROR_MASK)) { 499 errors = status & SPIFLG_ERROR_MASK; 500 goto out; 501 } 502 503 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { 504 spidat1 = ioread32(dspi->base + SPIDAT1); 505 dspi->wcount--; 506 spidat1 &= ~0xFFFF; 507 spidat1 |= 0xFFFF & dspi->get_tx(dspi); 508 iowrite32(spidat1, dspi->base + SPIDAT1); 509 } 510 511 out: 512 return errors; 513 } 514 515 static void davinci_spi_dma_rx_callback(void *data) 516 { 517 struct davinci_spi *dspi = (struct davinci_spi *)data; 518 519 dspi->rcount = 0; 520 521 if (!dspi->wcount && !dspi->rcount) 522 complete(&dspi->done); 523 } 524 525 static void davinci_spi_dma_tx_callback(void *data) 526 { 527 struct davinci_spi *dspi = (struct davinci_spi *)data; 528 529 dspi->wcount = 0; 530 531 if (!dspi->wcount && !dspi->rcount) 532 complete(&dspi->done); 533 } 534 535 /** 536 * davinci_spi_bufs - functions which will handle transfer data 537 * @spi: spi device on which data transfer to be done 538 * @t: spi transfer in which transfer info is filled 539 * 540 * This function will put data to be transferred into data register 541 * of SPI controller and then wait until the completion will be marked 542 * by the IRQ Handler. 543 */ 544 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) 545 { 546 struct davinci_spi *dspi; 547 int data_type, ret = -ENOMEM; 548 u32 tx_data, spidat1; 549 u32 errors = 0; 550 struct davinci_spi_config *spicfg; 551 struct davinci_spi_platform_data *pdata; 552 unsigned uninitialized_var(rx_buf_count); 553 void *dummy_buf = NULL; 554 struct scatterlist sg_rx, sg_tx; 555 556 dspi = spi_master_get_devdata(spi->master); 557 pdata = &dspi->pdata; 558 spicfg = (struct davinci_spi_config *)spi->controller_data; 559 if (!spicfg) 560 spicfg = &davinci_spi_default_cfg; 561 562 /* convert len to words based on bits_per_word */ 563 data_type = dspi->bytes_per_word[spi->chip_select]; 564 565 dspi->tx = t->tx_buf; 566 dspi->rx = t->rx_buf; 567 dspi->wcount = t->len / data_type; 568 dspi->rcount = dspi->wcount; 569 570 spidat1 = ioread32(dspi->base + SPIDAT1); 571 572 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 573 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); 574 575 reinit_completion(&dspi->done); 576 577 if (spicfg->io_type == SPI_IO_TYPE_INTR) 578 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); 579 580 if (spicfg->io_type != SPI_IO_TYPE_DMA) { 581 /* start the transfer */ 582 dspi->wcount--; 583 tx_data = dspi->get_tx(dspi); 584 spidat1 &= 0xFFFF0000; 585 spidat1 |= tx_data & 0xFFFF; 586 iowrite32(spidat1, dspi->base + SPIDAT1); 587 } else { 588 struct dma_slave_config dma_rx_conf = { 589 .direction = DMA_DEV_TO_MEM, 590 .src_addr = (unsigned long)dspi->pbase + SPIBUF, 591 .src_addr_width = data_type, 592 .src_maxburst = 1, 593 }; 594 struct dma_slave_config dma_tx_conf = { 595 .direction = DMA_MEM_TO_DEV, 596 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1, 597 .dst_addr_width = data_type, 598 .dst_maxburst = 1, 599 }; 600 struct dma_async_tx_descriptor *rxdesc; 601 struct dma_async_tx_descriptor *txdesc; 602 void *buf; 603 604 dummy_buf = kzalloc(t->len, GFP_KERNEL); 605 if (!dummy_buf) 606 goto err_alloc_dummy_buf; 607 608 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); 609 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); 610 611 sg_init_table(&sg_rx, 1); 612 if (!t->rx_buf) 613 buf = dummy_buf; 614 else 615 buf = t->rx_buf; 616 t->rx_dma = dma_map_single(&spi->dev, buf, 617 t->len, DMA_FROM_DEVICE); 618 if (!t->rx_dma) { 619 ret = -EFAULT; 620 goto err_rx_map; 621 } 622 sg_dma_address(&sg_rx) = t->rx_dma; 623 sg_dma_len(&sg_rx) = t->len; 624 625 sg_init_table(&sg_tx, 1); 626 if (!t->tx_buf) 627 buf = dummy_buf; 628 else 629 buf = (void *)t->tx_buf; 630 t->tx_dma = dma_map_single(&spi->dev, buf, 631 t->len, DMA_TO_DEVICE); 632 if (!t->tx_dma) { 633 ret = -EFAULT; 634 goto err_tx_map; 635 } 636 sg_dma_address(&sg_tx) = t->tx_dma; 637 sg_dma_len(&sg_tx) = t->len; 638 639 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, 640 &sg_rx, 1, DMA_DEV_TO_MEM, 641 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 642 if (!rxdesc) 643 goto err_desc; 644 645 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, 646 &sg_tx, 1, DMA_MEM_TO_DEV, 647 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 648 if (!txdesc) 649 goto err_desc; 650 651 rxdesc->callback = davinci_spi_dma_rx_callback; 652 rxdesc->callback_param = (void *)dspi; 653 txdesc->callback = davinci_spi_dma_tx_callback; 654 txdesc->callback_param = (void *)dspi; 655 656 if (pdata->cshold_bug) 657 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2); 658 659 dmaengine_submit(rxdesc); 660 dmaengine_submit(txdesc); 661 662 dma_async_issue_pending(dspi->dma_rx); 663 dma_async_issue_pending(dspi->dma_tx); 664 665 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); 666 } 667 668 /* Wait for the transfer to complete */ 669 if (spicfg->io_type != SPI_IO_TYPE_POLL) { 670 wait_for_completion_interruptible(&(dspi->done)); 671 } else { 672 while (dspi->rcount > 0 || dspi->wcount > 0) { 673 errors = davinci_spi_process_events(dspi); 674 if (errors) 675 break; 676 cpu_relax(); 677 } 678 } 679 680 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); 681 if (spicfg->io_type == SPI_IO_TYPE_DMA) { 682 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); 683 684 dma_unmap_single(&spi->dev, t->rx_dma, 685 t->len, DMA_FROM_DEVICE); 686 dma_unmap_single(&spi->dev, t->tx_dma, 687 t->len, DMA_TO_DEVICE); 688 kfree(dummy_buf); 689 } 690 691 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); 692 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 693 694 /* 695 * Check for bit error, desync error,parity error,timeout error and 696 * receive overflow errors 697 */ 698 if (errors) { 699 ret = davinci_spi_check_error(dspi, errors); 700 WARN(!ret, "%s: error reported but no error found!\n", 701 dev_name(&spi->dev)); 702 return ret; 703 } 704 705 if (dspi->rcount != 0 || dspi->wcount != 0) { 706 dev_err(&spi->dev, "SPI data transfer error\n"); 707 return -EIO; 708 } 709 710 return t->len; 711 712 err_desc: 713 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE); 714 err_tx_map: 715 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE); 716 err_rx_map: 717 kfree(dummy_buf); 718 err_alloc_dummy_buf: 719 return ret; 720 } 721 722 /** 723 * dummy_thread_fn - dummy thread function 724 * @irq: IRQ number for this SPI Master 725 * @context_data: structure for SPI Master controller davinci_spi 726 * 727 * This is to satisfy the request_threaded_irq() API so that the irq 728 * handler is called in interrupt context. 729 */ 730 static irqreturn_t dummy_thread_fn(s32 irq, void *data) 731 { 732 return IRQ_HANDLED; 733 } 734 735 /** 736 * davinci_spi_irq - Interrupt handler for SPI Master Controller 737 * @irq: IRQ number for this SPI Master 738 * @context_data: structure for SPI Master controller davinci_spi 739 * 740 * ISR will determine that interrupt arrives either for READ or WRITE command. 741 * According to command it will do the appropriate action. It will check 742 * transfer length and if it is not zero then dispatch transfer command again. 743 * If transfer length is zero then it will indicate the COMPLETION so that 744 * davinci_spi_bufs function can go ahead. 745 */ 746 static irqreturn_t davinci_spi_irq(s32 irq, void *data) 747 { 748 struct davinci_spi *dspi = data; 749 int status; 750 751 status = davinci_spi_process_events(dspi); 752 if (unlikely(status != 0)) 753 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); 754 755 if ((!dspi->rcount && !dspi->wcount) || status) 756 complete(&dspi->done); 757 758 return IRQ_HANDLED; 759 } 760 761 static int davinci_spi_request_dma(struct davinci_spi *dspi) 762 { 763 dma_cap_mask_t mask; 764 struct device *sdev = dspi->bitbang.master->dev.parent; 765 int r; 766 767 dma_cap_zero(mask); 768 dma_cap_set(DMA_SLAVE, mask); 769 770 dspi->dma_rx = dma_request_channel(mask, edma_filter_fn, 771 &dspi->dma_rx_chnum); 772 if (!dspi->dma_rx) { 773 dev_err(sdev, "request RX DMA channel failed\n"); 774 r = -ENODEV; 775 goto rx_dma_failed; 776 } 777 778 dspi->dma_tx = dma_request_channel(mask, edma_filter_fn, 779 &dspi->dma_tx_chnum); 780 if (!dspi->dma_tx) { 781 dev_err(sdev, "request TX DMA channel failed\n"); 782 r = -ENODEV; 783 goto tx_dma_failed; 784 } 785 786 return 0; 787 788 tx_dma_failed: 789 dma_release_channel(dspi->dma_rx); 790 rx_dma_failed: 791 return r; 792 } 793 794 #if defined(CONFIG_OF) 795 static const struct of_device_id davinci_spi_of_match[] = { 796 { 797 .compatible = "ti,dm6441-spi", 798 }, 799 { 800 .compatible = "ti,da830-spi", 801 .data = (void *)SPI_VERSION_2, 802 }, 803 { }, 804 }; 805 MODULE_DEVICE_TABLE(of, davinci_spi_of_match); 806 807 /** 808 * spi_davinci_get_pdata - Get platform data from DTS binding 809 * @pdev: ptr to platform data 810 * @dspi: ptr to driver data 811 * 812 * Parses and populates pdata in dspi from device tree bindings. 813 * 814 * NOTE: Not all platform data params are supported currently. 815 */ 816 static int spi_davinci_get_pdata(struct platform_device *pdev, 817 struct davinci_spi *dspi) 818 { 819 struct device_node *node = pdev->dev.of_node; 820 struct davinci_spi_platform_data *pdata; 821 unsigned int num_cs, intr_line = 0; 822 const struct of_device_id *match; 823 824 pdata = &dspi->pdata; 825 826 pdata->version = SPI_VERSION_1; 827 match = of_match_device(davinci_spi_of_match, &pdev->dev); 828 if (!match) 829 return -ENODEV; 830 831 /* match data has the SPI version number for SPI_VERSION_2 */ 832 if (match->data == (void *)SPI_VERSION_2) 833 pdata->version = SPI_VERSION_2; 834 835 /* 836 * default num_cs is 1 and all chipsel are internal to the chip 837 * indicated by chip_sel being NULL or cs_gpios being NULL or 838 * set to -ENOENT. num-cs includes internal as well as gpios. 839 * indicated by chip_sel being NULL. GPIO based CS is not 840 * supported yet in DT bindings. 841 */ 842 num_cs = 1; 843 of_property_read_u32(node, "num-cs", &num_cs); 844 pdata->num_chipselect = num_cs; 845 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line); 846 pdata->intr_line = intr_line; 847 return 0; 848 } 849 #else 850 static struct davinci_spi_platform_data 851 *spi_davinci_get_pdata(struct platform_device *pdev, 852 struct davinci_spi *dspi) 853 { 854 return -ENODEV; 855 } 856 #endif 857 858 /** 859 * davinci_spi_probe - probe function for SPI Master Controller 860 * @pdev: platform_device structure which contains plateform specific data 861 * 862 * According to Linux Device Model this function will be invoked by Linux 863 * with platform_device struct which contains the device specific info. 864 * This function will map the SPI controller's memory, register IRQ, 865 * Reset SPI controller and setting its registers to default value. 866 * It will invoke spi_bitbang_start to create work queue so that client driver 867 * can register transfer method to work queue. 868 */ 869 static int davinci_spi_probe(struct platform_device *pdev) 870 { 871 struct spi_master *master; 872 struct davinci_spi *dspi; 873 struct davinci_spi_platform_data *pdata; 874 struct resource *r; 875 resource_size_t dma_rx_chan = SPI_NO_RESOURCE; 876 resource_size_t dma_tx_chan = SPI_NO_RESOURCE; 877 int ret = 0; 878 u32 spipc0; 879 880 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); 881 if (master == NULL) { 882 ret = -ENOMEM; 883 goto err; 884 } 885 886 platform_set_drvdata(pdev, master); 887 888 dspi = spi_master_get_devdata(master); 889 890 if (dev_get_platdata(&pdev->dev)) { 891 pdata = dev_get_platdata(&pdev->dev); 892 dspi->pdata = *pdata; 893 } else { 894 /* update dspi pdata with that from the DT */ 895 ret = spi_davinci_get_pdata(pdev, dspi); 896 if (ret < 0) 897 goto free_master; 898 } 899 900 /* pdata in dspi is now updated and point pdata to that */ 901 pdata = &dspi->pdata; 902 903 dspi->bytes_per_word = devm_kzalloc(&pdev->dev, 904 sizeof(*dspi->bytes_per_word) * 905 pdata->num_chipselect, GFP_KERNEL); 906 if (dspi->bytes_per_word == NULL) { 907 ret = -ENOMEM; 908 goto free_master; 909 } 910 911 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 912 if (r == NULL) { 913 ret = -ENOENT; 914 goto free_master; 915 } 916 917 dspi->pbase = r->start; 918 919 dspi->base = devm_ioremap_resource(&pdev->dev, r); 920 if (IS_ERR(dspi->base)) { 921 ret = PTR_ERR(dspi->base); 922 goto free_master; 923 } 924 925 dspi->irq = platform_get_irq(pdev, 0); 926 if (dspi->irq <= 0) { 927 ret = -EINVAL; 928 goto free_master; 929 } 930 931 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq, 932 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi); 933 if (ret) 934 goto free_master; 935 936 dspi->bitbang.master = master; 937 938 dspi->clk = devm_clk_get(&pdev->dev, NULL); 939 if (IS_ERR(dspi->clk)) { 940 ret = -ENODEV; 941 goto free_master; 942 } 943 clk_prepare_enable(dspi->clk); 944 945 master->dev.of_node = pdev->dev.of_node; 946 master->bus_num = pdev->id; 947 master->num_chipselect = pdata->num_chipselect; 948 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); 949 master->setup = davinci_spi_setup; 950 951 dspi->bitbang.chipselect = davinci_spi_chipselect; 952 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; 953 954 dspi->version = pdata->version; 955 956 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; 957 if (dspi->version == SPI_VERSION_2) 958 dspi->bitbang.flags |= SPI_READY; 959 960 if (pdev->dev.of_node) { 961 int i; 962 963 for (i = 0; i < pdata->num_chipselect; i++) { 964 int cs_gpio = of_get_named_gpio(pdev->dev.of_node, 965 "cs-gpios", i); 966 967 if (cs_gpio == -EPROBE_DEFER) { 968 ret = cs_gpio; 969 goto free_clk; 970 } 971 972 if (gpio_is_valid(cs_gpio)) { 973 ret = devm_gpio_request(&pdev->dev, cs_gpio, 974 dev_name(&pdev->dev)); 975 if (ret) 976 goto free_clk; 977 } 978 } 979 } 980 981 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 982 if (r) 983 dma_rx_chan = r->start; 984 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 985 if (r) 986 dma_tx_chan = r->start; 987 988 dspi->bitbang.txrx_bufs = davinci_spi_bufs; 989 if (dma_rx_chan != SPI_NO_RESOURCE && 990 dma_tx_chan != SPI_NO_RESOURCE) { 991 dspi->dma_rx_chnum = dma_rx_chan; 992 dspi->dma_tx_chnum = dma_tx_chan; 993 994 ret = davinci_spi_request_dma(dspi); 995 if (ret) 996 goto free_clk; 997 998 dev_info(&pdev->dev, "DMA: supported\n"); 999 dev_info(&pdev->dev, "DMA: RX channel: %pa, TX channel: %pa, " 1000 "event queue: %d\n", &dma_rx_chan, &dma_tx_chan, 1001 pdata->dma_event_q); 1002 } 1003 1004 dspi->get_rx = davinci_spi_rx_buf_u8; 1005 dspi->get_tx = davinci_spi_tx_buf_u8; 1006 1007 init_completion(&dspi->done); 1008 1009 /* Reset In/OUT SPI module */ 1010 iowrite32(0, dspi->base + SPIGCR0); 1011 udelay(100); 1012 iowrite32(1, dspi->base + SPIGCR0); 1013 1014 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ 1015 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; 1016 iowrite32(spipc0, dspi->base + SPIPC0); 1017 1018 if (pdata->intr_line) 1019 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL); 1020 else 1021 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL); 1022 1023 iowrite32(CS_DEFAULT, dspi->base + SPIDEF); 1024 1025 /* master mode default */ 1026 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); 1027 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); 1028 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); 1029 1030 ret = spi_bitbang_start(&dspi->bitbang); 1031 if (ret) 1032 goto free_dma; 1033 1034 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base); 1035 1036 return ret; 1037 1038 free_dma: 1039 dma_release_channel(dspi->dma_rx); 1040 dma_release_channel(dspi->dma_tx); 1041 free_clk: 1042 clk_disable_unprepare(dspi->clk); 1043 free_master: 1044 spi_master_put(master); 1045 err: 1046 return ret; 1047 } 1048 1049 /** 1050 * davinci_spi_remove - remove function for SPI Master Controller 1051 * @pdev: platform_device structure which contains plateform specific data 1052 * 1053 * This function will do the reverse action of davinci_spi_probe function 1054 * It will free the IRQ and SPI controller's memory region. 1055 * It will also call spi_bitbang_stop to destroy the work queue which was 1056 * created by spi_bitbang_start. 1057 */ 1058 static int davinci_spi_remove(struct platform_device *pdev) 1059 { 1060 struct davinci_spi *dspi; 1061 struct spi_master *master; 1062 1063 master = platform_get_drvdata(pdev); 1064 dspi = spi_master_get_devdata(master); 1065 1066 spi_bitbang_stop(&dspi->bitbang); 1067 1068 clk_disable_unprepare(dspi->clk); 1069 spi_master_put(master); 1070 1071 return 0; 1072 } 1073 1074 static struct platform_driver davinci_spi_driver = { 1075 .driver = { 1076 .name = "spi_davinci", 1077 .owner = THIS_MODULE, 1078 .of_match_table = of_match_ptr(davinci_spi_of_match), 1079 }, 1080 .probe = davinci_spi_probe, 1081 .remove = davinci_spi_remove, 1082 }; 1083 module_platform_driver(davinci_spi_driver); 1084 1085 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); 1086 MODULE_LICENSE("GPL"); 1087