1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // CS42L43 SPI Controller Driver 4 // 5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/acpi.h> 9 #include <linux/array_size.h> 10 #include <linux/bits.h> 11 #include <linux/bitfield.h> 12 #include <linux/cleanup.h> 13 #include <linux/device.h> 14 #include <linux/errno.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/gpio/machine.h> 17 #include <linux/gpio/property.h> 18 #include <linux/mfd/cs42l43.h> 19 #include <linux/mfd/cs42l43-regs.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/property.h> 26 #include <linux/regmap.h> 27 #include <linux/spi/spi.h> 28 #include <linux/units.h> 29 30 #define CS42L43_FIFO_SIZE 16 31 #define CS42L43_SPI_ROOT_HZ 49152000 32 #define CS42L43_SPI_MAX_LENGTH 65532 33 34 enum cs42l43_spi_cmd { 35 CS42L43_WRITE, 36 CS42L43_READ 37 }; 38 39 struct cs42l43_spi { 40 struct device *dev; 41 struct regmap *regmap; 42 struct spi_controller *ctlr; 43 }; 44 45 static const unsigned int cs42l43_clock_divs[] = { 46 2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 47 }; 48 49 static struct spi_board_info amp_info_template = { 50 .modalias = "cs35l56", 51 .max_speed_hz = 11 * HZ_PER_MHZ, 52 .mode = SPI_MODE_0, 53 }; 54 55 static int cs42l43_spi_tx(struct regmap *regmap, const u8 *buf, unsigned int len) 56 { 57 const u8 *end = buf + len; 58 u32 val = 0; 59 int ret; 60 61 while (buf < end) { 62 const u8 *block = min(buf + CS42L43_FIFO_SIZE, end); 63 64 while (buf < block) { 65 const u8 *word = min(buf + sizeof(u32), block); 66 int pad = (buf + sizeof(u32)) - word; 67 68 while (buf < word) { 69 val >>= BITS_PER_BYTE; 70 val |= FIELD_PREP(GENMASK(31, 24), *buf); 71 72 buf++; 73 } 74 75 val >>= pad * BITS_PER_BYTE; 76 77 regmap_write(regmap, CS42L43_TX_DATA, val); 78 } 79 80 regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_TX_DONE_MASK); 81 82 ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1, 83 val, (val & CS42L43_SPI_TX_REQUEST_MASK), 84 1000, 5000); 85 if (ret) 86 return ret; 87 } 88 89 return 0; 90 } 91 92 static int cs42l43_spi_rx(struct regmap *regmap, u8 *buf, unsigned int len) 93 { 94 u8 *end = buf + len; 95 u32 val; 96 int ret; 97 98 while (buf < end) { 99 u8 *block = min(buf + CS42L43_FIFO_SIZE, end); 100 101 ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1, 102 val, (val & CS42L43_SPI_RX_REQUEST_MASK), 103 1000, 5000); 104 if (ret) 105 return ret; 106 107 while (buf < block) { 108 u8 *word = min(buf + sizeof(u32), block); 109 110 ret = regmap_read(regmap, CS42L43_RX_DATA, &val); 111 if (ret) 112 return ret; 113 114 while (buf < word) { 115 *buf = FIELD_GET(GENMASK(7, 0), val); 116 117 val >>= BITS_PER_BYTE; 118 buf++; 119 } 120 } 121 122 regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_RX_DONE_MASK); 123 } 124 125 return 0; 126 } 127 128 static int cs42l43_transfer_one(struct spi_controller *ctlr, struct spi_device *spi, 129 struct spi_transfer *tfr) 130 { 131 struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller); 132 int i, ret = -EINVAL; 133 134 for (i = 0; i < ARRAY_SIZE(cs42l43_clock_divs); i++) { 135 if (CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[i] <= tfr->speed_hz) 136 break; 137 } 138 139 if (i == ARRAY_SIZE(cs42l43_clock_divs)) 140 return -EINVAL; 141 142 regmap_write(priv->regmap, CS42L43_SPI_CLK_CONFIG1, i); 143 144 if (tfr->tx_buf) { 145 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_WRITE); 146 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG4, tfr->len - 1); 147 } else if (tfr->rx_buf) { 148 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_READ); 149 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG5, tfr->len - 1); 150 } 151 152 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG1, CS42L43_SPI_START_MASK); 153 154 if (tfr->tx_buf) 155 ret = cs42l43_spi_tx(priv->regmap, (const u8 *)tfr->tx_buf, tfr->len); 156 else if (tfr->rx_buf) 157 ret = cs42l43_spi_rx(priv->regmap, (u8 *)tfr->rx_buf, tfr->len); 158 159 return ret; 160 } 161 162 static void cs42l43_set_cs(struct spi_device *spi, bool is_high) 163 { 164 struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller); 165 166 regmap_write(priv->regmap, CS42L43_SPI_CONFIG2, !is_high); 167 } 168 169 static int cs42l43_prepare_message(struct spi_controller *ctlr, struct spi_message *msg) 170 { 171 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr); 172 struct spi_device *spi = msg->spi; 173 unsigned int spi_config1 = 0; 174 175 /* select another internal CS, which doesn't exist, so CS 0 is not used */ 176 if (spi_get_csgpiod(spi, 0)) 177 spi_config1 |= 1 << CS42L43_SPI_SS_SEL_SHIFT; 178 if (spi->mode & SPI_CPOL) 179 spi_config1 |= CS42L43_SPI_CPOL_MASK; 180 if (spi->mode & SPI_CPHA) 181 spi_config1 |= CS42L43_SPI_CPHA_MASK; 182 if (spi->mode & SPI_3WIRE) 183 spi_config1 |= CS42L43_SPI_THREE_WIRE_MASK; 184 185 regmap_write(priv->regmap, CS42L43_SPI_CONFIG1, spi_config1); 186 187 return 0; 188 } 189 190 static int cs42l43_prepare_transfer_hardware(struct spi_controller *ctlr) 191 { 192 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr); 193 int ret; 194 195 ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, CS42L43_SPI_MSTR_EN_MASK); 196 if (ret) 197 dev_err(priv->dev, "Failed to enable SPI controller: %d\n", ret); 198 199 return ret; 200 } 201 202 static int cs42l43_unprepare_transfer_hardware(struct spi_controller *ctlr) 203 { 204 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr); 205 int ret; 206 207 ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, 0); 208 if (ret) 209 dev_err(priv->dev, "Failed to disable SPI controller: %d\n", ret); 210 211 return ret; 212 } 213 214 static size_t cs42l43_spi_max_length(struct spi_device *spi) 215 { 216 return CS42L43_SPI_MAX_LENGTH; 217 } 218 219 static int cs42l43_get_speaker_id_gpios(struct cs42l43_spi *priv, int *result) 220 { 221 struct gpio_descs *descs; 222 u32 spkid; 223 int i, ret; 224 225 descs = gpiod_get_array_optional(priv->dev, "spk-id", GPIOD_IN); 226 if (!descs) 227 return 0; 228 else if (IS_ERR(descs)) 229 return PTR_ERR(descs); 230 231 spkid = 0; 232 for (i = 0; i < descs->ndescs; i++) { 233 ret = gpiod_get_value_cansleep(descs->desc[i]); 234 if (ret < 0) 235 goto err; 236 237 spkid |= (ret << i); 238 } 239 240 dev_dbg(priv->dev, "spk-id-gpios = %d\n", spkid); 241 *result = spkid; 242 err: 243 gpiod_put_array(descs); 244 245 return ret; 246 } 247 248 static struct fwnode_handle *cs42l43_find_xu_node(struct fwnode_handle *fwnode) 249 { 250 static const u32 func_smart_amp = 0x1; 251 struct fwnode_handle *child_fwnode, *ext_fwnode; 252 u32 function; 253 int ret; 254 255 fwnode_for_each_child_node(fwnode, child_fwnode) { 256 acpi_handle handle = ACPI_HANDLE_FWNODE(child_fwnode); 257 258 ret = acpi_get_local_address(handle, &function); 259 if (ret || function != func_smart_amp) 260 continue; 261 262 ext_fwnode = fwnode_get_named_child_node(child_fwnode, 263 "mipi-sdca-function-expansion-subproperties"); 264 if (!ext_fwnode) 265 continue; 266 267 fwnode_handle_put(child_fwnode); 268 269 return ext_fwnode; 270 } 271 272 return NULL; 273 } 274 275 static struct spi_board_info *cs42l43_create_bridge_amp(struct cs42l43_spi *priv, 276 const char * const name, 277 int cs, int spkid) 278 { 279 struct property_entry *props = NULL; 280 struct software_node *swnode; 281 struct spi_board_info *info; 282 283 if (spkid >= 0) { 284 props = devm_kcalloc(priv->dev, 2, sizeof(*props), GFP_KERNEL); 285 if (!props) 286 return NULL; 287 288 *props = PROPERTY_ENTRY_U32("cirrus,speaker-id", spkid); 289 } 290 291 swnode = devm_kmalloc(priv->dev, sizeof(*swnode), GFP_KERNEL); 292 if (!swnode) 293 return NULL; 294 295 *swnode = SOFTWARE_NODE(name, props, NULL); 296 297 info = devm_kmemdup(priv->dev, &_info_template, 298 sizeof(amp_info_template), GFP_KERNEL); 299 if (!info) 300 return NULL; 301 302 info->chip_select = cs; 303 info->swnode = swnode; 304 305 return info; 306 } 307 308 static void cs42l43_release_of_node(void *data) 309 { 310 fwnode_handle_put(data); 311 } 312 313 static int cs42l43_spi_probe(struct platform_device *pdev) 314 { 315 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent); 316 struct cs42l43_spi *priv; 317 struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev); 318 struct fwnode_handle *xu_fwnode __free(fwnode_handle) = cs42l43_find_xu_node(fwnode); 319 int nsidecars = 0; 320 int spkid = -EINVAL; 321 int ret; 322 323 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 324 if (!priv) 325 return -ENOMEM; 326 327 priv->ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*priv->ctlr)); 328 if (!priv->ctlr) 329 return -ENOMEM; 330 331 spi_controller_set_devdata(priv->ctlr, priv); 332 333 priv->dev = &pdev->dev; 334 priv->regmap = cs42l43->regmap; 335 336 priv->ctlr->prepare_message = cs42l43_prepare_message; 337 priv->ctlr->prepare_transfer_hardware = cs42l43_prepare_transfer_hardware; 338 priv->ctlr->unprepare_transfer_hardware = cs42l43_unprepare_transfer_hardware; 339 priv->ctlr->transfer_one = cs42l43_transfer_one; 340 priv->ctlr->set_cs = cs42l43_set_cs; 341 priv->ctlr->max_transfer_size = cs42l43_spi_max_length; 342 priv->ctlr->mode_bits = SPI_3WIRE | SPI_MODE_X_MASK; 343 priv->ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX; 344 priv->ctlr->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 345 SPI_BPW_MASK(32); 346 priv->ctlr->min_speed_hz = CS42L43_SPI_ROOT_HZ / 347 cs42l43_clock_divs[ARRAY_SIZE(cs42l43_clock_divs) - 1]; 348 priv->ctlr->max_speed_hz = CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[0]; 349 priv->ctlr->use_gpio_descriptors = true; 350 priv->ctlr->auto_runtime_pm = true; 351 352 ret = devm_pm_runtime_enable(priv->dev); 353 if (ret) 354 return ret; 355 356 pm_runtime_idle(priv->dev); 357 358 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG6, CS42L43_FIFO_SIZE - 1); 359 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG7, CS42L43_FIFO_SIZE - 1); 360 361 // Disable Watchdog timer and enable stall 362 regmap_write(priv->regmap, CS42L43_SPI_CONFIG3, 0); 363 regmap_write(priv->regmap, CS42L43_SPI_CONFIG4, CS42L43_SPI_STALL_ENA_MASK); 364 365 if (is_of_node(fwnode)) { 366 fwnode = fwnode_get_named_child_node(fwnode, "spi"); 367 ret = devm_add_action_or_reset(priv->dev, cs42l43_release_of_node, fwnode); 368 if (ret) 369 return ret; 370 } 371 372 fwnode_property_read_u32(xu_fwnode, "01fa-sidecar-instances", &nsidecars); 373 374 if (nsidecars) { 375 struct software_node_ref_args args[] = { 376 SOFTWARE_NODE_REFERENCE(fwnode, 0, GPIO_ACTIVE_LOW), 377 SOFTWARE_NODE_REFERENCE(&swnode_gpio_undefined), 378 }; 379 struct property_entry props[] = { 380 PROPERTY_ENTRY_REF_ARRAY("cs-gpios", args), 381 { } 382 }; 383 384 ret = fwnode_property_read_u32(xu_fwnode, "01fa-spk-id-val", &spkid); 385 if (!ret) { 386 dev_dbg(priv->dev, "01fa-spk-id-val = %d\n", spkid); 387 } else if (ret != -EINVAL) { 388 return dev_err_probe(priv->dev, ret, "Failed to get spk-id-val\n"); 389 } else { 390 ret = cs42l43_get_speaker_id_gpios(priv, &spkid); 391 if (ret < 0) 392 return dev_err_probe(priv->dev, ret, 393 "Failed to get spk-id-gpios\n"); 394 } 395 396 ret = device_create_managed_software_node(&priv->ctlr->dev, props, NULL); 397 if (ret) 398 return dev_err_probe(priv->dev, ret, "Failed to add swnode\n"); 399 } else { 400 device_set_node(&priv->ctlr->dev, fwnode); 401 } 402 403 ret = devm_spi_register_controller(priv->dev, priv->ctlr); 404 if (ret) 405 return dev_err_probe(priv->dev, ret, 406 "Failed to register SPI controller\n"); 407 408 if (nsidecars) { 409 struct spi_board_info *ampl_info; 410 struct spi_board_info *ampr_info; 411 412 ampl_info = cs42l43_create_bridge_amp(priv, "cs35l56-left", 0, spkid); 413 if (!ampl_info) 414 return -ENOMEM; 415 416 ampr_info = cs42l43_create_bridge_amp(priv, "cs35l56-right", 1, spkid); 417 if (!ampr_info) 418 return -ENOMEM; 419 420 if (!spi_new_device(priv->ctlr, ampl_info)) 421 return dev_err_probe(priv->dev, -ENODEV, 422 "Failed to create left amp slave\n"); 423 424 if (!spi_new_device(priv->ctlr, ampr_info)) 425 return dev_err_probe(priv->dev, -ENODEV, 426 "Failed to create right amp slave\n"); 427 } 428 429 return 0; 430 } 431 432 static const struct platform_device_id cs42l43_spi_id_table[] = { 433 { "cs42l43-spi", }, 434 {} 435 }; 436 MODULE_DEVICE_TABLE(platform, cs42l43_spi_id_table); 437 438 static struct platform_driver cs42l43_spi_driver = { 439 .driver = { 440 .name = "cs42l43-spi", 441 }, 442 .probe = cs42l43_spi_probe, 443 .id_table = cs42l43_spi_id_table, 444 }; 445 module_platform_driver(cs42l43_spi_driver); 446 447 MODULE_IMPORT_NS("GPIO_SWNODE"); 448 MODULE_DESCRIPTION("CS42L43 SPI Driver"); 449 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>"); 450 MODULE_AUTHOR("Maciej Strozek <mstrozek@opensource.cirrus.com>"); 451 MODULE_LICENSE("GPL"); 452