1 // SPDX-License-Identifier: GPL-2.0+ 2 // Cadence XSPI flash controller driver 3 // Copyright (C) 2020-21 Cadence 4 5 #include <linux/completion.h> 6 #include <linux/delay.h> 7 #include <linux/err.h> 8 #include <linux/errno.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/spi/spi.h> 18 #include <linux/spi/spi-mem.h> 19 #include <linux/bitfield.h> 20 #include <linux/limits.h> 21 #include <linux/log2.h> 22 23 #define CDNS_XSPI_MAGIC_NUM_VALUE 0x6522 24 #define CDNS_XSPI_MAX_BANKS 8 25 #define CDNS_XSPI_NAME "cadence-xspi" 26 27 /* 28 * Note: below are additional auxiliary registers to 29 * configure XSPI controller pin-strap settings 30 */ 31 32 /* PHY DQ timing register */ 33 #define CDNS_XSPI_CCP_PHY_DQ_TIMING 0x0000 34 35 /* PHY DQS timing register */ 36 #define CDNS_XSPI_CCP_PHY_DQS_TIMING 0x0004 37 38 /* PHY gate loopback control register */ 39 #define CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL 0x0008 40 41 /* PHY DLL slave control register */ 42 #define CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL 0x0010 43 44 /* DLL PHY control register */ 45 #define CDNS_XSPI_DLL_PHY_CTRL 0x1034 46 47 /* Command registers */ 48 #define CDNS_XSPI_CMD_REG_0 0x0000 49 #define CDNS_XSPI_CMD_REG_1 0x0004 50 #define CDNS_XSPI_CMD_REG_2 0x0008 51 #define CDNS_XSPI_CMD_REG_3 0x000C 52 #define CDNS_XSPI_CMD_REG_4 0x0010 53 #define CDNS_XSPI_CMD_REG_5 0x0014 54 55 /* Command status registers */ 56 #define CDNS_XSPI_CMD_STATUS_REG 0x0044 57 58 /* Controller status register */ 59 #define CDNS_XSPI_CTRL_STATUS_REG 0x0100 60 #define CDNS_XSPI_INIT_COMPLETED BIT(16) 61 #define CDNS_XSPI_INIT_LEGACY BIT(9) 62 #define CDNS_XSPI_INIT_FAIL BIT(8) 63 #define CDNS_XSPI_CTRL_BUSY BIT(7) 64 65 /* Controller interrupt status register */ 66 #define CDNS_XSPI_INTR_STATUS_REG 0x0110 67 #define CDNS_XSPI_STIG_DONE BIT(23) 68 #define CDNS_XSPI_SDMA_ERROR BIT(22) 69 #define CDNS_XSPI_SDMA_TRIGGER BIT(21) 70 #define CDNS_XSPI_CMD_IGNRD_EN BIT(20) 71 #define CDNS_XSPI_DDMA_TERR_EN BIT(18) 72 #define CDNS_XSPI_CDMA_TREE_EN BIT(17) 73 #define CDNS_XSPI_CTRL_IDLE_EN BIT(16) 74 75 #define CDNS_XSPI_TRD_COMP_INTR_STATUS 0x0120 76 #define CDNS_XSPI_TRD_ERR_INTR_STATUS 0x0130 77 #define CDNS_XSPI_TRD_ERR_INTR_EN 0x0134 78 79 /* Controller interrupt enable register */ 80 #define CDNS_XSPI_INTR_ENABLE_REG 0x0114 81 #define CDNS_XSPI_INTR_EN BIT(31) 82 #define CDNS_XSPI_STIG_DONE_EN BIT(23) 83 #define CDNS_XSPI_SDMA_ERROR_EN BIT(22) 84 #define CDNS_XSPI_SDMA_TRIGGER_EN BIT(21) 85 86 #define CDNS_XSPI_INTR_MASK (CDNS_XSPI_INTR_EN | \ 87 CDNS_XSPI_STIG_DONE_EN | \ 88 CDNS_XSPI_SDMA_ERROR_EN | \ 89 CDNS_XSPI_SDMA_TRIGGER_EN) 90 91 /* Controller config register */ 92 #define CDNS_XSPI_CTRL_CONFIG_REG 0x0230 93 #define CDNS_XSPI_CTRL_WORK_MODE GENMASK(6, 5) 94 95 #define CDNS_XSPI_WORK_MODE_DIRECT 0 96 #define CDNS_XSPI_WORK_MODE_STIG 1 97 #define CDNS_XSPI_WORK_MODE_ACMD 3 98 99 /* SDMA trigger transaction registers */ 100 #define CDNS_XSPI_SDMA_SIZE_REG 0x0240 101 #define CDNS_XSPI_SDMA_TRD_INFO_REG 0x0244 102 #define CDNS_XSPI_SDMA_DIR BIT(8) 103 104 /* Controller features register */ 105 #define CDNS_XSPI_CTRL_FEATURES_REG 0x0F04 106 #define CDNS_XSPI_NUM_BANKS GENMASK(25, 24) 107 #define CDNS_XSPI_DMA_DATA_WIDTH BIT(21) 108 #define CDNS_XSPI_NUM_THREADS GENMASK(3, 0) 109 110 /* Controller version register */ 111 #define CDNS_XSPI_CTRL_VERSION_REG 0x0F00 112 #define CDNS_XSPI_MAGIC_NUM GENMASK(31, 16) 113 #define CDNS_XSPI_CTRL_REV GENMASK(7, 0) 114 115 /* STIG Profile 1.0 instruction fields (split into registers) */ 116 #define CDNS_XSPI_CMD_INSTR_TYPE GENMASK(6, 0) 117 #define CDNS_XSPI_CMD_P1_R1_ADDR0 GENMASK(31, 24) 118 #define CDNS_XSPI_CMD_P1_R2_ADDR1 GENMASK(7, 0) 119 #define CDNS_XSPI_CMD_P1_R2_ADDR2 GENMASK(15, 8) 120 #define CDNS_XSPI_CMD_P1_R2_ADDR3 GENMASK(23, 16) 121 #define CDNS_XSPI_CMD_P1_R2_ADDR4 GENMASK(31, 24) 122 #define CDNS_XSPI_CMD_P1_R3_ADDR5 GENMASK(7, 0) 123 #define CDNS_XSPI_CMD_P1_R3_CMD GENMASK(23, 16) 124 #define CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES GENMASK(30, 28) 125 #define CDNS_XSPI_CMD_P1_R4_ADDR_IOS GENMASK(1, 0) 126 #define CDNS_XSPI_CMD_P1_R4_CMD_IOS GENMASK(9, 8) 127 #define CDNS_XSPI_CMD_P1_R4_BANK GENMASK(14, 12) 128 129 /* STIG data sequence instruction fields (split into registers) */ 130 #define CDNS_XSPI_CMD_DSEQ_R2_DCNT_L GENMASK(31, 16) 131 #define CDNS_XSPI_CMD_DSEQ_R3_DCNT_H GENMASK(15, 0) 132 #define CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY GENMASK(25, 20) 133 #define CDNS_XSPI_CMD_DSEQ_R4_BANK GENMASK(14, 12) 134 #define CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS GENMASK(9, 8) 135 #define CDNS_XSPI_CMD_DSEQ_R4_DIR BIT(4) 136 137 /* STIG command status fields */ 138 #define CDNS_XSPI_CMD_STATUS_COMPLETED BIT(15) 139 #define CDNS_XSPI_CMD_STATUS_FAILED BIT(14) 140 #define CDNS_XSPI_CMD_STATUS_DQS_ERROR BIT(3) 141 #define CDNS_XSPI_CMD_STATUS_CRC_ERROR BIT(2) 142 #define CDNS_XSPI_CMD_STATUS_BUS_ERROR BIT(1) 143 #define CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR BIT(0) 144 145 #define CDNS_XSPI_STIG_DONE_FLAG BIT(0) 146 #define CDNS_XSPI_TRD_STATUS 0x0104 147 148 #define MODE_NO_OF_BYTES GENMASK(25, 24) 149 #define MODEBYTES_COUNT 1 150 151 /* Helper macros for filling command registers */ 152 #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase) ( \ 153 FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, (data_phase) ? \ 154 CDNS_XSPI_STIG_INSTR_TYPE_1 : CDNS_XSPI_STIG_INSTR_TYPE_0) | \ 155 FIELD_PREP(CDNS_XSPI_CMD_P1_R1_ADDR0, (op)->addr.val & 0xff)) 156 157 #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op) ( \ 158 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR1, ((op)->addr.val >> 8) & 0xFF) | \ 159 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR2, ((op)->addr.val >> 16) & 0xFF) | \ 160 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR3, ((op)->addr.val >> 24) & 0xFF) | \ 161 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR4, ((op)->addr.val >> 32) & 0xFF)) 162 163 #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, modebytes) ( \ 164 FIELD_PREP(CDNS_XSPI_CMD_P1_R3_ADDR5, ((op)->addr.val >> 40) & 0xFF) | \ 165 FIELD_PREP(CDNS_XSPI_CMD_P1_R3_CMD, (op)->cmd.opcode) | \ 166 FIELD_PREP(MODE_NO_OF_BYTES, modebytes) | \ 167 FIELD_PREP(CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES, (op)->addr.nbytes)) 168 169 #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, chipsel) ( \ 170 FIELD_PREP(CDNS_XSPI_CMD_P1_R4_ADDR_IOS, ilog2((op)->addr.buswidth)) | \ 171 FIELD_PREP(CDNS_XSPI_CMD_P1_R4_CMD_IOS, ilog2((op)->cmd.buswidth)) | \ 172 FIELD_PREP(CDNS_XSPI_CMD_P1_R4_BANK, chipsel)) 173 174 #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op) \ 175 FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ) 176 177 #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op) \ 178 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R2_DCNT_L, (op)->data.nbytes & 0xFFFF) 179 180 #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes) ( \ 181 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \ 182 ((op)->data.nbytes >> 16) & 0xffff) | \ 183 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, \ 184 (op)->dummy.buswidth != 0 ? \ 185 (((dummybytes) * 8) / (op)->dummy.buswidth) : \ 186 0)) 187 188 #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \ 189 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_BANK, chipsel) | \ 190 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS, \ 191 ilog2((op)->data.buswidth)) | \ 192 FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DIR, \ 193 ((op)->data.dir == SPI_MEM_DATA_IN) ? \ 194 CDNS_XSPI_STIG_CMD_DIR_READ : CDNS_XSPI_STIG_CMD_DIR_WRITE)) 195 196 enum cdns_xspi_stig_instr_type { 197 CDNS_XSPI_STIG_INSTR_TYPE_0, 198 CDNS_XSPI_STIG_INSTR_TYPE_1, 199 CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ = 127, 200 }; 201 202 enum cdns_xspi_sdma_dir { 203 CDNS_XSPI_SDMA_DIR_READ, 204 CDNS_XSPI_SDMA_DIR_WRITE, 205 }; 206 207 enum cdns_xspi_stig_cmd_dir { 208 CDNS_XSPI_STIG_CMD_DIR_READ, 209 CDNS_XSPI_STIG_CMD_DIR_WRITE, 210 }; 211 212 struct cdns_xspi_dev { 213 struct platform_device *pdev; 214 struct device *dev; 215 216 void __iomem *iobase; 217 void __iomem *auxbase; 218 void __iomem *sdmabase; 219 220 int irq; 221 int cur_cs; 222 unsigned int sdmasize; 223 224 struct completion cmd_complete; 225 struct completion auto_cmd_complete; 226 struct completion sdma_complete; 227 bool sdma_error; 228 229 void *in_buffer; 230 const void *out_buffer; 231 232 u8 hw_num_banks; 233 }; 234 235 static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_xspi) 236 { 237 u32 ctrl_stat; 238 239 return readl_relaxed_poll_timeout(cdns_xspi->iobase + 240 CDNS_XSPI_CTRL_STATUS_REG, 241 ctrl_stat, 242 ((ctrl_stat & 243 CDNS_XSPI_CTRL_BUSY) == 0), 244 100, 1000); 245 } 246 247 static void cdns_xspi_trigger_command(struct cdns_xspi_dev *cdns_xspi, 248 u32 cmd_regs[6]) 249 { 250 writel(cmd_regs[5], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_5); 251 writel(cmd_regs[4], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_4); 252 writel(cmd_regs[3], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_3); 253 writel(cmd_regs[2], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_2); 254 writel(cmd_regs[1], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_1); 255 writel(cmd_regs[0], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_0); 256 } 257 258 static int cdns_xspi_check_command_status(struct cdns_xspi_dev *cdns_xspi) 259 { 260 int ret = 0; 261 u32 cmd_status = readl(cdns_xspi->iobase + CDNS_XSPI_CMD_STATUS_REG); 262 263 if (cmd_status & CDNS_XSPI_CMD_STATUS_COMPLETED) { 264 if ((cmd_status & CDNS_XSPI_CMD_STATUS_FAILED) != 0) { 265 if (cmd_status & CDNS_XSPI_CMD_STATUS_DQS_ERROR) { 266 dev_err(cdns_xspi->dev, 267 "Incorrect DQS pulses detected\n"); 268 ret = -EPROTO; 269 } 270 if (cmd_status & CDNS_XSPI_CMD_STATUS_CRC_ERROR) { 271 dev_err(cdns_xspi->dev, 272 "CRC error received\n"); 273 ret = -EPROTO; 274 } 275 if (cmd_status & CDNS_XSPI_CMD_STATUS_BUS_ERROR) { 276 dev_err(cdns_xspi->dev, 277 "Error resp on system DMA interface\n"); 278 ret = -EPROTO; 279 } 280 if (cmd_status & CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR) { 281 dev_err(cdns_xspi->dev, 282 "Invalid command sequence detected\n"); 283 ret = -EPROTO; 284 } 285 } 286 } else { 287 dev_err(cdns_xspi->dev, "Fatal err - command not completed\n"); 288 ret = -EPROTO; 289 } 290 291 return ret; 292 } 293 294 static void cdns_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi, 295 bool enabled) 296 { 297 u32 intr_enable; 298 299 intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG); 300 if (enabled) 301 intr_enable |= CDNS_XSPI_INTR_MASK; 302 else 303 intr_enable &= ~CDNS_XSPI_INTR_MASK; 304 writel(intr_enable, cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG); 305 } 306 307 static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi) 308 { 309 u32 ctrl_ver; 310 u32 ctrl_features; 311 u16 hw_magic_num; 312 313 ctrl_ver = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_VERSION_REG); 314 hw_magic_num = FIELD_GET(CDNS_XSPI_MAGIC_NUM, ctrl_ver); 315 if (hw_magic_num != CDNS_XSPI_MAGIC_NUM_VALUE) { 316 dev_err(cdns_xspi->dev, 317 "Incorrect XSPI magic number: %x, expected: %x\n", 318 hw_magic_num, CDNS_XSPI_MAGIC_NUM_VALUE); 319 return -EIO; 320 } 321 322 ctrl_features = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_FEATURES_REG); 323 cdns_xspi->hw_num_banks = FIELD_GET(CDNS_XSPI_NUM_BANKS, ctrl_features); 324 cdns_xspi_set_interrupts(cdns_xspi, false); 325 326 return 0; 327 } 328 329 static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi) 330 { 331 u32 sdma_size, sdma_trd_info; 332 u8 sdma_dir; 333 334 sdma_size = readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_SIZE_REG); 335 sdma_trd_info = readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_TRD_INFO_REG); 336 sdma_dir = FIELD_GET(CDNS_XSPI_SDMA_DIR, sdma_trd_info); 337 338 switch (sdma_dir) { 339 case CDNS_XSPI_SDMA_DIR_READ: 340 ioread8_rep(cdns_xspi->sdmabase, 341 cdns_xspi->in_buffer, sdma_size); 342 break; 343 344 case CDNS_XSPI_SDMA_DIR_WRITE: 345 iowrite8_rep(cdns_xspi->sdmabase, 346 cdns_xspi->out_buffer, sdma_size); 347 break; 348 } 349 } 350 351 static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi, 352 const struct spi_mem_op *op, 353 bool data_phase) 354 { 355 u32 cmd_regs[6]; 356 u32 cmd_status; 357 int ret; 358 int dummybytes = op->dummy.nbytes; 359 360 ret = cdns_xspi_wait_for_controller_idle(cdns_xspi); 361 if (ret < 0) 362 return -EIO; 363 364 writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG), 365 cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG); 366 367 cdns_xspi_set_interrupts(cdns_xspi, true); 368 cdns_xspi->sdma_error = false; 369 370 memset(cmd_regs, 0, sizeof(cmd_regs)); 371 cmd_regs[1] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase); 372 cmd_regs[2] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op); 373 if (dummybytes != 0) { 374 cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, 1); 375 dummybytes--; 376 } else { 377 cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, 0); 378 } 379 cmd_regs[4] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, 380 cdns_xspi->cur_cs); 381 382 cdns_xspi_trigger_command(cdns_xspi, cmd_regs); 383 384 if (data_phase) { 385 cmd_regs[0] = CDNS_XSPI_STIG_DONE_FLAG; 386 cmd_regs[1] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op); 387 cmd_regs[2] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op); 388 cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes); 389 cmd_regs[4] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, 390 cdns_xspi->cur_cs); 391 392 cdns_xspi->in_buffer = op->data.buf.in; 393 cdns_xspi->out_buffer = op->data.buf.out; 394 395 cdns_xspi_trigger_command(cdns_xspi, cmd_regs); 396 397 wait_for_completion(&cdns_xspi->sdma_complete); 398 if (cdns_xspi->sdma_error) { 399 cdns_xspi_set_interrupts(cdns_xspi, false); 400 return -EIO; 401 } 402 cdns_xspi_sdma_handle(cdns_xspi); 403 } 404 405 wait_for_completion(&cdns_xspi->cmd_complete); 406 cdns_xspi_set_interrupts(cdns_xspi, false); 407 408 cmd_status = cdns_xspi_check_command_status(cdns_xspi); 409 if (cmd_status) 410 return -EPROTO; 411 412 return 0; 413 } 414 415 static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi, 416 struct spi_mem *mem, 417 const struct spi_mem_op *op) 418 { 419 enum spi_mem_data_dir dir = op->data.dir; 420 421 if (cdns_xspi->cur_cs != spi_get_chipselect(mem->spi, 0)) 422 cdns_xspi->cur_cs = spi_get_chipselect(mem->spi, 0); 423 424 return cdns_xspi_send_stig_command(cdns_xspi, op, 425 (dir != SPI_MEM_NO_DATA)); 426 } 427 428 static int cdns_xspi_mem_op_execute(struct spi_mem *mem, 429 const struct spi_mem_op *op) 430 { 431 struct cdns_xspi_dev *cdns_xspi = 432 spi_controller_get_devdata(mem->spi->controller); 433 int ret = 0; 434 435 ret = cdns_xspi_mem_op(cdns_xspi, mem, op); 436 437 return ret; 438 } 439 440 static int cdns_xspi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op) 441 { 442 struct cdns_xspi_dev *cdns_xspi = 443 spi_controller_get_devdata(mem->spi->controller); 444 445 op->data.nbytes = clamp_val(op->data.nbytes, 0, cdns_xspi->sdmasize); 446 447 return 0; 448 } 449 450 static const struct spi_controller_mem_ops cadence_xspi_mem_ops = { 451 .exec_op = cdns_xspi_mem_op_execute, 452 .adjust_op_size = cdns_xspi_adjust_mem_op_size, 453 }; 454 455 static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev) 456 { 457 struct cdns_xspi_dev *cdns_xspi = dev; 458 u32 irq_status; 459 irqreturn_t result = IRQ_NONE; 460 461 irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG); 462 writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG); 463 464 if (irq_status & 465 (CDNS_XSPI_SDMA_ERROR | CDNS_XSPI_SDMA_TRIGGER | 466 CDNS_XSPI_STIG_DONE)) { 467 if (irq_status & CDNS_XSPI_SDMA_ERROR) { 468 dev_err(cdns_xspi->dev, 469 "Slave DMA transaction error\n"); 470 cdns_xspi->sdma_error = true; 471 complete(&cdns_xspi->sdma_complete); 472 } 473 474 if (irq_status & CDNS_XSPI_SDMA_TRIGGER) 475 complete(&cdns_xspi->sdma_complete); 476 477 if (irq_status & CDNS_XSPI_STIG_DONE) 478 complete(&cdns_xspi->cmd_complete); 479 480 result = IRQ_HANDLED; 481 } 482 483 irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_TRD_COMP_INTR_STATUS); 484 if (irq_status) { 485 writel(irq_status, 486 cdns_xspi->iobase + CDNS_XSPI_TRD_COMP_INTR_STATUS); 487 488 complete(&cdns_xspi->auto_cmd_complete); 489 490 result = IRQ_HANDLED; 491 } 492 493 return result; 494 } 495 496 static int cdns_xspi_of_get_plat_data(struct platform_device *pdev) 497 { 498 struct device_node *node_prop = pdev->dev.of_node; 499 unsigned int cs; 500 501 for_each_available_child_of_node_scoped(node_prop, node_child) { 502 if (of_property_read_u32(node_child, "reg", &cs)) { 503 dev_err(&pdev->dev, "Couldn't get memory chip select\n"); 504 return -ENXIO; 505 } else if (cs >= CDNS_XSPI_MAX_BANKS) { 506 dev_err(&pdev->dev, "reg (cs) parameter value too large\n"); 507 return -ENXIO; 508 } 509 } 510 511 return 0; 512 } 513 514 static void cdns_xspi_print_phy_config(struct cdns_xspi_dev *cdns_xspi) 515 { 516 struct device *dev = cdns_xspi->dev; 517 518 dev_info(dev, "PHY configuration\n"); 519 dev_info(dev, " * xspi_dll_phy_ctrl: %08x\n", 520 readl(cdns_xspi->iobase + CDNS_XSPI_DLL_PHY_CTRL)); 521 dev_info(dev, " * phy_dq_timing: %08x\n", 522 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DQ_TIMING)); 523 dev_info(dev, " * phy_dqs_timing: %08x\n", 524 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DQS_TIMING)); 525 dev_info(dev, " * phy_gate_loopback_ctrl: %08x\n", 526 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL)); 527 dev_info(dev, " * phy_dll_slave_ctrl: %08x\n", 528 readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL)); 529 } 530 531 static int cdns_xspi_probe(struct platform_device *pdev) 532 { 533 struct device *dev = &pdev->dev; 534 struct spi_controller *host = NULL; 535 struct cdns_xspi_dev *cdns_xspi = NULL; 536 struct resource *res; 537 int ret; 538 539 host = devm_spi_alloc_host(dev, sizeof(*cdns_xspi)); 540 if (!host) 541 return -ENOMEM; 542 543 host->mode_bits = SPI_3WIRE | SPI_TX_DUAL | SPI_TX_QUAD | 544 SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL | SPI_RX_OCTAL | 545 SPI_MODE_0 | SPI_MODE_3; 546 547 host->mem_ops = &cadence_xspi_mem_ops; 548 host->dev.of_node = pdev->dev.of_node; 549 host->bus_num = -1; 550 551 platform_set_drvdata(pdev, host); 552 553 cdns_xspi = spi_controller_get_devdata(host); 554 cdns_xspi->pdev = pdev; 555 cdns_xspi->dev = &pdev->dev; 556 cdns_xspi->cur_cs = 0; 557 558 init_completion(&cdns_xspi->cmd_complete); 559 init_completion(&cdns_xspi->auto_cmd_complete); 560 init_completion(&cdns_xspi->sdma_complete); 561 562 ret = cdns_xspi_of_get_plat_data(pdev); 563 if (ret) 564 return -ENODEV; 565 566 cdns_xspi->iobase = devm_platform_ioremap_resource_byname(pdev, "io"); 567 if (IS_ERR(cdns_xspi->iobase)) { 568 dev_err(dev, "Failed to remap controller base address\n"); 569 return PTR_ERR(cdns_xspi->iobase); 570 } 571 572 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sdma"); 573 cdns_xspi->sdmabase = devm_ioremap_resource(dev, res); 574 if (IS_ERR(cdns_xspi->sdmabase)) 575 return PTR_ERR(cdns_xspi->sdmabase); 576 cdns_xspi->sdmasize = resource_size(res); 577 578 cdns_xspi->auxbase = devm_platform_ioremap_resource_byname(pdev, "aux"); 579 if (IS_ERR(cdns_xspi->auxbase)) { 580 dev_err(dev, "Failed to remap AUX address\n"); 581 return PTR_ERR(cdns_xspi->auxbase); 582 } 583 584 cdns_xspi->irq = platform_get_irq(pdev, 0); 585 if (cdns_xspi->irq < 0) 586 return -ENXIO; 587 588 ret = devm_request_irq(dev, cdns_xspi->irq, cdns_xspi_irq_handler, 589 IRQF_SHARED, pdev->name, cdns_xspi); 590 if (ret) { 591 dev_err(dev, "Failed to request IRQ: %d\n", cdns_xspi->irq); 592 return ret; 593 } 594 595 cdns_xspi_print_phy_config(cdns_xspi); 596 597 ret = cdns_xspi_controller_init(cdns_xspi); 598 if (ret) { 599 dev_err(dev, "Failed to initialize controller\n"); 600 return ret; 601 } 602 603 host->num_chipselect = 1 << cdns_xspi->hw_num_banks; 604 605 ret = devm_spi_register_controller(dev, host); 606 if (ret) { 607 dev_err(dev, "Failed to register SPI host\n"); 608 return ret; 609 } 610 611 dev_info(dev, "Successfully registered SPI host\n"); 612 613 return 0; 614 } 615 616 static const struct of_device_id cdns_xspi_of_match[] = { 617 { 618 .compatible = "cdns,xspi-nor", 619 }, 620 { /* end of table */} 621 }; 622 MODULE_DEVICE_TABLE(of, cdns_xspi_of_match); 623 624 static struct platform_driver cdns_xspi_platform_driver = { 625 .probe = cdns_xspi_probe, 626 .driver = { 627 .name = CDNS_XSPI_NAME, 628 .of_match_table = cdns_xspi_of_match, 629 }, 630 }; 631 632 module_platform_driver(cdns_xspi_platform_driver); 633 634 MODULE_DESCRIPTION("Cadence XSPI Controller Driver"); 635 MODULE_LICENSE("GPL v2"); 636 MODULE_ALIAS("platform:" CDNS_XSPI_NAME); 637 MODULE_AUTHOR("Konrad Kociolek <konrad@cadence.com>"); 638 MODULE_AUTHOR("Jayshri Pawar <jpawar@cadence.com>"); 639 MODULE_AUTHOR("Parshuram Thombare <pthombar@cadence.com>"); 640