1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cadence QSPI Controller 4 // 5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 8 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/firmware/xlnx-zynqmp.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/jiffies.h> 21 #include <linux/kernel.h> 22 #include <linux/log2.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/reset.h> 28 #include <linux/sched.h> 29 #include <linux/spi/spi.h> 30 #include <linux/spi/spi-mem.h> 31 #include <linux/timer.h> 32 33 #define CQSPI_NAME "cadence-qspi" 34 #define CQSPI_MAX_CHIPSELECT 4 35 36 static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX); 37 38 /* Quirks */ 39 #define CQSPI_NEEDS_WR_DELAY BIT(0) 40 #define CQSPI_DISABLE_DAC_MODE BIT(1) 41 #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 42 #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 43 #define CQSPI_SLOW_SRAM BIT(4) 44 #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) 45 #define CQSPI_RD_NO_IRQ BIT(6) 46 #define CQSPI_DMA_SET_MASK BIT(7) 47 #define CQSPI_SUPPORT_DEVICE_RESET BIT(8) 48 #define CQSPI_DISABLE_STIG_MODE BIT(9) 49 #define CQSPI_DISABLE_RUNTIME_PM BIT(10) 50 51 /* Capabilities */ 52 #define CQSPI_SUPPORTS_OCTAL BIT(0) 53 #define CQSPI_SUPPORTS_QUAD BIT(1) 54 55 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 56 57 enum { 58 CLK_QSPI_APB = 0, 59 CLK_QSPI_AHB, 60 CLK_QSPI_NUM, 61 }; 62 63 struct cqspi_st; 64 65 struct cqspi_flash_pdata { 66 struct cqspi_st *cqspi; 67 u32 clk_rate; 68 u32 read_delay; 69 u32 tshsl_ns; 70 u32 tsd2d_ns; 71 u32 tchsh_ns; 72 u32 tslch_ns; 73 u8 cs; 74 }; 75 76 struct cqspi_st { 77 struct platform_device *pdev; 78 struct spi_controller *host; 79 struct clk *clk; 80 struct clk *clks[CLK_QSPI_NUM]; 81 unsigned int sclk; 82 83 void __iomem *iobase; 84 void __iomem *ahb_base; 85 resource_size_t ahb_size; 86 struct completion transfer_complete; 87 88 struct dma_chan *rx_chan; 89 struct completion rx_dma_complete; 90 dma_addr_t mmap_phys_base; 91 92 int current_cs; 93 unsigned long master_ref_clk_hz; 94 bool is_decoded_cs; 95 u32 fifo_depth; 96 u32 fifo_width; 97 u32 num_chipselect; 98 bool rclk_en; 99 u32 trigger_address; 100 u32 wr_delay; 101 bool use_direct_mode; 102 bool use_direct_mode_wr; 103 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 104 bool use_dma_read; 105 u32 pd_dev_id; 106 bool wr_completion; 107 bool slow_sram; 108 bool apb_ahb_hazard; 109 110 bool is_jh7110; /* Flag for StarFive JH7110 SoC */ 111 bool disable_stig_mode; 112 refcount_t refcount; 113 refcount_t inflight_ops; 114 115 const struct cqspi_driver_platdata *ddata; 116 }; 117 118 struct cqspi_driver_platdata { 119 u32 hwcaps_mask; 120 u16 quirks; 121 int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 122 u_char *rxbuf, loff_t from_addr, size_t n_rx); 123 u32 (*get_dma_status)(struct cqspi_st *cqspi); 124 int (*jh7110_clk_init)(struct platform_device *pdev, 125 struct cqspi_st *cqspi); 126 }; 127 128 /* Operation timeout value */ 129 #define CQSPI_TIMEOUT_MS 500 130 #define CQSPI_READ_TIMEOUT_MS 10 131 #define CQSPI_BUSYWAIT_TIMEOUT_US 500 132 133 /* Runtime_pm autosuspend delay */ 134 #define CQSPI_AUTOSUSPEND_TIMEOUT 2000 135 136 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 137 #define CQSPI_DUMMY_BYTES_MAX 4 138 #define CQSPI_DUMMY_CLKS_MAX 31 139 140 #define CQSPI_STIG_DATA_LEN_MAX 8 141 142 /* Register map */ 143 #define CQSPI_REG_CONFIG 0x00 144 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 145 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 146 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 147 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 148 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 149 #define CQSPI_REG_CONFIG_BAUD_LSB 19 150 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 151 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 152 #define CQSPI_REG_CONFIG_IDLE_LSB 31 153 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 154 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 155 #define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5) 156 #define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6) 157 158 #define CQSPI_REG_RD_INSTR 0x04 159 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 160 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 161 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 162 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 163 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 164 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 165 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 166 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 167 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 168 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 169 170 #define CQSPI_REG_WR_INSTR 0x08 171 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 172 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 173 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 174 175 #define CQSPI_REG_DELAY 0x0C 176 #define CQSPI_REG_DELAY_TSLCH_LSB 0 177 #define CQSPI_REG_DELAY_TCHSH_LSB 8 178 #define CQSPI_REG_DELAY_TSD2D_LSB 16 179 #define CQSPI_REG_DELAY_TSHSL_LSB 24 180 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 181 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 182 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 183 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 184 185 #define CQSPI_REG_READCAPTURE 0x10 186 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 187 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 188 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 189 190 #define CQSPI_REG_SIZE 0x14 191 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 192 #define CQSPI_REG_SIZE_PAGE_LSB 4 193 #define CQSPI_REG_SIZE_BLOCK_LSB 16 194 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 195 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 196 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 197 198 #define CQSPI_REG_SRAMPARTITION 0x18 199 #define CQSPI_REG_INDIRECTTRIGGER 0x1C 200 201 #define CQSPI_REG_DMA 0x20 202 #define CQSPI_REG_DMA_SINGLE_LSB 0 203 #define CQSPI_REG_DMA_BURST_LSB 8 204 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 205 #define CQSPI_REG_DMA_BURST_MASK 0xFF 206 207 #define CQSPI_REG_REMAP 0x24 208 #define CQSPI_REG_MODE_BIT 0x28 209 210 #define CQSPI_REG_SDRAMLEVEL 0x2C 211 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 212 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 213 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 214 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 215 216 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 217 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 218 219 #define CQSPI_REG_IRQSTATUS 0x40 220 #define CQSPI_REG_IRQMASK 0x44 221 222 #define CQSPI_REG_INDIRECTRD 0x60 223 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 224 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 225 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 226 227 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 228 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 229 #define CQSPI_REG_INDIRECTRDBYTES 0x6C 230 231 #define CQSPI_REG_CMDCTRL 0x90 232 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 233 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 234 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 235 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 236 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 237 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 238 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 239 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 240 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 241 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 242 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 243 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 244 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 245 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 246 247 #define CQSPI_REG_INDIRECTWR 0x70 248 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 249 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 250 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 251 252 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 253 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 254 #define CQSPI_REG_INDIRECTWRBYTES 0x7C 255 256 #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 257 258 #define CQSPI_REG_CMDADDRESS 0x94 259 #define CQSPI_REG_CMDREADDATALOWER 0xA0 260 #define CQSPI_REG_CMDREADDATAUPPER 0xA4 261 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 262 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 263 264 #define CQSPI_REG_POLLING_STATUS 0xB0 265 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 266 267 #define CQSPI_REG_OP_EXT_LOWER 0xE0 268 #define CQSPI_REG_OP_EXT_READ_LSB 24 269 #define CQSPI_REG_OP_EXT_WRITE_LSB 16 270 #define CQSPI_REG_OP_EXT_STIG_LSB 0 271 272 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 273 274 #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 275 #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 276 277 #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 278 279 #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 280 #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 281 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 282 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 283 284 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 285 286 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 287 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 288 289 /* Interrupt status bits */ 290 #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 291 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 292 #define CQSPI_REG_IRQ_IND_COMP BIT(2) 293 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 294 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 295 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 296 #define CQSPI_REG_IRQ_WATERMARK BIT(6) 297 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 298 299 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 300 CQSPI_REG_IRQ_IND_SRAM_FULL | \ 301 CQSPI_REG_IRQ_IND_COMP) 302 303 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 304 CQSPI_REG_IRQ_WATERMARK | \ 305 CQSPI_REG_IRQ_UNDERFLOW) 306 307 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 308 #define CQSPI_DMA_UNALIGN 0x3 309 310 #define CQSPI_REG_VERSAL_DMA_VAL 0x602 311 312 static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata, 313 void __iomem *reg, const u32 mask, bool clr, 314 bool busywait) 315 { 316 u64 timeout_us = CQSPI_TIMEOUT_MS * USEC_PER_MSEC; 317 u32 val; 318 319 if (busywait) { 320 int ret = readl_relaxed_poll_timeout(reg, val, 321 (((clr ? ~val : val) & mask) == mask), 322 0, CQSPI_BUSYWAIT_TIMEOUT_US); 323 324 if (ret != -ETIMEDOUT) 325 return ret; 326 327 timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US; 328 } 329 330 return readl_relaxed_poll_timeout(reg, val, 331 (((clr ? ~val : val) & mask) == mask), 332 10, timeout_us); 333 } 334 335 static bool cqspi_is_idle(struct cqspi_st *cqspi) 336 { 337 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 338 339 return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 340 } 341 342 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 343 { 344 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 345 346 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 347 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 348 } 349 350 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 351 { 352 u32 dma_status; 353 354 dma_status = readl(cqspi->iobase + 355 CQSPI_REG_VERSAL_DMA_DST_I_STS); 356 writel(dma_status, cqspi->iobase + 357 CQSPI_REG_VERSAL_DMA_DST_I_STS); 358 359 return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 360 } 361 362 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 363 { 364 struct cqspi_st *cqspi = dev; 365 const struct cqspi_driver_platdata *ddata = cqspi->ddata; 366 unsigned int irq_status; 367 368 /* Read interrupt status */ 369 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 370 371 /* Clear interrupt */ 372 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 373 374 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 375 if (ddata->get_dma_status(cqspi)) { 376 complete(&cqspi->transfer_complete); 377 return IRQ_HANDLED; 378 } 379 } 380 381 else if (!cqspi->slow_sram) 382 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 383 else 384 irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR; 385 386 if (irq_status) 387 complete(&cqspi->transfer_complete); 388 389 return IRQ_HANDLED; 390 } 391 392 static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) 393 { 394 u32 rdreg = 0; 395 396 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 397 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 398 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 399 400 return rdreg; 401 } 402 403 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 404 { 405 unsigned int dummy_clk; 406 407 if (!op->dummy.nbytes) 408 return 0; 409 410 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 411 if (op->cmd.dtr) 412 dummy_clk /= 2; 413 414 return dummy_clk; 415 } 416 417 static int cqspi_wait_idle(struct cqspi_st *cqspi) 418 { 419 const unsigned int poll_idle_retry = 3; 420 unsigned int count = 0; 421 unsigned long timeout; 422 423 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 424 while (1) { 425 /* 426 * Read few times in succession to ensure the controller 427 * is indeed idle, that is, the bit does not transition 428 * low again. 429 */ 430 if (cqspi_is_idle(cqspi)) 431 count++; 432 else 433 count = 0; 434 435 if (count >= poll_idle_retry) 436 return 0; 437 438 if (time_after(jiffies, timeout)) { 439 /* Timeout, in busy mode. */ 440 dev_err(&cqspi->pdev->dev, 441 "QSPI is still busy after %dms timeout.\n", 442 CQSPI_TIMEOUT_MS); 443 return -ETIMEDOUT; 444 } 445 446 cpu_relax(); 447 } 448 } 449 450 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 451 { 452 void __iomem *reg_base = cqspi->iobase; 453 int ret; 454 455 /* Write the CMDCTRL without start execution. */ 456 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 457 /* Start execute */ 458 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 459 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 460 461 /* Polling for completion. */ 462 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL, 463 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1, true); 464 if (ret) { 465 dev_err(&cqspi->pdev->dev, 466 "Flash command execution timed out.\n"); 467 return ret; 468 } 469 470 /* Polling QSPI idle status. */ 471 return cqspi_wait_idle(cqspi); 472 } 473 474 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 475 const struct spi_mem_op *op, 476 unsigned int shift) 477 { 478 struct cqspi_st *cqspi = f_pdata->cqspi; 479 void __iomem *reg_base = cqspi->iobase; 480 unsigned int reg; 481 u8 ext; 482 483 if (op->cmd.nbytes != 2) 484 return -EINVAL; 485 486 /* Opcode extension is the LSB. */ 487 ext = op->cmd.opcode & 0xff; 488 489 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 490 reg &= ~(0xff << shift); 491 reg |= ext << shift; 492 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 493 494 return 0; 495 } 496 497 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 498 const struct spi_mem_op *op, unsigned int shift) 499 { 500 struct cqspi_st *cqspi = f_pdata->cqspi; 501 void __iomem *reg_base = cqspi->iobase; 502 unsigned int reg; 503 int ret; 504 505 reg = readl(reg_base + CQSPI_REG_CONFIG); 506 507 /* 508 * We enable dual byte opcode here. The callers have to set up the 509 * extension opcode based on which type of operation it is. 510 */ 511 if (op->cmd.dtr) { 512 reg |= CQSPI_REG_CONFIG_DTR_PROTO; 513 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 514 515 /* Set up command opcode extension. */ 516 ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 517 if (ret) 518 return ret; 519 } else { 520 unsigned int mask = CQSPI_REG_CONFIG_DTR_PROTO | CQSPI_REG_CONFIG_DUAL_OPCODE; 521 /* Shortcut if DTR is already disabled. */ 522 if ((reg & mask) == 0) 523 return 0; 524 reg &= ~mask; 525 } 526 527 writel(reg, reg_base + CQSPI_REG_CONFIG); 528 529 return cqspi_wait_idle(cqspi); 530 } 531 532 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 533 const struct spi_mem_op *op) 534 { 535 struct cqspi_st *cqspi = f_pdata->cqspi; 536 void __iomem *reg_base = cqspi->iobase; 537 u8 *rxbuf = op->data.buf.in; 538 u8 opcode; 539 size_t n_rx = op->data.nbytes; 540 unsigned int rdreg; 541 unsigned int reg; 542 unsigned int dummy_clk; 543 size_t read_len; 544 int status; 545 546 status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 547 if (status) 548 return status; 549 550 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 551 dev_err(&cqspi->pdev->dev, 552 "Invalid input argument, len %zu rxbuf 0x%p\n", 553 n_rx, rxbuf); 554 return -EINVAL; 555 } 556 557 if (op->cmd.dtr) 558 opcode = op->cmd.opcode >> 8; 559 else 560 opcode = op->cmd.opcode; 561 562 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 563 564 rdreg = cqspi_calc_rdreg(op); 565 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 566 567 dummy_clk = cqspi_calc_dummy(op); 568 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 569 return -EOPNOTSUPP; 570 571 if (dummy_clk) 572 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 573 << CQSPI_REG_CMDCTRL_DUMMY_LSB; 574 575 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 576 577 /* 0 means 1 byte. */ 578 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 579 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 580 581 /* setup ADDR BIT field */ 582 if (op->addr.nbytes) { 583 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 584 reg |= ((op->addr.nbytes - 1) & 585 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 586 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 587 588 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 589 } 590 591 status = cqspi_exec_flash_cmd(cqspi, reg); 592 if (status) 593 return status; 594 595 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 596 597 /* Put the read value into rx_buf */ 598 read_len = (n_rx > 4) ? 4 : n_rx; 599 memcpy(rxbuf, ®, read_len); 600 rxbuf += read_len; 601 602 if (n_rx > 4) { 603 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 604 605 read_len = n_rx - read_len; 606 memcpy(rxbuf, ®, read_len); 607 } 608 609 /* Reset CMD_CTRL Reg once command read completes */ 610 writel(0, reg_base + CQSPI_REG_CMDCTRL); 611 612 return 0; 613 } 614 615 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 616 const struct spi_mem_op *op) 617 { 618 struct cqspi_st *cqspi = f_pdata->cqspi; 619 void __iomem *reg_base = cqspi->iobase; 620 u8 opcode; 621 const u8 *txbuf = op->data.buf.out; 622 size_t n_tx = op->data.nbytes; 623 unsigned int reg; 624 unsigned int data; 625 size_t write_len; 626 int ret; 627 628 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 629 if (ret) 630 return ret; 631 632 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 633 dev_err(&cqspi->pdev->dev, 634 "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 635 n_tx, txbuf); 636 return -EINVAL; 637 } 638 639 reg = cqspi_calc_rdreg(op); 640 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 641 642 if (op->cmd.dtr) 643 opcode = op->cmd.opcode >> 8; 644 else 645 opcode = op->cmd.opcode; 646 647 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 648 649 if (op->addr.nbytes) { 650 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 651 reg |= ((op->addr.nbytes - 1) & 652 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 653 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 654 655 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 656 } 657 658 if (n_tx) { 659 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 660 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 661 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 662 data = 0; 663 write_len = (n_tx > 4) ? 4 : n_tx; 664 memcpy(&data, txbuf, write_len); 665 txbuf += write_len; 666 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 667 668 if (n_tx > 4) { 669 data = 0; 670 write_len = n_tx - 4; 671 memcpy(&data, txbuf, write_len); 672 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 673 } 674 } 675 676 ret = cqspi_exec_flash_cmd(cqspi, reg); 677 678 /* Reset CMD_CTRL Reg once command write completes */ 679 writel(0, reg_base + CQSPI_REG_CMDCTRL); 680 681 return ret; 682 } 683 684 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 685 const struct spi_mem_op *op) 686 { 687 struct cqspi_st *cqspi = f_pdata->cqspi; 688 void __iomem *reg_base = cqspi->iobase; 689 unsigned int dummy_clk = 0; 690 unsigned int reg; 691 int ret; 692 u8 opcode; 693 694 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); 695 if (ret) 696 return ret; 697 698 if (op->cmd.dtr) 699 opcode = op->cmd.opcode >> 8; 700 else 701 opcode = op->cmd.opcode; 702 703 reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 704 reg |= cqspi_calc_rdreg(op); 705 706 /* Setup dummy clock cycles */ 707 dummy_clk = cqspi_calc_dummy(op); 708 709 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 710 return -EOPNOTSUPP; 711 712 if (dummy_clk) 713 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 714 << CQSPI_REG_RD_INSTR_DUMMY_LSB; 715 716 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 717 718 /* Set address width */ 719 reg = readl(reg_base + CQSPI_REG_SIZE); 720 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 721 reg |= (op->addr.nbytes - 1); 722 writel(reg, reg_base + CQSPI_REG_SIZE); 723 return 0; 724 } 725 726 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 727 u8 *rxbuf, loff_t from_addr, 728 const size_t n_rx) 729 { 730 struct cqspi_st *cqspi = f_pdata->cqspi; 731 bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ); 732 struct device *dev = &cqspi->pdev->dev; 733 void __iomem *reg_base = cqspi->iobase; 734 void __iomem *ahb_base = cqspi->ahb_base; 735 unsigned int remaining = n_rx; 736 unsigned int mod_bytes = n_rx % 4; 737 unsigned int bytes_to_read = 0; 738 u8 *rxbuf_end = rxbuf + n_rx; 739 int ret = 0; 740 741 if (!refcount_read(&cqspi->refcount)) 742 return -ENODEV; 743 744 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 745 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 746 747 /* Clear all interrupts. */ 748 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 749 750 /* 751 * On SoCFPGA platform reading the SRAM is slow due to 752 * hardware limitation and causing read interrupt storm to CPU, 753 * so enabling only watermark interrupt to disable all read 754 * interrupts later as we want to run "bytes to read" loop with 755 * all the read interrupts disabled for max performance. 756 */ 757 758 if (use_irq && cqspi->slow_sram) 759 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 760 else if (use_irq) 761 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 762 else 763 writel(0, reg_base + CQSPI_REG_IRQMASK); 764 765 reinit_completion(&cqspi->transfer_complete); 766 writel(CQSPI_REG_INDIRECTRD_START_MASK, 767 reg_base + CQSPI_REG_INDIRECTRD); 768 769 while (remaining > 0) { 770 if (use_irq && 771 !wait_for_completion_timeout(&cqspi->transfer_complete, 772 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 773 ret = -ETIMEDOUT; 774 775 /* 776 * Disable all read interrupts until 777 * we are out of "bytes to read" 778 */ 779 if (cqspi->slow_sram) 780 writel(0x0, reg_base + CQSPI_REG_IRQMASK); 781 782 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 783 784 if (ret && bytes_to_read == 0) { 785 dev_err(dev, "Indirect read timeout, no bytes\n"); 786 goto failrd; 787 } 788 789 while (bytes_to_read != 0) { 790 unsigned int word_remain = round_down(remaining, 4); 791 792 bytes_to_read *= cqspi->fifo_width; 793 bytes_to_read = bytes_to_read > remaining ? 794 remaining : bytes_to_read; 795 bytes_to_read = round_down(bytes_to_read, 4); 796 /* Read 4 byte word chunks then single bytes */ 797 if (bytes_to_read) { 798 ioread32_rep(ahb_base, rxbuf, 799 (bytes_to_read / 4)); 800 } else if (!word_remain && mod_bytes) { 801 unsigned int temp = ioread32(ahb_base); 802 803 bytes_to_read = mod_bytes; 804 memcpy(rxbuf, &temp, min((unsigned int) 805 (rxbuf_end - rxbuf), 806 bytes_to_read)); 807 } 808 rxbuf += bytes_to_read; 809 remaining -= bytes_to_read; 810 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 811 } 812 813 if (use_irq && remaining > 0) { 814 reinit_completion(&cqspi->transfer_complete); 815 if (cqspi->slow_sram) 816 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 817 } 818 } 819 820 /* Check indirect done status */ 821 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD, 822 CQSPI_REG_INDIRECTRD_DONE_MASK, 0, true); 823 if (ret) { 824 dev_err(dev, "Indirect read completion error (%i)\n", ret); 825 goto failrd; 826 } 827 828 /* Disable interrupt */ 829 writel(0, reg_base + CQSPI_REG_IRQMASK); 830 831 /* Clear indirect completion status */ 832 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 833 834 return 0; 835 836 failrd: 837 /* Disable interrupt */ 838 writel(0, reg_base + CQSPI_REG_IRQMASK); 839 840 /* Cancel the indirect read */ 841 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, 842 reg_base + CQSPI_REG_INDIRECTRD); 843 return ret; 844 } 845 846 static void cqspi_device_reset(struct cqspi_st *cqspi) 847 { 848 u32 reg; 849 850 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 851 reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK; 852 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 853 /* 854 * NOTE: Delay timing implementation is derived from 855 * spi_nor_hw_reset() 856 */ 857 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); 858 usleep_range(1, 5); 859 writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); 860 usleep_range(100, 150); 861 writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_REG_CONFIG); 862 usleep_range(1000, 1200); 863 } 864 865 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 866 { 867 void __iomem *reg_base = cqspi->iobase; 868 unsigned int reg; 869 870 reg = readl(reg_base + CQSPI_REG_CONFIG); 871 872 if (enable) 873 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 874 else 875 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 876 877 writel(reg, reg_base + CQSPI_REG_CONFIG); 878 } 879 880 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 881 u_char *rxbuf, loff_t from_addr, 882 size_t n_rx) 883 { 884 struct cqspi_st *cqspi = f_pdata->cqspi; 885 struct device *dev = &cqspi->pdev->dev; 886 void __iomem *reg_base = cqspi->iobase; 887 u32 reg, bytes_to_dma; 888 loff_t addr = from_addr; 889 void *buf = rxbuf; 890 dma_addr_t dma_addr; 891 u8 bytes_rem; 892 int ret = 0; 893 894 bytes_rem = n_rx % 4; 895 bytes_to_dma = (n_rx - bytes_rem); 896 897 if (!bytes_to_dma) 898 goto nondmard; 899 900 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 901 if (ret) 902 return ret; 903 904 cqspi_controller_enable(cqspi, 0); 905 906 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 907 reg |= CQSPI_REG_CONFIG_DMA_MASK; 908 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 909 910 cqspi_controller_enable(cqspi, 1); 911 912 dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 913 if (dma_mapping_error(dev, dma_addr)) { 914 dev_err(dev, "dma mapping failed\n"); 915 return -ENOMEM; 916 } 917 918 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 919 writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 920 writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 921 reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 922 923 /* Clear all interrupts. */ 924 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 925 926 /* Enable DMA done interrupt */ 927 writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 928 reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 929 930 /* Default DMA periph configuration */ 931 writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 932 933 /* Configure DMA Dst address */ 934 writel(lower_32_bits(dma_addr), 935 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 936 writel(upper_32_bits(dma_addr), 937 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 938 939 /* Configure DMA Src address */ 940 writel(cqspi->trigger_address, reg_base + 941 CQSPI_REG_VERSAL_DMA_SRC_ADDR); 942 943 /* Set DMA destination size */ 944 writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 945 946 /* Set DMA destination control */ 947 writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 948 reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 949 950 writel(CQSPI_REG_INDIRECTRD_START_MASK, 951 reg_base + CQSPI_REG_INDIRECTRD); 952 953 reinit_completion(&cqspi->transfer_complete); 954 955 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 956 msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { 957 ret = -ETIMEDOUT; 958 goto failrd; 959 } 960 961 /* Disable DMA interrupt */ 962 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 963 964 /* Clear indirect completion status */ 965 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 966 cqspi->iobase + CQSPI_REG_INDIRECTRD); 967 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 968 969 cqspi_controller_enable(cqspi, 0); 970 971 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 972 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 973 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 974 975 cqspi_controller_enable(cqspi, 1); 976 977 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 978 PM_OSPI_MUX_SEL_LINEAR); 979 if (ret) 980 return ret; 981 982 nondmard: 983 if (bytes_rem) { 984 addr += bytes_to_dma; 985 buf += bytes_to_dma; 986 ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 987 bytes_rem); 988 if (ret) 989 return ret; 990 } 991 992 return 0; 993 994 failrd: 995 /* Disable DMA interrupt */ 996 writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 997 998 /* Cancel the indirect read */ 999 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 1000 reg_base + CQSPI_REG_INDIRECTRD); 1001 1002 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 1003 1004 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1005 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 1006 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1007 1008 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 1009 1010 return ret; 1011 } 1012 1013 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 1014 const struct spi_mem_op *op) 1015 { 1016 unsigned int reg; 1017 int ret; 1018 struct cqspi_st *cqspi = f_pdata->cqspi; 1019 void __iomem *reg_base = cqspi->iobase; 1020 u8 opcode; 1021 1022 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); 1023 if (ret) 1024 return ret; 1025 1026 if (op->cmd.dtr) 1027 opcode = op->cmd.opcode >> 8; 1028 else 1029 opcode = op->cmd.opcode; 1030 1031 /* Set opcode. */ 1032 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 1033 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 1034 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 1035 writel(reg, reg_base + CQSPI_REG_WR_INSTR); 1036 reg = cqspi_calc_rdreg(op); 1037 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 1038 1039 /* 1040 * SPI NAND flashes require the address of the status register to be 1041 * passed in the Read SR command. Also, some SPI NOR flashes like the 1042 * cypress Semper flash expect a 4-byte dummy address in the Read SR 1043 * command in DTR mode. 1044 * 1045 * But this controller does not support address phase in the Read SR 1046 * command when doing auto-HW polling. So, disable write completion 1047 * polling on the controller's side. spinand and spi-nor will take 1048 * care of polling the status register. 1049 */ 1050 if (cqspi->wr_completion) { 1051 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 1052 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 1053 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 1054 /* 1055 * DAC mode require auto polling as flash needs to be polled 1056 * for write completion in case of bubble in SPI transaction 1057 * due to slow CPU/DMA master. 1058 */ 1059 cqspi->use_direct_mode_wr = false; 1060 } 1061 1062 reg = readl(reg_base + CQSPI_REG_SIZE); 1063 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 1064 reg |= (op->addr.nbytes - 1); 1065 writel(reg, reg_base + CQSPI_REG_SIZE); 1066 return 0; 1067 } 1068 1069 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 1070 loff_t to_addr, const u8 *txbuf, 1071 const size_t n_tx) 1072 { 1073 struct cqspi_st *cqspi = f_pdata->cqspi; 1074 struct device *dev = &cqspi->pdev->dev; 1075 void __iomem *reg_base = cqspi->iobase; 1076 unsigned int remaining = n_tx; 1077 unsigned int write_bytes; 1078 int ret; 1079 1080 if (!refcount_read(&cqspi->refcount)) 1081 return -ENODEV; 1082 1083 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 1084 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 1085 1086 /* Clear all interrupts. */ 1087 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 1088 1089 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 1090 1091 reinit_completion(&cqspi->transfer_complete); 1092 writel(CQSPI_REG_INDIRECTWR_START_MASK, 1093 reg_base + CQSPI_REG_INDIRECTWR); 1094 /* 1095 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 1096 * Controller programming sequence, couple of cycles of 1097 * QSPI_REF_CLK delay is required for the above bit to 1098 * be internally synchronized by the QSPI module. Provide 5 1099 * cycles of delay. 1100 */ 1101 if (cqspi->wr_delay) 1102 ndelay(cqspi->wr_delay); 1103 1104 /* 1105 * If a hazard exists between the APB and AHB interfaces, perform a 1106 * dummy readback from the controller to ensure synchronization. 1107 */ 1108 if (cqspi->apb_ahb_hazard) 1109 readl(reg_base + CQSPI_REG_INDIRECTWR); 1110 1111 while (remaining > 0) { 1112 size_t write_words, mod_bytes; 1113 1114 write_bytes = remaining; 1115 write_words = write_bytes / 4; 1116 mod_bytes = write_bytes % 4; 1117 /* Write 4 bytes at a time then single bytes. */ 1118 if (write_words) { 1119 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 1120 txbuf += (write_words * 4); 1121 } 1122 if (mod_bytes) { 1123 unsigned int temp = 0xFFFFFFFF; 1124 1125 memcpy(&temp, txbuf, mod_bytes); 1126 iowrite32(temp, cqspi->ahb_base); 1127 txbuf += mod_bytes; 1128 } 1129 1130 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 1131 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 1132 dev_err(dev, "Indirect write timeout\n"); 1133 ret = -ETIMEDOUT; 1134 goto failwr; 1135 } 1136 1137 remaining -= write_bytes; 1138 1139 if (remaining > 0) 1140 reinit_completion(&cqspi->transfer_complete); 1141 } 1142 1143 /* Check indirect done status */ 1144 ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR, 1145 CQSPI_REG_INDIRECTWR_DONE_MASK, 0, false); 1146 if (ret) { 1147 dev_err(dev, "Indirect write completion error (%i)\n", ret); 1148 goto failwr; 1149 } 1150 1151 /* Disable interrupt. */ 1152 writel(0, reg_base + CQSPI_REG_IRQMASK); 1153 1154 /* Clear indirect completion status */ 1155 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 1156 1157 cqspi_wait_idle(cqspi); 1158 1159 return 0; 1160 1161 failwr: 1162 /* Disable interrupt. */ 1163 writel(0, reg_base + CQSPI_REG_IRQMASK); 1164 1165 /* Cancel the indirect write */ 1166 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 1167 reg_base + CQSPI_REG_INDIRECTWR); 1168 return ret; 1169 } 1170 1171 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 1172 { 1173 struct cqspi_st *cqspi = f_pdata->cqspi; 1174 void __iomem *reg_base = cqspi->iobase; 1175 unsigned int chip_select = f_pdata->cs; 1176 unsigned int reg; 1177 1178 reg = readl(reg_base + CQSPI_REG_CONFIG); 1179 if (cqspi->is_decoded_cs) { 1180 reg |= CQSPI_REG_CONFIG_DECODE_MASK; 1181 } else { 1182 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 1183 1184 /* Convert CS if without decoder. 1185 * CS0 to 4b'1110 1186 * CS1 to 4b'1101 1187 * CS2 to 4b'1011 1188 * CS3 to 4b'0111 1189 */ 1190 chip_select = 0xF & ~(1 << chip_select); 1191 } 1192 1193 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 1194 << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 1195 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 1196 << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 1197 writel(reg, reg_base + CQSPI_REG_CONFIG); 1198 } 1199 1200 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 1201 const unsigned int ns_val) 1202 { 1203 unsigned int ticks; 1204 1205 ticks = ref_clk_hz / 1000; /* kHz */ 1206 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 1207 1208 return ticks; 1209 } 1210 1211 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 1212 { 1213 struct cqspi_st *cqspi = f_pdata->cqspi; 1214 void __iomem *iobase = cqspi->iobase; 1215 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1216 unsigned int tshsl, tchsh, tslch, tsd2d; 1217 unsigned int reg; 1218 unsigned int tsclk; 1219 1220 /* calculate the number of ref ticks for one sclk tick */ 1221 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 1222 1223 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 1224 /* this particular value must be at least one sclk */ 1225 if (tshsl < tsclk) 1226 tshsl = tsclk; 1227 1228 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 1229 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 1230 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 1231 1232 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 1233 << CQSPI_REG_DELAY_TSHSL_LSB; 1234 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 1235 << CQSPI_REG_DELAY_TCHSH_LSB; 1236 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 1237 << CQSPI_REG_DELAY_TSLCH_LSB; 1238 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 1239 << CQSPI_REG_DELAY_TSD2D_LSB; 1240 writel(reg, iobase + CQSPI_REG_DELAY); 1241 } 1242 1243 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 1244 { 1245 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1246 void __iomem *reg_base = cqspi->iobase; 1247 u32 reg, div; 1248 1249 /* Recalculate the baudrate divisor based on QSPI specification. */ 1250 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 1251 1252 /* Maximum baud divisor */ 1253 if (div > CQSPI_REG_CONFIG_BAUD_MASK) { 1254 div = CQSPI_REG_CONFIG_BAUD_MASK; 1255 dev_warn(&cqspi->pdev->dev, 1256 "Unable to adjust clock <= %d hz. Reduced to %d hz\n", 1257 cqspi->sclk, ref_clk_hz/((div+1)*2)); 1258 } 1259 1260 reg = readl(reg_base + CQSPI_REG_CONFIG); 1261 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 1262 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 1263 writel(reg, reg_base + CQSPI_REG_CONFIG); 1264 } 1265 1266 static void cqspi_readdata_capture(struct cqspi_st *cqspi, 1267 const bool bypass, 1268 const unsigned int delay) 1269 { 1270 void __iomem *reg_base = cqspi->iobase; 1271 unsigned int reg; 1272 1273 reg = readl(reg_base + CQSPI_REG_READCAPTURE); 1274 1275 if (bypass) 1276 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1277 else 1278 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1279 1280 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 1281 << CQSPI_REG_READCAPTURE_DELAY_LSB); 1282 1283 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 1284 << CQSPI_REG_READCAPTURE_DELAY_LSB; 1285 1286 writel(reg, reg_base + CQSPI_REG_READCAPTURE); 1287 } 1288 1289 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 1290 unsigned long sclk) 1291 { 1292 struct cqspi_st *cqspi = f_pdata->cqspi; 1293 int switch_cs = (cqspi->current_cs != f_pdata->cs); 1294 int switch_ck = (cqspi->sclk != sclk); 1295 1296 if (switch_cs || switch_ck) 1297 cqspi_controller_enable(cqspi, 0); 1298 1299 /* Switch chip select. */ 1300 if (switch_cs) { 1301 cqspi->current_cs = f_pdata->cs; 1302 cqspi_chipselect(f_pdata); 1303 } 1304 1305 /* Setup baudrate divisor and delays */ 1306 if (switch_ck) { 1307 cqspi->sclk = sclk; 1308 cqspi_config_baudrate_div(cqspi); 1309 cqspi_delay(f_pdata); 1310 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 1311 f_pdata->read_delay); 1312 } 1313 1314 if (switch_cs || switch_ck) 1315 cqspi_controller_enable(cqspi, 1); 1316 } 1317 1318 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 1319 const struct spi_mem_op *op) 1320 { 1321 struct cqspi_st *cqspi = f_pdata->cqspi; 1322 loff_t to = op->addr.val; 1323 size_t len = op->data.nbytes; 1324 const u_char *buf = op->data.buf.out; 1325 int ret; 1326 1327 ret = cqspi_write_setup(f_pdata, op); 1328 if (ret) 1329 return ret; 1330 1331 /* 1332 * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1333 * address (all 0s) with the read status register command in DTR mode. 1334 * But this controller does not support sending dummy address bytes to 1335 * the flash when it is polling the write completion register in DTR 1336 * mode. So, we can not use direct mode when in DTR mode for writing 1337 * data. 1338 */ 1339 if (!op->cmd.dtr && cqspi->use_direct_mode && 1340 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { 1341 memcpy_toio(cqspi->ahb_base + to, buf, len); 1342 return cqspi_wait_idle(cqspi); 1343 } 1344 1345 return cqspi_indirect_write_execute(f_pdata, to, buf, len); 1346 } 1347 1348 static void cqspi_rx_dma_callback(void *param) 1349 { 1350 struct cqspi_st *cqspi = param; 1351 1352 complete(&cqspi->rx_dma_complete); 1353 } 1354 1355 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 1356 u_char *buf, loff_t from, size_t len) 1357 { 1358 struct cqspi_st *cqspi = f_pdata->cqspi; 1359 struct device *dev = &cqspi->pdev->dev; 1360 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 1361 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 1362 int ret = 0; 1363 struct dma_async_tx_descriptor *tx; 1364 dma_cookie_t cookie; 1365 dma_addr_t dma_dst; 1366 struct device *ddev; 1367 1368 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 1369 memcpy_fromio(buf, cqspi->ahb_base + from, len); 1370 return 0; 1371 } 1372 1373 ddev = cqspi->rx_chan->device->dev; 1374 dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 1375 if (dma_mapping_error(ddev, dma_dst)) { 1376 dev_err(dev, "dma mapping failed\n"); 1377 return -ENOMEM; 1378 } 1379 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 1380 len, flags); 1381 if (!tx) { 1382 dev_err(dev, "device_prep_dma_memcpy error\n"); 1383 ret = -EIO; 1384 goto err_unmap; 1385 } 1386 1387 tx->callback = cqspi_rx_dma_callback; 1388 tx->callback_param = cqspi; 1389 cookie = tx->tx_submit(tx); 1390 reinit_completion(&cqspi->rx_dma_complete); 1391 1392 ret = dma_submit_error(cookie); 1393 if (ret) { 1394 dev_err(dev, "dma_submit_error %d\n", cookie); 1395 ret = -EIO; 1396 goto err_unmap; 1397 } 1398 1399 dma_async_issue_pending(cqspi->rx_chan); 1400 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 1401 msecs_to_jiffies(max_t(size_t, len, 500)))) { 1402 dmaengine_terminate_sync(cqspi->rx_chan); 1403 dev_err(dev, "DMA wait_for_completion_timeout\n"); 1404 ret = -ETIMEDOUT; 1405 goto err_unmap; 1406 } 1407 1408 err_unmap: 1409 dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 1410 1411 return ret; 1412 } 1413 1414 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 1415 const struct spi_mem_op *op) 1416 { 1417 struct cqspi_st *cqspi = f_pdata->cqspi; 1418 const struct cqspi_driver_platdata *ddata = cqspi->ddata; 1419 loff_t from = op->addr.val; 1420 size_t len = op->data.nbytes; 1421 u_char *buf = op->data.buf.in; 1422 u64 dma_align = (u64)(uintptr_t)buf; 1423 int ret; 1424 1425 ret = cqspi_read_setup(f_pdata, op); 1426 if (ret) 1427 return ret; 1428 1429 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 1430 return cqspi_direct_read_execute(f_pdata, buf, from, len); 1431 1432 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 1433 virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 1434 return ddata->indirect_read_dma(f_pdata, buf, from, len); 1435 1436 return cqspi_indirect_read_execute(f_pdata, buf, from, len); 1437 } 1438 1439 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 1440 { 1441 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1442 struct cqspi_flash_pdata *f_pdata; 1443 1444 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; 1445 cqspi_configure(f_pdata, op->max_freq); 1446 1447 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 1448 /* 1449 * Performing reads in DAC mode forces to read minimum 4 bytes 1450 * which is unsupported on some flash devices during register 1451 * reads, prefer STIG mode for such small reads. 1452 */ 1453 if (!op->addr.nbytes || 1454 (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX && 1455 !cqspi->disable_stig_mode)) 1456 return cqspi_command_read(f_pdata, op); 1457 1458 return cqspi_read(f_pdata, op); 1459 } 1460 1461 if (!op->addr.nbytes || !op->data.buf.out) 1462 return cqspi_command_write(f_pdata, op); 1463 1464 return cqspi_write(f_pdata, op); 1465 } 1466 1467 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 1468 { 1469 int ret; 1470 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1471 struct device *dev = &cqspi->pdev->dev; 1472 const struct cqspi_driver_platdata *ddata = of_device_get_match_data(dev); 1473 1474 if (refcount_read(&cqspi->inflight_ops) == 0) 1475 return -ENODEV; 1476 1477 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { 1478 ret = pm_runtime_resume_and_get(dev); 1479 if (ret) { 1480 dev_err(&mem->spi->dev, "resume failed with %d\n", ret); 1481 return ret; 1482 } 1483 } 1484 1485 if (!refcount_read(&cqspi->refcount)) 1486 return -EBUSY; 1487 1488 refcount_inc(&cqspi->inflight_ops); 1489 1490 if (!refcount_read(&cqspi->refcount)) { 1491 if (refcount_read(&cqspi->inflight_ops)) 1492 refcount_dec(&cqspi->inflight_ops); 1493 return -EBUSY; 1494 } 1495 1496 ret = cqspi_mem_process(mem, op); 1497 1498 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 1499 pm_runtime_put_autosuspend(dev); 1500 1501 if (ret) 1502 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 1503 1504 if (refcount_read(&cqspi->inflight_ops) > 1) 1505 refcount_dec(&cqspi->inflight_ops); 1506 1507 return ret; 1508 } 1509 1510 static bool cqspi_supports_mem_op(struct spi_mem *mem, 1511 const struct spi_mem_op *op) 1512 { 1513 bool all_true, all_false; 1514 1515 /* 1516 * op->dummy.dtr is required for converting nbytes into ncycles. 1517 * Also, don't check the dtr field of the op phase having zero nbytes. 1518 */ 1519 all_true = op->cmd.dtr && 1520 (!op->addr.nbytes || op->addr.dtr) && 1521 (!op->dummy.nbytes || op->dummy.dtr) && 1522 (!op->data.nbytes || op->data.dtr); 1523 1524 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1525 !op->data.dtr; 1526 1527 if (all_true) { 1528 /* Right now we only support 8-8-8 DTR mode. */ 1529 if (op->cmd.nbytes && op->cmd.buswidth != 8) 1530 return false; 1531 if (op->addr.nbytes && op->addr.buswidth != 8) 1532 return false; 1533 if (op->data.nbytes && op->data.buswidth != 8) 1534 return false; 1535 } else if (!all_false) { 1536 /* Mixed DTR modes are not supported. */ 1537 return false; 1538 } 1539 1540 return spi_mem_default_supports_op(mem, op); 1541 } 1542 1543 static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 1544 struct cqspi_flash_pdata *f_pdata, 1545 struct device_node *np) 1546 { 1547 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 1548 dev_err(&pdev->dev, "couldn't determine read-delay\n"); 1549 return -ENXIO; 1550 } 1551 1552 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 1553 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 1554 return -ENXIO; 1555 } 1556 1557 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 1558 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 1559 return -ENXIO; 1560 } 1561 1562 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 1563 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 1564 return -ENXIO; 1565 } 1566 1567 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 1568 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 1569 return -ENXIO; 1570 } 1571 1572 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 1573 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 1574 return -ENXIO; 1575 } 1576 1577 return 0; 1578 } 1579 1580 static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 1581 { 1582 struct device *dev = &cqspi->pdev->dev; 1583 struct device_node *np = dev->of_node; 1584 u32 id[2]; 1585 1586 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 1587 1588 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 1589 /* Zero signals FIFO depth should be runtime detected. */ 1590 cqspi->fifo_depth = 0; 1591 } 1592 1593 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 1594 dev_err(dev, "couldn't determine fifo-width\n"); 1595 return -ENXIO; 1596 } 1597 1598 if (of_property_read_u32(np, "cdns,trigger-address", 1599 &cqspi->trigger_address)) { 1600 dev_err(dev, "couldn't determine trigger-address\n"); 1601 return -ENXIO; 1602 } 1603 1604 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1605 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1606 1607 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 1608 1609 if (!of_property_read_u32_array(np, "power-domains", id, 1610 ARRAY_SIZE(id))) 1611 cqspi->pd_dev_id = id[1]; 1612 1613 return 0; 1614 } 1615 1616 static void cqspi_controller_init(struct cqspi_st *cqspi) 1617 { 1618 u32 reg; 1619 1620 /* Configure the remap address register, no remap */ 1621 writel(0, cqspi->iobase + CQSPI_REG_REMAP); 1622 1623 /* Disable all interrupts. */ 1624 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 1625 1626 /* Configure the SRAM split to 1:1 . */ 1627 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1628 1629 /* Load indirect trigger address. */ 1630 writel(cqspi->trigger_address, 1631 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 1632 1633 /* Program read watermark -- 1/2 of the FIFO. */ 1634 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 1635 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 1636 /* Program write watermark -- 1/8 of the FIFO. */ 1637 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 1638 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 1639 1640 /* Disable direct access controller */ 1641 if (!cqspi->use_direct_mode) { 1642 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1643 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 1644 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1645 } 1646 1647 /* Enable DMA interface */ 1648 if (cqspi->use_dma_read) { 1649 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1650 reg |= CQSPI_REG_CONFIG_DMA_MASK; 1651 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1652 } 1653 } 1654 1655 static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi) 1656 { 1657 struct device *dev = &cqspi->pdev->dev; 1658 u32 reg, fifo_depth; 1659 1660 /* 1661 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N 1662 * the FIFO depth. 1663 */ 1664 writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1665 reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1666 fifo_depth = reg + 1; 1667 1668 /* FIFO depth of zero means no value from devicetree was provided. */ 1669 if (cqspi->fifo_depth == 0) { 1670 cqspi->fifo_depth = fifo_depth; 1671 dev_dbg(dev, "using FIFO depth of %u\n", fifo_depth); 1672 } else if (fifo_depth != cqspi->fifo_depth) { 1673 dev_warn(dev, "detected FIFO depth (%u) different from config (%u)\n", 1674 fifo_depth, cqspi->fifo_depth); 1675 } 1676 } 1677 1678 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 1679 { 1680 dma_cap_mask_t mask; 1681 1682 dma_cap_zero(mask); 1683 dma_cap_set(DMA_MEMCPY, mask); 1684 1685 cqspi->rx_chan = dma_request_chan_by_mask(&mask); 1686 if (IS_ERR(cqspi->rx_chan)) { 1687 int ret = PTR_ERR(cqspi->rx_chan); 1688 1689 cqspi->rx_chan = NULL; 1690 if (ret == -ENODEV) { 1691 /* DMA support is not mandatory */ 1692 dev_info(&cqspi->pdev->dev, "No Rx DMA available\n"); 1693 return 0; 1694 } 1695 1696 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 1697 } 1698 init_completion(&cqspi->rx_dma_complete); 1699 1700 return 0; 1701 } 1702 1703 static const char *cqspi_get_name(struct spi_mem *mem) 1704 { 1705 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); 1706 struct device *dev = &cqspi->pdev->dev; 1707 1708 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), 1709 spi_get_chipselect(mem->spi, 0)); 1710 } 1711 1712 static const struct spi_controller_mem_ops cqspi_mem_ops = { 1713 .exec_op = cqspi_exec_mem_op, 1714 .get_name = cqspi_get_name, 1715 .supports_op = cqspi_supports_mem_op, 1716 }; 1717 1718 static const struct spi_controller_mem_caps cqspi_mem_caps = { 1719 .dtr = true, 1720 .per_op_freq = true, 1721 }; 1722 1723 static int cqspi_setup_flash(struct cqspi_st *cqspi) 1724 { 1725 unsigned int max_cs = cqspi->num_chipselect - 1; 1726 struct platform_device *pdev = cqspi->pdev; 1727 struct device *dev = &pdev->dev; 1728 struct cqspi_flash_pdata *f_pdata; 1729 unsigned int cs; 1730 int ret; 1731 1732 /* Get flash device data */ 1733 for_each_available_child_of_node_scoped(dev->of_node, np) { 1734 ret = of_property_read_u32(np, "reg", &cs); 1735 if (ret) { 1736 dev_err(dev, "Couldn't determine chip select.\n"); 1737 return ret; 1738 } 1739 1740 if (cs >= cqspi->num_chipselect) { 1741 dev_err(dev, "Chip select %d out of range.\n", cs); 1742 return -EINVAL; 1743 } else if (cs < max_cs) { 1744 max_cs = cs; 1745 } 1746 1747 f_pdata = &cqspi->f_pdata[cs]; 1748 f_pdata->cqspi = cqspi; 1749 f_pdata->cs = cs; 1750 1751 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 1752 if (ret) 1753 return ret; 1754 } 1755 1756 cqspi->num_chipselect = max_cs + 1; 1757 return 0; 1758 } 1759 1760 static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi) 1761 { 1762 static struct clk_bulk_data qspiclk[] = { 1763 { .id = "apb" }, 1764 { .id = "ahb" }, 1765 }; 1766 1767 int ret = 0; 1768 1769 ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); 1770 if (ret) { 1771 dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); 1772 return ret; 1773 } 1774 1775 cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk; 1776 cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk; 1777 1778 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); 1779 if (ret) { 1780 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); 1781 return ret; 1782 } 1783 1784 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); 1785 if (ret) { 1786 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); 1787 goto disable_apb_clk; 1788 } 1789 1790 cqspi->is_jh7110 = true; 1791 1792 return 0; 1793 1794 disable_apb_clk: 1795 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); 1796 1797 return ret; 1798 } 1799 1800 static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi) 1801 { 1802 clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); 1803 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); 1804 } 1805 static int cqspi_probe(struct platform_device *pdev) 1806 { 1807 const struct cqspi_driver_platdata *ddata; 1808 struct reset_control *rstc, *rstc_ocp, *rstc_ref; 1809 struct device *dev = &pdev->dev; 1810 struct spi_controller *host; 1811 struct resource *res_ahb; 1812 struct cqspi_st *cqspi; 1813 int ret; 1814 int irq; 1815 1816 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); 1817 if (!host) 1818 return -ENOMEM; 1819 1820 host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 1821 host->mem_ops = &cqspi_mem_ops; 1822 host->mem_caps = &cqspi_mem_caps; 1823 host->dev.of_node = pdev->dev.of_node; 1824 1825 cqspi = spi_controller_get_devdata(host); 1826 1827 cqspi->pdev = pdev; 1828 cqspi->host = host; 1829 cqspi->is_jh7110 = false; 1830 cqspi->ddata = ddata = of_device_get_match_data(dev); 1831 platform_set_drvdata(pdev, cqspi); 1832 1833 /* Obtain configuration from OF. */ 1834 ret = cqspi_of_get_pdata(cqspi); 1835 if (ret) { 1836 dev_err(dev, "Cannot get mandatory OF data.\n"); 1837 return -ENODEV; 1838 } 1839 1840 /* Obtain QSPI clock. */ 1841 cqspi->clk = devm_clk_get(dev, NULL); 1842 if (IS_ERR(cqspi->clk)) { 1843 dev_err(dev, "Cannot claim QSPI clock.\n"); 1844 ret = PTR_ERR(cqspi->clk); 1845 return ret; 1846 } 1847 1848 /* Obtain and remap controller address. */ 1849 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); 1850 if (IS_ERR(cqspi->iobase)) { 1851 dev_err(dev, "Cannot remap controller address.\n"); 1852 ret = PTR_ERR(cqspi->iobase); 1853 return ret; 1854 } 1855 1856 /* Obtain and remap AHB address. */ 1857 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); 1858 if (IS_ERR(cqspi->ahb_base)) { 1859 dev_err(dev, "Cannot remap AHB address.\n"); 1860 ret = PTR_ERR(cqspi->ahb_base); 1861 return ret; 1862 } 1863 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 1864 cqspi->ahb_size = resource_size(res_ahb); 1865 1866 init_completion(&cqspi->transfer_complete); 1867 1868 /* Obtain IRQ line. */ 1869 irq = platform_get_irq(pdev, 0); 1870 if (irq < 0) 1871 return -ENXIO; 1872 1873 ret = pm_runtime_set_active(dev); 1874 if (ret) 1875 return ret; 1876 1877 1878 ret = clk_prepare_enable(cqspi->clk); 1879 if (ret) { 1880 dev_err(dev, "Cannot enable QSPI clock.\n"); 1881 goto probe_clk_failed; 1882 } 1883 1884 /* Obtain QSPI reset control */ 1885 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 1886 if (IS_ERR(rstc)) { 1887 ret = PTR_ERR(rstc); 1888 dev_err(dev, "Cannot get QSPI reset.\n"); 1889 goto probe_reset_failed; 1890 } 1891 1892 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 1893 if (IS_ERR(rstc_ocp)) { 1894 ret = PTR_ERR(rstc_ocp); 1895 dev_err(dev, "Cannot get QSPI OCP reset.\n"); 1896 goto probe_reset_failed; 1897 } 1898 1899 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { 1900 rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); 1901 if (IS_ERR(rstc_ref)) { 1902 ret = PTR_ERR(rstc_ref); 1903 dev_err(dev, "Cannot get QSPI REF reset.\n"); 1904 goto probe_reset_failed; 1905 } 1906 reset_control_assert(rstc_ref); 1907 reset_control_deassert(rstc_ref); 1908 } 1909 1910 reset_control_assert(rstc); 1911 reset_control_deassert(rstc); 1912 1913 reset_control_assert(rstc_ocp); 1914 reset_control_deassert(rstc_ocp); 1915 1916 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 1917 host->max_speed_hz = cqspi->master_ref_clk_hz; 1918 1919 /* write completion is supported by default */ 1920 cqspi->wr_completion = true; 1921 1922 if (ddata) { 1923 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1924 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 1925 cqspi->master_ref_clk_hz); 1926 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1927 host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 1928 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_QUAD) 1929 host->mode_bits |= SPI_TX_QUAD; 1930 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { 1931 cqspi->use_direct_mode = true; 1932 cqspi->use_direct_mode_wr = true; 1933 } 1934 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 1935 cqspi->use_dma_read = true; 1936 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 1937 cqspi->wr_completion = false; 1938 if (ddata->quirks & CQSPI_SLOW_SRAM) 1939 cqspi->slow_sram = true; 1940 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) 1941 cqspi->apb_ahb_hazard = true; 1942 1943 if (ddata->jh7110_clk_init) { 1944 ret = cqspi_jh7110_clk_init(pdev, cqspi); 1945 if (ret) 1946 goto probe_reset_failed; 1947 } 1948 if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) 1949 cqspi->disable_stig_mode = true; 1950 1951 if (ddata->quirks & CQSPI_DMA_SET_MASK) { 1952 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1953 if (ret) 1954 goto probe_reset_failed; 1955 } 1956 } 1957 1958 refcount_set(&cqspi->refcount, 1); 1959 refcount_set(&cqspi->inflight_ops, 1); 1960 1961 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 1962 pdev->name, cqspi); 1963 if (ret) { 1964 dev_err(dev, "Cannot request IRQ.\n"); 1965 goto probe_reset_failed; 1966 } 1967 1968 cqspi_wait_idle(cqspi); 1969 cqspi_controller_enable(cqspi, 0); 1970 cqspi_controller_detect_fifo_depth(cqspi); 1971 cqspi_controller_init(cqspi); 1972 cqspi_controller_enable(cqspi, 1); 1973 cqspi->current_cs = -1; 1974 cqspi->sclk = 0; 1975 1976 ret = cqspi_setup_flash(cqspi); 1977 if (ret) { 1978 dev_err(dev, "failed to setup flash parameters %d\n", ret); 1979 goto probe_setup_failed; 1980 } 1981 1982 host->num_chipselect = cqspi->num_chipselect; 1983 1984 if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)) 1985 cqspi_device_reset(cqspi); 1986 1987 if (cqspi->use_direct_mode) { 1988 ret = cqspi_request_mmap_dma(cqspi); 1989 if (ret == -EPROBE_DEFER) 1990 goto probe_setup_failed; 1991 } 1992 1993 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { 1994 pm_runtime_enable(dev); 1995 pm_runtime_set_autosuspend_delay(dev, CQSPI_AUTOSUSPEND_TIMEOUT); 1996 pm_runtime_use_autosuspend(dev); 1997 pm_runtime_get_noresume(dev); 1998 } 1999 2000 ret = spi_register_controller(host); 2001 if (ret) { 2002 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 2003 goto probe_setup_failed; 2004 } 2005 2006 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { 2007 pm_runtime_put_autosuspend(dev); 2008 pm_runtime_mark_last_busy(dev); 2009 pm_runtime_put_autosuspend(dev); 2010 } 2011 2012 return 0; 2013 probe_setup_failed: 2014 cqspi_controller_enable(cqspi, 0); 2015 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 2016 pm_runtime_disable(dev); 2017 probe_reset_failed: 2018 if (cqspi->is_jh7110) 2019 cqspi_jh7110_disable_clk(pdev, cqspi); 2020 clk_disable_unprepare(cqspi->clk); 2021 probe_clk_failed: 2022 return ret; 2023 } 2024 2025 static void cqspi_remove(struct platform_device *pdev) 2026 { 2027 const struct cqspi_driver_platdata *ddata; 2028 struct cqspi_st *cqspi = platform_get_drvdata(pdev); 2029 struct device *dev = &pdev->dev; 2030 2031 ddata = of_device_get_match_data(dev); 2032 2033 refcount_set(&cqspi->refcount, 0); 2034 2035 if (!refcount_dec_and_test(&cqspi->inflight_ops)) 2036 cqspi_wait_idle(cqspi); 2037 2038 spi_unregister_controller(cqspi->host); 2039 cqspi_controller_enable(cqspi, 0); 2040 2041 if (cqspi->rx_chan) 2042 dma_release_channel(cqspi->rx_chan); 2043 2044 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) 2045 if (pm_runtime_get_sync(&pdev->dev) >= 0) 2046 clk_disable(cqspi->clk); 2047 2048 if (cqspi->is_jh7110) 2049 cqspi_jh7110_disable_clk(pdev, cqspi); 2050 2051 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { 2052 pm_runtime_put_sync(&pdev->dev); 2053 pm_runtime_disable(&pdev->dev); 2054 } 2055 } 2056 2057 static int cqspi_runtime_suspend(struct device *dev) 2058 { 2059 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2060 2061 cqspi_controller_enable(cqspi, 0); 2062 clk_disable_unprepare(cqspi->clk); 2063 return 0; 2064 } 2065 2066 static int cqspi_runtime_resume(struct device *dev) 2067 { 2068 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2069 2070 clk_prepare_enable(cqspi->clk); 2071 cqspi_wait_idle(cqspi); 2072 cqspi_controller_enable(cqspi, 0); 2073 cqspi_controller_init(cqspi); 2074 cqspi_controller_enable(cqspi, 1); 2075 2076 cqspi->current_cs = -1; 2077 cqspi->sclk = 0; 2078 return 0; 2079 } 2080 2081 static int cqspi_suspend(struct device *dev) 2082 { 2083 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2084 int ret; 2085 2086 ret = spi_controller_suspend(cqspi->host); 2087 if (ret) 2088 return ret; 2089 2090 return pm_runtime_force_suspend(dev); 2091 } 2092 2093 static int cqspi_resume(struct device *dev) 2094 { 2095 struct cqspi_st *cqspi = dev_get_drvdata(dev); 2096 int ret; 2097 2098 ret = pm_runtime_force_resume(dev); 2099 if (ret) { 2100 dev_err(dev, "pm_runtime_force_resume failed on resume\n"); 2101 return ret; 2102 } 2103 2104 return spi_controller_resume(cqspi->host); 2105 } 2106 2107 static const struct dev_pm_ops cqspi_dev_pm_ops = { 2108 RUNTIME_PM_OPS(cqspi_runtime_suspend, cqspi_runtime_resume, NULL) 2109 SYSTEM_SLEEP_PM_OPS(cqspi_suspend, cqspi_resume) 2110 }; 2111 2112 static const struct cqspi_driver_platdata cdns_qspi = { 2113 .quirks = CQSPI_DISABLE_DAC_MODE, 2114 }; 2115 2116 static const struct cqspi_driver_platdata k2g_qspi = { 2117 .quirks = CQSPI_NEEDS_WR_DELAY, 2118 }; 2119 2120 static const struct cqspi_driver_platdata am654_ospi = { 2121 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL | CQSPI_SUPPORTS_QUAD, 2122 .quirks = CQSPI_NEEDS_WR_DELAY, 2123 }; 2124 2125 static const struct cqspi_driver_platdata intel_lgm_qspi = { 2126 .quirks = CQSPI_DISABLE_DAC_MODE, 2127 }; 2128 2129 static const struct cqspi_driver_platdata socfpga_qspi = { 2130 .quirks = CQSPI_DISABLE_DAC_MODE 2131 | CQSPI_NO_SUPPORT_WR_COMPLETION 2132 | CQSPI_SLOW_SRAM 2133 | CQSPI_DISABLE_STIG_MODE 2134 | CQSPI_DISABLE_RUNTIME_PM, 2135 }; 2136 2137 static const struct cqspi_driver_platdata versal_ospi = { 2138 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 2139 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA 2140 | CQSPI_DMA_SET_MASK, 2141 .indirect_read_dma = cqspi_versal_indirect_read_dma, 2142 .get_dma_status = cqspi_get_versal_dma_status, 2143 }; 2144 2145 static const struct cqspi_driver_platdata versal2_ospi = { 2146 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 2147 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA 2148 | CQSPI_DMA_SET_MASK 2149 | CQSPI_SUPPORT_DEVICE_RESET, 2150 .indirect_read_dma = cqspi_versal_indirect_read_dma, 2151 .get_dma_status = cqspi_get_versal_dma_status, 2152 }; 2153 2154 static const struct cqspi_driver_platdata jh7110_qspi = { 2155 .quirks = CQSPI_DISABLE_DAC_MODE, 2156 .jh7110_clk_init = cqspi_jh7110_clk_init, 2157 }; 2158 2159 static const struct cqspi_driver_platdata pensando_cdns_qspi = { 2160 .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, 2161 }; 2162 2163 static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = { 2164 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 2165 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | 2166 CQSPI_RD_NO_IRQ, 2167 }; 2168 2169 static const struct of_device_id cqspi_dt_ids[] = { 2170 { 2171 .compatible = "cdns,qspi-nor", 2172 .data = &cdns_qspi, 2173 }, 2174 { 2175 .compatible = "ti,k2g-qspi", 2176 .data = &k2g_qspi, 2177 }, 2178 { 2179 .compatible = "ti,am654-ospi", 2180 .data = &am654_ospi, 2181 }, 2182 { 2183 .compatible = "intel,lgm-qspi", 2184 .data = &intel_lgm_qspi, 2185 }, 2186 { 2187 .compatible = "xlnx,versal-ospi-1.0", 2188 .data = &versal_ospi, 2189 }, 2190 { 2191 .compatible = "intel,socfpga-qspi", 2192 .data = &socfpga_qspi, 2193 }, 2194 { 2195 .compatible = "starfive,jh7110-qspi", 2196 .data = &jh7110_qspi, 2197 }, 2198 { 2199 .compatible = "amd,pensando-elba-qspi", 2200 .data = &pensando_cdns_qspi, 2201 }, 2202 { 2203 .compatible = "mobileye,eyeq5-ospi", 2204 .data = &mobileye_eyeq5_ospi, 2205 }, 2206 { 2207 .compatible = "amd,versal2-ospi", 2208 .data = &versal2_ospi, 2209 }, 2210 { /* end of table */ } 2211 }; 2212 2213 MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 2214 2215 static struct platform_driver cqspi_platform_driver = { 2216 .probe = cqspi_probe, 2217 .remove = cqspi_remove, 2218 .driver = { 2219 .name = CQSPI_NAME, 2220 .pm = pm_ptr(&cqspi_dev_pm_ops), 2221 .of_match_table = cqspi_dt_ids, 2222 }, 2223 }; 2224 2225 module_platform_driver(cqspi_platform_driver); 2226 2227 MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 2228 MODULE_LICENSE("GPL v2"); 2229 MODULE_ALIAS("platform:" CQSPI_NAME); 2230 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 2231 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 2232 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 2233 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 2234 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 2235