1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cadence QSPI Controller 4 // 5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 8 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/err.h> 15 #include <linux/errno.h> 16 #include <linux/firmware/xlnx-zynqmp.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/jiffies.h> 21 #include <linux/kernel.h> 22 #include <linux/log2.h> 23 #include <linux/module.h> 24 #include <linux/of_device.h> 25 #include <linux/of.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/reset.h> 29 #include <linux/sched.h> 30 #include <linux/spi/spi.h> 31 #include <linux/spi/spi-mem.h> 32 #include <linux/timer.h> 33 34 #define CQSPI_NAME "cadence-qspi" 35 #define CQSPI_MAX_CHIPSELECT 16 36 37 /* Quirks */ 38 #define CQSPI_NEEDS_WR_DELAY BIT(0) 39 #define CQSPI_DISABLE_DAC_MODE BIT(1) 40 #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) 41 #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) 42 #define CQSPI_SLOW_SRAM BIT(4) 43 44 /* Capabilities */ 45 #define CQSPI_SUPPORTS_OCTAL BIT(0) 46 47 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) 48 49 struct cqspi_st; 50 51 struct cqspi_flash_pdata { 52 struct cqspi_st *cqspi; 53 u32 clk_rate; 54 u32 read_delay; 55 u32 tshsl_ns; 56 u32 tsd2d_ns; 57 u32 tchsh_ns; 58 u32 tslch_ns; 59 u8 cs; 60 }; 61 62 struct cqspi_st { 63 struct platform_device *pdev; 64 struct spi_master *master; 65 struct clk *clk; 66 unsigned int sclk; 67 68 void __iomem *iobase; 69 void __iomem *ahb_base; 70 resource_size_t ahb_size; 71 struct completion transfer_complete; 72 73 struct dma_chan *rx_chan; 74 struct completion rx_dma_complete; 75 dma_addr_t mmap_phys_base; 76 77 int current_cs; 78 unsigned long master_ref_clk_hz; 79 bool is_decoded_cs; 80 u32 fifo_depth; 81 u32 fifo_width; 82 u32 num_chipselect; 83 bool rclk_en; 84 u32 trigger_address; 85 u32 wr_delay; 86 bool use_direct_mode; 87 bool use_direct_mode_wr; 88 struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; 89 bool use_dma_read; 90 u32 pd_dev_id; 91 bool wr_completion; 92 bool slow_sram; 93 }; 94 95 struct cqspi_driver_platdata { 96 u32 hwcaps_mask; 97 u8 quirks; 98 int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, 99 u_char *rxbuf, loff_t from_addr, size_t n_rx); 100 u32 (*get_dma_status)(struct cqspi_st *cqspi); 101 }; 102 103 /* Operation timeout value */ 104 #define CQSPI_TIMEOUT_MS 500 105 #define CQSPI_READ_TIMEOUT_MS 10 106 107 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 108 #define CQSPI_DUMMY_BYTES_MAX 4 109 #define CQSPI_DUMMY_CLKS_MAX 31 110 111 #define CQSPI_STIG_DATA_LEN_MAX 8 112 113 /* Register map */ 114 #define CQSPI_REG_CONFIG 0x00 115 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 116 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) 117 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 118 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 119 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) 120 #define CQSPI_REG_CONFIG_BAUD_LSB 19 121 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) 122 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) 123 #define CQSPI_REG_CONFIG_IDLE_LSB 31 124 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 125 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 126 127 #define CQSPI_REG_RD_INSTR 0x04 128 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 129 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 130 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 131 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 132 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 133 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 134 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 135 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 136 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 137 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 138 139 #define CQSPI_REG_WR_INSTR 0x08 140 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 141 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12 142 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 143 144 #define CQSPI_REG_DELAY 0x0C 145 #define CQSPI_REG_DELAY_TSLCH_LSB 0 146 #define CQSPI_REG_DELAY_TCHSH_LSB 8 147 #define CQSPI_REG_DELAY_TSD2D_LSB 16 148 #define CQSPI_REG_DELAY_TSHSL_LSB 24 149 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 150 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 151 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 152 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 153 154 #define CQSPI_REG_READCAPTURE 0x10 155 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 156 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 157 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF 158 159 #define CQSPI_REG_SIZE 0x14 160 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 161 #define CQSPI_REG_SIZE_PAGE_LSB 4 162 #define CQSPI_REG_SIZE_BLOCK_LSB 16 163 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 164 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 165 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 166 167 #define CQSPI_REG_SRAMPARTITION 0x18 168 #define CQSPI_REG_INDIRECTTRIGGER 0x1C 169 170 #define CQSPI_REG_DMA 0x20 171 #define CQSPI_REG_DMA_SINGLE_LSB 0 172 #define CQSPI_REG_DMA_BURST_LSB 8 173 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF 174 #define CQSPI_REG_DMA_BURST_MASK 0xFF 175 176 #define CQSPI_REG_REMAP 0x24 177 #define CQSPI_REG_MODE_BIT 0x28 178 179 #define CQSPI_REG_SDRAMLEVEL 0x2C 180 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 181 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 182 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 183 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 184 185 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38 186 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) 187 188 #define CQSPI_REG_IRQSTATUS 0x40 189 #define CQSPI_REG_IRQMASK 0x44 190 191 #define CQSPI_REG_INDIRECTRD 0x60 192 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 193 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 194 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 195 196 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 197 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 198 #define CQSPI_REG_INDIRECTRDBYTES 0x6C 199 200 #define CQSPI_REG_CMDCTRL 0x90 201 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 202 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 203 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 204 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 205 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 206 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 207 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 208 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 209 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 210 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 211 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 212 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 213 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 214 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 215 216 #define CQSPI_REG_INDIRECTWR 0x70 217 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 218 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 219 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 220 221 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 222 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 223 #define CQSPI_REG_INDIRECTWRBYTES 0x7C 224 225 #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80 226 227 #define CQSPI_REG_CMDADDRESS 0x94 228 #define CQSPI_REG_CMDREADDATALOWER 0xA0 229 #define CQSPI_REG_CMDREADDATAUPPER 0xA4 230 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 231 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 232 233 #define CQSPI_REG_POLLING_STATUS 0xB0 234 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 235 236 #define CQSPI_REG_OP_EXT_LOWER 0xE0 237 #define CQSPI_REG_OP_EXT_READ_LSB 24 238 #define CQSPI_REG_OP_EXT_WRITE_LSB 16 239 #define CQSPI_REG_OP_EXT_STIG_LSB 0 240 241 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000 242 243 #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800 244 #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804 245 246 #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C 247 248 #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814 249 #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818 250 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C 251 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1) 252 253 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828 254 255 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00 256 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6 257 258 /* Interrupt status bits */ 259 #define CQSPI_REG_IRQ_MODE_ERR BIT(0) 260 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) 261 #define CQSPI_REG_IRQ_IND_COMP BIT(2) 262 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3) 263 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4) 264 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5) 265 #define CQSPI_REG_IRQ_WATERMARK BIT(6) 266 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12) 267 268 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \ 269 CQSPI_REG_IRQ_IND_SRAM_FULL | \ 270 CQSPI_REG_IRQ_IND_COMP) 271 272 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \ 273 CQSPI_REG_IRQ_WATERMARK | \ 274 CQSPI_REG_IRQ_UNDERFLOW) 275 276 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF 277 #define CQSPI_DMA_UNALIGN 0x3 278 279 #define CQSPI_REG_VERSAL_DMA_VAL 0x602 280 281 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) 282 { 283 u32 val; 284 285 return readl_relaxed_poll_timeout(reg, val, 286 (((clr ? ~val : val) & mask) == mask), 287 10, CQSPI_TIMEOUT_MS * 1000); 288 } 289 290 static bool cqspi_is_idle(struct cqspi_st *cqspi) 291 { 292 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 293 294 return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB); 295 } 296 297 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi) 298 { 299 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); 300 301 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 302 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 303 } 304 305 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) 306 { 307 u32 dma_status; 308 309 dma_status = readl(cqspi->iobase + 310 CQSPI_REG_VERSAL_DMA_DST_I_STS); 311 writel(dma_status, cqspi->iobase + 312 CQSPI_REG_VERSAL_DMA_DST_I_STS); 313 314 return dma_status & CQSPI_REG_VERSAL_DMA_DST_DONE_MASK; 315 } 316 317 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) 318 { 319 struct cqspi_st *cqspi = dev; 320 unsigned int irq_status; 321 struct device *device = &cqspi->pdev->dev; 322 const struct cqspi_driver_platdata *ddata; 323 324 ddata = of_device_get_match_data(device); 325 326 /* Read interrupt status */ 327 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); 328 329 /* Clear interrupt */ 330 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); 331 332 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { 333 if (ddata->get_dma_status(cqspi)) { 334 complete(&cqspi->transfer_complete); 335 return IRQ_HANDLED; 336 } 337 } 338 339 else if (!cqspi->slow_sram) 340 irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR; 341 else 342 irq_status &= CQSPI_REG_IRQ_WATERMARK | CQSPI_IRQ_MASK_WR; 343 344 if (irq_status) 345 complete(&cqspi->transfer_complete); 346 347 return IRQ_HANDLED; 348 } 349 350 static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) 351 { 352 u32 rdreg = 0; 353 354 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; 355 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; 356 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 357 358 return rdreg; 359 } 360 361 static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) 362 { 363 unsigned int dummy_clk; 364 365 if (!op->dummy.nbytes) 366 return 0; 367 368 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); 369 if (op->cmd.dtr) 370 dummy_clk /= 2; 371 372 return dummy_clk; 373 } 374 375 static int cqspi_wait_idle(struct cqspi_st *cqspi) 376 { 377 const unsigned int poll_idle_retry = 3; 378 unsigned int count = 0; 379 unsigned long timeout; 380 381 timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS); 382 while (1) { 383 /* 384 * Read few times in succession to ensure the controller 385 * is indeed idle, that is, the bit does not transition 386 * low again. 387 */ 388 if (cqspi_is_idle(cqspi)) 389 count++; 390 else 391 count = 0; 392 393 if (count >= poll_idle_retry) 394 return 0; 395 396 if (time_after(jiffies, timeout)) { 397 /* Timeout, in busy mode. */ 398 dev_err(&cqspi->pdev->dev, 399 "QSPI is still busy after %dms timeout.\n", 400 CQSPI_TIMEOUT_MS); 401 return -ETIMEDOUT; 402 } 403 404 cpu_relax(); 405 } 406 } 407 408 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) 409 { 410 void __iomem *reg_base = cqspi->iobase; 411 int ret; 412 413 /* Write the CMDCTRL without start execution. */ 414 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 415 /* Start execute */ 416 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 417 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 418 419 /* Polling for completion. */ 420 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, 421 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); 422 if (ret) { 423 dev_err(&cqspi->pdev->dev, 424 "Flash command execution timed out.\n"); 425 return ret; 426 } 427 428 /* Polling QSPI idle status. */ 429 return cqspi_wait_idle(cqspi); 430 } 431 432 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, 433 const struct spi_mem_op *op, 434 unsigned int shift) 435 { 436 struct cqspi_st *cqspi = f_pdata->cqspi; 437 void __iomem *reg_base = cqspi->iobase; 438 unsigned int reg; 439 u8 ext; 440 441 if (op->cmd.nbytes != 2) 442 return -EINVAL; 443 444 /* Opcode extension is the LSB. */ 445 ext = op->cmd.opcode & 0xff; 446 447 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); 448 reg &= ~(0xff << shift); 449 reg |= ext << shift; 450 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); 451 452 return 0; 453 } 454 455 static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, 456 const struct spi_mem_op *op, unsigned int shift) 457 { 458 struct cqspi_st *cqspi = f_pdata->cqspi; 459 void __iomem *reg_base = cqspi->iobase; 460 unsigned int reg; 461 int ret; 462 463 reg = readl(reg_base + CQSPI_REG_CONFIG); 464 465 /* 466 * We enable dual byte opcode here. The callers have to set up the 467 * extension opcode based on which type of operation it is. 468 */ 469 if (op->cmd.dtr) { 470 reg |= CQSPI_REG_CONFIG_DTR_PROTO; 471 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; 472 473 /* Set up command opcode extension. */ 474 ret = cqspi_setup_opcode_ext(f_pdata, op, shift); 475 if (ret) 476 return ret; 477 } else { 478 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; 479 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; 480 } 481 482 writel(reg, reg_base + CQSPI_REG_CONFIG); 483 484 return cqspi_wait_idle(cqspi); 485 } 486 487 static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 488 const struct spi_mem_op *op) 489 { 490 struct cqspi_st *cqspi = f_pdata->cqspi; 491 void __iomem *reg_base = cqspi->iobase; 492 u8 *rxbuf = op->data.buf.in; 493 u8 opcode; 494 size_t n_rx = op->data.nbytes; 495 unsigned int rdreg; 496 unsigned int reg; 497 unsigned int dummy_clk; 498 size_t read_len; 499 int status; 500 501 status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 502 if (status) 503 return status; 504 505 if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) { 506 dev_err(&cqspi->pdev->dev, 507 "Invalid input argument, len %zu rxbuf 0x%p\n", 508 n_rx, rxbuf); 509 return -EINVAL; 510 } 511 512 if (op->cmd.dtr) 513 opcode = op->cmd.opcode >> 8; 514 else 515 opcode = op->cmd.opcode; 516 517 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 518 519 rdreg = cqspi_calc_rdreg(op); 520 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); 521 522 dummy_clk = cqspi_calc_dummy(op); 523 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 524 return -EOPNOTSUPP; 525 526 if (dummy_clk) 527 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) 528 << CQSPI_REG_CMDCTRL_DUMMY_LSB; 529 530 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 531 532 /* 0 means 1 byte. */ 533 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 534 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 535 536 /* setup ADDR BIT field */ 537 if (op->addr.nbytes) { 538 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 539 reg |= ((op->addr.nbytes - 1) & 540 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 541 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 542 543 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 544 } 545 546 status = cqspi_exec_flash_cmd(cqspi, reg); 547 if (status) 548 return status; 549 550 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 551 552 /* Put the read value into rx_buf */ 553 read_len = (n_rx > 4) ? 4 : n_rx; 554 memcpy(rxbuf, ®, read_len); 555 rxbuf += read_len; 556 557 if (n_rx > 4) { 558 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 559 560 read_len = n_rx - read_len; 561 memcpy(rxbuf, ®, read_len); 562 } 563 564 /* Reset CMD_CTRL Reg once command read completes */ 565 writel(0, reg_base + CQSPI_REG_CMDCTRL); 566 567 return 0; 568 } 569 570 static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 571 const struct spi_mem_op *op) 572 { 573 struct cqspi_st *cqspi = f_pdata->cqspi; 574 void __iomem *reg_base = cqspi->iobase; 575 u8 opcode; 576 const u8 *txbuf = op->data.buf.out; 577 size_t n_tx = op->data.nbytes; 578 unsigned int reg; 579 unsigned int data; 580 size_t write_len; 581 int ret; 582 583 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); 584 if (ret) 585 return ret; 586 587 if (n_tx > CQSPI_STIG_DATA_LEN_MAX || (n_tx && !txbuf)) { 588 dev_err(&cqspi->pdev->dev, 589 "Invalid input argument, cmdlen %zu txbuf 0x%p\n", 590 n_tx, txbuf); 591 return -EINVAL; 592 } 593 594 reg = cqspi_calc_rdreg(op); 595 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 596 597 if (op->cmd.dtr) 598 opcode = op->cmd.opcode >> 8; 599 else 600 opcode = op->cmd.opcode; 601 602 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; 603 604 if (op->addr.nbytes) { 605 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 606 reg |= ((op->addr.nbytes - 1) & 607 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 608 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 609 610 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); 611 } 612 613 if (n_tx) { 614 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 615 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 616 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 617 data = 0; 618 write_len = (n_tx > 4) ? 4 : n_tx; 619 memcpy(&data, txbuf, write_len); 620 txbuf += write_len; 621 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER); 622 623 if (n_tx > 4) { 624 data = 0; 625 write_len = n_tx - 4; 626 memcpy(&data, txbuf, write_len); 627 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER); 628 } 629 } 630 631 ret = cqspi_exec_flash_cmd(cqspi, reg); 632 633 /* Reset CMD_CTRL Reg once command write completes */ 634 writel(0, reg_base + CQSPI_REG_CMDCTRL); 635 636 return ret; 637 } 638 639 static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, 640 const struct spi_mem_op *op) 641 { 642 struct cqspi_st *cqspi = f_pdata->cqspi; 643 void __iomem *reg_base = cqspi->iobase; 644 unsigned int dummy_clk = 0; 645 unsigned int reg; 646 int ret; 647 u8 opcode; 648 649 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); 650 if (ret) 651 return ret; 652 653 if (op->cmd.dtr) 654 opcode = op->cmd.opcode >> 8; 655 else 656 opcode = op->cmd.opcode; 657 658 reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; 659 reg |= cqspi_calc_rdreg(op); 660 661 /* Setup dummy clock cycles */ 662 dummy_clk = cqspi_calc_dummy(op); 663 664 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) 665 return -EOPNOTSUPP; 666 667 if (dummy_clk) 668 reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 669 << CQSPI_REG_RD_INSTR_DUMMY_LSB; 670 671 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 672 673 /* Set address width */ 674 reg = readl(reg_base + CQSPI_REG_SIZE); 675 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 676 reg |= (op->addr.nbytes - 1); 677 writel(reg, reg_base + CQSPI_REG_SIZE); 678 return 0; 679 } 680 681 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, 682 u8 *rxbuf, loff_t from_addr, 683 const size_t n_rx) 684 { 685 struct cqspi_st *cqspi = f_pdata->cqspi; 686 struct device *dev = &cqspi->pdev->dev; 687 void __iomem *reg_base = cqspi->iobase; 688 void __iomem *ahb_base = cqspi->ahb_base; 689 unsigned int remaining = n_rx; 690 unsigned int mod_bytes = n_rx % 4; 691 unsigned int bytes_to_read = 0; 692 u8 *rxbuf_end = rxbuf + n_rx; 693 int ret = 0; 694 695 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 696 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES); 697 698 /* Clear all interrupts. */ 699 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 700 701 /* 702 * On SoCFPGA platform reading the SRAM is slow due to 703 * hardware limitation and causing read interrupt storm to CPU, 704 * so enabling only watermark interrupt to disable all read 705 * interrupts later as we want to run "bytes to read" loop with 706 * all the read interrupts disabled for max performance. 707 */ 708 709 if (!cqspi->slow_sram) 710 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); 711 else 712 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 713 714 reinit_completion(&cqspi->transfer_complete); 715 writel(CQSPI_REG_INDIRECTRD_START_MASK, 716 reg_base + CQSPI_REG_INDIRECTRD); 717 718 while (remaining > 0) { 719 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 720 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) 721 ret = -ETIMEDOUT; 722 723 /* 724 * Disable all read interrupts until 725 * we are out of "bytes to read" 726 */ 727 if (cqspi->slow_sram) 728 writel(0x0, reg_base + CQSPI_REG_IRQMASK); 729 730 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 731 732 if (ret && bytes_to_read == 0) { 733 dev_err(dev, "Indirect read timeout, no bytes\n"); 734 goto failrd; 735 } 736 737 while (bytes_to_read != 0) { 738 unsigned int word_remain = round_down(remaining, 4); 739 740 bytes_to_read *= cqspi->fifo_width; 741 bytes_to_read = bytes_to_read > remaining ? 742 remaining : bytes_to_read; 743 bytes_to_read = round_down(bytes_to_read, 4); 744 /* Read 4 byte word chunks then single bytes */ 745 if (bytes_to_read) { 746 ioread32_rep(ahb_base, rxbuf, 747 (bytes_to_read / 4)); 748 } else if (!word_remain && mod_bytes) { 749 unsigned int temp = ioread32(ahb_base); 750 751 bytes_to_read = mod_bytes; 752 memcpy(rxbuf, &temp, min((unsigned int) 753 (rxbuf_end - rxbuf), 754 bytes_to_read)); 755 } 756 rxbuf += bytes_to_read; 757 remaining -= bytes_to_read; 758 bytes_to_read = cqspi_get_rd_sram_level(cqspi); 759 } 760 761 if (remaining > 0) { 762 reinit_completion(&cqspi->transfer_complete); 763 if (cqspi->slow_sram) 764 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); 765 } 766 } 767 768 /* Check indirect done status */ 769 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, 770 CQSPI_REG_INDIRECTRD_DONE_MASK, 0); 771 if (ret) { 772 dev_err(dev, "Indirect read completion error (%i)\n", ret); 773 goto failrd; 774 } 775 776 /* Disable interrupt */ 777 writel(0, reg_base + CQSPI_REG_IRQMASK); 778 779 /* Clear indirect completion status */ 780 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD); 781 782 return 0; 783 784 failrd: 785 /* Disable interrupt */ 786 writel(0, reg_base + CQSPI_REG_IRQMASK); 787 788 /* Cancel the indirect read */ 789 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, 790 reg_base + CQSPI_REG_INDIRECTRD); 791 return ret; 792 } 793 794 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, 795 u_char *rxbuf, loff_t from_addr, 796 size_t n_rx) 797 { 798 struct cqspi_st *cqspi = f_pdata->cqspi; 799 struct device *dev = &cqspi->pdev->dev; 800 void __iomem *reg_base = cqspi->iobase; 801 u32 reg, bytes_to_dma; 802 loff_t addr = from_addr; 803 void *buf = rxbuf; 804 dma_addr_t dma_addr; 805 u8 bytes_rem; 806 int ret = 0; 807 808 bytes_rem = n_rx % 4; 809 bytes_to_dma = (n_rx - bytes_rem); 810 811 if (!bytes_to_dma) 812 goto nondmard; 813 814 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); 815 if (ret) 816 return ret; 817 818 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 819 reg |= CQSPI_REG_CONFIG_DMA_MASK; 820 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 821 822 dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); 823 if (dma_mapping_error(dev, dma_addr)) { 824 dev_err(dev, "dma mapping failed\n"); 825 return -ENOMEM; 826 } 827 828 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR); 829 writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES); 830 writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL, 831 reg_base + CQSPI_REG_INDTRIG_ADDRRANGE); 832 833 /* Clear all interrupts. */ 834 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 835 836 /* Enable DMA done interrupt */ 837 writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK, 838 reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN); 839 840 /* Default DMA periph configuration */ 841 writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA); 842 843 /* Configure DMA Dst address */ 844 writel(lower_32_bits(dma_addr), 845 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR); 846 writel(upper_32_bits(dma_addr), 847 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB); 848 849 /* Configure DMA Src address */ 850 writel(cqspi->trigger_address, reg_base + 851 CQSPI_REG_VERSAL_DMA_SRC_ADDR); 852 853 /* Set DMA destination size */ 854 writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE); 855 856 /* Set DMA destination control */ 857 writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL, 858 reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL); 859 860 writel(CQSPI_REG_INDIRECTRD_START_MASK, 861 reg_base + CQSPI_REG_INDIRECTRD); 862 863 reinit_completion(&cqspi->transfer_complete); 864 865 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 866 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { 867 ret = -ETIMEDOUT; 868 goto failrd; 869 } 870 871 /* Disable DMA interrupt */ 872 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 873 874 /* Clear indirect completion status */ 875 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 876 cqspi->iobase + CQSPI_REG_INDIRECTRD); 877 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 878 879 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 880 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 881 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 882 883 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, 884 PM_OSPI_MUX_SEL_LINEAR); 885 if (ret) 886 return ret; 887 888 nondmard: 889 if (bytes_rem) { 890 addr += bytes_to_dma; 891 buf += bytes_to_dma; 892 ret = cqspi_indirect_read_execute(f_pdata, buf, addr, 893 bytes_rem); 894 if (ret) 895 return ret; 896 } 897 898 return 0; 899 900 failrd: 901 /* Disable DMA interrupt */ 902 writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS); 903 904 /* Cancel the indirect read */ 905 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 906 reg_base + CQSPI_REG_INDIRECTRD); 907 908 dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); 909 910 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 911 reg &= ~CQSPI_REG_CONFIG_DMA_MASK; 912 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 913 914 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); 915 916 return ret; 917 } 918 919 static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, 920 const struct spi_mem_op *op) 921 { 922 unsigned int reg; 923 int ret; 924 struct cqspi_st *cqspi = f_pdata->cqspi; 925 void __iomem *reg_base = cqspi->iobase; 926 u8 opcode; 927 928 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); 929 if (ret) 930 return ret; 931 932 if (op->cmd.dtr) 933 opcode = op->cmd.opcode >> 8; 934 else 935 opcode = op->cmd.opcode; 936 937 /* Set opcode. */ 938 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; 939 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; 940 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; 941 writel(reg, reg_base + CQSPI_REG_WR_INSTR); 942 reg = cqspi_calc_rdreg(op); 943 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 944 945 /* 946 * SPI NAND flashes require the address of the status register to be 947 * passed in the Read SR command. Also, some SPI NOR flashes like the 948 * cypress Semper flash expect a 4-byte dummy address in the Read SR 949 * command in DTR mode. 950 * 951 * But this controller does not support address phase in the Read SR 952 * command when doing auto-HW polling. So, disable write completion 953 * polling on the controller's side. spinand and spi-nor will take 954 * care of polling the status register. 955 */ 956 if (cqspi->wr_completion) { 957 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 958 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL; 959 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL); 960 /* 961 * DAC mode require auto polling as flash needs to be polled 962 * for write completion in case of bubble in SPI transaction 963 * due to slow CPU/DMA master. 964 */ 965 cqspi->use_direct_mode_wr = false; 966 } 967 968 reg = readl(reg_base + CQSPI_REG_SIZE); 969 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 970 reg |= (op->addr.nbytes - 1); 971 writel(reg, reg_base + CQSPI_REG_SIZE); 972 return 0; 973 } 974 975 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, 976 loff_t to_addr, const u8 *txbuf, 977 const size_t n_tx) 978 { 979 struct cqspi_st *cqspi = f_pdata->cqspi; 980 struct device *dev = &cqspi->pdev->dev; 981 void __iomem *reg_base = cqspi->iobase; 982 unsigned int remaining = n_tx; 983 unsigned int write_bytes; 984 int ret; 985 986 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); 987 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 988 989 /* Clear all interrupts. */ 990 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 991 992 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 993 994 reinit_completion(&cqspi->transfer_complete); 995 writel(CQSPI_REG_INDIRECTWR_START_MASK, 996 reg_base + CQSPI_REG_INDIRECTWR); 997 /* 998 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access 999 * Controller programming sequence, couple of cycles of 1000 * QSPI_REF_CLK delay is required for the above bit to 1001 * be internally synchronized by the QSPI module. Provide 5 1002 * cycles of delay. 1003 */ 1004 if (cqspi->wr_delay) 1005 ndelay(cqspi->wr_delay); 1006 1007 while (remaining > 0) { 1008 size_t write_words, mod_bytes; 1009 1010 write_bytes = remaining; 1011 write_words = write_bytes / 4; 1012 mod_bytes = write_bytes % 4; 1013 /* Write 4 bytes at a time then single bytes. */ 1014 if (write_words) { 1015 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); 1016 txbuf += (write_words * 4); 1017 } 1018 if (mod_bytes) { 1019 unsigned int temp = 0xFFFFFFFF; 1020 1021 memcpy(&temp, txbuf, mod_bytes); 1022 iowrite32(temp, cqspi->ahb_base); 1023 txbuf += mod_bytes; 1024 } 1025 1026 if (!wait_for_completion_timeout(&cqspi->transfer_complete, 1027 msecs_to_jiffies(CQSPI_TIMEOUT_MS))) { 1028 dev_err(dev, "Indirect write timeout\n"); 1029 ret = -ETIMEDOUT; 1030 goto failwr; 1031 } 1032 1033 remaining -= write_bytes; 1034 1035 if (remaining > 0) 1036 reinit_completion(&cqspi->transfer_complete); 1037 } 1038 1039 /* Check indirect done status */ 1040 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, 1041 CQSPI_REG_INDIRECTWR_DONE_MASK, 0); 1042 if (ret) { 1043 dev_err(dev, "Indirect write completion error (%i)\n", ret); 1044 goto failwr; 1045 } 1046 1047 /* Disable interrupt. */ 1048 writel(0, reg_base + CQSPI_REG_IRQMASK); 1049 1050 /* Clear indirect completion status */ 1051 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); 1052 1053 cqspi_wait_idle(cqspi); 1054 1055 return 0; 1056 1057 failwr: 1058 /* Disable interrupt. */ 1059 writel(0, reg_base + CQSPI_REG_IRQMASK); 1060 1061 /* Cancel the indirect write */ 1062 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 1063 reg_base + CQSPI_REG_INDIRECTWR); 1064 return ret; 1065 } 1066 1067 static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 1068 { 1069 struct cqspi_st *cqspi = f_pdata->cqspi; 1070 void __iomem *reg_base = cqspi->iobase; 1071 unsigned int chip_select = f_pdata->cs; 1072 unsigned int reg; 1073 1074 reg = readl(reg_base + CQSPI_REG_CONFIG); 1075 if (cqspi->is_decoded_cs) { 1076 reg |= CQSPI_REG_CONFIG_DECODE_MASK; 1077 } else { 1078 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 1079 1080 /* Convert CS if without decoder. 1081 * CS0 to 4b'1110 1082 * CS1 to 4b'1101 1083 * CS2 to 4b'1011 1084 * CS3 to 4b'0111 1085 */ 1086 chip_select = 0xF & ~(1 << chip_select); 1087 } 1088 1089 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 1090 << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 1091 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 1092 << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 1093 writel(reg, reg_base + CQSPI_REG_CONFIG); 1094 } 1095 1096 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, 1097 const unsigned int ns_val) 1098 { 1099 unsigned int ticks; 1100 1101 ticks = ref_clk_hz / 1000; /* kHz */ 1102 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000); 1103 1104 return ticks; 1105 } 1106 1107 static void cqspi_delay(struct cqspi_flash_pdata *f_pdata) 1108 { 1109 struct cqspi_st *cqspi = f_pdata->cqspi; 1110 void __iomem *iobase = cqspi->iobase; 1111 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1112 unsigned int tshsl, tchsh, tslch, tsd2d; 1113 unsigned int reg; 1114 unsigned int tsclk; 1115 1116 /* calculate the number of ref ticks for one sclk tick */ 1117 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); 1118 1119 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); 1120 /* this particular value must be at least one sclk */ 1121 if (tshsl < tsclk) 1122 tshsl = tsclk; 1123 1124 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); 1125 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); 1126 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); 1127 1128 reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 1129 << CQSPI_REG_DELAY_TSHSL_LSB; 1130 reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 1131 << CQSPI_REG_DELAY_TCHSH_LSB; 1132 reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK) 1133 << CQSPI_REG_DELAY_TSLCH_LSB; 1134 reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 1135 << CQSPI_REG_DELAY_TSD2D_LSB; 1136 writel(reg, iobase + CQSPI_REG_DELAY); 1137 } 1138 1139 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi) 1140 { 1141 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; 1142 void __iomem *reg_base = cqspi->iobase; 1143 u32 reg, div; 1144 1145 /* Recalculate the baudrate divisor based on QSPI specification. */ 1146 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; 1147 1148 /* Maximum baud divisor */ 1149 if (div > CQSPI_REG_CONFIG_BAUD_MASK) { 1150 div = CQSPI_REG_CONFIG_BAUD_MASK; 1151 dev_warn(&cqspi->pdev->dev, 1152 "Unable to adjust clock <= %d hz. Reduced to %d hz\n", 1153 cqspi->sclk, ref_clk_hz/((div+1)*2)); 1154 } 1155 1156 reg = readl(reg_base + CQSPI_REG_CONFIG); 1157 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 1158 reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 1159 writel(reg, reg_base + CQSPI_REG_CONFIG); 1160 } 1161 1162 static void cqspi_readdata_capture(struct cqspi_st *cqspi, 1163 const bool bypass, 1164 const unsigned int delay) 1165 { 1166 void __iomem *reg_base = cqspi->iobase; 1167 unsigned int reg; 1168 1169 reg = readl(reg_base + CQSPI_REG_READCAPTURE); 1170 1171 if (bypass) 1172 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1173 else 1174 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB); 1175 1176 reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK 1177 << CQSPI_REG_READCAPTURE_DELAY_LSB); 1178 1179 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) 1180 << CQSPI_REG_READCAPTURE_DELAY_LSB; 1181 1182 writel(reg, reg_base + CQSPI_REG_READCAPTURE); 1183 } 1184 1185 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) 1186 { 1187 void __iomem *reg_base = cqspi->iobase; 1188 unsigned int reg; 1189 1190 reg = readl(reg_base + CQSPI_REG_CONFIG); 1191 1192 if (enable) 1193 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 1194 else 1195 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 1196 1197 writel(reg, reg_base + CQSPI_REG_CONFIG); 1198 } 1199 1200 static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, 1201 unsigned long sclk) 1202 { 1203 struct cqspi_st *cqspi = f_pdata->cqspi; 1204 int switch_cs = (cqspi->current_cs != f_pdata->cs); 1205 int switch_ck = (cqspi->sclk != sclk); 1206 1207 if (switch_cs || switch_ck) 1208 cqspi_controller_enable(cqspi, 0); 1209 1210 /* Switch chip select. */ 1211 if (switch_cs) { 1212 cqspi->current_cs = f_pdata->cs; 1213 cqspi_chipselect(f_pdata); 1214 } 1215 1216 /* Setup baudrate divisor and delays */ 1217 if (switch_ck) { 1218 cqspi->sclk = sclk; 1219 cqspi_config_baudrate_div(cqspi); 1220 cqspi_delay(f_pdata); 1221 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, 1222 f_pdata->read_delay); 1223 } 1224 1225 if (switch_cs || switch_ck) 1226 cqspi_controller_enable(cqspi, 1); 1227 } 1228 1229 static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, 1230 const struct spi_mem_op *op) 1231 { 1232 struct cqspi_st *cqspi = f_pdata->cqspi; 1233 loff_t to = op->addr.val; 1234 size_t len = op->data.nbytes; 1235 const u_char *buf = op->data.buf.out; 1236 int ret; 1237 1238 ret = cqspi_write_setup(f_pdata, op); 1239 if (ret) 1240 return ret; 1241 1242 /* 1243 * Some flashes like the Cypress Semper flash expect a dummy 4-byte 1244 * address (all 0s) with the read status register command in DTR mode. 1245 * But this controller does not support sending dummy address bytes to 1246 * the flash when it is polling the write completion register in DTR 1247 * mode. So, we can not use direct mode when in DTR mode for writing 1248 * data. 1249 */ 1250 if (!op->cmd.dtr && cqspi->use_direct_mode && 1251 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { 1252 memcpy_toio(cqspi->ahb_base + to, buf, len); 1253 return cqspi_wait_idle(cqspi); 1254 } 1255 1256 return cqspi_indirect_write_execute(f_pdata, to, buf, len); 1257 } 1258 1259 static void cqspi_rx_dma_callback(void *param) 1260 { 1261 struct cqspi_st *cqspi = param; 1262 1263 complete(&cqspi->rx_dma_complete); 1264 } 1265 1266 static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, 1267 u_char *buf, loff_t from, size_t len) 1268 { 1269 struct cqspi_st *cqspi = f_pdata->cqspi; 1270 struct device *dev = &cqspi->pdev->dev; 1271 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 1272 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; 1273 int ret = 0; 1274 struct dma_async_tx_descriptor *tx; 1275 dma_cookie_t cookie; 1276 dma_addr_t dma_dst; 1277 struct device *ddev; 1278 1279 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { 1280 memcpy_fromio(buf, cqspi->ahb_base + from, len); 1281 return 0; 1282 } 1283 1284 ddev = cqspi->rx_chan->device->dev; 1285 dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); 1286 if (dma_mapping_error(ddev, dma_dst)) { 1287 dev_err(dev, "dma mapping failed\n"); 1288 return -ENOMEM; 1289 } 1290 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, 1291 len, flags); 1292 if (!tx) { 1293 dev_err(dev, "device_prep_dma_memcpy error\n"); 1294 ret = -EIO; 1295 goto err_unmap; 1296 } 1297 1298 tx->callback = cqspi_rx_dma_callback; 1299 tx->callback_param = cqspi; 1300 cookie = tx->tx_submit(tx); 1301 reinit_completion(&cqspi->rx_dma_complete); 1302 1303 ret = dma_submit_error(cookie); 1304 if (ret) { 1305 dev_err(dev, "dma_submit_error %d\n", cookie); 1306 ret = -EIO; 1307 goto err_unmap; 1308 } 1309 1310 dma_async_issue_pending(cqspi->rx_chan); 1311 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, 1312 msecs_to_jiffies(max_t(size_t, len, 500)))) { 1313 dmaengine_terminate_sync(cqspi->rx_chan); 1314 dev_err(dev, "DMA wait_for_completion_timeout\n"); 1315 ret = -ETIMEDOUT; 1316 goto err_unmap; 1317 } 1318 1319 err_unmap: 1320 dma_unmap_single(ddev, dma_dst, len, DMA_FROM_DEVICE); 1321 1322 return ret; 1323 } 1324 1325 static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, 1326 const struct spi_mem_op *op) 1327 { 1328 struct cqspi_st *cqspi = f_pdata->cqspi; 1329 struct device *dev = &cqspi->pdev->dev; 1330 const struct cqspi_driver_platdata *ddata; 1331 loff_t from = op->addr.val; 1332 size_t len = op->data.nbytes; 1333 u_char *buf = op->data.buf.in; 1334 u64 dma_align = (u64)(uintptr_t)buf; 1335 int ret; 1336 1337 ddata = of_device_get_match_data(dev); 1338 1339 ret = cqspi_read_setup(f_pdata, op); 1340 if (ret) 1341 return ret; 1342 1343 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) 1344 return cqspi_direct_read_execute(f_pdata, buf, from, len); 1345 1346 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && 1347 virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) 1348 return ddata->indirect_read_dma(f_pdata, buf, from, len); 1349 1350 return cqspi_indirect_read_execute(f_pdata, buf, from, len); 1351 } 1352 1353 static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) 1354 { 1355 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 1356 struct cqspi_flash_pdata *f_pdata; 1357 1358 f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; 1359 cqspi_configure(f_pdata, mem->spi->max_speed_hz); 1360 1361 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 1362 /* 1363 * Performing reads in DAC mode forces to read minimum 4 bytes 1364 * which is unsupported on some flash devices during register 1365 * reads, prefer STIG mode for such small reads. 1366 */ 1367 if (!op->addr.nbytes || 1368 op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) 1369 return cqspi_command_read(f_pdata, op); 1370 1371 return cqspi_read(f_pdata, op); 1372 } 1373 1374 if (!op->addr.nbytes || !op->data.buf.out) 1375 return cqspi_command_write(f_pdata, op); 1376 1377 return cqspi_write(f_pdata, op); 1378 } 1379 1380 static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 1381 { 1382 int ret; 1383 1384 ret = cqspi_mem_process(mem, op); 1385 if (ret) 1386 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); 1387 1388 return ret; 1389 } 1390 1391 static bool cqspi_supports_mem_op(struct spi_mem *mem, 1392 const struct spi_mem_op *op) 1393 { 1394 bool all_true, all_false; 1395 1396 /* 1397 * op->dummy.dtr is required for converting nbytes into ncycles. 1398 * Also, don't check the dtr field of the op phase having zero nbytes. 1399 */ 1400 all_true = op->cmd.dtr && 1401 (!op->addr.nbytes || op->addr.dtr) && 1402 (!op->dummy.nbytes || op->dummy.dtr) && 1403 (!op->data.nbytes || op->data.dtr); 1404 1405 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 1406 !op->data.dtr; 1407 1408 if (all_true) { 1409 /* Right now we only support 8-8-8 DTR mode. */ 1410 if (op->cmd.nbytes && op->cmd.buswidth != 8) 1411 return false; 1412 if (op->addr.nbytes && op->addr.buswidth != 8) 1413 return false; 1414 if (op->data.nbytes && op->data.buswidth != 8) 1415 return false; 1416 } else if (!all_false) { 1417 /* Mixed DTR modes are not supported. */ 1418 return false; 1419 } 1420 1421 return spi_mem_default_supports_op(mem, op); 1422 } 1423 1424 static int cqspi_of_get_flash_pdata(struct platform_device *pdev, 1425 struct cqspi_flash_pdata *f_pdata, 1426 struct device_node *np) 1427 { 1428 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { 1429 dev_err(&pdev->dev, "couldn't determine read-delay\n"); 1430 return -ENXIO; 1431 } 1432 1433 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { 1434 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); 1435 return -ENXIO; 1436 } 1437 1438 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { 1439 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); 1440 return -ENXIO; 1441 } 1442 1443 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { 1444 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); 1445 return -ENXIO; 1446 } 1447 1448 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { 1449 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); 1450 return -ENXIO; 1451 } 1452 1453 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { 1454 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); 1455 return -ENXIO; 1456 } 1457 1458 return 0; 1459 } 1460 1461 static int cqspi_of_get_pdata(struct cqspi_st *cqspi) 1462 { 1463 struct device *dev = &cqspi->pdev->dev; 1464 struct device_node *np = dev->of_node; 1465 u32 id[2]; 1466 1467 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); 1468 1469 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { 1470 dev_err(dev, "couldn't determine fifo-depth\n"); 1471 return -ENXIO; 1472 } 1473 1474 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { 1475 dev_err(dev, "couldn't determine fifo-width\n"); 1476 return -ENXIO; 1477 } 1478 1479 if (of_property_read_u32(np, "cdns,trigger-address", 1480 &cqspi->trigger_address)) { 1481 dev_err(dev, "couldn't determine trigger-address\n"); 1482 return -ENXIO; 1483 } 1484 1485 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) 1486 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; 1487 1488 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); 1489 1490 if (!of_property_read_u32_array(np, "power-domains", id, 1491 ARRAY_SIZE(id))) 1492 cqspi->pd_dev_id = id[1]; 1493 1494 return 0; 1495 } 1496 1497 static void cqspi_controller_init(struct cqspi_st *cqspi) 1498 { 1499 u32 reg; 1500 1501 cqspi_controller_enable(cqspi, 0); 1502 1503 /* Configure the remap address register, no remap */ 1504 writel(0, cqspi->iobase + CQSPI_REG_REMAP); 1505 1506 /* Disable all interrupts. */ 1507 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); 1508 1509 /* Configure the SRAM split to 1:1 . */ 1510 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); 1511 1512 /* Load indirect trigger address. */ 1513 writel(cqspi->trigger_address, 1514 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); 1515 1516 /* Program read watermark -- 1/2 of the FIFO. */ 1517 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, 1518 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); 1519 /* Program write watermark -- 1/8 of the FIFO. */ 1520 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, 1521 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); 1522 1523 /* Disable direct access controller */ 1524 if (!cqspi->use_direct_mode) { 1525 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1526 reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; 1527 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1528 } 1529 1530 /* Enable DMA interface */ 1531 if (cqspi->use_dma_read) { 1532 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); 1533 reg |= CQSPI_REG_CONFIG_DMA_MASK; 1534 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); 1535 } 1536 1537 cqspi_controller_enable(cqspi, 1); 1538 } 1539 1540 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) 1541 { 1542 dma_cap_mask_t mask; 1543 1544 dma_cap_zero(mask); 1545 dma_cap_set(DMA_MEMCPY, mask); 1546 1547 cqspi->rx_chan = dma_request_chan_by_mask(&mask); 1548 if (IS_ERR(cqspi->rx_chan)) { 1549 int ret = PTR_ERR(cqspi->rx_chan); 1550 1551 cqspi->rx_chan = NULL; 1552 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); 1553 } 1554 init_completion(&cqspi->rx_dma_complete); 1555 1556 return 0; 1557 } 1558 1559 static const char *cqspi_get_name(struct spi_mem *mem) 1560 { 1561 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); 1562 struct device *dev = &cqspi->pdev->dev; 1563 1564 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); 1565 } 1566 1567 static const struct spi_controller_mem_ops cqspi_mem_ops = { 1568 .exec_op = cqspi_exec_mem_op, 1569 .get_name = cqspi_get_name, 1570 .supports_op = cqspi_supports_mem_op, 1571 }; 1572 1573 static const struct spi_controller_mem_caps cqspi_mem_caps = { 1574 .dtr = true, 1575 }; 1576 1577 static int cqspi_setup_flash(struct cqspi_st *cqspi) 1578 { 1579 struct platform_device *pdev = cqspi->pdev; 1580 struct device *dev = &pdev->dev; 1581 struct device_node *np = dev->of_node; 1582 struct cqspi_flash_pdata *f_pdata; 1583 unsigned int cs; 1584 int ret; 1585 1586 /* Get flash device data */ 1587 for_each_available_child_of_node(dev->of_node, np) { 1588 ret = of_property_read_u32(np, "reg", &cs); 1589 if (ret) { 1590 dev_err(dev, "Couldn't determine chip select.\n"); 1591 of_node_put(np); 1592 return ret; 1593 } 1594 1595 if (cs >= CQSPI_MAX_CHIPSELECT) { 1596 dev_err(dev, "Chip select %d out of range.\n", cs); 1597 of_node_put(np); 1598 return -EINVAL; 1599 } 1600 1601 f_pdata = &cqspi->f_pdata[cs]; 1602 f_pdata->cqspi = cqspi; 1603 f_pdata->cs = cs; 1604 1605 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np); 1606 if (ret) { 1607 of_node_put(np); 1608 return ret; 1609 } 1610 } 1611 1612 return 0; 1613 } 1614 1615 static int cqspi_probe(struct platform_device *pdev) 1616 { 1617 const struct cqspi_driver_platdata *ddata; 1618 struct reset_control *rstc, *rstc_ocp; 1619 struct device *dev = &pdev->dev; 1620 struct spi_master *master; 1621 struct resource *res_ahb; 1622 struct cqspi_st *cqspi; 1623 int ret; 1624 int irq; 1625 1626 master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi)); 1627 if (!master) { 1628 dev_err(&pdev->dev, "spi_alloc_master failed\n"); 1629 return -ENOMEM; 1630 } 1631 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; 1632 master->mem_ops = &cqspi_mem_ops; 1633 master->mem_caps = &cqspi_mem_caps; 1634 master->dev.of_node = pdev->dev.of_node; 1635 1636 cqspi = spi_master_get_devdata(master); 1637 1638 cqspi->pdev = pdev; 1639 cqspi->master = master; 1640 platform_set_drvdata(pdev, cqspi); 1641 1642 /* Obtain configuration from OF. */ 1643 ret = cqspi_of_get_pdata(cqspi); 1644 if (ret) { 1645 dev_err(dev, "Cannot get mandatory OF data.\n"); 1646 return -ENODEV; 1647 } 1648 1649 /* Obtain QSPI clock. */ 1650 cqspi->clk = devm_clk_get(dev, NULL); 1651 if (IS_ERR(cqspi->clk)) { 1652 dev_err(dev, "Cannot claim QSPI clock.\n"); 1653 ret = PTR_ERR(cqspi->clk); 1654 return ret; 1655 } 1656 1657 /* Obtain and remap controller address. */ 1658 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); 1659 if (IS_ERR(cqspi->iobase)) { 1660 dev_err(dev, "Cannot remap controller address.\n"); 1661 ret = PTR_ERR(cqspi->iobase); 1662 return ret; 1663 } 1664 1665 /* Obtain and remap AHB address. */ 1666 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); 1667 if (IS_ERR(cqspi->ahb_base)) { 1668 dev_err(dev, "Cannot remap AHB address.\n"); 1669 ret = PTR_ERR(cqspi->ahb_base); 1670 return ret; 1671 } 1672 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; 1673 cqspi->ahb_size = resource_size(res_ahb); 1674 1675 init_completion(&cqspi->transfer_complete); 1676 1677 /* Obtain IRQ line. */ 1678 irq = platform_get_irq(pdev, 0); 1679 if (irq < 0) 1680 return -ENXIO; 1681 1682 pm_runtime_enable(dev); 1683 ret = pm_runtime_resume_and_get(dev); 1684 if (ret < 0) 1685 goto probe_pm_failed; 1686 1687 ret = clk_prepare_enable(cqspi->clk); 1688 if (ret) { 1689 dev_err(dev, "Cannot enable QSPI clock.\n"); 1690 goto probe_clk_failed; 1691 } 1692 1693 /* Obtain QSPI reset control */ 1694 rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); 1695 if (IS_ERR(rstc)) { 1696 ret = PTR_ERR(rstc); 1697 dev_err(dev, "Cannot get QSPI reset.\n"); 1698 goto probe_reset_failed; 1699 } 1700 1701 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); 1702 if (IS_ERR(rstc_ocp)) { 1703 ret = PTR_ERR(rstc_ocp); 1704 dev_err(dev, "Cannot get QSPI OCP reset.\n"); 1705 goto probe_reset_failed; 1706 } 1707 1708 reset_control_assert(rstc); 1709 reset_control_deassert(rstc); 1710 1711 reset_control_assert(rstc_ocp); 1712 reset_control_deassert(rstc_ocp); 1713 1714 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); 1715 master->max_speed_hz = cqspi->master_ref_clk_hz; 1716 1717 /* write completion is supported by default */ 1718 cqspi->wr_completion = true; 1719 1720 ddata = of_device_get_match_data(dev); 1721 if (ddata) { 1722 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) 1723 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, 1724 cqspi->master_ref_clk_hz); 1725 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) 1726 master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; 1727 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { 1728 cqspi->use_direct_mode = true; 1729 cqspi->use_direct_mode_wr = true; 1730 } 1731 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) 1732 cqspi->use_dma_read = true; 1733 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) 1734 cqspi->wr_completion = false; 1735 if (ddata->quirks & CQSPI_SLOW_SRAM) 1736 cqspi->slow_sram = true; 1737 1738 if (of_device_is_compatible(pdev->dev.of_node, 1739 "xlnx,versal-ospi-1.0")) 1740 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1741 } 1742 1743 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, 1744 pdev->name, cqspi); 1745 if (ret) { 1746 dev_err(dev, "Cannot request IRQ.\n"); 1747 goto probe_reset_failed; 1748 } 1749 1750 cqspi_wait_idle(cqspi); 1751 cqspi_controller_init(cqspi); 1752 cqspi->current_cs = -1; 1753 cqspi->sclk = 0; 1754 1755 master->num_chipselect = cqspi->num_chipselect; 1756 1757 ret = cqspi_setup_flash(cqspi); 1758 if (ret) { 1759 dev_err(dev, "failed to setup flash parameters %d\n", ret); 1760 goto probe_setup_failed; 1761 } 1762 1763 if (cqspi->use_direct_mode) { 1764 ret = cqspi_request_mmap_dma(cqspi); 1765 if (ret == -EPROBE_DEFER) 1766 goto probe_setup_failed; 1767 } 1768 1769 ret = spi_register_master(master); 1770 if (ret) { 1771 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); 1772 goto probe_setup_failed; 1773 } 1774 1775 return 0; 1776 probe_setup_failed: 1777 cqspi_controller_enable(cqspi, 0); 1778 probe_reset_failed: 1779 clk_disable_unprepare(cqspi->clk); 1780 probe_clk_failed: 1781 pm_runtime_put_sync(dev); 1782 probe_pm_failed: 1783 pm_runtime_disable(dev); 1784 return ret; 1785 } 1786 1787 static int cqspi_remove(struct platform_device *pdev) 1788 { 1789 struct cqspi_st *cqspi = platform_get_drvdata(pdev); 1790 1791 spi_unregister_master(cqspi->master); 1792 cqspi_controller_enable(cqspi, 0); 1793 1794 if (cqspi->rx_chan) 1795 dma_release_channel(cqspi->rx_chan); 1796 1797 clk_disable_unprepare(cqspi->clk); 1798 1799 pm_runtime_put_sync(&pdev->dev); 1800 pm_runtime_disable(&pdev->dev); 1801 1802 return 0; 1803 } 1804 1805 #ifdef CONFIG_PM_SLEEP 1806 static int cqspi_suspend(struct device *dev) 1807 { 1808 struct cqspi_st *cqspi = dev_get_drvdata(dev); 1809 1810 cqspi_controller_enable(cqspi, 0); 1811 return 0; 1812 } 1813 1814 static int cqspi_resume(struct device *dev) 1815 { 1816 struct cqspi_st *cqspi = dev_get_drvdata(dev); 1817 1818 cqspi_controller_enable(cqspi, 1); 1819 return 0; 1820 } 1821 1822 static const struct dev_pm_ops cqspi__dev_pm_ops = { 1823 .suspend = cqspi_suspend, 1824 .resume = cqspi_resume, 1825 }; 1826 1827 #define CQSPI_DEV_PM_OPS (&cqspi__dev_pm_ops) 1828 #else 1829 #define CQSPI_DEV_PM_OPS NULL 1830 #endif 1831 1832 static const struct cqspi_driver_platdata cdns_qspi = { 1833 .quirks = CQSPI_DISABLE_DAC_MODE, 1834 }; 1835 1836 static const struct cqspi_driver_platdata k2g_qspi = { 1837 .quirks = CQSPI_NEEDS_WR_DELAY, 1838 }; 1839 1840 static const struct cqspi_driver_platdata am654_ospi = { 1841 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 1842 .quirks = CQSPI_NEEDS_WR_DELAY, 1843 }; 1844 1845 static const struct cqspi_driver_platdata intel_lgm_qspi = { 1846 .quirks = CQSPI_DISABLE_DAC_MODE, 1847 }; 1848 1849 static const struct cqspi_driver_platdata socfpga_qspi = { 1850 .quirks = CQSPI_DISABLE_DAC_MODE 1851 | CQSPI_NO_SUPPORT_WR_COMPLETION 1852 | CQSPI_SLOW_SRAM, 1853 }; 1854 1855 static const struct cqspi_driver_platdata versal_ospi = { 1856 .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, 1857 .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, 1858 .indirect_read_dma = cqspi_versal_indirect_read_dma, 1859 .get_dma_status = cqspi_get_versal_dma_status, 1860 }; 1861 1862 static const struct of_device_id cqspi_dt_ids[] = { 1863 { 1864 .compatible = "cdns,qspi-nor", 1865 .data = &cdns_qspi, 1866 }, 1867 { 1868 .compatible = "ti,k2g-qspi", 1869 .data = &k2g_qspi, 1870 }, 1871 { 1872 .compatible = "ti,am654-ospi", 1873 .data = &am654_ospi, 1874 }, 1875 { 1876 .compatible = "intel,lgm-qspi", 1877 .data = &intel_lgm_qspi, 1878 }, 1879 { 1880 .compatible = "xlnx,versal-ospi-1.0", 1881 .data = &versal_ospi, 1882 }, 1883 { 1884 .compatible = "intel,socfpga-qspi", 1885 .data = &socfpga_qspi, 1886 }, 1887 { /* end of table */ } 1888 }; 1889 1890 MODULE_DEVICE_TABLE(of, cqspi_dt_ids); 1891 1892 static struct platform_driver cqspi_platform_driver = { 1893 .probe = cqspi_probe, 1894 .remove = cqspi_remove, 1895 .driver = { 1896 .name = CQSPI_NAME, 1897 .pm = CQSPI_DEV_PM_OPS, 1898 .of_match_table = cqspi_dt_ids, 1899 }, 1900 }; 1901 1902 module_platform_driver(cqspi_platform_driver); 1903 1904 MODULE_DESCRIPTION("Cadence QSPI Controller Driver"); 1905 MODULE_LICENSE("GPL v2"); 1906 MODULE_ALIAS("platform:" CQSPI_NAME); 1907 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>"); 1908 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>"); 1909 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>"); 1910 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>"); 1911 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>"); 1912