1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Broadcom BCM63xx SPI controller support 4 * 5 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> 6 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/delay.h> 15 #include <linux/interrupt.h> 16 #include <linux/spi/spi.h> 17 #include <linux/completion.h> 18 #include <linux/err.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/of.h> 21 #include <linux/reset.h> 22 23 /* BCM 6338/6348 SPI core */ 24 #define SPI_6348_RSET_SIZE 64 25 #define SPI_6348_CMD 0x00 /* 16-bits register */ 26 #define SPI_6348_INT_STATUS 0x02 27 #define SPI_6348_INT_MASK_ST 0x03 28 #define SPI_6348_INT_MASK 0x04 29 #define SPI_6348_ST 0x05 30 #define SPI_6348_CLK_CFG 0x06 31 #define SPI_6348_FILL_BYTE 0x07 32 #define SPI_6348_MSG_TAIL 0x09 33 #define SPI_6348_RX_TAIL 0x0b 34 #define SPI_6348_MSG_CTL 0x40 /* 8-bits register */ 35 #define SPI_6348_MSG_CTL_WIDTH 8 36 #define SPI_6348_MSG_DATA 0x41 37 #define SPI_6348_MSG_DATA_SIZE 0x3f 38 #define SPI_6348_RX_DATA 0x80 39 #define SPI_6348_RX_DATA_SIZE 0x3f 40 41 /* BCM 3368/6358/6262/6368 SPI core */ 42 #define SPI_6358_RSET_SIZE 1804 43 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ 44 #define SPI_6358_MSG_CTL_WIDTH 16 45 #define SPI_6358_MSG_DATA 0x02 46 #define SPI_6358_MSG_DATA_SIZE 0x21e 47 #define SPI_6358_RX_DATA 0x400 48 #define SPI_6358_RX_DATA_SIZE 0x220 49 #define SPI_6358_CMD 0x700 /* 16-bits register */ 50 #define SPI_6358_INT_STATUS 0x702 51 #define SPI_6358_INT_MASK_ST 0x703 52 #define SPI_6358_INT_MASK 0x704 53 #define SPI_6358_ST 0x705 54 #define SPI_6358_CLK_CFG 0x706 55 #define SPI_6358_FILL_BYTE 0x707 56 #define SPI_6358_MSG_TAIL 0x709 57 #define SPI_6358_RX_TAIL 0x70B 58 59 /* Shared SPI definitions */ 60 61 /* Message configuration */ 62 #define SPI_FD_RW 0x00 63 #define SPI_HD_W 0x01 64 #define SPI_HD_R 0x02 65 #define SPI_BYTE_CNT_SHIFT 0 66 #define SPI_6348_MSG_TYPE_SHIFT 6 67 #define SPI_6358_MSG_TYPE_SHIFT 14 68 69 /* Command */ 70 #define SPI_CMD_NOOP 0x00 71 #define SPI_CMD_SOFT_RESET 0x01 72 #define SPI_CMD_HARD_RESET 0x02 73 #define SPI_CMD_START_IMMEDIATE 0x03 74 #define SPI_CMD_COMMAND_SHIFT 0 75 #define SPI_CMD_COMMAND_MASK 0x000f 76 #define SPI_CMD_DEVICE_ID_SHIFT 4 77 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 78 #define SPI_CMD_ONE_BYTE_SHIFT 11 79 #define SPI_CMD_ONE_WIRE_SHIFT 12 80 #define SPI_DEV_ID_0 0 81 #define SPI_DEV_ID_1 1 82 #define SPI_DEV_ID_2 2 83 #define SPI_DEV_ID_3 3 84 85 /* Interrupt mask */ 86 #define SPI_INTR_CMD_DONE 0x01 87 #define SPI_INTR_RX_OVERFLOW 0x02 88 #define SPI_INTR_TX_UNDERFLOW 0x04 89 #define SPI_INTR_TX_OVERFLOW 0x08 90 #define SPI_INTR_RX_UNDERFLOW 0x10 91 #define SPI_INTR_CLEAR_ALL 0x1f 92 93 /* Status */ 94 #define SPI_RX_EMPTY 0x02 95 #define SPI_CMD_BUSY 0x04 96 #define SPI_SERIAL_BUSY 0x08 97 98 /* Clock configuration */ 99 #define SPI_CLK_20MHZ 0x00 100 #define SPI_CLK_0_391MHZ 0x01 101 #define SPI_CLK_0_781MHZ 0x02 /* default */ 102 #define SPI_CLK_1_563MHZ 0x03 103 #define SPI_CLK_3_125MHZ 0x04 104 #define SPI_CLK_6_250MHZ 0x05 105 #define SPI_CLK_12_50MHZ 0x06 106 #define SPI_CLK_MASK 0x07 107 #define SPI_SSOFFTIME_MASK 0x38 108 #define SPI_SSOFFTIME_SHIFT 3 109 #define SPI_BYTE_SWAP 0x80 110 111 enum bcm63xx_regs_spi { 112 SPI_CMD, 113 SPI_INT_STATUS, 114 SPI_INT_MASK_ST, 115 SPI_INT_MASK, 116 SPI_ST, 117 SPI_CLK_CFG, 118 SPI_FILL_BYTE, 119 SPI_MSG_TAIL, 120 SPI_RX_TAIL, 121 SPI_MSG_CTL, 122 SPI_MSG_DATA, 123 SPI_RX_DATA, 124 SPI_MSG_TYPE_SHIFT, 125 SPI_MSG_CTL_WIDTH, 126 SPI_MSG_DATA_SIZE, 127 }; 128 129 #define BCM63XX_SPI_MAX_PREPEND 7 130 131 #define BCM63XX_SPI_MAX_CS 8 132 #define BCM63XX_SPI_BUS_NUM 0 133 134 struct bcm63xx_spi { 135 struct completion done; 136 137 void __iomem *regs; 138 int irq; 139 140 /* Platform data */ 141 const unsigned long *reg_offsets; 142 unsigned int fifo_size; 143 unsigned int msg_type_shift; 144 unsigned int msg_ctl_width; 145 146 /* data iomem */ 147 u8 __iomem *tx_io; 148 const u8 __iomem *rx_io; 149 150 struct clk *clk; 151 struct platform_device *pdev; 152 }; 153 154 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, 155 unsigned int offset) 156 { 157 return readb(bs->regs + bs->reg_offsets[offset]); 158 } 159 160 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, 161 u8 value, unsigned int offset) 162 { 163 writeb(value, bs->regs + bs->reg_offsets[offset]); 164 } 165 166 static inline void bcm_spi_writew(struct bcm63xx_spi *bs, 167 u16 value, unsigned int offset) 168 { 169 #ifdef CONFIG_CPU_BIG_ENDIAN 170 iowrite16be(value, bs->regs + bs->reg_offsets[offset]); 171 #else 172 writew(value, bs->regs + bs->reg_offsets[offset]); 173 #endif 174 } 175 176 static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { 177 { 20000000, SPI_CLK_20MHZ }, 178 { 12500000, SPI_CLK_12_50MHZ }, 179 { 6250000, SPI_CLK_6_250MHZ }, 180 { 3125000, SPI_CLK_3_125MHZ }, 181 { 1563000, SPI_CLK_1_563MHZ }, 182 { 781000, SPI_CLK_0_781MHZ }, 183 { 391000, SPI_CLK_0_391MHZ } 184 }; 185 186 static void bcm63xx_spi_setup_transfer(struct spi_device *spi, 187 struct spi_transfer *t) 188 { 189 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller); 190 u8 clk_cfg, reg; 191 int i; 192 193 /* Default to lowest clock configuration */ 194 clk_cfg = SPI_CLK_0_391MHZ; 195 196 /* Find the closest clock configuration */ 197 for (i = 0; i < SPI_CLK_MASK; i++) { 198 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) { 199 clk_cfg = bcm63xx_spi_freq_table[i][1]; 200 break; 201 } 202 } 203 204 /* clear existing clock configuration bits of the register */ 205 reg = bcm_spi_readb(bs, SPI_CLK_CFG); 206 reg &= ~SPI_CLK_MASK; 207 reg |= clk_cfg; 208 209 bcm_spi_writeb(bs, reg, SPI_CLK_CFG); 210 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", 211 clk_cfg, t->speed_hz); 212 } 213 214 /* the spi->mode bits understood by this driver: */ 215 #define MODEBITS (SPI_CPOL | SPI_CPHA) 216 217 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, 218 unsigned int num_transfers) 219 { 220 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller); 221 u16 msg_ctl; 222 u16 cmd; 223 unsigned int i, timeout = 0, prepend_len = 0, len = 0; 224 struct spi_transfer *t = first; 225 bool do_rx = false; 226 bool do_tx = false; 227 228 /* Disable the CMD_DONE interrupt */ 229 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 230 231 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", 232 t->tx_buf, t->rx_buf, t->len); 233 234 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) 235 prepend_len = t->len; 236 237 /* prepare the buffer */ 238 for (i = 0; i < num_transfers; i++) { 239 if (t->tx_buf) { 240 do_tx = true; 241 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); 242 243 /* don't prepend more than one tx */ 244 if (t != first) 245 prepend_len = 0; 246 } 247 248 if (t->rx_buf) { 249 do_rx = true; 250 251 /* 252 * In certain hardware implementations, there appears to be a 253 * hidden accumulator that tracks the number of bytes written into 254 * the hardware FIFO, and this accumulator overrides the length in 255 * the SPI_MSG_CTL register. 256 * 257 * Therefore, for read-only transfers, we need to write some dummy 258 * value into the FIFO to keep the accumulator tracking the correct 259 * length. 260 */ 261 if (!t->tx_buf) 262 memset_io(bs->tx_io + len, 0xFF, t->len); 263 264 /* prepend is half-duplex write only */ 265 if (t == first) 266 prepend_len = 0; 267 } 268 269 len += t->len; 270 271 t = list_entry(t->transfer_list.next, struct spi_transfer, 272 transfer_list); 273 } 274 275 reinit_completion(&bs->done); 276 277 /* Fill in the Message control register */ 278 msg_ctl = (len << SPI_BYTE_CNT_SHIFT); 279 280 if (do_rx && do_tx && prepend_len == 0) 281 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); 282 else if (do_rx) 283 msg_ctl |= (SPI_HD_R << bs->msg_type_shift); 284 else if (do_tx) 285 msg_ctl |= (SPI_HD_W << bs->msg_type_shift); 286 287 switch (bs->msg_ctl_width) { 288 case 8: 289 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); 290 break; 291 case 16: 292 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); 293 break; 294 } 295 296 /* Issue the transfer */ 297 cmd = SPI_CMD_START_IMMEDIATE; 298 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); 299 cmd |= (spi_get_chipselect(spi, 0) << SPI_CMD_DEVICE_ID_SHIFT); 300 bcm_spi_writew(bs, cmd, SPI_CMD); 301 302 /* Enable the CMD_DONE interrupt */ 303 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); 304 305 timeout = wait_for_completion_timeout(&bs->done, HZ); 306 if (!timeout) 307 return -ETIMEDOUT; 308 309 if (!do_rx) 310 return 0; 311 312 len = 0; 313 t = first; 314 /* Read out all the data */ 315 for (i = 0; i < num_transfers; i++) { 316 if (t->rx_buf) 317 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); 318 319 if (t != first || prepend_len == 0) 320 len += t->len; 321 322 t = list_entry(t->transfer_list.next, struct spi_transfer, 323 transfer_list); 324 } 325 326 return 0; 327 } 328 329 static int bcm63xx_spi_transfer_one(struct spi_controller *host, 330 struct spi_message *m) 331 { 332 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 333 struct spi_transfer *t, *first = NULL; 334 struct spi_device *spi = m->spi; 335 int status = 0; 336 unsigned int n_transfers = 0, total_len = 0; 337 bool can_use_prepend = false; 338 339 /* 340 * This SPI controller does not support keeping CS active after a 341 * transfer. 342 * Work around this by merging as many transfers we can into one big 343 * full-duplex transfers. 344 */ 345 list_for_each_entry(t, &m->transfers, transfer_list) { 346 if (!first) 347 first = t; 348 349 n_transfers++; 350 total_len += t->len; 351 352 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && 353 first->len <= BCM63XX_SPI_MAX_PREPEND) 354 can_use_prepend = true; 355 else if (can_use_prepend && t->tx_buf) 356 can_use_prepend = false; 357 358 /* we can only transfer one fifo worth of data */ 359 if ((can_use_prepend && 360 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || 361 (!can_use_prepend && total_len > bs->fifo_size)) { 362 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", 363 total_len, bs->fifo_size); 364 status = -EINVAL; 365 goto exit; 366 } 367 368 /* all combined transfers have to have the same speed */ 369 if (t->speed_hz != first->speed_hz) { 370 dev_err(&spi->dev, "unable to change speed between transfers\n"); 371 status = -EINVAL; 372 goto exit; 373 } 374 375 /* CS will be deasserted directly after transfer */ 376 if (t->delay.value) { 377 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); 378 status = -EINVAL; 379 goto exit; 380 } 381 382 if (t->cs_change || 383 list_is_last(&t->transfer_list, &m->transfers)) { 384 /* configure adapter for a new transfer */ 385 bcm63xx_spi_setup_transfer(spi, first); 386 387 /* send the data */ 388 status = bcm63xx_txrx_bufs(spi, first, n_transfers); 389 if (status) 390 goto exit; 391 392 m->actual_length += total_len; 393 394 first = NULL; 395 n_transfers = 0; 396 total_len = 0; 397 can_use_prepend = false; 398 } 399 } 400 exit: 401 m->status = status; 402 spi_finalize_current_message(host); 403 404 return 0; 405 } 406 407 /* This driver supports single host mode only. Hence 408 * CMD_DONE is the only interrupt we care about 409 */ 410 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) 411 { 412 struct spi_controller *host = (struct spi_controller *)dev_id; 413 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 414 u8 intr; 415 416 /* Read interupts and clear them immediately */ 417 intr = bcm_spi_readb(bs, SPI_INT_STATUS); 418 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 419 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 420 421 /* A transfer completed */ 422 if (intr & SPI_INTR_CMD_DONE) 423 complete(&bs->done); 424 425 return IRQ_HANDLED; 426 } 427 428 static size_t bcm63xx_spi_max_length(struct spi_device *spi) 429 { 430 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller); 431 432 return bs->fifo_size; 433 } 434 435 static const unsigned long bcm6348_spi_reg_offsets[] = { 436 [SPI_CMD] = SPI_6348_CMD, 437 [SPI_INT_STATUS] = SPI_6348_INT_STATUS, 438 [SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST, 439 [SPI_INT_MASK] = SPI_6348_INT_MASK, 440 [SPI_ST] = SPI_6348_ST, 441 [SPI_CLK_CFG] = SPI_6348_CLK_CFG, 442 [SPI_FILL_BYTE] = SPI_6348_FILL_BYTE, 443 [SPI_MSG_TAIL] = SPI_6348_MSG_TAIL, 444 [SPI_RX_TAIL] = SPI_6348_RX_TAIL, 445 [SPI_MSG_CTL] = SPI_6348_MSG_CTL, 446 [SPI_MSG_DATA] = SPI_6348_MSG_DATA, 447 [SPI_RX_DATA] = SPI_6348_RX_DATA, 448 [SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT, 449 [SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH, 450 [SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE, 451 }; 452 453 static const unsigned long bcm6358_spi_reg_offsets[] = { 454 [SPI_CMD] = SPI_6358_CMD, 455 [SPI_INT_STATUS] = SPI_6358_INT_STATUS, 456 [SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST, 457 [SPI_INT_MASK] = SPI_6358_INT_MASK, 458 [SPI_ST] = SPI_6358_ST, 459 [SPI_CLK_CFG] = SPI_6358_CLK_CFG, 460 [SPI_FILL_BYTE] = SPI_6358_FILL_BYTE, 461 [SPI_MSG_TAIL] = SPI_6358_MSG_TAIL, 462 [SPI_RX_TAIL] = SPI_6358_RX_TAIL, 463 [SPI_MSG_CTL] = SPI_6358_MSG_CTL, 464 [SPI_MSG_DATA] = SPI_6358_MSG_DATA, 465 [SPI_RX_DATA] = SPI_6358_RX_DATA, 466 [SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT, 467 [SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH, 468 [SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE, 469 }; 470 471 static const struct platform_device_id bcm63xx_spi_dev_match[] = { 472 { 473 .name = "bcm6348-spi", 474 .driver_data = (unsigned long)bcm6348_spi_reg_offsets, 475 }, 476 { 477 .name = "bcm6358-spi", 478 .driver_data = (unsigned long)bcm6358_spi_reg_offsets, 479 }, 480 { 481 }, 482 }; 483 MODULE_DEVICE_TABLE(platform, bcm63xx_spi_dev_match); 484 485 static const struct of_device_id bcm63xx_spi_of_match[] = { 486 { .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets }, 487 { .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets }, 488 { }, 489 }; 490 MODULE_DEVICE_TABLE(of, bcm63xx_spi_of_match); 491 492 static int bcm63xx_spi_probe(struct platform_device *pdev) 493 { 494 struct resource *r; 495 const unsigned long *bcm63xx_spireg; 496 struct device *dev = &pdev->dev; 497 int irq, bus_num; 498 struct spi_controller *host; 499 struct clk *clk; 500 struct bcm63xx_spi *bs; 501 int ret; 502 u32 num_cs = BCM63XX_SPI_MAX_CS; 503 struct reset_control *reset; 504 505 if (dev->of_node) { 506 const struct of_device_id *match; 507 508 match = of_match_node(bcm63xx_spi_of_match, dev->of_node); 509 if (!match) 510 return -EINVAL; 511 bcm63xx_spireg = match->data; 512 513 of_property_read_u32(dev->of_node, "num-cs", &num_cs); 514 if (num_cs > BCM63XX_SPI_MAX_CS) { 515 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n", 516 num_cs); 517 num_cs = BCM63XX_SPI_MAX_CS; 518 } 519 520 bus_num = -1; 521 } else if (pdev->id_entry->driver_data) { 522 const struct platform_device_id *match = pdev->id_entry; 523 524 bcm63xx_spireg = (const unsigned long *)match->driver_data; 525 bus_num = BCM63XX_SPI_BUS_NUM; 526 } else { 527 return -EINVAL; 528 } 529 530 irq = platform_get_irq(pdev, 0); 531 if (irq < 0) 532 return irq; 533 534 clk = devm_clk_get(dev, "spi"); 535 if (IS_ERR(clk)) { 536 dev_err(dev, "no clock for device\n"); 537 return PTR_ERR(clk); 538 } 539 540 reset = devm_reset_control_get_optional_shared(dev, NULL); 541 if (IS_ERR(reset)) 542 return PTR_ERR(reset); 543 544 host = spi_alloc_host(dev, sizeof(*bs)); 545 if (!host) { 546 dev_err(dev, "out of memory\n"); 547 return -ENOMEM; 548 } 549 550 bs = spi_controller_get_devdata(host); 551 init_completion(&bs->done); 552 553 platform_set_drvdata(pdev, host); 554 bs->pdev = pdev; 555 556 bs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r); 557 if (IS_ERR(bs->regs)) { 558 ret = PTR_ERR(bs->regs); 559 goto out_err; 560 } 561 562 bs->irq = irq; 563 bs->clk = clk; 564 bs->reg_offsets = bcm63xx_spireg; 565 bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE]; 566 567 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, 568 pdev->name, host); 569 if (ret) { 570 dev_err(dev, "unable to request irq\n"); 571 goto out_err; 572 } 573 574 host->dev.of_node = dev->of_node; 575 host->bus_num = bus_num; 576 host->num_chipselect = num_cs; 577 host->transfer_one_message = bcm63xx_spi_transfer_one; 578 host->mode_bits = MODEBITS; 579 host->bits_per_word_mask = SPI_BPW_MASK(8); 580 host->max_transfer_size = bcm63xx_spi_max_length; 581 host->max_message_size = bcm63xx_spi_max_length; 582 host->auto_runtime_pm = true; 583 bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT]; 584 bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH]; 585 bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]); 586 bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]); 587 588 /* Initialize hardware */ 589 ret = clk_prepare_enable(bs->clk); 590 if (ret) 591 goto out_err; 592 593 ret = reset_control_reset(reset); 594 if (ret) { 595 dev_err(dev, "unable to reset device: %d\n", ret); 596 goto out_clk_disable; 597 } 598 599 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); 600 601 ret = devm_pm_runtime_enable(&pdev->dev); 602 if (ret) 603 goto out_clk_disable; 604 605 /* register and we are done */ 606 ret = devm_spi_register_controller(dev, host); 607 if (ret) { 608 dev_err(dev, "spi register failed\n"); 609 goto out_clk_disable; 610 } 611 612 dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n", 613 r, irq, bs->fifo_size); 614 615 return 0; 616 617 out_clk_disable: 618 clk_disable_unprepare(clk); 619 out_err: 620 spi_controller_put(host); 621 return ret; 622 } 623 624 static void bcm63xx_spi_remove(struct platform_device *pdev) 625 { 626 struct spi_controller *host = platform_get_drvdata(pdev); 627 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 628 629 /* reset spi block */ 630 bcm_spi_writeb(bs, 0, SPI_INT_MASK); 631 632 /* HW shutdown */ 633 clk_disable_unprepare(bs->clk); 634 } 635 636 static int bcm63xx_spi_suspend(struct device *dev) 637 { 638 struct spi_controller *host = dev_get_drvdata(dev); 639 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 640 641 spi_controller_suspend(host); 642 643 clk_disable_unprepare(bs->clk); 644 645 return 0; 646 } 647 648 static int bcm63xx_spi_resume(struct device *dev) 649 { 650 struct spi_controller *host = dev_get_drvdata(dev); 651 struct bcm63xx_spi *bs = spi_controller_get_devdata(host); 652 int ret; 653 654 ret = clk_prepare_enable(bs->clk); 655 if (ret) 656 return ret; 657 658 spi_controller_resume(host); 659 660 return 0; 661 } 662 663 static DEFINE_SIMPLE_DEV_PM_OPS(bcm63xx_spi_pm_ops, bcm63xx_spi_suspend, bcm63xx_spi_resume); 664 665 static struct platform_driver bcm63xx_spi_driver = { 666 .driver = { 667 .name = "bcm63xx-spi", 668 .pm = &bcm63xx_spi_pm_ops, 669 .of_match_table = bcm63xx_spi_of_match, 670 }, 671 .id_table = bcm63xx_spi_dev_match, 672 .probe = bcm63xx_spi_probe, 673 .remove = bcm63xx_spi_remove, 674 }; 675 676 module_platform_driver(bcm63xx_spi_driver); 677 678 MODULE_ALIAS("platform:bcm63xx_spi"); 679 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); 680 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); 681 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); 682 MODULE_LICENSE("GPL"); 683