1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ASPEED FMC/SPI Memory Controller Driver 4 * 5 * Copyright (c) 2015-2022, IBM Corporation. 6 * Copyright (c) 2020, ASPEED Corporation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/spi/spi.h> 16 #include <linux/spi/spi-mem.h> 17 18 #define DEVICE_NAME "spi-aspeed-smc" 19 20 /* Type setting Register */ 21 #define CONFIG_REG 0x0 22 #define CONFIG_TYPE_SPI 0x2 23 24 /* CE Control Register */ 25 #define CE_CTRL_REG 0x4 26 27 /* CEx Control Register */ 28 #define CE0_CTRL_REG 0x10 29 #define CTRL_IO_MODE_MASK GENMASK(30, 28) 30 #define CTRL_IO_SINGLE_DATA 0x0 31 #define CTRL_IO_DUAL_DATA BIT(29) 32 #define CTRL_IO_QUAD_DATA BIT(30) 33 #define CTRL_COMMAND_SHIFT 16 34 #define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */ 35 #define CTRL_IO_DUMMY_SET(dummy) \ 36 (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6)) 37 #define CTRL_FREQ_SEL_SHIFT 8 38 #define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT) 39 #define CTRL_CE_STOP_ACTIVE BIT(2) 40 #define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0) 41 #define CTRL_IO_MODE_NORMAL 0x0 42 #define CTRL_IO_MODE_READ 0x1 43 #define CTRL_IO_MODE_WRITE 0x2 44 #define CTRL_IO_MODE_USER 0x3 45 46 #define CTRL_IO_CMD_MASK 0xf0ff40c3 47 48 /* CEx Address Decoding Range Register */ 49 #define CE0_SEGMENT_ADDR_REG 0x30 50 51 #define FULL_DUPLEX_RX_DATA 0x1e4 52 53 /* CEx Read timing compensation register */ 54 #define CE0_TIMING_COMPENSATION_REG 0x94 55 56 enum aspeed_spi_ctl_reg_value { 57 ASPEED_SPI_BASE, 58 ASPEED_SPI_READ, 59 ASPEED_SPI_WRITE, 60 ASPEED_SPI_MAX, 61 }; 62 63 struct aspeed_spi; 64 65 struct aspeed_spi_chip { 66 struct aspeed_spi *aspi; 67 u32 cs; 68 void __iomem *ctl; 69 void __iomem *ahb_base; 70 u32 ahb_window_size; 71 u32 ctl_val[ASPEED_SPI_MAX]; 72 u32 clk_freq; 73 bool force_user_mode; 74 }; 75 76 struct aspeed_spi_data { 77 u32 ctl0; 78 u32 max_cs; 79 bool hastype; 80 u32 mode_bits; 81 u32 we0; 82 u32 timing; 83 u32 hclk_mask; 84 u32 hdiv_max; 85 u32 min_window_size; 86 bool full_duplex; 87 88 phys_addr_t (*segment_start)(struct aspeed_spi *aspi, u32 reg); 89 phys_addr_t (*segment_end)(struct aspeed_spi *aspi, u32 reg); 90 u32 (*segment_reg)(struct aspeed_spi *aspi, phys_addr_t start, 91 phys_addr_t end); 92 int (*adjust_window)(struct aspeed_spi *aspi); 93 u32 (*get_clk_div)(struct aspeed_spi_chip *chip, u32 hz); 94 int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv, 95 const u8 *golden_buf, u8 *test_buf); 96 }; 97 98 #define ASPEED_SPI_MAX_NUM_CS 5 99 100 struct aspeed_spi { 101 const struct aspeed_spi_data *data; 102 103 void __iomem *regs; 104 phys_addr_t ahb_base_phy; 105 u32 ahb_window_size; 106 u32 num_cs; 107 struct device *dev; 108 109 struct clk *clk; 110 u32 clk_freq; 111 u8 cs_change; 112 113 struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS]; 114 }; 115 116 static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op) 117 { 118 switch (op->data.buswidth) { 119 case 1: 120 return CTRL_IO_SINGLE_DATA; 121 case 2: 122 return CTRL_IO_DUAL_DATA; 123 case 4: 124 return CTRL_IO_QUAD_DATA; 125 default: 126 return CTRL_IO_SINGLE_DATA; 127 } 128 } 129 130 static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode) 131 { 132 u32 ctl; 133 134 if (io_mode > 0) { 135 ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK; 136 ctl |= io_mode; 137 writel(ctl, chip->ctl); 138 } 139 } 140 141 static void aspeed_spi_start_user(struct aspeed_spi_chip *chip) 142 { 143 u32 ctl = chip->ctl_val[ASPEED_SPI_BASE]; 144 145 ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE; 146 writel(ctl, chip->ctl); 147 148 ctl &= ~CTRL_CE_STOP_ACTIVE; 149 writel(ctl, chip->ctl); 150 } 151 152 static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip) 153 { 154 u32 ctl = chip->ctl_val[ASPEED_SPI_READ] | 155 CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE; 156 157 writel(ctl, chip->ctl); 158 159 /* Restore defaults */ 160 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl); 161 } 162 163 static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len) 164 { 165 size_t offset = 0; 166 167 if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) && 168 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { 169 ioread32_rep(src, buf, len >> 2); 170 offset = len & ~0x3; 171 len -= offset; 172 } 173 ioread8_rep(src, (u8 *)buf + offset, len); 174 return 0; 175 } 176 177 static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len) 178 { 179 size_t offset = 0; 180 181 if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) && 182 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { 183 iowrite32_rep(dst, buf, len >> 2); 184 offset = len & ~0x3; 185 len -= offset; 186 } 187 iowrite8_rep(dst, (const u8 *)buf + offset, len); 188 return 0; 189 } 190 191 static int aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes, 192 u64 offset, u32 opcode) 193 { 194 __be32 temp; 195 u32 cmdaddr; 196 197 switch (addr_nbytes) { 198 case 3: 199 cmdaddr = offset & 0xFFFFFF; 200 cmdaddr |= opcode << 24; 201 202 temp = cpu_to_be32(cmdaddr); 203 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4); 204 break; 205 case 4: 206 temp = cpu_to_be32(offset); 207 aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1); 208 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4); 209 break; 210 default: 211 WARN_ONCE(1, "Unexpected address width %u", addr_nbytes); 212 return -EOPNOTSUPP; 213 } 214 return 0; 215 } 216 217 static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip, 218 const struct spi_mem_op *op) 219 { 220 aspeed_spi_start_user(chip); 221 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1); 222 aspeed_spi_read_from_ahb(op->data.buf.in, 223 chip->ahb_base, op->data.nbytes); 224 aspeed_spi_stop_user(chip); 225 return 0; 226 } 227 228 static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip, 229 const struct spi_mem_op *op) 230 { 231 aspeed_spi_start_user(chip); 232 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1); 233 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, 234 op->data.nbytes); 235 aspeed_spi_stop_user(chip); 236 return 0; 237 } 238 239 static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip, 240 const struct spi_mem_op *op, 241 u64 offset, size_t len, void *buf) 242 { 243 int io_mode = aspeed_spi_get_io_mode(op); 244 u8 dummy = 0xFF; 245 int i; 246 int ret; 247 248 aspeed_spi_start_user(chip); 249 250 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode); 251 if (ret < 0) 252 goto stop_user; 253 254 if (op->dummy.buswidth && op->dummy.nbytes) { 255 for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++) 256 aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy)); 257 } 258 259 aspeed_spi_set_io_mode(chip, io_mode); 260 261 aspeed_spi_read_from_ahb(buf, chip->ahb_base, len); 262 stop_user: 263 aspeed_spi_stop_user(chip); 264 return ret; 265 } 266 267 static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip, 268 const struct spi_mem_op *op) 269 { 270 int ret; 271 int io_mode = aspeed_spi_get_io_mode(op); 272 273 aspeed_spi_start_user(chip); 274 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode); 275 if (ret < 0) 276 goto stop_user; 277 278 aspeed_spi_set_io_mode(chip, io_mode); 279 280 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes); 281 stop_user: 282 aspeed_spi_stop_user(chip); 283 return ret; 284 } 285 286 /* support for 1-1-1, 1-1-2 or 1-1-4 */ 287 static bool aspeed_spi_supports_mem_op(struct spi_mem *mem, 288 const struct spi_mem_op *op) 289 { 290 if (op->cmd.buswidth > 1) 291 return false; 292 293 if (op->addr.nbytes != 0) { 294 if (op->addr.buswidth > 1) 295 return false; 296 if (op->addr.nbytes < 3 || op->addr.nbytes > 4) 297 return false; 298 } 299 300 if (op->dummy.nbytes != 0) { 301 if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7) 302 return false; 303 } 304 305 if (op->data.nbytes != 0 && op->data.buswidth > 4) 306 return false; 307 308 return spi_mem_default_supports_op(mem, op); 309 } 310 311 static const struct aspeed_spi_data ast2400_spi_data; 312 313 static int do_aspeed_spi_exec_mem_op(struct spi_mem *mem, 314 const struct spi_mem_op *op) 315 { 316 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->controller); 317 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(mem->spi, 0)]; 318 u32 addr_mode, addr_mode_backup; 319 u32 ctl_val; 320 int ret = 0; 321 322 addr_mode = readl(aspi->regs + CE_CTRL_REG); 323 addr_mode_backup = addr_mode; 324 325 ctl_val = chip->ctl_val[ASPEED_SPI_BASE]; 326 ctl_val &= ~CTRL_IO_CMD_MASK; 327 328 ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT; 329 330 /* 4BYTE address mode */ 331 if (op->addr.nbytes) { 332 if (op->addr.nbytes == 4) 333 addr_mode |= (0x11 << chip->cs); 334 else 335 addr_mode &= ~(0x11 << chip->cs); 336 337 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data) 338 ctl_val |= CTRL_IO_ADDRESS_4B; 339 } 340 341 if (op->dummy.nbytes) 342 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth); 343 344 if (op->data.nbytes) 345 ctl_val |= aspeed_spi_get_io_mode(op); 346 347 if (op->data.dir == SPI_MEM_DATA_OUT) 348 ctl_val |= CTRL_IO_MODE_WRITE; 349 else 350 ctl_val |= CTRL_IO_MODE_READ; 351 352 if (addr_mode != addr_mode_backup) 353 writel(addr_mode, aspi->regs + CE_CTRL_REG); 354 writel(ctl_val, chip->ctl); 355 356 if (op->data.dir == SPI_MEM_DATA_IN) { 357 if (!op->addr.nbytes) 358 ret = aspeed_spi_read_reg(chip, op); 359 else 360 ret = aspeed_spi_read_user(chip, op, op->addr.val, 361 op->data.nbytes, op->data.buf.in); 362 } else { 363 if (!op->addr.nbytes) 364 ret = aspeed_spi_write_reg(chip, op); 365 else 366 ret = aspeed_spi_write_user(chip, op); 367 } 368 369 /* Restore defaults */ 370 if (addr_mode != addr_mode_backup) 371 writel(addr_mode_backup, aspi->regs + CE_CTRL_REG); 372 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl); 373 return ret; 374 } 375 376 static int aspeed_spi_exec_mem_op(struct spi_mem *mem, 377 const struct spi_mem_op *op) 378 { 379 int ret; 380 381 ret = do_aspeed_spi_exec_mem_op(mem, op); 382 if (ret) 383 dev_err(&mem->spi->dev, "operation failed: %d\n", ret); 384 return ret; 385 } 386 387 static const char *aspeed_spi_get_name(struct spi_mem *mem) 388 { 389 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->controller); 390 struct device *dev = aspi->dev; 391 392 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), 393 spi_get_chipselect(mem->spi, 0)); 394 } 395 396 static int aspeed_spi_set_window(struct aspeed_spi *aspi) 397 { 398 struct device *dev = aspi->dev; 399 off_t offset = 0; 400 phys_addr_t start; 401 phys_addr_t end; 402 void __iomem *seg_reg_base = aspi->regs + CE0_SEGMENT_ADDR_REG; 403 void __iomem *seg_reg; 404 u32 seg_val_backup; 405 u32 seg_val; 406 u32 cs; 407 size_t window_size; 408 409 for (cs = 0; cs < aspi->data->max_cs; cs++) { 410 if (aspi->chips[cs].ahb_base) { 411 devm_iounmap(dev, aspi->chips[cs].ahb_base); 412 aspi->chips[cs].ahb_base = NULL; 413 } 414 } 415 416 for (cs = 0; cs < aspi->data->max_cs; cs++) { 417 seg_reg = seg_reg_base + cs * 4; 418 seg_val_backup = readl(seg_reg); 419 420 start = aspi->ahb_base_phy + offset; 421 window_size = aspi->chips[cs].ahb_window_size; 422 end = start + window_size; 423 424 seg_val = aspi->data->segment_reg(aspi, start, end); 425 writel(seg_val, seg_reg); 426 427 /* 428 * Restore initial value if something goes wrong or the segment 429 * register is written protected. 430 */ 431 if (seg_val != readl(seg_reg)) { 432 dev_warn(dev, "CE%d expected window [ 0x%.9llx - 0x%.9llx ] %zdMB\n", 433 cs, (u64)start, (u64)end - 1, window_size >> 20); 434 writel(seg_val_backup, seg_reg); 435 window_size = aspi->data->segment_end(aspi, seg_val_backup) - 436 aspi->data->segment_start(aspi, seg_val_backup); 437 aspi->chips[cs].ahb_window_size = window_size; 438 end = start + window_size; 439 } 440 441 if (window_size != 0) 442 dev_dbg(dev, "CE%d window [ 0x%.9llx - 0x%.9llx ] %zdMB\n", 443 cs, (u64)start, (u64)end - 1, window_size >> 20); 444 else 445 dev_dbg(dev, "CE%d window closed\n", cs); 446 447 offset += window_size; 448 if (offset > aspi->ahb_window_size) { 449 dev_err(dev, "CE%d offset value 0x%llx is too large.\n", 450 cs, (u64)offset); 451 return -ENOSPC; 452 } 453 454 /* 455 * No need to map the address deocding range when 456 * - window size is 0. 457 * - the CS is unused. 458 */ 459 if (window_size == 0 || cs >= aspi->num_cs) 460 continue; 461 462 aspi->chips[cs].ahb_base = 463 devm_ioremap(aspi->dev, start, window_size); 464 if (!aspi->chips[cs].ahb_base) { 465 dev_err(aspi->dev, 466 "Fail to remap window [0x%.9llx - 0x%.9llx]\n", 467 (u64)start, (u64)end - 1); 468 return -ENOMEM; 469 } 470 } 471 472 return 0; 473 } 474 475 static const struct aspeed_spi_data ast2500_spi_data; 476 static const struct aspeed_spi_data ast2600_spi_data; 477 static const struct aspeed_spi_data ast2600_fmc_data; 478 479 static int aspeed_spi_chip_set_default_window(struct aspeed_spi *aspi) 480 { 481 u32 cs; 482 483 /* No segment registers for the AST2400 SPI controller */ 484 if (aspi->data == &ast2400_spi_data) { 485 aspi->chips[0].ahb_base = devm_ioremap(aspi->dev, 486 aspi->ahb_base_phy, 487 aspi->ahb_window_size); 488 aspi->chips[0].ahb_window_size = aspi->ahb_window_size; 489 return 0; 490 } 491 492 /* Assign the minimum window size to each CS */ 493 for (cs = 0; cs < aspi->num_cs; cs++) { 494 aspi->chips[cs].ahb_window_size = aspi->data->min_window_size; 495 dev_dbg(aspi->dev, "CE%d default window [ 0x%.9llx - 0x%.9llx ]", 496 cs, (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs), 497 (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs - 1)); 498 } 499 500 /* Close unused CS */ 501 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++) 502 aspi->chips[cs].ahb_window_size = 0; 503 504 if (aspi->data->adjust_window) 505 aspi->data->adjust_window(aspi); 506 507 return aspeed_spi_set_window(aspi); 508 } 509 510 /* 511 * As the flash size grows up, we need to trim some decoding 512 * size if needed for the sake of conforming the maximum 513 * decoding size. We trim the decoding size from the rear CS 514 * to avoid affecting the default boot up sequence, usually, 515 * from CS0. Notice, if a CS decoding size is trimmed, 516 * command mode may not work perfectly on that CS, but it only 517 * affect performance and the debug function. 518 */ 519 static int aspeed_spi_trim_window_size(struct aspeed_spi *aspi) 520 { 521 struct aspeed_spi_chip *chips = aspi->chips; 522 size_t total_sz; 523 int cs = aspi->data->max_cs - 1; 524 u32 i; 525 bool trimmed = false; 526 527 do { 528 total_sz = 0; 529 for (i = 0; i < aspi->data->max_cs; i++) 530 total_sz += chips[i].ahb_window_size; 531 532 if (cs < 0) 533 return -ENOMEM; 534 535 if (chips[cs].ahb_window_size <= aspi->data->min_window_size) { 536 cs--; 537 continue; 538 } 539 540 if (total_sz > aspi->ahb_window_size) { 541 chips[cs].ahb_window_size -= 542 aspi->data->min_window_size; 543 total_sz -= aspi->data->min_window_size; 544 /* 545 * If the ahb window size is ever trimmed, only user 546 * mode can be adopted to access the whole flash. 547 */ 548 chips[cs].force_user_mode = true; 549 trimmed = true; 550 } 551 } while (total_sz > aspi->ahb_window_size); 552 553 if (trimmed) { 554 dev_warn(aspi->dev, "Window size after trimming:\n"); 555 for (cs = 0; cs < aspi->data->max_cs; cs++) { 556 dev_warn(aspi->dev, "CE%d: 0x%08x\n", 557 cs, chips[cs].ahb_window_size); 558 } 559 } 560 561 return 0; 562 } 563 564 static int aspeed_adjust_window_ast2400(struct aspeed_spi *aspi) 565 { 566 int ret; 567 int cs; 568 struct aspeed_spi_chip *chips = aspi->chips; 569 570 /* Close unused CS. */ 571 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++) 572 chips[cs].ahb_window_size = 0; 573 574 ret = aspeed_spi_trim_window_size(aspi); 575 if (ret != 0) 576 return ret; 577 578 return 0; 579 } 580 581 /* 582 * For AST2500, the minimum address decoding size for each CS 583 * is 8MB. This address decoding size is mandatory for each 584 * CS no matter whether it will be used. This is a HW limitation. 585 */ 586 static int aspeed_adjust_window_ast2500(struct aspeed_spi *aspi) 587 { 588 int ret; 589 int cs, i; 590 u32 cum_size, rem_size; 591 struct aspeed_spi_chip *chips = aspi->chips; 592 593 /* Assign min_window_sz to unused CS. */ 594 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++) { 595 if (chips[cs].ahb_window_size < aspi->data->min_window_size) 596 chips[cs].ahb_window_size = 597 aspi->data->min_window_size; 598 } 599 600 /* 601 * If command mode or normal mode is used by dirmap read, the start 602 * address of a window should be multiple of its related flash size. 603 * Namely, the total windows size from flash 0 to flash N should 604 * be multiple of the size of flash (N + 1). 605 */ 606 for (cs = aspi->num_cs - 1; cs >= 0; cs--) { 607 cum_size = 0; 608 for (i = 0; i < cs; i++) 609 cum_size += chips[i].ahb_window_size; 610 611 rem_size = cum_size % chips[cs].ahb_window_size; 612 if (chips[cs].ahb_window_size != 0 && rem_size != 0) 613 chips[0].ahb_window_size += 614 chips[cs].ahb_window_size - rem_size; 615 } 616 617 ret = aspeed_spi_trim_window_size(aspi); 618 if (ret != 0) 619 return ret; 620 621 /* The total window size of AST2500 SPI1 CS0 and CS1 must be 128MB */ 622 if (aspi->data == &ast2500_spi_data) 623 chips[1].ahb_window_size = 624 0x08000000 - chips[0].ahb_window_size; 625 626 return 0; 627 } 628 629 static int aspeed_adjust_window_ast2600(struct aspeed_spi *aspi) 630 { 631 int ret; 632 int cs, i; 633 u32 cum_size, rem_size; 634 struct aspeed_spi_chip *chips = aspi->chips; 635 636 /* Close unused CS. */ 637 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++) 638 chips[cs].ahb_window_size = 0; 639 640 /* 641 * If command mode or normal mode is used by dirmap read, the start 642 * address of a window should be multiple of its related flash size. 643 * Namely, the total windows size from flash 0 to flash N should 644 * be multiple of the size of flash (N + 1). 645 */ 646 for (cs = aspi->num_cs - 1; cs >= 0; cs--) { 647 cum_size = 0; 648 for (i = 0; i < cs; i++) 649 cum_size += chips[i].ahb_window_size; 650 651 rem_size = cum_size % chips[cs].ahb_window_size; 652 if (chips[cs].ahb_window_size != 0 && rem_size != 0) 653 chips[0].ahb_window_size += 654 chips[cs].ahb_window_size - rem_size; 655 } 656 657 ret = aspeed_spi_trim_window_size(aspi); 658 if (ret != 0) 659 return ret; 660 661 return 0; 662 } 663 664 /* 665 * Yet to be done when possible : 666 * - Align mappings on flash size (we don't have the info) 667 * - ioremap each window, not strictly necessary since the overall window 668 * is correct. 669 */ 670 static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip, 671 u32 local_offset, u32 size) 672 { 673 struct aspeed_spi *aspi = chip->aspi; 674 int ret; 675 676 /* No segment registers for the AST2400 SPI controller */ 677 if (aspi->data == &ast2400_spi_data) 678 return 0; 679 680 /* Adjust this chip window */ 681 aspi->chips[chip->cs].ahb_window_size = size; 682 683 /* Adjust the overall windows size regarding each platform */ 684 if (aspi->data->adjust_window) 685 aspi->data->adjust_window(aspi); 686 687 ret = aspeed_spi_set_window(aspi); 688 if (ret) 689 return ret; 690 691 return 0; 692 } 693 694 static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip); 695 696 static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) 697 { 698 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller); 699 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)]; 700 struct spi_mem_op *op = &desc->info.op_tmpl; 701 u32 ctl_val; 702 int ret = 0; 703 704 dev_dbg(aspi->dev, 705 "CE%d %s dirmap [ 0x%.8llx - 0x%.8llx ] OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x\n", 706 chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write", 707 desc->info.offset, desc->info.offset + desc->info.length, 708 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 709 op->dummy.buswidth, op->data.buswidth, 710 op->addr.nbytes, op->dummy.nbytes); 711 712 chip->clk_freq = desc->mem->spi->max_speed_hz; 713 714 /* Only for reads */ 715 if (op->data.dir != SPI_MEM_DATA_IN) 716 return -EOPNOTSUPP; 717 718 aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length); 719 720 if (desc->info.length > chip->ahb_window_size) 721 dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping", 722 chip->cs, chip->ahb_window_size >> 20); 723 724 /* Define the default IO read settings */ 725 ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK; 726 ctl_val |= aspeed_spi_get_io_mode(op) | 727 op->cmd.opcode << CTRL_COMMAND_SHIFT | 728 CTRL_IO_MODE_READ; 729 730 if (op->dummy.nbytes) 731 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth); 732 733 /* Tune 4BYTE address mode */ 734 if (op->addr.nbytes) { 735 u32 addr_mode = readl(aspi->regs + CE_CTRL_REG); 736 737 if (op->addr.nbytes == 4) 738 addr_mode |= (0x11 << chip->cs); 739 else 740 addr_mode &= ~(0x11 << chip->cs); 741 writel(addr_mode, aspi->regs + CE_CTRL_REG); 742 743 /* AST2400 SPI controller sets 4BYTE address mode in 744 * CE0 Control Register 745 */ 746 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data) 747 ctl_val |= CTRL_IO_ADDRESS_4B; 748 } 749 750 /* READ mode is the controller default setting */ 751 chip->ctl_val[ASPEED_SPI_READ] = ctl_val; 752 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl); 753 754 ret = aspeed_spi_do_calibration(chip); 755 756 dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n", 757 chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]); 758 759 return ret; 760 } 761 762 static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, 763 u64 offset, size_t len, void *buf) 764 { 765 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller); 766 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)]; 767 768 /* Switch to USER command mode if mapping window is too small */ 769 if (chip->ahb_window_size < offset + len || chip->force_user_mode) { 770 int ret; 771 772 ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf); 773 if (ret < 0) 774 return ret; 775 } else { 776 memcpy_fromio(buf, chip->ahb_base + offset, len); 777 } 778 779 return len; 780 } 781 782 static const struct spi_controller_mem_ops aspeed_spi_mem_ops = { 783 .supports_op = aspeed_spi_supports_mem_op, 784 .exec_op = aspeed_spi_exec_mem_op, 785 .get_name = aspeed_spi_get_name, 786 .dirmap_create = aspeed_spi_dirmap_create, 787 .dirmap_read = aspeed_spi_dirmap_read, 788 }; 789 790 static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type) 791 { 792 u32 reg; 793 794 reg = readl(aspi->regs + CONFIG_REG); 795 reg &= ~(0x3 << (cs * 2)); 796 reg |= type << (cs * 2); 797 writel(reg, aspi->regs + CONFIG_REG); 798 } 799 800 static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable) 801 { 802 u32 we_bit = BIT(aspi->data->we0 + cs); 803 u32 reg = readl(aspi->regs + CONFIG_REG); 804 805 if (enable) 806 reg |= we_bit; 807 else 808 reg &= ~we_bit; 809 writel(reg, aspi->regs + CONFIG_REG); 810 } 811 812 static int aspeed_spi_setup(struct spi_device *spi) 813 { 814 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->controller); 815 const struct aspeed_spi_data *data = aspi->data; 816 unsigned int cs = spi_get_chipselect(spi, 0); 817 struct aspeed_spi_chip *chip = &aspi->chips[cs]; 818 819 chip->aspi = aspi; 820 chip->cs = cs; 821 chip->ctl = aspi->regs + data->ctl0 + cs * 4; 822 823 /* The driver only supports SPI type flash */ 824 if (data->hastype) 825 aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI); 826 827 aspeed_spi_chip_enable(aspi, cs, true); 828 829 chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER; 830 831 dev_dbg(aspi->dev, "CE%d setup done\n", cs); 832 return 0; 833 } 834 835 static void aspeed_spi_cleanup(struct spi_device *spi) 836 { 837 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->controller); 838 unsigned int cs = spi_get_chipselect(spi, 0); 839 840 aspeed_spi_chip_enable(aspi, cs, false); 841 842 dev_dbg(aspi->dev, "CE%d cleanup done\n", cs); 843 } 844 845 static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable) 846 { 847 int cs; 848 849 for (cs = 0; cs < aspi->data->max_cs; cs++) 850 aspeed_spi_chip_enable(aspi, cs, enable); 851 } 852 853 static int aspeed_spi_user_prepare_msg(struct spi_controller *ctlr, 854 struct spi_message *msg) 855 { 856 struct aspeed_spi *aspi = 857 (struct aspeed_spi *)spi_controller_get_devdata(ctlr); 858 const struct aspeed_spi_data *data = aspi->data; 859 struct spi_device *spi = msg->spi; 860 u32 cs = spi_get_chipselect(spi, 0); 861 struct aspeed_spi_chip *chip = &aspi->chips[cs]; 862 u32 ctrl_val; 863 u32 clk_div = data->get_clk_div(chip, spi->max_speed_hz); 864 865 ctrl_val = chip->ctl_val[ASPEED_SPI_BASE]; 866 ctrl_val &= ~CTRL_IO_MODE_MASK & data->hclk_mask; 867 ctrl_val |= clk_div; 868 chip->ctl_val[ASPEED_SPI_BASE] = ctrl_val; 869 870 if (aspi->cs_change == 0) 871 aspeed_spi_start_user(chip); 872 873 return 0; 874 } 875 876 static int aspeed_spi_user_unprepare_msg(struct spi_controller *ctlr, 877 struct spi_message *msg) 878 { 879 struct aspeed_spi *aspi = 880 (struct aspeed_spi *)spi_controller_get_devdata(ctlr); 881 struct spi_device *spi = msg->spi; 882 u32 cs = spi_get_chipselect(spi, 0); 883 struct aspeed_spi_chip *chip = &aspi->chips[cs]; 884 885 if (aspi->cs_change == 0) 886 aspeed_spi_stop_user(chip); 887 888 return 0; 889 } 890 891 static void aspeed_spi_user_transfer_tx(struct aspeed_spi *aspi, 892 struct spi_device *spi, 893 const u8 *tx_buf, u8 *rx_buf, 894 void *dst, u32 len) 895 { 896 const struct aspeed_spi_data *data = aspi->data; 897 bool full_duplex_transfer = data->full_duplex && tx_buf == rx_buf; 898 u32 i; 899 900 if (full_duplex_transfer && 901 !!(spi->mode & (SPI_TX_DUAL | SPI_TX_QUAD | 902 SPI_RX_DUAL | SPI_RX_QUAD))) { 903 dev_err(aspi->dev, 904 "full duplex is only supported for single IO mode\n"); 905 return; 906 } 907 908 for (i = 0; i < len; i++) { 909 writeb(tx_buf[i], dst); 910 if (full_duplex_transfer) 911 rx_buf[i] = readb(aspi->regs + FULL_DUPLEX_RX_DATA); 912 } 913 } 914 915 static int aspeed_spi_user_transfer(struct spi_controller *ctlr, 916 struct spi_device *spi, 917 struct spi_transfer *xfer) 918 { 919 struct aspeed_spi *aspi = 920 (struct aspeed_spi *)spi_controller_get_devdata(ctlr); 921 u32 cs = spi_get_chipselect(spi, 0); 922 struct aspeed_spi_chip *chip = &aspi->chips[cs]; 923 void __iomem *ahb_base = aspi->chips[cs].ahb_base; 924 const u8 *tx_buf = xfer->tx_buf; 925 u8 *rx_buf = xfer->rx_buf; 926 927 dev_dbg(aspi->dev, 928 "[cs%d] xfer: width %d, len %u, tx %p, rx %p\n", 929 cs, xfer->bits_per_word, xfer->len, 930 tx_buf, rx_buf); 931 932 if (tx_buf) { 933 if (spi->mode & SPI_TX_DUAL) 934 aspeed_spi_set_io_mode(chip, CTRL_IO_DUAL_DATA); 935 else if (spi->mode & SPI_TX_QUAD) 936 aspeed_spi_set_io_mode(chip, CTRL_IO_QUAD_DATA); 937 938 aspeed_spi_user_transfer_tx(aspi, spi, tx_buf, rx_buf, 939 (void *)ahb_base, xfer->len); 940 } 941 942 if (rx_buf && rx_buf != tx_buf) { 943 if (spi->mode & SPI_RX_DUAL) 944 aspeed_spi_set_io_mode(chip, CTRL_IO_DUAL_DATA); 945 else if (spi->mode & SPI_RX_QUAD) 946 aspeed_spi_set_io_mode(chip, CTRL_IO_QUAD_DATA); 947 948 ioread8_rep(ahb_base, rx_buf, xfer->len); 949 } 950 951 xfer->error = 0; 952 aspi->cs_change = xfer->cs_change; 953 954 return 0; 955 } 956 957 static int aspeed_spi_probe(struct platform_device *pdev) 958 { 959 struct device *dev = &pdev->dev; 960 const struct aspeed_spi_data *data; 961 struct spi_controller *ctlr; 962 struct aspeed_spi *aspi; 963 struct resource *res; 964 int ret; 965 966 data = of_device_get_match_data(&pdev->dev); 967 if (!data) 968 return -ENODEV; 969 970 ctlr = devm_spi_alloc_host(dev, sizeof(*aspi)); 971 if (!ctlr) 972 return -ENOMEM; 973 974 aspi = spi_controller_get_devdata(ctlr); 975 platform_set_drvdata(pdev, aspi); 976 aspi->data = data; 977 aspi->dev = dev; 978 979 aspi->regs = devm_platform_ioremap_resource(pdev, 0); 980 if (IS_ERR(aspi->regs)) 981 return PTR_ERR(aspi->regs); 982 983 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 984 if (!res) { 985 dev_err(dev, "missing AHB memory\n"); 986 return -EINVAL; 987 } 988 989 aspi->ahb_window_size = resource_size(res); 990 aspi->ahb_base_phy = res->start; 991 992 aspi->clk = devm_clk_get_enabled(&pdev->dev, NULL); 993 if (IS_ERR(aspi->clk)) { 994 dev_err(dev, "missing clock\n"); 995 return PTR_ERR(aspi->clk); 996 } 997 998 aspi->clk_freq = clk_get_rate(aspi->clk); 999 if (!aspi->clk_freq) { 1000 dev_err(dev, "invalid clock\n"); 1001 return -EINVAL; 1002 } 1003 1004 /* IRQ is for DMA, which the driver doesn't support yet */ 1005 1006 ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits; 1007 ctlr->bus_num = pdev->id; 1008 ctlr->mem_ops = &aspeed_spi_mem_ops; 1009 ctlr->setup = aspeed_spi_setup; 1010 ctlr->cleanup = aspeed_spi_cleanup; 1011 ctlr->num_chipselect = of_get_available_child_count(dev->of_node); 1012 ctlr->prepare_message = aspeed_spi_user_prepare_msg; 1013 ctlr->unprepare_message = aspeed_spi_user_unprepare_msg; 1014 ctlr->transfer_one = aspeed_spi_user_transfer; 1015 1016 aspi->num_cs = ctlr->num_chipselect; 1017 1018 ret = aspeed_spi_chip_set_default_window(aspi); 1019 if (ret) { 1020 dev_err(&pdev->dev, "fail to set default window\n"); 1021 return ret; 1022 } 1023 1024 ret = devm_spi_register_controller(dev, ctlr); 1025 if (ret) 1026 dev_err(&pdev->dev, "spi_register_controller failed\n"); 1027 1028 return ret; 1029 } 1030 1031 static void aspeed_spi_remove(struct platform_device *pdev) 1032 { 1033 struct aspeed_spi *aspi = platform_get_drvdata(pdev); 1034 1035 aspeed_spi_enable(aspi, false); 1036 } 1037 1038 /* 1039 * AHB mappings 1040 */ 1041 1042 /* 1043 * The Segment Registers of the AST2400 and AST2500 use a 8MB unit. 1044 * The address range is encoded with absolute addresses in the overall 1045 * mapping window. 1046 */ 1047 static phys_addr_t aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg) 1048 { 1049 return ((reg >> 16) & 0xFF) << 23; 1050 } 1051 1052 static phys_addr_t aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg) 1053 { 1054 return ((reg >> 24) & 0xFF) << 23; 1055 } 1056 1057 static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, 1058 phys_addr_t start, phys_addr_t end) 1059 { 1060 return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24); 1061 } 1062 1063 /* 1064 * The Segment Registers of the AST2600 use a 1MB unit. The address 1065 * range is encoded with offsets in the overall mapping window. 1066 */ 1067 1068 #define AST2600_SEG_ADDR_MASK 0x0ff00000 1069 1070 static phys_addr_t aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi, 1071 u32 reg) 1072 { 1073 u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; 1074 1075 return aspi->ahb_base_phy + start_offset; 1076 } 1077 1078 static phys_addr_t aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi, 1079 u32 reg) 1080 { 1081 u32 end_offset = reg & AST2600_SEG_ADDR_MASK; 1082 1083 /* segment is disabled */ 1084 if (!end_offset) 1085 return aspi->ahb_base_phy; 1086 1087 return aspi->ahb_base_phy + end_offset + 0x100000; 1088 } 1089 1090 static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi, 1091 phys_addr_t start, phys_addr_t end) 1092 { 1093 /* disable zero size segments */ 1094 if (start == end) 1095 return 0; 1096 1097 return ((start & AST2600_SEG_ADDR_MASK) >> 16) | 1098 ((end - 1) & AST2600_SEG_ADDR_MASK); 1099 } 1100 1101 /* The Segment Registers of the AST2700 use a 64KB unit. */ 1102 #define AST2700_SEG_ADDR_MASK 0x7fff0000 1103 1104 static phys_addr_t aspeed_spi_segment_ast2700_start(struct aspeed_spi *aspi, 1105 u32 reg) 1106 { 1107 u64 start_offset = (reg << 16) & AST2700_SEG_ADDR_MASK; 1108 1109 if (!start_offset) 1110 return aspi->ahb_base_phy; 1111 1112 return aspi->ahb_base_phy + start_offset; 1113 } 1114 1115 static phys_addr_t aspeed_spi_segment_ast2700_end(struct aspeed_spi *aspi, 1116 u32 reg) 1117 { 1118 u64 end_offset = reg & AST2700_SEG_ADDR_MASK; 1119 1120 if (!end_offset) 1121 return aspi->ahb_base_phy; 1122 1123 return aspi->ahb_base_phy + end_offset; 1124 } 1125 1126 static u32 aspeed_spi_segment_ast2700_reg(struct aspeed_spi *aspi, 1127 phys_addr_t start, phys_addr_t end) 1128 { 1129 if (start == end) 1130 return 0; 1131 1132 return (u32)(((start & AST2700_SEG_ADDR_MASK) >> 16) | 1133 (end & AST2700_SEG_ADDR_MASK)); 1134 } 1135 1136 /* 1137 * Read timing compensation sequences 1138 */ 1139 1140 #define CALIBRATE_BUF_SIZE SZ_16K 1141 1142 static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip, 1143 const u8 *golden_buf, u8 *test_buf) 1144 { 1145 int i; 1146 1147 for (i = 0; i < 10; i++) { 1148 memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE); 1149 if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) { 1150 #if defined(VERBOSE_DEBUG) 1151 print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE, 1152 test_buf, 0x100); 1153 #endif 1154 return false; 1155 } 1156 } 1157 return true; 1158 } 1159 1160 #define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8)) 1161 1162 /* 1163 * The timing register is shared by all devices. Only update for CE0. 1164 */ 1165 static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv, 1166 const u8 *golden_buf, u8 *test_buf) 1167 { 1168 struct aspeed_spi *aspi = chip->aspi; 1169 const struct aspeed_spi_data *data = aspi->data; 1170 int i; 1171 int good_pass = -1, pass_count = 0; 1172 u32 shift = (hdiv - 1) << 2; 1173 u32 mask = ~(0xfu << shift); 1174 u32 fread_timing_val = 0; 1175 1176 /* Try HCLK delay 0..5, each one with/without delay and look for a 1177 * good pair. 1178 */ 1179 for (i = 0; i < 12; i++) { 1180 bool pass; 1181 1182 if (chip->cs == 0) { 1183 fread_timing_val &= mask; 1184 fread_timing_val |= FREAD_TPASS(i) << shift; 1185 writel(fread_timing_val, aspi->regs + data->timing); 1186 } 1187 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf); 1188 dev_dbg(aspi->dev, 1189 " * [%08x] %d HCLK delay, %dns DI delay : %s", 1190 fread_timing_val, i / 2, (i & 1) ? 0 : 4, 1191 pass ? "PASS" : "FAIL"); 1192 if (pass) { 1193 pass_count++; 1194 if (pass_count == 3) { 1195 good_pass = i - 1; 1196 break; 1197 } 1198 } else { 1199 pass_count = 0; 1200 } 1201 } 1202 1203 /* No good setting for this frequency */ 1204 if (good_pass < 0) 1205 return -1; 1206 1207 /* We have at least one pass of margin, let's use first pass */ 1208 if (chip->cs == 0) { 1209 fread_timing_val &= mask; 1210 fread_timing_val |= FREAD_TPASS(good_pass) << shift; 1211 writel(fread_timing_val, aspi->regs + data->timing); 1212 } 1213 dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]", 1214 good_pass, fread_timing_val); 1215 return 0; 1216 } 1217 1218 static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size) 1219 { 1220 const u32 *tb32 = (const u32 *)test_buf; 1221 u32 i, cnt = 0; 1222 1223 /* We check if we have enough words that are neither all 0 1224 * nor all 1's so the calibration can be considered valid. 1225 * 1226 * I use an arbitrary threshold for now of 64 1227 */ 1228 size >>= 2; 1229 for (i = 0; i < size; i++) { 1230 if (tb32[i] != 0 && tb32[i] != 0xffffffff) 1231 cnt++; 1232 } 1233 return cnt >= 64; 1234 } 1235 1236 static const u32 aspeed_spi_hclk_divs[] = { 1237 /* HCLK, HCLK/2, HCLK/3, HCLK/4, HCLK/5, ..., HCLK/16 */ 1238 0xf, 0x7, 0xe, 0x6, 0xd, 1239 0x5, 0xc, 0x4, 0xb, 0x3, 1240 0xa, 0x2, 0x9, 0x1, 0x8, 1241 0x0 1242 }; 1243 1244 #define ASPEED_SPI_HCLK_DIV(i) \ 1245 (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT) 1246 1247 /* Transfer maximum clock frequency to register setting */ 1248 static u32 aspeed_get_clk_div_ast2400(struct aspeed_spi_chip *chip, 1249 u32 max_hz) 1250 { 1251 struct device *dev = chip->aspi->dev; 1252 u32 hclk_clk = chip->aspi->clk_freq; 1253 u32 div_ctl = 0; 1254 u32 i; 1255 bool found = false; 1256 1257 /* FMC/SPIR10[11:8] */ 1258 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) { 1259 if (hclk_clk / i <= max_hz) { 1260 found = true; 1261 break; 1262 } 1263 } 1264 1265 if (found) { 1266 div_ctl = ASPEED_SPI_HCLK_DIV(i); 1267 chip->clk_freq = hclk_clk / i; 1268 } 1269 1270 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", 1271 found ? "yes" : "no", hclk_clk, max_hz); 1272 1273 if (found) { 1274 dev_dbg(dev, "h_div: 0x%08x, speed: %d\n", 1275 div_ctl, chip->clk_freq); 1276 } 1277 1278 return div_ctl; 1279 } 1280 1281 static u32 aspeed_get_clk_div_ast2500(struct aspeed_spi_chip *chip, 1282 u32 max_hz) 1283 { 1284 struct device *dev = chip->aspi->dev; 1285 u32 hclk_clk = chip->aspi->clk_freq; 1286 u32 div_ctl = 0; 1287 u32 i; 1288 bool found = false; 1289 1290 /* FMC/SPIR10[11:8] */ 1291 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) { 1292 if (hclk_clk / i <= max_hz) { 1293 found = true; 1294 chip->clk_freq = hclk_clk / i; 1295 break; 1296 } 1297 } 1298 1299 if (found) { 1300 div_ctl = ASPEED_SPI_HCLK_DIV(i); 1301 goto end; 1302 } 1303 1304 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) { 1305 if (hclk_clk / (i * 4) <= max_hz) { 1306 found = true; 1307 chip->clk_freq = hclk_clk / (i * 4); 1308 break; 1309 } 1310 } 1311 1312 if (found) 1313 div_ctl = BIT(13) | ASPEED_SPI_HCLK_DIV(i); 1314 1315 end: 1316 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", 1317 found ? "yes" : "no", hclk_clk, max_hz); 1318 1319 if (found) { 1320 dev_dbg(dev, "h_div: 0x%08x, speed: %d\n", 1321 div_ctl, chip->clk_freq); 1322 } 1323 1324 return div_ctl; 1325 } 1326 1327 static u32 aspeed_get_clk_div_ast2600(struct aspeed_spi_chip *chip, 1328 u32 max_hz) 1329 { 1330 struct device *dev = chip->aspi->dev; 1331 u32 hclk_clk = chip->aspi->clk_freq; 1332 u32 div_ctl = 0; 1333 u32 i, j; 1334 bool found = false; 1335 1336 /* FMC/SPIR10[27:24] */ 1337 for (j = 0; j < 16; j++) { 1338 /* FMC/SPIR10[11:8] */ 1339 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) { 1340 if (j == 0 && i == 1) 1341 continue; 1342 1343 if (hclk_clk / (j * 16 + i) <= max_hz) { 1344 found = true; 1345 break; 1346 } 1347 } 1348 1349 if (found) { 1350 div_ctl = ((j << 24) | ASPEED_SPI_HCLK_DIV(i)); 1351 chip->clk_freq = hclk_clk / (j * 16 + i); 1352 break; 1353 } 1354 } 1355 1356 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", 1357 found ? "yes" : "no", hclk_clk, max_hz); 1358 1359 if (found) { 1360 dev_dbg(dev, "h_div: 0x%08x, speed: %d\n", 1361 div_ctl, chip->clk_freq); 1362 } 1363 1364 return div_ctl; 1365 } 1366 1367 static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip) 1368 { 1369 struct aspeed_spi *aspi = chip->aspi; 1370 const struct aspeed_spi_data *data = aspi->data; 1371 u32 ahb_freq = aspi->clk_freq; 1372 u32 max_freq = chip->clk_freq; 1373 bool exec_calib = false; 1374 u32 best_freq = 0; 1375 u32 ctl_val; 1376 u8 *golden_buf = NULL; 1377 u8 *test_buf = NULL; 1378 int i, rc; 1379 u32 div_ctl; 1380 1381 dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz", 1382 ahb_freq / 1000000); 1383 1384 /* 1385 * use the related low frequency to get check calibration data 1386 * and get golden data. 1387 */ 1388 ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask; 1389 writel(ctl_val, chip->ctl); 1390 1391 test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL); 1392 if (!test_buf) 1393 return -ENOMEM; 1394 1395 golden_buf = test_buf + CALIBRATE_BUF_SIZE; 1396 1397 memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE); 1398 if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) { 1399 dev_info(aspi->dev, "Calibration area too uniform, using low speed"); 1400 goto end_calib; 1401 } 1402 1403 #if defined(VERBOSE_DEBUG) 1404 print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE, 1405 golden_buf, 0x100); 1406 #endif 1407 1408 /* Now we iterate the HCLK dividers until we find our breaking point */ 1409 for (i = 5; i > data->hdiv_max - 1; i--) { 1410 u32 tv, freq; 1411 1412 freq = ahb_freq / i; 1413 if (freq > max_freq) 1414 continue; 1415 1416 /* Set the timing */ 1417 tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i); 1418 writel(tv, chip->ctl); 1419 dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv); 1420 rc = data->calibrate(chip, i, golden_buf, test_buf); 1421 if (rc == 0) 1422 best_freq = freq; 1423 1424 exec_calib = true; 1425 } 1426 1427 end_calib: 1428 if (!exec_calib) { 1429 /* calibration process is not executed */ 1430 dev_warn(aspi->dev, "Force to dts configuration %dkHz.\n", 1431 max_freq / 1000); 1432 div_ctl = data->get_clk_div(chip, max_freq); 1433 } else if (best_freq == 0) { 1434 /* calibration process is executed, but no good frequency */ 1435 dev_warn(aspi->dev, "No good frequency, using dumb slow\n"); 1436 div_ctl = 0; 1437 } else { 1438 dev_dbg(aspi->dev, "Found good read timings at %dMHz.\n", 1439 best_freq / 1000000); 1440 div_ctl = data->get_clk_div(chip, best_freq); 1441 } 1442 1443 /* Record the freq */ 1444 for (i = 0; i < ASPEED_SPI_MAX; i++) { 1445 chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) | 1446 div_ctl; 1447 } 1448 1449 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl); 1450 kfree(test_buf); 1451 return 0; 1452 } 1453 1454 #define TIMING_DELAY_DI BIT(3) 1455 #define TIMING_DELAY_HCYCLE_MAX 5 1456 #define TIMING_DELAY_INPUT_MAX 16 1457 #define TIMING_REG_AST2600(chip) \ 1458 ((chip)->aspi->regs + (chip)->aspi->data->timing + \ 1459 (chip)->cs * 4) 1460 1461 /* 1462 * This function returns the center point of the longest 1463 * continuous "pass" interval within the buffer. The interval 1464 * must contains the highest number of consecutive "pass" 1465 * results and not span across multiple rows. 1466 */ 1467 static u32 aspeed_spi_ast2600_optimized_timing(u32 rows, u32 cols, 1468 u8 buf[rows][cols]) 1469 { 1470 int r = 0, c = 0; 1471 int max = 0; 1472 int i, j; 1473 1474 for (i = 0; i < rows; i++) { 1475 for (j = 0; j < cols;) { 1476 int k = j; 1477 1478 while (k < cols && buf[i][k]) 1479 k++; 1480 1481 if (k - j > max) { 1482 max = k - j; 1483 r = i; 1484 c = j + (k - j) / 2; 1485 } 1486 1487 j = k + 1; 1488 } 1489 } 1490 1491 return max > 4 ? r * cols + c : 0; 1492 } 1493 1494 static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv, 1495 const u8 *golden_buf, u8 *test_buf) 1496 { 1497 struct aspeed_spi *aspi = chip->aspi; 1498 int hcycle; 1499 int delay_ns; 1500 u32 shift = (hdiv - 2) << 3; 1501 u32 mask = ~(0xffu << shift); 1502 u32 fread_timing_val = 0; 1503 u8 calib_res[6][17] = {0}; 1504 u32 calib_point; 1505 1506 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 1507 bool pass = false; 1508 1509 fread_timing_val &= mask; 1510 fread_timing_val |= hcycle << shift; 1511 1512 /* no DI input delay first */ 1513 writel(fread_timing_val, TIMING_REG_AST2600(chip)); 1514 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf); 1515 dev_dbg(aspi->dev, 1516 " * [%08x] %d HCLK delay, DI delay none : %s", 1517 fread_timing_val, hcycle, pass ? "PASS" : "FAIL"); 1518 if (pass) 1519 calib_res[hcycle][0] = 1; 1520 1521 /* Add DI input delays */ 1522 fread_timing_val &= mask; 1523 fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift; 1524 1525 for (delay_ns = 0; delay_ns < TIMING_DELAY_INPUT_MAX; delay_ns++) { 1526 fread_timing_val &= ~(0xfu << (4 + shift)); 1527 fread_timing_val |= delay_ns << (4 + shift); 1528 1529 writel(fread_timing_val, TIMING_REG_AST2600(chip)); 1530 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf); 1531 dev_dbg(aspi->dev, 1532 " * [%08x] %d HCLK delay, DI delay %d.%dns : %s", 1533 fread_timing_val, hcycle, (delay_ns + 1) / 2, 1534 (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL"); 1535 1536 if (pass) 1537 calib_res[hcycle][delay_ns + 1] = 1; 1538 } 1539 } 1540 1541 calib_point = aspeed_spi_ast2600_optimized_timing(6, 17, calib_res); 1542 /* No good setting for this frequency */ 1543 if (calib_point == 0) 1544 return -1; 1545 1546 hcycle = calib_point / 17; 1547 delay_ns = calib_point % 17; 1548 1549 fread_timing_val = (TIMING_DELAY_DI | hcycle | (delay_ns << 4)) << shift; 1550 1551 dev_dbg(aspi->dev, "timing val: %08x, final hcycle: %d, delay_ns: %d\n", 1552 fread_timing_val, hcycle, delay_ns); 1553 1554 writel(fread_timing_val, TIMING_REG_AST2600(chip)); 1555 1556 return 0; 1557 } 1558 1559 /* 1560 * Platform definitions 1561 */ 1562 static const struct aspeed_spi_data ast2400_fmc_data = { 1563 .max_cs = 5, 1564 .hastype = true, 1565 .we0 = 16, 1566 .ctl0 = CE0_CTRL_REG, 1567 .timing = CE0_TIMING_COMPENSATION_REG, 1568 .hclk_mask = 0xfffff0ff, 1569 .hdiv_max = 1, 1570 .min_window_size = 0x800000, 1571 .full_duplex = false, 1572 .calibrate = aspeed_spi_calibrate, 1573 .get_clk_div = aspeed_get_clk_div_ast2400, 1574 .segment_start = aspeed_spi_segment_start, 1575 .segment_end = aspeed_spi_segment_end, 1576 .segment_reg = aspeed_spi_segment_reg, 1577 .adjust_window = aspeed_adjust_window_ast2400, 1578 }; 1579 1580 static const struct aspeed_spi_data ast2400_spi_data = { 1581 .max_cs = 1, 1582 .hastype = false, 1583 .we0 = 0, 1584 .ctl0 = 0x04, 1585 .timing = 0x14, 1586 .hclk_mask = 0xfffff0ff, 1587 .hdiv_max = 1, 1588 .full_duplex = false, 1589 .get_clk_div = aspeed_get_clk_div_ast2400, 1590 .calibrate = aspeed_spi_calibrate, 1591 /* No segment registers */ 1592 }; 1593 1594 static const struct aspeed_spi_data ast2500_fmc_data = { 1595 .max_cs = 3, 1596 .hastype = true, 1597 .we0 = 16, 1598 .ctl0 = CE0_CTRL_REG, 1599 .timing = CE0_TIMING_COMPENSATION_REG, 1600 .hclk_mask = 0xffffd0ff, 1601 .hdiv_max = 1, 1602 .min_window_size = 0x800000, 1603 .full_duplex = false, 1604 .get_clk_div = aspeed_get_clk_div_ast2500, 1605 .calibrate = aspeed_spi_calibrate, 1606 .segment_start = aspeed_spi_segment_start, 1607 .segment_end = aspeed_spi_segment_end, 1608 .segment_reg = aspeed_spi_segment_reg, 1609 .adjust_window = aspeed_adjust_window_ast2500, 1610 }; 1611 1612 static const struct aspeed_spi_data ast2500_spi_data = { 1613 .max_cs = 2, 1614 .hastype = false, 1615 .we0 = 16, 1616 .ctl0 = CE0_CTRL_REG, 1617 .timing = CE0_TIMING_COMPENSATION_REG, 1618 .hclk_mask = 0xffffd0ff, 1619 .hdiv_max = 1, 1620 .min_window_size = 0x800000, 1621 .full_duplex = false, 1622 .get_clk_div = aspeed_get_clk_div_ast2500, 1623 .calibrate = aspeed_spi_calibrate, 1624 .segment_start = aspeed_spi_segment_start, 1625 .segment_end = aspeed_spi_segment_end, 1626 .segment_reg = aspeed_spi_segment_reg, 1627 .adjust_window = aspeed_adjust_window_ast2500, 1628 }; 1629 1630 static const struct aspeed_spi_data ast2600_fmc_data = { 1631 .max_cs = 3, 1632 .hastype = false, 1633 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, 1634 .we0 = 16, 1635 .ctl0 = CE0_CTRL_REG, 1636 .timing = CE0_TIMING_COMPENSATION_REG, 1637 .hclk_mask = 0xf0fff0ff, 1638 .hdiv_max = 2, 1639 .min_window_size = 0x200000, 1640 .full_duplex = false, 1641 .get_clk_div = aspeed_get_clk_div_ast2600, 1642 .calibrate = aspeed_spi_ast2600_calibrate, 1643 .segment_start = aspeed_spi_segment_ast2600_start, 1644 .segment_end = aspeed_spi_segment_ast2600_end, 1645 .segment_reg = aspeed_spi_segment_ast2600_reg, 1646 .adjust_window = aspeed_adjust_window_ast2600, 1647 }; 1648 1649 static const struct aspeed_spi_data ast2600_spi_data = { 1650 .max_cs = 2, 1651 .hastype = false, 1652 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, 1653 .we0 = 16, 1654 .ctl0 = CE0_CTRL_REG, 1655 .timing = CE0_TIMING_COMPENSATION_REG, 1656 .hclk_mask = 0xf0fff0ff, 1657 .hdiv_max = 2, 1658 .min_window_size = 0x200000, 1659 .full_duplex = false, 1660 .get_clk_div = aspeed_get_clk_div_ast2600, 1661 .calibrate = aspeed_spi_ast2600_calibrate, 1662 .segment_start = aspeed_spi_segment_ast2600_start, 1663 .segment_end = aspeed_spi_segment_ast2600_end, 1664 .segment_reg = aspeed_spi_segment_ast2600_reg, 1665 .adjust_window = aspeed_adjust_window_ast2600, 1666 }; 1667 1668 static const struct aspeed_spi_data ast2700_fmc_data = { 1669 .max_cs = 3, 1670 .hastype = false, 1671 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, 1672 .we0 = 16, 1673 .ctl0 = CE0_CTRL_REG, 1674 .timing = CE0_TIMING_COMPENSATION_REG, 1675 .hclk_mask = 0xf0fff0ff, 1676 .hdiv_max = 2, 1677 .min_window_size = 0x10000, 1678 .full_duplex = true, 1679 .get_clk_div = aspeed_get_clk_div_ast2600, 1680 .calibrate = aspeed_spi_ast2600_calibrate, 1681 .segment_start = aspeed_spi_segment_ast2700_start, 1682 .segment_end = aspeed_spi_segment_ast2700_end, 1683 .segment_reg = aspeed_spi_segment_ast2700_reg, 1684 }; 1685 1686 static const struct aspeed_spi_data ast2700_spi_data = { 1687 .max_cs = 2, 1688 .hastype = false, 1689 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, 1690 .we0 = 16, 1691 .ctl0 = CE0_CTRL_REG, 1692 .timing = CE0_TIMING_COMPENSATION_REG, 1693 .hclk_mask = 0xf0fff0ff, 1694 .hdiv_max = 2, 1695 .min_window_size = 0x10000, 1696 .full_duplex = true, 1697 .get_clk_div = aspeed_get_clk_div_ast2600, 1698 .calibrate = aspeed_spi_ast2600_calibrate, 1699 .segment_start = aspeed_spi_segment_ast2700_start, 1700 .segment_end = aspeed_spi_segment_ast2700_end, 1701 .segment_reg = aspeed_spi_segment_ast2700_reg, 1702 }; 1703 1704 static const struct of_device_id aspeed_spi_matches[] = { 1705 { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data }, 1706 { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data }, 1707 { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data }, 1708 { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data }, 1709 { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data }, 1710 { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data }, 1711 { .compatible = "aspeed,ast2700-fmc", .data = &ast2700_fmc_data }, 1712 { .compatible = "aspeed,ast2700-spi", .data = &ast2700_spi_data }, 1713 { } 1714 }; 1715 MODULE_DEVICE_TABLE(of, aspeed_spi_matches); 1716 1717 static struct platform_driver aspeed_spi_driver = { 1718 .probe = aspeed_spi_probe, 1719 .remove = aspeed_spi_remove, 1720 .driver = { 1721 .name = DEVICE_NAME, 1722 .of_match_table = aspeed_spi_matches, 1723 } 1724 }; 1725 1726 module_platform_driver(aspeed_spi_driver); 1727 1728 MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver"); 1729 MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>"); 1730 MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>"); 1731 MODULE_LICENSE("GPL v2"); 1732