1 /* 2 * Marvell Armada-3700 SPI controller driver 3 * 4 * Copyright (C) 2016 Marvell Ltd. 5 * 6 * Author: Wilson Ding <dingwei@marvell.com> 7 * Author: Romain Perier <romain.perier@free-electrons.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/completion.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/spi/spi.h> 27 28 #define DRIVER_NAME "armada_3700_spi" 29 30 #define A3700_SPI_TIMEOUT 10 31 32 /* SPI Register Offest */ 33 #define A3700_SPI_IF_CTRL_REG 0x00 34 #define A3700_SPI_IF_CFG_REG 0x04 35 #define A3700_SPI_DATA_OUT_REG 0x08 36 #define A3700_SPI_DATA_IN_REG 0x0C 37 #define A3700_SPI_IF_INST_REG 0x10 38 #define A3700_SPI_IF_ADDR_REG 0x14 39 #define A3700_SPI_IF_RMODE_REG 0x18 40 #define A3700_SPI_IF_HDR_CNT_REG 0x1C 41 #define A3700_SPI_IF_DIN_CNT_REG 0x20 42 #define A3700_SPI_IF_TIME_REG 0x24 43 #define A3700_SPI_INT_STAT_REG 0x28 44 #define A3700_SPI_INT_MASK_REG 0x2C 45 46 /* A3700_SPI_IF_CTRL_REG */ 47 #define A3700_SPI_EN BIT(16) 48 #define A3700_SPI_ADDR_NOT_CONFIG BIT(12) 49 #define A3700_SPI_WFIFO_OVERFLOW BIT(11) 50 #define A3700_SPI_WFIFO_UNDERFLOW BIT(10) 51 #define A3700_SPI_RFIFO_OVERFLOW BIT(9) 52 #define A3700_SPI_RFIFO_UNDERFLOW BIT(8) 53 #define A3700_SPI_WFIFO_FULL BIT(7) 54 #define A3700_SPI_WFIFO_EMPTY BIT(6) 55 #define A3700_SPI_RFIFO_FULL BIT(5) 56 #define A3700_SPI_RFIFO_EMPTY BIT(4) 57 #define A3700_SPI_WFIFO_RDY BIT(3) 58 #define A3700_SPI_RFIFO_RDY BIT(2) 59 #define A3700_SPI_XFER_RDY BIT(1) 60 #define A3700_SPI_XFER_DONE BIT(0) 61 62 /* A3700_SPI_IF_CFG_REG */ 63 #define A3700_SPI_WFIFO_THRS BIT(28) 64 #define A3700_SPI_RFIFO_THRS BIT(24) 65 #define A3700_SPI_AUTO_CS BIT(20) 66 #define A3700_SPI_DMA_RD_EN BIT(18) 67 #define A3700_SPI_FIFO_MODE BIT(17) 68 #define A3700_SPI_SRST BIT(16) 69 #define A3700_SPI_XFER_START BIT(15) 70 #define A3700_SPI_XFER_STOP BIT(14) 71 #define A3700_SPI_INST_PIN BIT(13) 72 #define A3700_SPI_ADDR_PIN BIT(12) 73 #define A3700_SPI_DATA_PIN1 BIT(11) 74 #define A3700_SPI_DATA_PIN0 BIT(10) 75 #define A3700_SPI_FIFO_FLUSH BIT(9) 76 #define A3700_SPI_RW_EN BIT(8) 77 #define A3700_SPI_CLK_POL BIT(7) 78 #define A3700_SPI_CLK_PHA BIT(6) 79 #define A3700_SPI_BYTE_LEN BIT(5) 80 #define A3700_SPI_CLK_PRESCALE BIT(0) 81 #define A3700_SPI_CLK_PRESCALE_MASK (0x1f) 82 83 #define A3700_SPI_WFIFO_THRS_BIT 28 84 #define A3700_SPI_RFIFO_THRS_BIT 24 85 #define A3700_SPI_FIFO_THRS_MASK 0x7 86 87 #define A3700_SPI_DATA_PIN_MASK 0x3 88 89 /* A3700_SPI_IF_HDR_CNT_REG */ 90 #define A3700_SPI_DUMMY_CNT_BIT 12 91 #define A3700_SPI_DUMMY_CNT_MASK 0x7 92 #define A3700_SPI_RMODE_CNT_BIT 8 93 #define A3700_SPI_RMODE_CNT_MASK 0x3 94 #define A3700_SPI_ADDR_CNT_BIT 4 95 #define A3700_SPI_ADDR_CNT_MASK 0x7 96 #define A3700_SPI_INSTR_CNT_BIT 0 97 #define A3700_SPI_INSTR_CNT_MASK 0x3 98 99 /* A3700_SPI_IF_TIME_REG */ 100 #define A3700_SPI_CLK_CAPT_EDGE BIT(7) 101 102 struct a3700_spi { 103 struct spi_master *master; 104 void __iomem *base; 105 struct clk *clk; 106 unsigned int irq; 107 unsigned int flags; 108 bool xmit_data; 109 const u8 *tx_buf; 110 u8 *rx_buf; 111 size_t buf_len; 112 u8 byte_len; 113 u32 wait_mask; 114 struct completion done; 115 }; 116 117 static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) 118 { 119 return readl(a3700_spi->base + offset); 120 } 121 122 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) 123 { 124 writel(data, a3700_spi->base + offset); 125 } 126 127 static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) 128 { 129 u32 val; 130 131 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 132 val &= ~A3700_SPI_AUTO_CS; 133 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 134 } 135 136 static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) 137 { 138 u32 val; 139 140 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 141 val |= (A3700_SPI_EN << cs); 142 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); 143 } 144 145 static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, 146 unsigned int cs) 147 { 148 u32 val; 149 150 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 151 val &= ~(A3700_SPI_EN << cs); 152 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); 153 } 154 155 static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, 156 unsigned int pin_mode, bool receiving) 157 { 158 u32 val; 159 160 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 161 val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); 162 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); 163 164 switch (pin_mode) { 165 case SPI_NBITS_SINGLE: 166 break; 167 case SPI_NBITS_DUAL: 168 val |= A3700_SPI_DATA_PIN0; 169 break; 170 case SPI_NBITS_QUAD: 171 val |= A3700_SPI_DATA_PIN1; 172 /* RX during address reception uses 4-pin */ 173 if (receiving) 174 val |= A3700_SPI_ADDR_PIN; 175 break; 176 default: 177 dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); 178 return -EINVAL; 179 } 180 181 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 182 183 return 0; 184 } 185 186 static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi) 187 { 188 u32 val; 189 190 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 191 val |= A3700_SPI_FIFO_MODE; 192 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 193 } 194 195 static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, 196 unsigned int mode_bits) 197 { 198 u32 val; 199 200 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 201 202 if (mode_bits & SPI_CPOL) 203 val |= A3700_SPI_CLK_POL; 204 else 205 val &= ~A3700_SPI_CLK_POL; 206 207 if (mode_bits & SPI_CPHA) 208 val |= A3700_SPI_CLK_PHA; 209 else 210 val &= ~A3700_SPI_CLK_PHA; 211 212 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 213 } 214 215 static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, 216 unsigned int speed_hz, u16 mode) 217 { 218 u32 val; 219 u32 prescale; 220 221 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); 222 223 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 224 val = val & ~A3700_SPI_CLK_PRESCALE_MASK; 225 226 val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); 227 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 228 229 if (prescale <= 2) { 230 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); 231 val |= A3700_SPI_CLK_CAPT_EDGE; 232 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); 233 } 234 235 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 236 val &= ~(A3700_SPI_CLK_POL | A3700_SPI_CLK_PHA); 237 238 if (mode & SPI_CPOL) 239 val |= A3700_SPI_CLK_POL; 240 241 if (mode & SPI_CPHA) 242 val |= A3700_SPI_CLK_PHA; 243 244 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 245 } 246 247 static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) 248 { 249 u32 val; 250 251 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 252 if (len == 4) 253 val |= A3700_SPI_BYTE_LEN; 254 else 255 val &= ~A3700_SPI_BYTE_LEN; 256 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 257 258 a3700_spi->byte_len = len; 259 } 260 261 static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) 262 { 263 int timeout = A3700_SPI_TIMEOUT; 264 u32 val; 265 266 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 267 val |= A3700_SPI_FIFO_FLUSH; 268 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 269 270 while (--timeout) { 271 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 272 if (!(val & A3700_SPI_FIFO_FLUSH)) 273 return 0; 274 udelay(1); 275 } 276 277 return -ETIMEDOUT; 278 } 279 280 static int a3700_spi_init(struct a3700_spi *a3700_spi) 281 { 282 struct spi_master *master = a3700_spi->master; 283 u32 val; 284 int i, ret = 0; 285 286 /* Reset SPI unit */ 287 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 288 val |= A3700_SPI_SRST; 289 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 290 291 udelay(A3700_SPI_TIMEOUT); 292 293 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 294 val &= ~A3700_SPI_SRST; 295 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 296 297 /* Disable AUTO_CS and deactivate all chip-selects */ 298 a3700_spi_auto_cs_unset(a3700_spi); 299 for (i = 0; i < master->num_chipselect; i++) 300 a3700_spi_deactivate_cs(a3700_spi, i); 301 302 /* Enable FIFO mode */ 303 a3700_spi_fifo_mode_set(a3700_spi); 304 305 /* Set SPI mode */ 306 a3700_spi_mode_set(a3700_spi, master->mode_bits); 307 308 /* Reset counters */ 309 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); 310 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); 311 312 /* Mask the interrupts and clear cause bits */ 313 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 314 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); 315 316 return ret; 317 } 318 319 static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id) 320 { 321 struct spi_master *master = dev_id; 322 struct a3700_spi *a3700_spi; 323 u32 cause; 324 325 a3700_spi = spi_master_get_devdata(master); 326 327 /* Get interrupt causes */ 328 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); 329 330 if (!cause || !(a3700_spi->wait_mask & cause)) 331 return IRQ_NONE; 332 333 /* mask and acknowledge the SPI interrupts */ 334 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 335 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); 336 337 /* Wake up the transfer */ 338 complete(&a3700_spi->done); 339 340 return IRQ_HANDLED; 341 } 342 343 static bool a3700_spi_wait_completion(struct spi_device *spi) 344 { 345 struct a3700_spi *a3700_spi; 346 unsigned int timeout; 347 unsigned int ctrl_reg; 348 unsigned long timeout_jiffies; 349 350 a3700_spi = spi_master_get_devdata(spi->master); 351 352 /* SPI interrupt is edge-triggered, which means an interrupt will 353 * be generated only when detecting a specific status bit changed 354 * from '0' to '1'. So when we start waiting for a interrupt, we 355 * need to check status bit in control reg first, if it is already 1, 356 * then we do not need to wait for interrupt 357 */ 358 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 359 if (a3700_spi->wait_mask & ctrl_reg) 360 return true; 361 362 reinit_completion(&a3700_spi->done); 363 364 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 365 a3700_spi->wait_mask); 366 367 timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT); 368 timeout = wait_for_completion_timeout(&a3700_spi->done, 369 timeout_jiffies); 370 371 a3700_spi->wait_mask = 0; 372 373 if (timeout) 374 return true; 375 376 /* there might be the case that right after we checked the 377 * status bits in this routine and before start to wait for 378 * interrupt by wait_for_completion_timeout, the interrupt 379 * happens, to avoid missing it we need to double check 380 * status bits in control reg, if it is already 1, then 381 * consider that we have the interrupt successfully and 382 * return true. 383 */ 384 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 385 if (a3700_spi->wait_mask & ctrl_reg) 386 return true; 387 388 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 389 390 /* Timeout was reached */ 391 return false; 392 } 393 394 static bool a3700_spi_transfer_wait(struct spi_device *spi, 395 unsigned int bit_mask) 396 { 397 struct a3700_spi *a3700_spi; 398 399 a3700_spi = spi_master_get_devdata(spi->master); 400 a3700_spi->wait_mask = bit_mask; 401 402 return a3700_spi_wait_completion(spi); 403 } 404 405 static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, 406 unsigned int bytes) 407 { 408 u32 val; 409 410 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 411 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); 412 val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; 413 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); 414 val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; 415 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 416 } 417 418 static void a3700_spi_transfer_setup(struct spi_device *spi, 419 struct spi_transfer *xfer) 420 { 421 struct a3700_spi *a3700_spi; 422 unsigned int byte_len; 423 424 a3700_spi = spi_master_get_devdata(spi->master); 425 426 a3700_spi_clock_set(a3700_spi, xfer->speed_hz, spi->mode); 427 428 byte_len = xfer->bits_per_word >> 3; 429 430 a3700_spi_fifo_thres_set(a3700_spi, byte_len); 431 } 432 433 static void a3700_spi_set_cs(struct spi_device *spi, bool enable) 434 { 435 struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master); 436 437 if (!enable) 438 a3700_spi_activate_cs(a3700_spi, spi->chip_select); 439 else 440 a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); 441 } 442 443 static void a3700_spi_header_set(struct a3700_spi *a3700_spi) 444 { 445 unsigned int addr_cnt; 446 u32 val = 0; 447 448 /* Clear the header registers */ 449 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); 450 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); 451 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); 452 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); 453 454 /* Set header counters */ 455 if (a3700_spi->tx_buf) { 456 /* 457 * when tx data is not 4 bytes aligned, there will be unexpected 458 * bytes out of SPI output register, since it always shifts out 459 * as whole 4 bytes. This might cause incorrect transaction with 460 * some devices. To avoid that, use SPI header count feature to 461 * transfer up to 3 bytes of data first, and then make the rest 462 * of data 4-byte aligned. 463 */ 464 addr_cnt = a3700_spi->buf_len % 4; 465 if (addr_cnt) { 466 val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK) 467 << A3700_SPI_ADDR_CNT_BIT; 468 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); 469 470 /* Update the buffer length to be transferred */ 471 a3700_spi->buf_len -= addr_cnt; 472 473 /* transfer 1~3 bytes through address count */ 474 val = 0; 475 while (addr_cnt--) { 476 val = (val << 8) | a3700_spi->tx_buf[0]; 477 a3700_spi->tx_buf++; 478 } 479 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); 480 } 481 } 482 } 483 484 static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) 485 { 486 u32 val; 487 488 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 489 return (val & A3700_SPI_WFIFO_FULL); 490 } 491 492 static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) 493 { 494 u32 val; 495 496 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { 497 val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf); 498 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); 499 a3700_spi->buf_len -= 4; 500 a3700_spi->tx_buf += 4; 501 } 502 503 return 0; 504 } 505 506 static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) 507 { 508 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 509 510 return (val & A3700_SPI_RFIFO_EMPTY); 511 } 512 513 static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) 514 { 515 u32 val; 516 517 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { 518 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); 519 if (a3700_spi->buf_len >= 4) { 520 u32 data = le32_to_cpu(val); 521 522 memcpy(a3700_spi->rx_buf, &data, 4); 523 524 a3700_spi->buf_len -= 4; 525 a3700_spi->rx_buf += 4; 526 } else { 527 /* 528 * When remain bytes is not larger than 4, we should 529 * avoid memory overwriting and just write the left rx 530 * buffer bytes. 531 */ 532 while (a3700_spi->buf_len) { 533 *a3700_spi->rx_buf = val & 0xff; 534 val >>= 8; 535 536 a3700_spi->buf_len--; 537 a3700_spi->rx_buf++; 538 } 539 } 540 } 541 542 return 0; 543 } 544 545 static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) 546 { 547 int timeout = A3700_SPI_TIMEOUT; 548 u32 val; 549 550 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 551 val |= A3700_SPI_XFER_STOP; 552 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 553 554 while (--timeout) { 555 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 556 if (!(val & A3700_SPI_XFER_START)) 557 break; 558 udelay(1); 559 } 560 561 a3700_spi_fifo_flush(a3700_spi); 562 563 val &= ~A3700_SPI_XFER_STOP; 564 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 565 } 566 567 static int a3700_spi_prepare_message(struct spi_master *master, 568 struct spi_message *message) 569 { 570 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 571 struct spi_device *spi = message->spi; 572 int ret; 573 574 ret = clk_enable(a3700_spi->clk); 575 if (ret) { 576 dev_err(&spi->dev, "failed to enable clk with error %d\n", ret); 577 return ret; 578 } 579 580 /* Flush the FIFOs */ 581 ret = a3700_spi_fifo_flush(a3700_spi); 582 if (ret) 583 return ret; 584 585 a3700_spi_bytelen_set(a3700_spi, 4); 586 587 return 0; 588 } 589 590 static int a3700_spi_transfer_one(struct spi_master *master, 591 struct spi_device *spi, 592 struct spi_transfer *xfer) 593 { 594 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 595 int ret = 0, timeout = A3700_SPI_TIMEOUT; 596 unsigned int nbits = 0; 597 u32 val; 598 599 a3700_spi_transfer_setup(spi, xfer); 600 601 a3700_spi->tx_buf = xfer->tx_buf; 602 a3700_spi->rx_buf = xfer->rx_buf; 603 a3700_spi->buf_len = xfer->len; 604 605 if (xfer->tx_buf) 606 nbits = xfer->tx_nbits; 607 else if (xfer->rx_buf) 608 nbits = xfer->rx_nbits; 609 610 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false); 611 612 /* Flush the FIFOs */ 613 a3700_spi_fifo_flush(a3700_spi); 614 615 /* Transfer first bytes of data when buffer is not 4-byte aligned */ 616 a3700_spi_header_set(a3700_spi); 617 618 if (xfer->rx_buf) { 619 /* Set read data length */ 620 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 621 a3700_spi->buf_len); 622 /* Start READ transfer */ 623 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 624 val &= ~A3700_SPI_RW_EN; 625 val |= A3700_SPI_XFER_START; 626 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 627 } else if (xfer->tx_buf) { 628 /* Start Write transfer */ 629 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 630 val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); 631 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 632 633 /* 634 * If there are data to be written to the SPI device, xmit_data 635 * flag is set true; otherwise the instruction in SPI_INSTR does 636 * not require data to be written to the SPI device, then 637 * xmit_data flag is set false. 638 */ 639 a3700_spi->xmit_data = (a3700_spi->buf_len != 0); 640 } 641 642 while (a3700_spi->buf_len) { 643 if (a3700_spi->tx_buf) { 644 /* Wait wfifo ready */ 645 if (!a3700_spi_transfer_wait(spi, 646 A3700_SPI_WFIFO_RDY)) { 647 dev_err(&spi->dev, 648 "wait wfifo ready timed out\n"); 649 ret = -ETIMEDOUT; 650 goto error; 651 } 652 /* Fill up the wfifo */ 653 ret = a3700_spi_fifo_write(a3700_spi); 654 if (ret) 655 goto error; 656 } else if (a3700_spi->rx_buf) { 657 /* Wait rfifo ready */ 658 if (!a3700_spi_transfer_wait(spi, 659 A3700_SPI_RFIFO_RDY)) { 660 dev_err(&spi->dev, 661 "wait rfifo ready timed out\n"); 662 ret = -ETIMEDOUT; 663 goto error; 664 } 665 /* Drain out the rfifo */ 666 ret = a3700_spi_fifo_read(a3700_spi); 667 if (ret) 668 goto error; 669 } 670 } 671 672 /* 673 * Stop a write transfer in fifo mode: 674 * - wait all the bytes in wfifo to be shifted out 675 * - set XFER_STOP bit 676 * - wait XFER_START bit clear 677 * - clear XFER_STOP bit 678 * Stop a read transfer in fifo mode: 679 * - the hardware is to reset the XFER_START bit 680 * after the number of bytes indicated in DIN_CNT 681 * register 682 * - just wait XFER_START bit clear 683 */ 684 if (a3700_spi->tx_buf) { 685 if (a3700_spi->xmit_data) { 686 /* 687 * If there are data written to the SPI device, wait 688 * until SPI_WFIFO_EMPTY is 1 to wait for all data to 689 * transfer out of write FIFO. 690 */ 691 if (!a3700_spi_transfer_wait(spi, 692 A3700_SPI_WFIFO_EMPTY)) { 693 dev_err(&spi->dev, "wait wfifo empty timed out\n"); 694 return -ETIMEDOUT; 695 } 696 } 697 698 if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) { 699 dev_err(&spi->dev, "wait xfer ready timed out\n"); 700 return -ETIMEDOUT; 701 } 702 703 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 704 val |= A3700_SPI_XFER_STOP; 705 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 706 } 707 708 while (--timeout) { 709 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 710 if (!(val & A3700_SPI_XFER_START)) 711 break; 712 udelay(1); 713 } 714 715 if (timeout == 0) { 716 dev_err(&spi->dev, "wait transfer start clear timed out\n"); 717 ret = -ETIMEDOUT; 718 goto error; 719 } 720 721 val &= ~A3700_SPI_XFER_STOP; 722 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 723 goto out; 724 725 error: 726 a3700_spi_transfer_abort_fifo(a3700_spi); 727 out: 728 spi_finalize_current_transfer(master); 729 730 return ret; 731 } 732 733 static int a3700_spi_unprepare_message(struct spi_master *master, 734 struct spi_message *message) 735 { 736 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 737 738 clk_disable(a3700_spi->clk); 739 740 return 0; 741 } 742 743 static const struct of_device_id a3700_spi_dt_ids[] = { 744 { .compatible = "marvell,armada-3700-spi", .data = NULL }, 745 {}, 746 }; 747 748 MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids); 749 750 static int a3700_spi_probe(struct platform_device *pdev) 751 { 752 struct device *dev = &pdev->dev; 753 struct device_node *of_node = dev->of_node; 754 struct resource *res; 755 struct spi_master *master; 756 struct a3700_spi *spi; 757 u32 num_cs = 0; 758 int irq, ret = 0; 759 760 master = spi_alloc_master(dev, sizeof(*spi)); 761 if (!master) { 762 dev_err(dev, "master allocation failed\n"); 763 ret = -ENOMEM; 764 goto out; 765 } 766 767 if (of_property_read_u32(of_node, "num-cs", &num_cs)) { 768 dev_err(dev, "could not find num-cs\n"); 769 ret = -ENXIO; 770 goto error; 771 } 772 773 master->bus_num = pdev->id; 774 master->dev.of_node = of_node; 775 master->mode_bits = SPI_MODE_3; 776 master->num_chipselect = num_cs; 777 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32); 778 master->prepare_message = a3700_spi_prepare_message; 779 master->transfer_one = a3700_spi_transfer_one; 780 master->unprepare_message = a3700_spi_unprepare_message; 781 master->set_cs = a3700_spi_set_cs; 782 master->flags = SPI_MASTER_HALF_DUPLEX; 783 master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL | 784 SPI_RX_QUAD | SPI_TX_QUAD); 785 786 platform_set_drvdata(pdev, master); 787 788 spi = spi_master_get_devdata(master); 789 memset(spi, 0, sizeof(struct a3700_spi)); 790 791 spi->master = master; 792 793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 794 spi->base = devm_ioremap_resource(dev, res); 795 if (IS_ERR(spi->base)) { 796 ret = PTR_ERR(spi->base); 797 goto error; 798 } 799 800 irq = platform_get_irq(pdev, 0); 801 if (irq < 0) { 802 dev_err(dev, "could not get irq: %d\n", irq); 803 ret = -ENXIO; 804 goto error; 805 } 806 spi->irq = irq; 807 808 init_completion(&spi->done); 809 810 spi->clk = devm_clk_get(dev, NULL); 811 if (IS_ERR(spi->clk)) { 812 dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk)); 813 goto error; 814 } 815 816 ret = clk_prepare(spi->clk); 817 if (ret) { 818 dev_err(dev, "could not prepare clk: %d\n", ret); 819 goto error; 820 } 821 822 ret = a3700_spi_init(spi); 823 if (ret) 824 goto error_clk; 825 826 ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0, 827 dev_name(dev), master); 828 if (ret) { 829 dev_err(dev, "could not request IRQ: %d\n", ret); 830 goto error_clk; 831 } 832 833 ret = devm_spi_register_master(dev, master); 834 if (ret) { 835 dev_err(dev, "Failed to register master\n"); 836 goto error_clk; 837 } 838 839 return 0; 840 841 error_clk: 842 clk_disable_unprepare(spi->clk); 843 error: 844 spi_master_put(master); 845 out: 846 return ret; 847 } 848 849 static int a3700_spi_remove(struct platform_device *pdev) 850 { 851 struct spi_master *master = platform_get_drvdata(pdev); 852 struct a3700_spi *spi = spi_master_get_devdata(master); 853 854 clk_unprepare(spi->clk); 855 856 return 0; 857 } 858 859 static struct platform_driver a3700_spi_driver = { 860 .driver = { 861 .name = DRIVER_NAME, 862 .of_match_table = of_match_ptr(a3700_spi_dt_ids), 863 }, 864 .probe = a3700_spi_probe, 865 .remove = a3700_spi_remove, 866 }; 867 868 module_platform_driver(a3700_spi_driver); 869 870 MODULE_DESCRIPTION("Armada-3700 SPI driver"); 871 MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>"); 872 MODULE_LICENSE("GPL"); 873 MODULE_ALIAS("platform:" DRIVER_NAME); 874