1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Apple SoC SPI device driver 4 // 5 // Copyright The Asahi Linux Contributors 6 // 7 // Based on spi-sifive.c, Copyright 2018 SiFive, Inc. 8 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/spi/spi.h> 19 20 #define APPLE_SPI_CTRL 0x000 21 #define APPLE_SPI_CTRL_RUN BIT(0) 22 #define APPLE_SPI_CTRL_TX_RESET BIT(2) 23 #define APPLE_SPI_CTRL_RX_RESET BIT(3) 24 25 #define APPLE_SPI_CFG 0x004 26 #define APPLE_SPI_CFG_CPHA BIT(1) 27 #define APPLE_SPI_CFG_CPOL BIT(2) 28 #define APPLE_SPI_CFG_MODE GENMASK(6, 5) 29 #define APPLE_SPI_CFG_MODE_POLLED 0 30 #define APPLE_SPI_CFG_MODE_IRQ 1 31 #define APPLE_SPI_CFG_MODE_DMA 2 32 #define APPLE_SPI_CFG_IE_RXCOMPLETE BIT(7) 33 #define APPLE_SPI_CFG_IE_TXRXTHRESH BIT(8) 34 #define APPLE_SPI_CFG_LSB_FIRST BIT(13) 35 #define APPLE_SPI_CFG_WORD_SIZE GENMASK(16, 15) 36 #define APPLE_SPI_CFG_WORD_SIZE_8B 0 37 #define APPLE_SPI_CFG_WORD_SIZE_16B 1 38 #define APPLE_SPI_CFG_WORD_SIZE_32B 2 39 #define APPLE_SPI_CFG_FIFO_THRESH GENMASK(18, 17) 40 #define APPLE_SPI_CFG_FIFO_THRESH_8B 0 41 #define APPLE_SPI_CFG_FIFO_THRESH_4B 1 42 #define APPLE_SPI_CFG_FIFO_THRESH_1B 2 43 #define APPLE_SPI_CFG_IE_TXCOMPLETE BIT(21) 44 45 #define APPLE_SPI_STATUS 0x008 46 #define APPLE_SPI_STATUS_RXCOMPLETE BIT(0) 47 #define APPLE_SPI_STATUS_TXRXTHRESH BIT(1) 48 #define APPLE_SPI_STATUS_TXCOMPLETE BIT(2) 49 50 #define APPLE_SPI_PIN 0x00c 51 #define APPLE_SPI_PIN_KEEP_MOSI BIT(0) 52 #define APPLE_SPI_PIN_CS BIT(1) 53 54 #define APPLE_SPI_TXDATA 0x010 55 #define APPLE_SPI_RXDATA 0x020 56 #define APPLE_SPI_CLKDIV 0x030 57 #define APPLE_SPI_CLKDIV_MAX 0x7ff 58 #define APPLE_SPI_RXCNT 0x034 59 #define APPLE_SPI_WORD_DELAY 0x038 60 #define APPLE_SPI_TXCNT 0x04c 61 62 #define APPLE_SPI_FIFOSTAT 0x10c 63 #define APPLE_SPI_FIFOSTAT_TXFULL BIT(4) 64 #define APPLE_SPI_FIFOSTAT_LEVEL_TX GENMASK(15, 8) 65 #define APPLE_SPI_FIFOSTAT_RXEMPTY BIT(20) 66 #define APPLE_SPI_FIFOSTAT_LEVEL_RX GENMASK(31, 24) 67 68 #define APPLE_SPI_IE_XFER 0x130 69 #define APPLE_SPI_IF_XFER 0x134 70 #define APPLE_SPI_XFER_RXCOMPLETE BIT(0) 71 #define APPLE_SPI_XFER_TXCOMPLETE BIT(1) 72 73 #define APPLE_SPI_IE_FIFO 0x138 74 #define APPLE_SPI_IF_FIFO 0x13c 75 #define APPLE_SPI_FIFO_RXTHRESH BIT(4) 76 #define APPLE_SPI_FIFO_TXTHRESH BIT(5) 77 #define APPLE_SPI_FIFO_RXFULL BIT(8) 78 #define APPLE_SPI_FIFO_TXEMPTY BIT(9) 79 #define APPLE_SPI_FIFO_RXUNDERRUN BIT(16) 80 #define APPLE_SPI_FIFO_TXOVERFLOW BIT(17) 81 82 #define APPLE_SPI_SHIFTCFG 0x150 83 #define APPLE_SPI_SHIFTCFG_CLK_ENABLE BIT(0) 84 #define APPLE_SPI_SHIFTCFG_CS_ENABLE BIT(1) 85 #define APPLE_SPI_SHIFTCFG_AND_CLK_DATA BIT(8) 86 #define APPLE_SPI_SHIFTCFG_CS_AS_DATA BIT(9) 87 #define APPLE_SPI_SHIFTCFG_TX_ENABLE BIT(10) 88 #define APPLE_SPI_SHIFTCFG_RX_ENABLE BIT(11) 89 #define APPLE_SPI_SHIFTCFG_BITS GENMASK(21, 16) 90 #define APPLE_SPI_SHIFTCFG_OVERRIDE_CS BIT(24) 91 92 #define APPLE_SPI_PINCFG 0x154 93 #define APPLE_SPI_PINCFG_KEEP_CLK BIT(0) 94 #define APPLE_SPI_PINCFG_KEEP_CS BIT(1) 95 #define APPLE_SPI_PINCFG_KEEP_MOSI BIT(2) 96 #define APPLE_SPI_PINCFG_CLK_IDLE_VAL BIT(8) 97 #define APPLE_SPI_PINCFG_CS_IDLE_VAL BIT(9) 98 #define APPLE_SPI_PINCFG_MOSI_IDLE_VAL BIT(10) 99 100 #define APPLE_SPI_DELAY_PRE 0x160 101 #define APPLE_SPI_DELAY_POST 0x168 102 #define APPLE_SPI_DELAY_ENABLE BIT(0) 103 #define APPLE_SPI_DELAY_NO_INTERBYTE BIT(1) 104 #define APPLE_SPI_DELAY_SET_SCK BIT(4) 105 #define APPLE_SPI_DELAY_SET_MOSI BIT(6) 106 #define APPLE_SPI_DELAY_SCK_VAL BIT(8) 107 #define APPLE_SPI_DELAY_MOSI_VAL BIT(12) 108 109 #define APPLE_SPI_FIFO_DEPTH 16 110 111 /* 112 * The slowest refclock available is 24MHz, the highest divider is 0x7ff, 113 * the largest word size is 32 bits, the FIFO depth is 16, the maximum 114 * intra-word delay is 0xffff refclocks. So the maximum time a transfer 115 * cycle can take is: 116 * 117 * (0x7ff * 32 + 0xffff) * 16 / 24e6 Hz ~= 87ms 118 * 119 * Double it and round it up to 200ms for good measure. 120 */ 121 #define APPLE_SPI_TIMEOUT_MS 200 122 123 struct apple_spi { 124 void __iomem *regs; /* MMIO register address */ 125 struct clk *clk; /* bus clock */ 126 struct completion done; /* wake-up from interrupt */ 127 }; 128 129 static inline void reg_write(struct apple_spi *spi, int offset, u32 value) 130 { 131 writel_relaxed(value, spi->regs + offset); 132 } 133 134 static inline u32 reg_read(struct apple_spi *spi, int offset) 135 { 136 return readl_relaxed(spi->regs + offset); 137 } 138 139 static inline void reg_mask(struct apple_spi *spi, int offset, u32 clear, u32 set) 140 { 141 u32 val = reg_read(spi, offset); 142 143 val &= ~clear; 144 val |= set; 145 reg_write(spi, offset, val); 146 } 147 148 static void apple_spi_init(struct apple_spi *spi) 149 { 150 /* Set CS high (inactive) and disable override and auto-CS */ 151 reg_write(spi, APPLE_SPI_PIN, APPLE_SPI_PIN_CS); 152 reg_mask(spi, APPLE_SPI_SHIFTCFG, APPLE_SPI_SHIFTCFG_OVERRIDE_CS, 0); 153 reg_mask(spi, APPLE_SPI_PINCFG, APPLE_SPI_PINCFG_CS_IDLE_VAL, APPLE_SPI_PINCFG_KEEP_CS); 154 155 /* Reset FIFOs */ 156 reg_write(spi, APPLE_SPI_CTRL, APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET); 157 158 /* Configure defaults */ 159 reg_write(spi, APPLE_SPI_CFG, 160 FIELD_PREP(APPLE_SPI_CFG_FIFO_THRESH, APPLE_SPI_CFG_FIFO_THRESH_8B) | 161 FIELD_PREP(APPLE_SPI_CFG_MODE, APPLE_SPI_CFG_MODE_IRQ) | 162 FIELD_PREP(APPLE_SPI_CFG_WORD_SIZE, APPLE_SPI_CFG_WORD_SIZE_8B)); 163 164 /* Disable IRQs */ 165 reg_write(spi, APPLE_SPI_IE_FIFO, 0); 166 reg_write(spi, APPLE_SPI_IE_XFER, 0); 167 168 /* Disable delays */ 169 reg_write(spi, APPLE_SPI_DELAY_PRE, 0); 170 reg_write(spi, APPLE_SPI_DELAY_POST, 0); 171 } 172 173 static int apple_spi_prepare_message(struct spi_controller *ctlr, struct spi_message *msg) 174 { 175 struct apple_spi *spi = spi_controller_get_devdata(ctlr); 176 struct spi_device *device = msg->spi; 177 178 u32 cfg = ((device->mode & SPI_CPHA ? APPLE_SPI_CFG_CPHA : 0) | 179 (device->mode & SPI_CPOL ? APPLE_SPI_CFG_CPOL : 0) | 180 (device->mode & SPI_LSB_FIRST ? APPLE_SPI_CFG_LSB_FIRST : 0)); 181 182 /* Update core config */ 183 reg_mask(spi, APPLE_SPI_CFG, 184 APPLE_SPI_CFG_CPHA | APPLE_SPI_CFG_CPOL | APPLE_SPI_CFG_LSB_FIRST, cfg); 185 186 return 0; 187 } 188 189 static void apple_spi_set_cs(struct spi_device *device, bool is_high) 190 { 191 struct apple_spi *spi = spi_controller_get_devdata(device->controller); 192 193 reg_mask(spi, APPLE_SPI_PIN, APPLE_SPI_PIN_CS, is_high ? APPLE_SPI_PIN_CS : 0); 194 } 195 196 static bool apple_spi_prep_transfer(struct apple_spi *spi, struct spi_transfer *t) 197 { 198 u32 cr, fifo_threshold; 199 200 /* Calculate and program the clock rate */ 201 cr = DIV_ROUND_UP(clk_get_rate(spi->clk), t->speed_hz); 202 reg_write(spi, APPLE_SPI_CLKDIV, min_t(u32, cr, APPLE_SPI_CLKDIV_MAX)); 203 204 /* Update bits per word */ 205 reg_mask(spi, APPLE_SPI_SHIFTCFG, APPLE_SPI_SHIFTCFG_BITS, 206 FIELD_PREP(APPLE_SPI_SHIFTCFG_BITS, t->bits_per_word)); 207 208 /* We will want to poll if the time we need to wait is 209 * less than the context switching time. 210 * Let's call that threshold 5us. The operation will take: 211 * bits_per_word * fifo_threshold / hz <= 5 * 10^-6 212 * 200000 * bits_per_word * fifo_threshold <= hz 213 */ 214 fifo_threshold = APPLE_SPI_FIFO_DEPTH / 2; 215 return (200000 * t->bits_per_word * fifo_threshold) <= t->speed_hz; 216 } 217 218 static irqreturn_t apple_spi_irq(int irq, void *dev_id) 219 { 220 struct apple_spi *spi = dev_id; 221 u32 fifo = reg_read(spi, APPLE_SPI_IF_FIFO) & reg_read(spi, APPLE_SPI_IE_FIFO); 222 u32 xfer = reg_read(spi, APPLE_SPI_IF_XFER) & reg_read(spi, APPLE_SPI_IE_XFER); 223 224 if (fifo || xfer) { 225 /* Disable interrupts until next transfer */ 226 reg_write(spi, APPLE_SPI_IE_XFER, 0); 227 reg_write(spi, APPLE_SPI_IE_FIFO, 0); 228 complete(&spi->done); 229 return IRQ_HANDLED; 230 } 231 232 return IRQ_NONE; 233 } 234 235 static int apple_spi_wait(struct apple_spi *spi, u32 fifo_bit, u32 xfer_bit, int poll) 236 { 237 int ret = 0; 238 239 if (poll) { 240 u32 fifo, xfer; 241 unsigned long timeout = jiffies + APPLE_SPI_TIMEOUT_MS * HZ / 1000; 242 243 do { 244 fifo = reg_read(spi, APPLE_SPI_IF_FIFO); 245 xfer = reg_read(spi, APPLE_SPI_IF_XFER); 246 if (time_after(jiffies, timeout)) { 247 ret = -ETIMEDOUT; 248 break; 249 } 250 } while (!((fifo & fifo_bit) || (xfer & xfer_bit))); 251 } else { 252 reinit_completion(&spi->done); 253 reg_write(spi, APPLE_SPI_IE_XFER, xfer_bit); 254 reg_write(spi, APPLE_SPI_IE_FIFO, fifo_bit); 255 256 if (!wait_for_completion_timeout(&spi->done, 257 msecs_to_jiffies(APPLE_SPI_TIMEOUT_MS))) 258 ret = -ETIMEDOUT; 259 260 reg_write(spi, APPLE_SPI_IE_XFER, 0); 261 reg_write(spi, APPLE_SPI_IE_FIFO, 0); 262 } 263 264 return ret; 265 } 266 267 static void apple_spi_tx(struct apple_spi *spi, const void **tx_ptr, u32 *left, 268 unsigned int bytes_per_word) 269 { 270 u32 inuse, words, wrote; 271 272 if (!*tx_ptr) 273 return; 274 275 inuse = FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_TX, reg_read(spi, APPLE_SPI_FIFOSTAT)); 276 words = wrote = min_t(u32, *left, APPLE_SPI_FIFO_DEPTH - inuse); 277 278 if (!words) 279 return; 280 281 *left -= words; 282 283 switch (bytes_per_word) { 284 case 1: { 285 const u8 *p = *tx_ptr; 286 287 while (words--) 288 reg_write(spi, APPLE_SPI_TXDATA, *p++); 289 break; 290 } 291 case 2: { 292 const u16 *p = *tx_ptr; 293 294 while (words--) 295 reg_write(spi, APPLE_SPI_TXDATA, *p++); 296 break; 297 } 298 case 4: { 299 const u32 *p = *tx_ptr; 300 301 while (words--) 302 reg_write(spi, APPLE_SPI_TXDATA, *p++); 303 break; 304 } 305 default: 306 WARN_ON(1); 307 } 308 309 *tx_ptr = ((u8 *)*tx_ptr) + bytes_per_word * wrote; 310 } 311 312 static void apple_spi_rx(struct apple_spi *spi, void **rx_ptr, u32 *left, 313 unsigned int bytes_per_word) 314 { 315 u32 words, read; 316 317 if (!*rx_ptr) 318 return; 319 320 words = read = FIELD_GET(APPLE_SPI_FIFOSTAT_LEVEL_RX, reg_read(spi, APPLE_SPI_FIFOSTAT)); 321 WARN_ON(words > *left); 322 323 if (!words) 324 return; 325 326 *left -= min_t(u32, *left, words); 327 328 switch (bytes_per_word) { 329 case 1: { 330 u8 *p = *rx_ptr; 331 332 while (words--) 333 *p++ = reg_read(spi, APPLE_SPI_RXDATA); 334 break; 335 } 336 case 2: { 337 u16 *p = *rx_ptr; 338 339 while (words--) 340 *p++ = reg_read(spi, APPLE_SPI_RXDATA); 341 break; 342 } 343 case 4: { 344 u32 *p = *rx_ptr; 345 346 while (words--) 347 *p++ = reg_read(spi, APPLE_SPI_RXDATA); 348 break; 349 } 350 default: 351 WARN_ON(1); 352 } 353 354 *rx_ptr = ((u8 *)*rx_ptr) + bytes_per_word * read; 355 } 356 357 static int apple_spi_transfer_one(struct spi_controller *ctlr, struct spi_device *device, 358 struct spi_transfer *t) 359 { 360 struct apple_spi *spi = spi_controller_get_devdata(ctlr); 361 bool poll = apple_spi_prep_transfer(spi, t); 362 const void *tx_ptr = t->tx_buf; 363 void *rx_ptr = t->rx_buf; 364 unsigned int bytes_per_word; 365 u32 words, remaining_tx, remaining_rx; 366 u32 xfer_flags = 0; 367 u32 fifo_flags; 368 int retries = 100; 369 int ret = 0; 370 371 if (t->bits_per_word > 16) 372 bytes_per_word = 4; 373 else if (t->bits_per_word > 8) 374 bytes_per_word = 2; 375 else 376 bytes_per_word = 1; 377 378 words = t->len / bytes_per_word; 379 remaining_tx = tx_ptr ? words : 0; 380 remaining_rx = rx_ptr ? words : 0; 381 382 /* Reset FIFOs */ 383 reg_write(spi, APPLE_SPI_CTRL, APPLE_SPI_CTRL_RX_RESET | APPLE_SPI_CTRL_TX_RESET); 384 385 /* Clear IRQ flags */ 386 reg_write(spi, APPLE_SPI_IF_XFER, ~0); 387 reg_write(spi, APPLE_SPI_IF_FIFO, ~0); 388 389 /* Determine transfer completion flags we wait for */ 390 if (tx_ptr) 391 xfer_flags |= APPLE_SPI_XFER_TXCOMPLETE; 392 if (rx_ptr) 393 xfer_flags |= APPLE_SPI_XFER_RXCOMPLETE; 394 395 /* Set transfer length */ 396 reg_write(spi, APPLE_SPI_TXCNT, remaining_tx); 397 reg_write(spi, APPLE_SPI_RXCNT, remaining_rx); 398 399 /* Prime transmit FIFO */ 400 apple_spi_tx(spi, &tx_ptr, &remaining_tx, bytes_per_word); 401 402 /* Start transfer */ 403 reg_write(spi, APPLE_SPI_CTRL, APPLE_SPI_CTRL_RUN); 404 405 /* TX again since a few words get popped off immediately */ 406 apple_spi_tx(spi, &tx_ptr, &remaining_tx, bytes_per_word); 407 408 while (xfer_flags) { 409 fifo_flags = 0; 410 411 if (remaining_tx) 412 fifo_flags |= APPLE_SPI_FIFO_TXTHRESH; 413 if (remaining_rx) 414 fifo_flags |= APPLE_SPI_FIFO_RXTHRESH; 415 416 /* Wait for anything to happen */ 417 ret = apple_spi_wait(spi, fifo_flags, xfer_flags, poll); 418 if (ret) { 419 dev_err(&ctlr->dev, "transfer timed out (remaining %d tx, %d rx)\n", 420 remaining_tx, remaining_rx); 421 goto err; 422 } 423 424 /* Stop waiting on transfer halves once they complete */ 425 xfer_flags &= ~reg_read(spi, APPLE_SPI_IF_XFER); 426 427 /* Transmit and receive everything we can */ 428 apple_spi_tx(spi, &tx_ptr, &remaining_tx, bytes_per_word); 429 apple_spi_rx(spi, &rx_ptr, &remaining_rx, bytes_per_word); 430 } 431 432 /* 433 * Sometimes the transfer completes before the last word is in the RX FIFO. 434 * Normally one retry is all it takes to get the last word out. 435 */ 436 while (remaining_rx && retries--) 437 apple_spi_rx(spi, &rx_ptr, &remaining_rx, bytes_per_word); 438 439 if (remaining_tx) 440 dev_err(&ctlr->dev, "transfer completed with %d words left to transmit\n", 441 remaining_tx); 442 if (remaining_rx) 443 dev_err(&ctlr->dev, "transfer completed with %d words left to receive\n", 444 remaining_rx); 445 446 err: 447 fifo_flags = reg_read(spi, APPLE_SPI_IF_FIFO); 448 WARN_ON(fifo_flags & APPLE_SPI_FIFO_TXOVERFLOW); 449 WARN_ON(fifo_flags & APPLE_SPI_FIFO_RXUNDERRUN); 450 451 /* Stop transfer */ 452 reg_write(spi, APPLE_SPI_CTRL, 0); 453 454 return ret; 455 } 456 457 static int apple_spi_probe(struct platform_device *pdev) 458 { 459 struct apple_spi *spi; 460 int ret, irq; 461 struct spi_controller *ctlr; 462 463 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(struct apple_spi)); 464 if (!ctlr) 465 return -ENOMEM; 466 467 spi = spi_controller_get_devdata(ctlr); 468 init_completion(&spi->done); 469 470 spi->regs = devm_platform_ioremap_resource(pdev, 0); 471 if (IS_ERR(spi->regs)) 472 return PTR_ERR(spi->regs); 473 474 spi->clk = devm_clk_get_enabled(&pdev->dev, NULL); 475 if (IS_ERR(spi->clk)) 476 return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk), 477 "Unable to find or enable bus clock\n"); 478 479 irq = platform_get_irq(pdev, 0); 480 if (irq < 0) 481 return irq; 482 483 ret = devm_request_irq(&pdev->dev, irq, apple_spi_irq, 0, 484 dev_name(&pdev->dev), spi); 485 if (ret) 486 return dev_err_probe(&pdev->dev, ret, "Unable to bind to interrupt\n"); 487 488 ctlr->dev.of_node = pdev->dev.of_node; 489 ctlr->bus_num = pdev->id; 490 ctlr->num_chipselect = 1; 491 ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST; 492 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 493 ctlr->prepare_message = apple_spi_prepare_message; 494 ctlr->set_cs = apple_spi_set_cs; 495 ctlr->transfer_one = apple_spi_transfer_one; 496 ctlr->auto_runtime_pm = true; 497 498 pm_runtime_set_active(&pdev->dev); 499 ret = devm_pm_runtime_enable(&pdev->dev); 500 if (ret < 0) 501 return ret; 502 503 apple_spi_init(spi); 504 505 ret = devm_spi_register_controller(&pdev->dev, ctlr); 506 if (ret < 0) 507 return dev_err_probe(&pdev->dev, ret, "devm_spi_register_controller failed\n"); 508 509 return 0; 510 } 511 512 static const struct of_device_id apple_spi_of_match[] = { 513 { .compatible = "apple,spi", }, 514 {} 515 }; 516 MODULE_DEVICE_TABLE(of, apple_spi_of_match); 517 518 static struct platform_driver apple_spi_driver = { 519 .probe = apple_spi_probe, 520 .driver = { 521 .name = "apple-spi", 522 .of_match_table = apple_spi_of_match, 523 }, 524 }; 525 module_platform_driver(apple_spi_driver); 526 527 MODULE_AUTHOR("Hector Martin <marcan@marcan.st>"); 528 MODULE_DESCRIPTION("Apple SoC SPI driver"); 529 MODULE_LICENSE("GPL"); 530