1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 // 3 // AMD SPI controller driver 4 // 5 // Copyright (c) 2020, Advanced Micro Devices, Inc. 6 // 7 // Author: Sanjay R Mehta <sanju.mehta@amd.com> 8 9 #include <linux/acpi.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/init.h> 13 #include <linux/io-64-nonatomic-lo-hi.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/spi/spi.h> 18 #include <linux/spi/spi-mem.h> 19 20 #include "spi-amd.h" 21 22 #define AMD_SPI_CTRL0_REG 0x00 23 #define AMD_SPI_EXEC_CMD BIT(16) 24 #define AMD_SPI_FIFO_CLEAR BIT(20) 25 #define AMD_SPI_BUSY BIT(31) 26 27 #define AMD_SPI_OPCODE_REG 0x45 28 #define AMD_SPI_CMD_TRIGGER_REG 0x47 29 #define AMD_SPI_TRIGGER_CMD BIT(7) 30 31 #define AMD_SPI_OPCODE_MASK 0xFF 32 33 #define AMD_SPI_ALT_CS_REG 0x1D 34 #define AMD_SPI_ALT_CS_MASK 0x3 35 36 #define AMD_SPI_FIFO_BASE 0x80 37 #define AMD_SPI_TX_COUNT_REG 0x48 38 #define AMD_SPI_RX_COUNT_REG 0x4B 39 #define AMD_SPI_STATUS_REG 0x4C 40 #define AMD_SPI_ADDR32CTRL_REG 0x50 41 42 #define AMD_SPI_FIFO_SIZE 70 43 #define AMD_SPI_MEM_SIZE 200 44 #define AMD_SPI_MAX_DATA 64 45 #define AMD_SPI_HID2_DMA_SIZE 4096 46 47 #define AMD_SPI_ENA_REG 0x20 48 #define AMD_SPI_ALT_SPD_SHIFT 20 49 #define AMD_SPI_ALT_SPD_MASK GENMASK(23, AMD_SPI_ALT_SPD_SHIFT) 50 #define AMD_SPI_SPI100_SHIFT 0 51 #define AMD_SPI_SPI100_MASK GENMASK(AMD_SPI_SPI100_SHIFT, AMD_SPI_SPI100_SHIFT) 52 #define AMD_SPI_SPEED_REG 0x6C 53 #define AMD_SPI_SPD7_SHIFT 8 54 #define AMD_SPI_SPD7_MASK GENMASK(13, AMD_SPI_SPD7_SHIFT) 55 56 #define AMD_SPI_HID2_INPUT_RING_BUF0 0X100 57 #define AMD_SPI_HID2_OUTPUT_BUF0 0x140 58 #define AMD_SPI_HID2_CNTRL 0x150 59 #define AMD_SPI_HID2_INT_STATUS 0x154 60 #define AMD_SPI_HID2_CMD_START 0x156 61 #define AMD_SPI_HID2_INT_MASK 0x158 62 #define AMD_SPI_HID2_WRITE_CNTRL0 0x160 63 #define AMD_SPI_HID2_WRITE_CNTRL1 0x164 64 #define AMD_SPI_HID2_READ_CNTRL0 0x170 65 #define AMD_SPI_HID2_READ_CNTRL1 0x174 66 #define AMD_SPI_HID2_READ_CNTRL2 0x180 67 68 #define AMD_SPI_MAX_HZ 100000000 69 #define AMD_SPI_MIN_HZ 800000 70 71 #define AMD_SPI_IO_SLEEP_US 20 72 #define AMD_SPI_IO_TIMEOUT_US 2000000 73 74 /* SPI read command opcodes */ 75 #define AMD_SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ 76 #define AMD_SPI_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */ 77 #define AMD_SPI_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */ 78 #define AMD_SPI_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */ 79 #define AMD_SPI_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */ 80 #define AMD_SPI_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */ 81 82 /* SPI read command opcodes - 4B address */ 83 #define AMD_SPI_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */ 84 #define AMD_SPI_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */ 85 #define AMD_SPI_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */ 86 #define AMD_SPI_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */ 87 #define AMD_SPI_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */ 88 89 /* SPINAND write command opcodes */ 90 #define AMD_SPI_OP_PP 0x02 /* Page program */ 91 #define AMD_SPI_OP_PP_RANDOM 0x84 /* Page program */ 92 93 enum amd_spi_speed { 94 F_66_66MHz, 95 F_33_33MHz, 96 F_22_22MHz, 97 F_16_66MHz, 98 F_100MHz, 99 F_800KHz, 100 SPI_SPD7 = 0x7, 101 F_50MHz = 0x4, 102 F_4MHz = 0x32, 103 F_3_17MHz = 0x3F 104 }; 105 106 /** 107 * struct amd_spi_freq - Matches device speed with values to write in regs 108 * @speed_hz: Device frequency 109 * @enable_val: Value to be written to "enable register" 110 * @spd7_val: Some frequencies requires to have a value written at SPISPEED register 111 */ 112 struct amd_spi_freq { 113 u32 speed_hz; 114 u32 enable_val; 115 u32 spd7_val; 116 }; 117 118 static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx) 119 { 120 return readb((u8 __iomem *)amd_spi->io_remap_addr + idx); 121 } 122 123 static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val) 124 { 125 writeb(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); 126 } 127 128 static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear) 129 { 130 u8 tmp = amd_spi_readreg8(amd_spi, idx); 131 132 tmp = (tmp & ~clear) | set; 133 amd_spi_writereg8(amd_spi, idx, tmp); 134 } 135 136 static inline u16 amd_spi_readreg16(struct amd_spi *amd_spi, int idx) 137 { 138 return readw((u8 __iomem *)amd_spi->io_remap_addr + idx); 139 } 140 141 static inline void amd_spi_writereg16(struct amd_spi *amd_spi, int idx, u16 val) 142 { 143 writew(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); 144 } 145 146 static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx) 147 { 148 return readl((u8 __iomem *)amd_spi->io_remap_addr + idx); 149 } 150 151 static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val) 152 { 153 writel(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); 154 } 155 156 static inline u64 amd_spi_readreg64(struct amd_spi *amd_spi, int idx) 157 { 158 return readq((u8 __iomem *)amd_spi->io_remap_addr + idx); 159 } 160 161 static inline void amd_spi_writereg64(struct amd_spi *amd_spi, int idx, u64 val) 162 { 163 writeq(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); 164 } 165 166 static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear) 167 { 168 u32 tmp = amd_spi_readreg32(amd_spi, idx); 169 170 tmp = (tmp & ~clear) | set; 171 amd_spi_writereg32(amd_spi, idx, tmp); 172 } 173 174 static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs) 175 { 176 amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK); 177 } 178 179 static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select) 180 { 181 amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK); 182 } 183 184 static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi) 185 { 186 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR); 187 } 188 189 static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode) 190 { 191 switch (amd_spi->version) { 192 case AMD_SPI_V1: 193 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode, 194 AMD_SPI_OPCODE_MASK); 195 return 0; 196 case AMD_SPI_V2: 197 case AMD_HID2_SPI: 198 amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode); 199 return 0; 200 default: 201 return -ENODEV; 202 } 203 } 204 205 static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count) 206 { 207 amd_spi_writereg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count); 208 } 209 210 static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count) 211 { 212 amd_spi_writereg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count); 213 } 214 215 static int amd_spi_busy_wait(struct amd_spi *amd_spi) 216 { 217 u32 val; 218 int reg; 219 220 switch (amd_spi->version) { 221 case AMD_SPI_V1: 222 reg = AMD_SPI_CTRL0_REG; 223 break; 224 case AMD_SPI_V2: 225 case AMD_HID2_SPI: 226 reg = AMD_SPI_STATUS_REG; 227 break; 228 default: 229 return -ENODEV; 230 } 231 232 return readl_poll_timeout(amd_spi->io_remap_addr + reg, val, 233 !(val & AMD_SPI_BUSY), 20, 2000000); 234 } 235 236 static int amd_spi_execute_opcode(struct amd_spi *amd_spi) 237 { 238 int ret; 239 240 ret = amd_spi_busy_wait(amd_spi); 241 if (ret) 242 return ret; 243 244 switch (amd_spi->version) { 245 case AMD_SPI_V1: 246 /* Set ExecuteOpCode bit in the CTRL0 register */ 247 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, 248 AMD_SPI_EXEC_CMD); 249 return 0; 250 case AMD_SPI_V2: 251 case AMD_HID2_SPI: 252 /* Trigger the command execution */ 253 amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG, 254 AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD); 255 return 0; 256 default: 257 return -ENODEV; 258 } 259 } 260 261 static int amd_spi_host_setup(struct spi_device *spi) 262 { 263 struct amd_spi *amd_spi = spi_controller_get_devdata(spi->controller); 264 265 amd_spi_clear_fifo_ptr(amd_spi); 266 267 return 0; 268 } 269 270 static const struct amd_spi_freq amd_spi_freq[] = { 271 { AMD_SPI_MAX_HZ, F_100MHz, 0}, 272 { 66660000, F_66_66MHz, 0}, 273 { 50000000, SPI_SPD7, F_50MHz}, 274 { 33330000, F_33_33MHz, 0}, 275 { 22220000, F_22_22MHz, 0}, 276 { 16660000, F_16_66MHz, 0}, 277 { 4000000, SPI_SPD7, F_4MHz}, 278 { 3170000, SPI_SPD7, F_3_17MHz}, 279 { AMD_SPI_MIN_HZ, F_800KHz, 0}, 280 }; 281 282 static void amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz) 283 { 284 unsigned int i, spd7_val, alt_spd; 285 286 for (i = 0; i < ARRAY_SIZE(amd_spi_freq)-1; i++) 287 if (speed_hz >= amd_spi_freq[i].speed_hz) 288 break; 289 290 if (amd_spi->speed_hz == amd_spi_freq[i].speed_hz) 291 return; 292 293 amd_spi->speed_hz = amd_spi_freq[i].speed_hz; 294 295 alt_spd = (amd_spi_freq[i].enable_val << AMD_SPI_ALT_SPD_SHIFT) 296 & AMD_SPI_ALT_SPD_MASK; 297 amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, alt_spd, 298 AMD_SPI_ALT_SPD_MASK); 299 300 if (amd_spi->speed_hz == AMD_SPI_MAX_HZ) 301 amd_spi_setclear_reg32(amd_spi, AMD_SPI_ENA_REG, 1, 302 AMD_SPI_SPI100_MASK); 303 304 if (amd_spi_freq[i].spd7_val) { 305 spd7_val = (amd_spi_freq[i].spd7_val << AMD_SPI_SPD7_SHIFT) 306 & AMD_SPI_SPD7_MASK; 307 amd_spi_setclear_reg32(amd_spi, AMD_SPI_SPEED_REG, spd7_val, 308 AMD_SPI_SPD7_MASK); 309 } 310 } 311 312 static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, 313 struct spi_controller *host, 314 struct spi_message *message) 315 { 316 struct spi_transfer *xfer = NULL; 317 struct spi_device *spi = message->spi; 318 u8 cmd_opcode = 0, fifo_pos = AMD_SPI_FIFO_BASE; 319 u8 *buf = NULL; 320 u32 i = 0; 321 u32 tx_len = 0, rx_len = 0; 322 323 list_for_each_entry(xfer, &message->transfers, 324 transfer_list) { 325 /* Skip zero-length transfers to avoid len underflow below */ 326 if (!xfer->len) 327 continue; 328 329 if (xfer->speed_hz) 330 amd_set_spi_freq(amd_spi, xfer->speed_hz); 331 else 332 amd_set_spi_freq(amd_spi, spi->max_speed_hz); 333 334 /* Reject transfers that would overflow the FIFO window */ 335 if (fifo_pos + xfer->len > 336 AMD_SPI_FIFO_BASE + AMD_SPI_FIFO_SIZE) { 337 message->status = -EMSGSIZE; 338 goto fin_msg; 339 } 340 341 if (xfer->tx_buf) { 342 buf = (u8 *)xfer->tx_buf; 343 if (!tx_len) { 344 cmd_opcode = *(u8 *)xfer->tx_buf; 345 buf++; 346 xfer->len--; 347 } 348 tx_len += xfer->len; 349 350 /* Write data into the FIFO. */ 351 for (i = 0; i < xfer->len; i++) 352 amd_spi_writereg8(amd_spi, fifo_pos + i, buf[i]); 353 354 fifo_pos += xfer->len; 355 } 356 357 /* Store no. of bytes to be received from FIFO */ 358 if (xfer->rx_buf) 359 rx_len += xfer->len; 360 } 361 362 if (!buf) { 363 message->status = -EINVAL; 364 goto fin_msg; 365 } 366 367 amd_spi_set_opcode(amd_spi, cmd_opcode); 368 amd_spi_set_tx_count(amd_spi, tx_len); 369 amd_spi_set_rx_count(amd_spi, rx_len); 370 371 /* Execute command */ 372 message->status = amd_spi_execute_opcode(amd_spi); 373 if (message->status) 374 goto fin_msg; 375 376 if (rx_len) { 377 message->status = amd_spi_busy_wait(amd_spi); 378 if (message->status) 379 goto fin_msg; 380 381 list_for_each_entry(xfer, &message->transfers, transfer_list) 382 if (xfer->rx_buf) { 383 /* Reject transfers that would overflow the FIFO window */ 384 if (fifo_pos + xfer->len > 385 AMD_SPI_FIFO_BASE + AMD_SPI_FIFO_SIZE) { 386 message->status = -EMSGSIZE; 387 goto fin_msg; 388 } 389 buf = (u8 *)xfer->rx_buf; 390 /* Read data from FIFO to receive buffer */ 391 for (i = 0; i < xfer->len; i++) 392 buf[i] = amd_spi_readreg8(amd_spi, fifo_pos + i); 393 fifo_pos += xfer->len; 394 } 395 } 396 397 /* Update statistics */ 398 message->actual_length = tx_len + rx_len + 1; 399 400 fin_msg: 401 switch (amd_spi->version) { 402 case AMD_SPI_V1: 403 break; 404 case AMD_SPI_V2: 405 case AMD_HID2_SPI: 406 amd_spi_clear_chip(amd_spi, spi_get_chipselect(message->spi, 0)); 407 break; 408 default: 409 return -ENODEV; 410 } 411 412 spi_finalize_current_message(host); 413 414 return message->status; 415 } 416 417 static inline bool amd_is_spi_read_cmd_4b(const u16 op) 418 { 419 switch (op) { 420 case AMD_SPI_OP_READ_FAST_4B: 421 case AMD_SPI_OP_READ_1_1_2_4B: 422 case AMD_SPI_OP_READ_1_2_2_4B: 423 case AMD_SPI_OP_READ_1_1_4_4B: 424 case AMD_SPI_OP_READ_1_4_4_4B: 425 return true; 426 default: 427 return false; 428 } 429 } 430 431 static inline bool amd_is_spi_read_cmd(const u16 op) 432 { 433 switch (op) { 434 case AMD_SPI_OP_READ: 435 case AMD_SPI_OP_READ_FAST: 436 case AMD_SPI_OP_READ_1_1_2: 437 case AMD_SPI_OP_READ_1_2_2: 438 case AMD_SPI_OP_READ_1_1_4: 439 case AMD_SPI_OP_READ_1_4_4: 440 return true; 441 default: 442 return amd_is_spi_read_cmd_4b(op); 443 } 444 } 445 446 static inline bool amd_is_spi_write_cmd(const u16 op) 447 { 448 switch (op) { 449 case AMD_SPI_OP_PP: 450 case AMD_SPI_OP_PP_RANDOM: 451 return true; 452 default: 453 return false; 454 } 455 } 456 457 static bool amd_spi_supports_op(struct spi_mem *mem, 458 const struct spi_mem_op *op) 459 { 460 struct amd_spi *amd_spi = spi_controller_get_devdata(mem->spi->controller); 461 462 /* bus width is number of IO lines used to transmit */ 463 if (op->cmd.buswidth > 1 || op->addr.buswidth > 4) 464 return false; 465 466 /* AMD SPI controllers support quad mode only for read operations */ 467 if (amd_is_spi_read_cmd(op->cmd.opcode) || amd_is_spi_write_cmd(op->cmd.opcode)) { 468 if (op->data.buswidth > 4) 469 return false; 470 471 /* 472 * HID2 SPI controller supports DMA read up to 4K bytes and 473 * doesn't support 4-byte address commands. 474 */ 475 if (amd_spi->version == AMD_HID2_SPI) { 476 if ((amd_is_spi_read_cmd_4b(op->cmd.opcode) || 477 amd_is_spi_write_cmd(op->cmd.opcode)) && 478 op->data.nbytes > AMD_SPI_HID2_DMA_SIZE) 479 return false; 480 } else if (op->data.nbytes > AMD_SPI_MAX_DATA) { 481 return false; 482 } 483 } else if (op->data.buswidth > 1 || op->data.nbytes > AMD_SPI_MAX_DATA) { 484 return false; 485 } 486 487 if (op->max_freq < mem->spi->controller->min_speed_hz) 488 return false; 489 490 return spi_mem_default_supports_op(mem, op); 491 } 492 493 static int amd_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 494 { 495 struct amd_spi *amd_spi = spi_controller_get_devdata(mem->spi->controller); 496 497 /* 498 * HID2 SPI controller DMA read mode supports reading up to 4k 499 * bytes in single transaction, where as SPI0 and HID2 SPI 500 * controller index mode supports maximum of 64 bytes in a single 501 * transaction. 502 */ 503 if (amd_spi->version == AMD_HID2_SPI && (amd_is_spi_read_cmd(op->cmd.opcode) || 504 amd_is_spi_write_cmd(op->cmd.opcode))) 505 op->data.nbytes = clamp_val(op->data.nbytes, 0, AMD_SPI_HID2_DMA_SIZE); 506 else 507 op->data.nbytes = clamp_val(op->data.nbytes, 0, AMD_SPI_MAX_DATA); 508 509 return 0; 510 } 511 512 static void amd_spi_set_addr(struct amd_spi *amd_spi, 513 const struct spi_mem_op *op) 514 { 515 u8 nbytes = op->addr.nbytes; 516 u64 addr_val = op->addr.val; 517 int base_addr, i; 518 519 base_addr = AMD_SPI_FIFO_BASE + nbytes; 520 521 for (i = 0; i < nbytes; i++) { 522 amd_spi_writereg8(amd_spi, base_addr - i - 1, addr_val & 523 GENMASK(7, 0)); 524 addr_val >>= 8; 525 } 526 } 527 528 static void amd_spi_hiddma_write(struct amd_spi *amd_spi, const struct spi_mem_op *op) 529 { 530 u16 hid_cmd_start, val; 531 u32 hid_regval; 532 533 /* 534 * Program the HID2 output Buffer0. 4k aligned buf_memory_addr[31:12], 535 * buf_size[2:0]. 536 */ 537 hid_regval = amd_spi->phy_dma_buf | BIT(0); 538 amd_spi_writereg32(amd_spi, AMD_SPI_HID2_OUTPUT_BUF0, hid_regval); 539 540 /* Program max write length in hid2_write_control1 register */ 541 hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_WRITE_CNTRL1); 542 hid_regval = (hid_regval & ~GENMASK(15, 0)) | ((op->data.nbytes) + 3); 543 amd_spi_writereg32(amd_spi, AMD_SPI_HID2_WRITE_CNTRL1, hid_regval); 544 545 /* Set cmd start bit in hid2_cmd_start register to trigger HID basic write operation */ 546 hid_cmd_start = amd_spi_readreg16(amd_spi, AMD_SPI_HID2_CMD_START); 547 amd_spi_writereg16(amd_spi, AMD_SPI_HID2_CMD_START, (hid_cmd_start | BIT(2))); 548 549 /* Check interrupt status of HIDDMA basic write operation in hid2_int_status register */ 550 readw_poll_timeout(amd_spi->io_remap_addr + AMD_SPI_HID2_INT_STATUS, val, 551 (val & BIT(2)), AMD_SPI_IO_SLEEP_US, AMD_SPI_IO_TIMEOUT_US); 552 553 /* Clear the interrupts by writing to hid2_int_status register */ 554 val = amd_spi_readreg16(amd_spi, AMD_SPI_HID2_INT_STATUS); 555 amd_spi_writereg16(amd_spi, AMD_SPI_HID2_INT_STATUS, val); 556 } 557 558 static void amd_spi_mem_data_out(struct amd_spi *amd_spi, 559 const struct spi_mem_op *op) 560 { 561 int base_addr = AMD_SPI_FIFO_BASE + op->addr.nbytes; 562 u64 *buf_64 = (u64 *)op->data.buf.out; 563 u64 addr_val = op->addr.val; 564 u32 nbytes = op->data.nbytes; 565 u32 left_data = nbytes; 566 u8 *buf; 567 int i; 568 569 /* 570 * Condition for using HID write mode. Only for writing complete page data, use HID write. 571 * Use index mode otherwise. 572 */ 573 if (amd_spi->version == AMD_HID2_SPI && amd_is_spi_write_cmd(op->cmd.opcode)) { 574 u64 *dma_buf64 = (u64 *)(amd_spi->dma_virt_addr + op->addr.nbytes + op->cmd.nbytes); 575 u8 *dma_buf = (u8 *)amd_spi->dma_virt_addr; 576 577 /* Copy opcode and address to DMA buffer */ 578 *dma_buf = op->cmd.opcode; 579 580 dma_buf = (u8 *)dma_buf64; 581 for (i = 0; i < op->addr.nbytes; i++) { 582 *--dma_buf = addr_val & GENMASK(7, 0); 583 addr_val >>= 8; 584 } 585 586 /* Copy data to DMA buffer */ 587 while (left_data >= 8) { 588 *dma_buf64++ = *buf_64++; 589 left_data -= 8; 590 } 591 592 buf = (u8 *)buf_64; 593 dma_buf = (u8 *)dma_buf64; 594 while (left_data--) 595 *dma_buf++ = *buf++; 596 597 amd_spi_hiddma_write(amd_spi, op); 598 } else { 599 amd_spi_set_opcode(amd_spi, op->cmd.opcode); 600 amd_spi_set_addr(amd_spi, op); 601 602 for (i = 0; left_data >= 8; i++, left_data -= 8) 603 amd_spi_writereg64(amd_spi, base_addr + op->dummy.nbytes + (i * 8), 604 *buf_64++); 605 606 buf = (u8 *)buf_64; 607 for (i = 0; i < left_data; i++) { 608 amd_spi_writereg8(amd_spi, 609 base_addr + op->dummy.nbytes + nbytes + i - left_data, 610 buf[i]); 611 } 612 613 amd_spi_set_tx_count(amd_spi, op->addr.nbytes + op->data.nbytes); 614 amd_spi_set_rx_count(amd_spi, 0); 615 amd_spi_clear_fifo_ptr(amd_spi); 616 amd_spi_execute_opcode(amd_spi); 617 } 618 } 619 620 static void amd_spi_hiddma_read(struct amd_spi *amd_spi, const struct spi_mem_op *op) 621 { 622 u16 hid_cmd_start, val; 623 u32 hid_regval; 624 625 /* Set the opcode in hid2_read_control0 register */ 626 hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_READ_CNTRL0); 627 hid_regval = (hid_regval & ~GENMASK(7, 0)) | op->cmd.opcode; 628 629 /* 630 * Program the address in the hid2_read_control0 register [8:31]. The address should 631 * be written starting from the 8th bit of the register, requiring an 8-bit shift. 632 * Additionally, to convert a 2-byte spinand address to a 3-byte address, another 633 * 8-bit shift is needed. Therefore, a total shift of 16 bits is required. 634 */ 635 hid_regval = (hid_regval & ~GENMASK(31, 8)) | (op->addr.val << 16); 636 amd_spi_writereg32(amd_spi, AMD_SPI_HID2_READ_CNTRL0, hid_regval); 637 638 /* Configure dummy clock cycles for fast read, dual, quad I/O commands */ 639 hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_READ_CNTRL2); 640 /* Fast read dummy cycle */ 641 hid_regval &= ~GENMASK(4, 0); 642 643 /* Fast read Dual I/O dummy cycle */ 644 hid_regval &= ~GENMASK(12, 8); 645 646 /* Fast read Quad I/O dummy cycle */ 647 hid_regval = (hid_regval & ~GENMASK(20, 16)) | BIT(17); 648 649 /* Set no of preamble bytecount */ 650 hid_regval &= ~GENMASK(27, 24); 651 amd_spi_writereg32(amd_spi, AMD_SPI_HID2_READ_CNTRL2, hid_regval); 652 653 /* 654 * Program the HID2 Input Ring Buffer0. 4k aligned buf_memory_addr[31:12], 655 * buf_size[4:0], end_input_ring[5]. 656 */ 657 hid_regval = amd_spi->phy_dma_buf | BIT(5) | BIT(0); 658 amd_spi_writereg32(amd_spi, AMD_SPI_HID2_INPUT_RING_BUF0, hid_regval); 659 660 /* Program max read length(no of DWs) in hid2_read_control1 register */ 661 hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_READ_CNTRL1); 662 hid_regval = (hid_regval & ~GENMASK(15, 0)) | ((op->data.nbytes / 4) - 1); 663 amd_spi_writereg32(amd_spi, AMD_SPI_HID2_READ_CNTRL1, hid_regval); 664 665 /* Set cmd start bit in hid2_cmd_start register to trigger HID basic read operation */ 666 hid_cmd_start = amd_spi_readreg16(amd_spi, AMD_SPI_HID2_CMD_START); 667 amd_spi_writereg16(amd_spi, AMD_SPI_HID2_CMD_START, (hid_cmd_start | BIT(3))); 668 669 /* Check interrupt status of HIDDMA basic read operation in hid2_int_status register */ 670 readw_poll_timeout(amd_spi->io_remap_addr + AMD_SPI_HID2_INT_STATUS, val, 671 (val & BIT(3)), AMD_SPI_IO_SLEEP_US, AMD_SPI_IO_TIMEOUT_US); 672 673 /* Clear the interrupts by writing to hid2_int_status register */ 674 val = amd_spi_readreg16(amd_spi, AMD_SPI_HID2_INT_STATUS); 675 amd_spi_writereg16(amd_spi, AMD_SPI_HID2_INT_STATUS, val); 676 } 677 678 static void amd_spi_mem_data_in(struct amd_spi *amd_spi, 679 const struct spi_mem_op *op) 680 { 681 int base_addr = AMD_SPI_FIFO_BASE + op->addr.nbytes; 682 u64 *buf_64 = (u64 *)op->data.buf.in; 683 u32 nbytes = op->data.nbytes; 684 u32 left_data = nbytes; 685 u32 data; 686 u8 *buf; 687 int i; 688 689 /* 690 * Condition for using HID read mode. Only for reading complete page data, use HID read. 691 * Use index mode otherwise. 692 */ 693 if (amd_spi->version == AMD_HID2_SPI && amd_is_spi_read_cmd(op->cmd.opcode)) { 694 u64 *dma_buf64 = (u64 *)amd_spi->dma_virt_addr; 695 u8 *dma_buf; 696 697 amd_spi_hiddma_read(amd_spi, op); 698 699 /* Copy data from DMA buffer */ 700 while (left_data >= 8) { 701 *buf_64++ = *dma_buf64++; 702 left_data -= 8; 703 } 704 705 buf = (u8 *)buf_64; 706 dma_buf = (u8 *)dma_buf64; 707 while (left_data--) 708 *buf++ = *dma_buf++; 709 710 /* Reset HID RX memory logic */ 711 data = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_CNTRL); 712 amd_spi_writereg32(amd_spi, AMD_SPI_HID2_CNTRL, data | BIT(5)); 713 } else { 714 /* Index mode */ 715 amd_spi_set_opcode(amd_spi, op->cmd.opcode); 716 amd_spi_set_addr(amd_spi, op); 717 amd_spi_set_tx_count(amd_spi, op->addr.nbytes + op->dummy.nbytes); 718 719 for (i = 0; i < op->dummy.nbytes; i++) 720 amd_spi_writereg8(amd_spi, (base_addr + i), 0xff); 721 722 amd_spi_set_rx_count(amd_spi, op->data.nbytes); 723 amd_spi_clear_fifo_ptr(amd_spi); 724 amd_spi_execute_opcode(amd_spi); 725 amd_spi_busy_wait(amd_spi); 726 727 for (i = 0; left_data >= 8; i++, left_data -= 8) 728 *buf_64++ = amd_spi_readreg64(amd_spi, base_addr + op->dummy.nbytes + 729 (i * 8)); 730 731 buf = (u8 *)buf_64; 732 for (i = 0; i < left_data; i++) 733 buf[i] = amd_spi_readreg8(amd_spi, base_addr + op->dummy.nbytes + 734 nbytes + i - left_data); 735 } 736 737 } 738 739 static void amd_set_spi_addr_mode(struct amd_spi *amd_spi, 740 const struct spi_mem_op *op) 741 { 742 u32 val = amd_spi_readreg32(amd_spi, AMD_SPI_ADDR32CTRL_REG); 743 744 if (amd_is_spi_read_cmd_4b(op->cmd.opcode)) 745 amd_spi_writereg32(amd_spi, AMD_SPI_ADDR32CTRL_REG, val | BIT(0)); 746 else 747 amd_spi_writereg32(amd_spi, AMD_SPI_ADDR32CTRL_REG, val & ~BIT(0)); 748 } 749 750 static int amd_spi_exec_mem_op(struct spi_mem *mem, 751 const struct spi_mem_op *op) 752 { 753 struct amd_spi *amd_spi; 754 755 amd_spi = spi_controller_get_devdata(mem->spi->controller); 756 757 amd_set_spi_freq(amd_spi, op->max_freq); 758 759 if (amd_spi->version == AMD_SPI_V2) 760 amd_set_spi_addr_mode(amd_spi, op); 761 762 switch (op->data.dir) { 763 case SPI_MEM_DATA_IN: 764 amd_spi_mem_data_in(amd_spi, op); 765 break; 766 case SPI_MEM_DATA_OUT: 767 fallthrough; 768 case SPI_MEM_NO_DATA: 769 amd_spi_mem_data_out(amd_spi, op); 770 break; 771 default: 772 return -EOPNOTSUPP; 773 } 774 775 return 0; 776 } 777 778 static const struct spi_controller_mem_ops amd_spi_mem_ops = { 779 .exec_op = amd_spi_exec_mem_op, 780 .adjust_op_size = amd_spi_adjust_op_size, 781 .supports_op = amd_spi_supports_op, 782 }; 783 784 static const struct spi_controller_mem_caps amd_spi_mem_caps = { 785 .per_op_freq = true, 786 }; 787 788 static int amd_spi_host_transfer(struct spi_controller *host, 789 struct spi_message *msg) 790 { 791 struct amd_spi *amd_spi = spi_controller_get_devdata(host); 792 struct spi_device *spi = msg->spi; 793 794 amd_spi_select_chip(amd_spi, spi_get_chipselect(spi, 0)); 795 796 /* 797 * Extract spi_transfers from the spi message and 798 * program the controller. 799 */ 800 return amd_spi_fifo_xfer(amd_spi, host, msg); 801 } 802 803 static size_t amd_spi_max_transfer_size(struct spi_device *spi) 804 { 805 return AMD_SPI_FIFO_SIZE; 806 } 807 808 static int amd_spi_setup_hiddma(struct amd_spi *amd_spi, struct device *dev) 809 { 810 u32 hid_regval; 811 812 /* Allocate DMA buffer to use for HID basic read and write operations. For write 813 * operations, the DMA buffer should include the opcode, address bytes and dummy 814 * bytes(if any) in addition to the data bytes. Additionally, the hardware requires 815 * that the buffer address be 4K aligned. So, allocate DMA buffer of size 816 * 2 * AMD_SPI_HID2_DMA_SIZE. 817 */ 818 amd_spi->dma_virt_addr = dmam_alloc_coherent(dev, AMD_SPI_HID2_DMA_SIZE * 2, 819 &amd_spi->phy_dma_buf, GFP_KERNEL); 820 if (!amd_spi->dma_virt_addr) 821 return -ENOMEM; 822 823 /* 824 * Enable interrupts and set mask bits in hid2_int_mask register to generate interrupt 825 * properly for HIDDMA basic read and write operations. 826 */ 827 hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_INT_MASK); 828 hid_regval = (hid_regval & GENMASK(31, 8)) | BIT(18) | BIT(19); 829 amd_spi_writereg32(amd_spi, AMD_SPI_HID2_INT_MASK, hid_regval); 830 831 /* Configure buffer unit(4k) and write threshold in hid2_control register */ 832 hid_regval = amd_spi_readreg32(amd_spi, AMD_SPI_HID2_CNTRL); 833 amd_spi_writereg32(amd_spi, AMD_SPI_HID2_CNTRL, (hid_regval | GENMASK(13, 12)) & ~BIT(3)); 834 835 return 0; 836 } 837 838 int amd_spi_probe_common(struct device *dev, struct spi_controller *host) 839 { 840 struct amd_spi *amd_spi = spi_controller_get_devdata(host); 841 int err; 842 843 /* Initialize the spi_controller fields */ 844 host->num_chipselect = 4; 845 host->mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD; 846 host->flags = SPI_CONTROLLER_HALF_DUPLEX; 847 host->max_speed_hz = AMD_SPI_MAX_HZ; 848 host->min_speed_hz = AMD_SPI_MIN_HZ; 849 host->setup = amd_spi_host_setup; 850 host->transfer_one_message = amd_spi_host_transfer; 851 host->mem_ops = &amd_spi_mem_ops; 852 host->mem_caps = &amd_spi_mem_caps; 853 host->max_transfer_size = amd_spi_max_transfer_size; 854 host->max_message_size = amd_spi_max_transfer_size; 855 856 /* Register the controller with SPI framework */ 857 err = devm_spi_register_controller(dev, host); 858 if (err) 859 return dev_err_probe(dev, err, "error registering SPI controller\n"); 860 861 if (amd_spi->version == AMD_HID2_SPI) 862 err = amd_spi_setup_hiddma(amd_spi, dev); 863 864 return err; 865 } 866 EXPORT_SYMBOL_GPL(amd_spi_probe_common); 867 868 static int amd_spi_probe(struct platform_device *pdev) 869 { 870 struct device *dev = &pdev->dev; 871 struct spi_controller *host; 872 struct amd_spi *amd_spi; 873 874 /* Allocate storage for host and driver private data */ 875 host = devm_spi_alloc_host(dev, sizeof(struct amd_spi)); 876 if (!host) 877 return -ENOMEM; 878 879 amd_spi = spi_controller_get_devdata(host); 880 amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0); 881 if (IS_ERR(amd_spi->io_remap_addr)) 882 return dev_err_probe(dev, PTR_ERR(amd_spi->io_remap_addr), 883 "ioremap of SPI registers failed\n"); 884 885 dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr); 886 887 amd_spi->version = (uintptr_t)device_get_match_data(dev); 888 host->bus_num = (amd_spi->version == AMD_HID2_SPI) ? 2 : 0; 889 890 return amd_spi_probe_common(dev, host); 891 } 892 893 #ifdef CONFIG_ACPI 894 static const struct acpi_device_id spi_acpi_match[] = { 895 { "AMDI0061", AMD_SPI_V1 }, 896 { "AMDI0062", AMD_SPI_V2 }, 897 { "AMDI0063", AMD_HID2_SPI }, 898 {}, 899 }; 900 MODULE_DEVICE_TABLE(acpi, spi_acpi_match); 901 #endif 902 903 static struct platform_driver amd_spi_driver = { 904 .driver = { 905 .name = "amd_spi", 906 .acpi_match_table = ACPI_PTR(spi_acpi_match), 907 }, 908 .probe = amd_spi_probe, 909 }; 910 911 module_platform_driver(amd_spi_driver); 912 913 MODULE_LICENSE("Dual BSD/GPL"); 914 MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>"); 915 MODULE_DESCRIPTION("AMD SPI Master Controller Driver"); 916