1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 // 3 // AMD SPI controller driver 4 // 5 // Copyright (c) 2020, Advanced Micro Devices, Inc. 6 // 7 // Author: Sanjay R Mehta <sanju.mehta@amd.com> 8 9 #include <linux/acpi.h> 10 #include <linux/init.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/delay.h> 14 #include <linux/spi/spi.h> 15 16 #define AMD_SPI_CTRL0_REG 0x00 17 #define AMD_SPI_EXEC_CMD BIT(16) 18 #define AMD_SPI_FIFO_CLEAR BIT(20) 19 #define AMD_SPI_BUSY BIT(31) 20 21 #define AMD_SPI_OPCODE_MASK 0xFF 22 23 #define AMD_SPI_ALT_CS_REG 0x1D 24 #define AMD_SPI_ALT_CS_MASK 0x3 25 26 #define AMD_SPI_FIFO_BASE 0x80 27 #define AMD_SPI_TX_COUNT_REG 0x48 28 #define AMD_SPI_RX_COUNT_REG 0x4B 29 #define AMD_SPI_STATUS_REG 0x4C 30 31 #define AMD_SPI_MEM_SIZE 200 32 33 /* M_CMD OP codes for SPI */ 34 #define AMD_SPI_XFER_TX 1 35 #define AMD_SPI_XFER_RX 2 36 37 struct amd_spi { 38 void __iomem *io_remap_addr; 39 unsigned long io_base_addr; 40 u32 rom_addr; 41 }; 42 43 static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx) 44 { 45 return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx); 46 } 47 48 static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val) 49 { 50 iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); 51 } 52 53 static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear) 54 { 55 u8 tmp = amd_spi_readreg8(amd_spi, idx); 56 57 tmp = (tmp & ~clear) | set; 58 amd_spi_writereg8(amd_spi, idx, tmp); 59 } 60 61 static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx) 62 { 63 return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx); 64 } 65 66 static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val) 67 { 68 iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); 69 } 70 71 static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear) 72 { 73 u32 tmp = amd_spi_readreg32(amd_spi, idx); 74 75 tmp = (tmp & ~clear) | set; 76 amd_spi_writereg32(amd_spi, idx, tmp); 77 } 78 79 static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs) 80 { 81 amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK); 82 } 83 84 static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi) 85 { 86 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR); 87 } 88 89 static void amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode) 90 { 91 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode, AMD_SPI_OPCODE_MASK); 92 } 93 94 static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count) 95 { 96 amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); 97 } 98 99 static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count) 100 { 101 amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); 102 } 103 104 static int amd_spi_busy_wait(struct amd_spi *amd_spi) 105 { 106 int timeout = 100000; 107 108 /* poll for SPI bus to become idle */ 109 while (amd_spi_readreg32(amd_spi, AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) { 110 usleep_range(10, 20); 111 if (timeout-- < 0) 112 return -ETIMEDOUT; 113 } 114 115 return 0; 116 } 117 118 static int amd_spi_execute_opcode(struct amd_spi *amd_spi) 119 { 120 int ret; 121 122 ret = amd_spi_busy_wait(amd_spi); 123 if (ret) 124 return ret; 125 126 /* Set ExecuteOpCode bit in the CTRL0 register */ 127 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, AMD_SPI_EXEC_CMD); 128 129 return 0; 130 } 131 132 static int amd_spi_master_setup(struct spi_device *spi) 133 { 134 struct amd_spi *amd_spi = spi_master_get_devdata(spi->master); 135 136 amd_spi_clear_fifo_ptr(amd_spi); 137 138 return 0; 139 } 140 141 static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, 142 struct spi_master *master, 143 struct spi_message *message) 144 { 145 struct spi_transfer *xfer = NULL; 146 u8 cmd_opcode; 147 u8 *buf = NULL; 148 u32 m_cmd = 0; 149 u32 i = 0; 150 u32 tx_len = 0, rx_len = 0; 151 152 list_for_each_entry(xfer, &message->transfers, 153 transfer_list) { 154 if (xfer->rx_buf) 155 m_cmd = AMD_SPI_XFER_RX; 156 if (xfer->tx_buf) 157 m_cmd = AMD_SPI_XFER_TX; 158 159 if (m_cmd & AMD_SPI_XFER_TX) { 160 buf = (u8 *)xfer->tx_buf; 161 tx_len = xfer->len - 1; 162 cmd_opcode = *(u8 *)xfer->tx_buf; 163 buf++; 164 amd_spi_set_opcode(amd_spi, cmd_opcode); 165 166 /* Write data into the FIFO. */ 167 for (i = 0; i < tx_len; i++) { 168 iowrite8(buf[i], ((u8 __iomem *)amd_spi->io_remap_addr + 169 AMD_SPI_FIFO_BASE + i)); 170 } 171 172 amd_spi_set_tx_count(amd_spi, tx_len); 173 amd_spi_clear_fifo_ptr(amd_spi); 174 /* Execute command */ 175 amd_spi_execute_opcode(amd_spi); 176 } 177 if (m_cmd & AMD_SPI_XFER_RX) { 178 /* 179 * Store no. of bytes to be received from 180 * FIFO 181 */ 182 rx_len = xfer->len; 183 buf = (u8 *)xfer->rx_buf; 184 amd_spi_set_rx_count(amd_spi, rx_len); 185 amd_spi_clear_fifo_ptr(amd_spi); 186 /* Execute command */ 187 amd_spi_execute_opcode(amd_spi); 188 amd_spi_busy_wait(amd_spi); 189 /* Read data from FIFO to receive buffer */ 190 for (i = 0; i < rx_len; i++) 191 buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i); 192 } 193 } 194 195 /* Update statistics */ 196 message->actual_length = tx_len + rx_len + 1; 197 /* complete the transaction */ 198 message->status = 0; 199 spi_finalize_current_message(master); 200 201 return 0; 202 } 203 204 static int amd_spi_master_transfer(struct spi_master *master, 205 struct spi_message *msg) 206 { 207 struct amd_spi *amd_spi = spi_master_get_devdata(master); 208 struct spi_device *spi = msg->spi; 209 210 amd_spi_select_chip(amd_spi, spi->chip_select); 211 212 /* 213 * Extract spi_transfers from the spi message and 214 * program the controller. 215 */ 216 amd_spi_fifo_xfer(amd_spi, master, msg); 217 218 return 0; 219 } 220 221 static int amd_spi_probe(struct platform_device *pdev) 222 { 223 struct device *dev = &pdev->dev; 224 struct spi_master *master; 225 struct amd_spi *amd_spi; 226 int err = 0; 227 228 /* Allocate storage for spi_master and driver private data */ 229 master = spi_alloc_master(dev, sizeof(struct amd_spi)); 230 if (!master) { 231 dev_err(dev, "Error allocating SPI master\n"); 232 return -ENOMEM; 233 } 234 235 amd_spi = spi_master_get_devdata(master); 236 amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0); 237 if (IS_ERR(amd_spi->io_remap_addr)) { 238 err = PTR_ERR(amd_spi->io_remap_addr); 239 dev_err(dev, "error %d ioremap of SPI registers failed\n", err); 240 goto err_free_master; 241 } 242 dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr); 243 244 /* Initialize the spi_master fields */ 245 master->bus_num = 0; 246 master->num_chipselect = 4; 247 master->mode_bits = 0; 248 master->flags = SPI_MASTER_HALF_DUPLEX; 249 master->setup = amd_spi_master_setup; 250 master->transfer_one_message = amd_spi_master_transfer; 251 252 /* Register the controller with SPI framework */ 253 err = devm_spi_register_master(dev, master); 254 if (err) { 255 dev_err(dev, "error %d registering SPI controller\n", err); 256 goto err_free_master; 257 } 258 259 return 0; 260 261 err_free_master: 262 spi_master_put(master); 263 264 return err; 265 } 266 267 #ifdef CONFIG_ACPI 268 static const struct acpi_device_id spi_acpi_match[] = { 269 { "AMDI0061", 0 }, 270 {}, 271 }; 272 MODULE_DEVICE_TABLE(acpi, spi_acpi_match); 273 #endif 274 275 static struct platform_driver amd_spi_driver = { 276 .driver = { 277 .name = "amd_spi", 278 .acpi_match_table = ACPI_PTR(spi_acpi_match), 279 }, 280 .probe = amd_spi_probe, 281 }; 282 283 module_platform_driver(amd_spi_driver); 284 285 MODULE_LICENSE("Dual BSD/GPL"); 286 MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>"); 287 MODULE_DESCRIPTION("AMD SPI Master Controller Driver"); 288