1 /* 2 * Driver for Atmel QSPI Controller 3 * 4 * Copyright (C) 2015 Atmel Corporation 5 * Copyright (C) 2018 Cryptera A/S 6 * 7 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com> 8 * Author: Piotr Bugalski <bugalski.piotr@gmail.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 * 22 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale. 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/clk.h> 27 #include <linux/module.h> 28 #include <linux/platform_device.h> 29 #include <linux/delay.h> 30 #include <linux/err.h> 31 #include <linux/interrupt.h> 32 #include <linux/of.h> 33 34 #include <linux/io.h> 35 #include <linux/spi/spi-mem.h> 36 37 /* QSPI register offsets */ 38 #define QSPI_CR 0x0000 /* Control Register */ 39 #define QSPI_MR 0x0004 /* Mode Register */ 40 #define QSPI_RD 0x0008 /* Receive Data Register */ 41 #define QSPI_TD 0x000c /* Transmit Data Register */ 42 #define QSPI_SR 0x0010 /* Status Register */ 43 #define QSPI_IER 0x0014 /* Interrupt Enable Register */ 44 #define QSPI_IDR 0x0018 /* Interrupt Disable Register */ 45 #define QSPI_IMR 0x001c /* Interrupt Mask Register */ 46 #define QSPI_SCR 0x0020 /* Serial Clock Register */ 47 48 #define QSPI_IAR 0x0030 /* Instruction Address Register */ 49 #define QSPI_ICR 0x0034 /* Instruction Code Register */ 50 #define QSPI_IFR 0x0038 /* Instruction Frame Register */ 51 52 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */ 53 #define QSPI_SKR 0x0044 /* Scrambling Key Register */ 54 55 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */ 56 #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */ 57 58 #define QSPI_VERSION 0x00FC /* Version Register */ 59 60 61 /* Bitfields in QSPI_CR (Control Register) */ 62 #define QSPI_CR_QSPIEN BIT(0) 63 #define QSPI_CR_QSPIDIS BIT(1) 64 #define QSPI_CR_SWRST BIT(7) 65 #define QSPI_CR_LASTXFER BIT(24) 66 67 /* Bitfields in QSPI_MR (Mode Register) */ 68 #define QSPI_MR_SMM BIT(0) 69 #define QSPI_MR_LLB BIT(1) 70 #define QSPI_MR_WDRBT BIT(2) 71 #define QSPI_MR_SMRM BIT(3) 72 #define QSPI_MR_CSMODE_MASK GENMASK(5, 4) 73 #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4) 74 #define QSPI_MR_CSMODE_LASTXFER (1 << 4) 75 #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4) 76 #define QSPI_MR_NBBITS_MASK GENMASK(11, 8) 77 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK) 78 #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16) 79 #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK) 80 #define QSPI_MR_DLYCS_MASK GENMASK(31, 24) 81 #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK) 82 83 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */ 84 #define QSPI_SR_RDRF BIT(0) 85 #define QSPI_SR_TDRE BIT(1) 86 #define QSPI_SR_TXEMPTY BIT(2) 87 #define QSPI_SR_OVRES BIT(3) 88 #define QSPI_SR_CSR BIT(8) 89 #define QSPI_SR_CSS BIT(9) 90 #define QSPI_SR_INSTRE BIT(10) 91 #define QSPI_SR_QSPIENS BIT(24) 92 93 #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR) 94 95 /* Bitfields in QSPI_SCR (Serial Clock Register) */ 96 #define QSPI_SCR_CPOL BIT(0) 97 #define QSPI_SCR_CPHA BIT(1) 98 #define QSPI_SCR_SCBR_MASK GENMASK(15, 8) 99 #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK) 100 #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16) 101 #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK) 102 103 /* Bitfields in QSPI_ICR (Instruction Code Register) */ 104 #define QSPI_ICR_INST_MASK GENMASK(7, 0) 105 #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK) 106 #define QSPI_ICR_OPT_MASK GENMASK(23, 16) 107 #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK) 108 109 /* Bitfields in QSPI_IFR (Instruction Frame Register) */ 110 #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0) 111 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0) 112 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0) 113 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0) 114 #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0) 115 #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0) 116 #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0) 117 #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0) 118 #define QSPI_IFR_INSTEN BIT(4) 119 #define QSPI_IFR_ADDREN BIT(5) 120 #define QSPI_IFR_OPTEN BIT(6) 121 #define QSPI_IFR_DATAEN BIT(7) 122 #define QSPI_IFR_OPTL_MASK GENMASK(9, 8) 123 #define QSPI_IFR_OPTL_1BIT (0 << 8) 124 #define QSPI_IFR_OPTL_2BIT (1 << 8) 125 #define QSPI_IFR_OPTL_4BIT (2 << 8) 126 #define QSPI_IFR_OPTL_8BIT (3 << 8) 127 #define QSPI_IFR_ADDRL BIT(10) 128 #define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12) 129 #define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12) 130 #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12) 131 #define QSPI_IFR_TFRTYP_TRSFR_WRITE (2 << 12) 132 #define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM (3 << 13) 133 #define QSPI_IFR_CRM BIT(14) 134 #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16) 135 #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK) 136 137 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */ 138 #define QSPI_SMR_SCREN BIT(0) 139 #define QSPI_SMR_RVDIS BIT(1) 140 141 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */ 142 #define QSPI_WPMR_WPEN BIT(0) 143 #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8) 144 #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK) 145 146 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */ 147 #define QSPI_WPSR_WPVS BIT(0) 148 #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8) 149 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC) 150 151 152 struct atmel_qspi { 153 void __iomem *regs; 154 void __iomem *mem; 155 struct clk *clk; 156 struct platform_device *pdev; 157 u32 pending; 158 struct completion cmd_completion; 159 }; 160 161 struct qspi_mode { 162 u8 cmd_buswidth; 163 u8 addr_buswidth; 164 u8 data_buswidth; 165 u32 config; 166 }; 167 168 static const struct qspi_mode sama5d2_qspi_modes[] = { 169 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI }, 170 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT }, 171 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT }, 172 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO }, 173 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO }, 174 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD }, 175 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, 176 }; 177 178 /* Register access functions */ 179 static inline u32 qspi_readl(struct atmel_qspi *aq, u32 reg) 180 { 181 return readl_relaxed(aq->regs + reg); 182 } 183 184 static inline void qspi_writel(struct atmel_qspi *aq, u32 reg, u32 value) 185 { 186 writel_relaxed(value, aq->regs + reg); 187 } 188 189 static inline bool is_compatible(const struct spi_mem_op *op, 190 const struct qspi_mode *mode) 191 { 192 if (op->cmd.buswidth != mode->cmd_buswidth) 193 return false; 194 195 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth) 196 return false; 197 198 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth) 199 return false; 200 201 return true; 202 } 203 204 static int find_mode(const struct spi_mem_op *op) 205 { 206 u32 i; 207 208 for (i = 0; i < ARRAY_SIZE(sama5d2_qspi_modes); i++) 209 if (is_compatible(op, &sama5d2_qspi_modes[i])) 210 return i; 211 212 return -1; 213 } 214 215 static bool atmel_qspi_supports_op(struct spi_mem *mem, 216 const struct spi_mem_op *op) 217 { 218 if (find_mode(op) < 0) 219 return false; 220 221 /* special case not supported by hardware */ 222 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth && 223 op->dummy.nbytes == 0) 224 return false; 225 226 return true; 227 } 228 229 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 230 { 231 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master); 232 int mode; 233 u32 dummy_cycles = 0; 234 u32 iar, icr, ifr, sr; 235 int err = 0; 236 237 iar = 0; 238 icr = QSPI_ICR_INST(op->cmd.opcode); 239 ifr = QSPI_IFR_INSTEN; 240 241 qspi_writel(aq, QSPI_MR, QSPI_MR_SMM); 242 243 mode = find_mode(op); 244 if (mode < 0) 245 return -ENOTSUPP; 246 247 ifr |= sama5d2_qspi_modes[mode].config; 248 249 if (op->dummy.buswidth && op->dummy.nbytes) 250 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth; 251 252 if (op->addr.buswidth) { 253 switch (op->addr.nbytes) { 254 case 0: 255 break; 256 case 1: 257 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT; 258 icr |= QSPI_ICR_OPT(op->addr.val & 0xff); 259 break; 260 case 2: 261 if (dummy_cycles < 8 / op->addr.buswidth) { 262 ifr &= ~QSPI_IFR_INSTEN; 263 ifr |= QSPI_IFR_ADDREN; 264 iar = (op->cmd.opcode << 16) | 265 (op->addr.val & 0xffff); 266 } else { 267 ifr |= QSPI_IFR_ADDREN; 268 iar = (op->addr.val << 8) & 0xffffff; 269 dummy_cycles -= 8 / op->addr.buswidth; 270 } 271 break; 272 case 3: 273 ifr |= QSPI_IFR_ADDREN; 274 iar = op->addr.val & 0xffffff; 275 break; 276 case 4: 277 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL; 278 iar = op->addr.val & 0x7ffffff; 279 break; 280 default: 281 return -ENOTSUPP; 282 } 283 } 284 285 /* Set number of dummy cycles */ 286 if (dummy_cycles) 287 ifr |= QSPI_IFR_NBDUM(dummy_cycles); 288 289 /* Set data enable */ 290 if (op->data.nbytes) 291 ifr |= QSPI_IFR_DATAEN; 292 293 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) 294 ifr |= QSPI_IFR_TFRTYP_TRSFR_READ; 295 else 296 ifr |= QSPI_IFR_TFRTYP_TRSFR_WRITE; 297 298 /* Clear pending interrupts */ 299 (void)qspi_readl(aq, QSPI_SR); 300 301 /* Set QSPI Instruction Frame registers */ 302 qspi_writel(aq, QSPI_IAR, iar); 303 qspi_writel(aq, QSPI_ICR, icr); 304 qspi_writel(aq, QSPI_IFR, ifr); 305 306 /* Skip to the final steps if there is no data */ 307 if (op->data.nbytes) { 308 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ 309 (void)qspi_readl(aq, QSPI_IFR); 310 311 /* Send/Receive data */ 312 if (op->data.dir == SPI_MEM_DATA_IN) 313 _memcpy_fromio(op->data.buf.in, 314 aq->mem + iar, op->data.nbytes); 315 else 316 _memcpy_toio(aq->mem + iar, 317 op->data.buf.out, op->data.nbytes); 318 319 /* Release the chip-select */ 320 qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER); 321 } 322 323 /* Poll INSTRuction End status */ 324 sr = qspi_readl(aq, QSPI_SR); 325 if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) 326 return err; 327 328 /* Wait for INSTRuction End interrupt */ 329 reinit_completion(&aq->cmd_completion); 330 aq->pending = sr & QSPI_SR_CMD_COMPLETED; 331 qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED); 332 if (!wait_for_completion_timeout(&aq->cmd_completion, 333 msecs_to_jiffies(1000))) 334 err = -ETIMEDOUT; 335 qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED); 336 337 return err; 338 } 339 340 const char *atmel_qspi_get_name(struct spi_mem *spimem) 341 { 342 return dev_name(spimem->spi->dev.parent); 343 } 344 345 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = { 346 .supports_op = atmel_qspi_supports_op, 347 .exec_op = atmel_qspi_exec_op, 348 .get_name = atmel_qspi_get_name 349 }; 350 351 static int atmel_qspi_setup(struct spi_device *spi) 352 { 353 struct spi_controller *ctrl = spi->master; 354 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); 355 unsigned long src_rate; 356 u32 scr, scbr; 357 358 if (ctrl->busy) 359 return -EBUSY; 360 361 if (!spi->max_speed_hz) 362 return -EINVAL; 363 364 src_rate = clk_get_rate(aq->clk); 365 if (!src_rate) 366 return -EINVAL; 367 368 /* Compute the QSPI baudrate */ 369 scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz); 370 if (scbr > 0) 371 scbr--; 372 373 scr = QSPI_SCR_SCBR(scbr); 374 qspi_writel(aq, QSPI_SCR, scr); 375 376 return 0; 377 } 378 379 static int atmel_qspi_init(struct atmel_qspi *aq) 380 { 381 /* Reset the QSPI controller */ 382 qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST); 383 384 /* Enable the QSPI controller */ 385 qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN); 386 387 return 0; 388 } 389 390 static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) 391 { 392 struct atmel_qspi *aq = (struct atmel_qspi *)dev_id; 393 u32 status, mask, pending; 394 395 status = qspi_readl(aq, QSPI_SR); 396 mask = qspi_readl(aq, QSPI_IMR); 397 pending = status & mask; 398 399 if (!pending) 400 return IRQ_NONE; 401 402 aq->pending |= pending; 403 if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) 404 complete(&aq->cmd_completion); 405 406 return IRQ_HANDLED; 407 } 408 409 static int atmel_qspi_probe(struct platform_device *pdev) 410 { 411 struct spi_controller *ctrl; 412 struct atmel_qspi *aq; 413 struct resource *res; 414 int irq, err = 0; 415 416 ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq)); 417 if (!ctrl) 418 return -ENOMEM; 419 420 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; 421 ctrl->setup = atmel_qspi_setup; 422 ctrl->bus_num = -1; 423 ctrl->mem_ops = &atmel_qspi_mem_ops; 424 ctrl->num_chipselect = 1; 425 ctrl->dev.of_node = pdev->dev.of_node; 426 platform_set_drvdata(pdev, ctrl); 427 428 aq = spi_controller_get_devdata(ctrl); 429 430 init_completion(&aq->cmd_completion); 431 aq->pdev = pdev; 432 433 /* Map the registers */ 434 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base"); 435 aq->regs = devm_ioremap_resource(&pdev->dev, res); 436 if (IS_ERR(aq->regs)) { 437 dev_err(&pdev->dev, "missing registers\n"); 438 err = PTR_ERR(aq->regs); 439 goto exit; 440 } 441 442 /* Map the AHB memory */ 443 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap"); 444 aq->mem = devm_ioremap_resource(&pdev->dev, res); 445 if (IS_ERR(aq->mem)) { 446 dev_err(&pdev->dev, "missing AHB memory\n"); 447 err = PTR_ERR(aq->mem); 448 goto exit; 449 } 450 451 /* Get the peripheral clock */ 452 aq->clk = devm_clk_get(&pdev->dev, NULL); 453 if (IS_ERR(aq->clk)) { 454 dev_err(&pdev->dev, "missing peripheral clock\n"); 455 err = PTR_ERR(aq->clk); 456 goto exit; 457 } 458 459 /* Enable the peripheral clock */ 460 err = clk_prepare_enable(aq->clk); 461 if (err) { 462 dev_err(&pdev->dev, "failed to enable the peripheral clock\n"); 463 goto exit; 464 } 465 466 /* Request the IRQ */ 467 irq = platform_get_irq(pdev, 0); 468 if (irq < 0) { 469 dev_err(&pdev->dev, "missing IRQ\n"); 470 err = irq; 471 goto disable_clk; 472 } 473 err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt, 474 0, dev_name(&pdev->dev), aq); 475 if (err) 476 goto disable_clk; 477 478 err = atmel_qspi_init(aq); 479 if (err) 480 goto disable_clk; 481 482 err = spi_register_controller(ctrl); 483 if (err) 484 goto disable_clk; 485 486 return 0; 487 488 disable_clk: 489 clk_disable_unprepare(aq->clk); 490 exit: 491 spi_controller_put(ctrl); 492 493 return err; 494 } 495 496 static int atmel_qspi_remove(struct platform_device *pdev) 497 { 498 struct spi_controller *ctrl = platform_get_drvdata(pdev); 499 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); 500 501 spi_unregister_controller(ctrl); 502 qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS); 503 clk_disable_unprepare(aq->clk); 504 return 0; 505 } 506 507 static int __maybe_unused atmel_qspi_suspend(struct device *dev) 508 { 509 struct atmel_qspi *aq = dev_get_drvdata(dev); 510 511 clk_disable_unprepare(aq->clk); 512 513 return 0; 514 } 515 516 static int __maybe_unused atmel_qspi_resume(struct device *dev) 517 { 518 struct atmel_qspi *aq = dev_get_drvdata(dev); 519 520 clk_prepare_enable(aq->clk); 521 522 return atmel_qspi_init(aq); 523 } 524 525 static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend, 526 atmel_qspi_resume); 527 528 static const struct of_device_id atmel_qspi_dt_ids[] = { 529 { .compatible = "atmel,sama5d2-qspi" }, 530 { /* sentinel */ } 531 }; 532 533 MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids); 534 535 static struct platform_driver atmel_qspi_driver = { 536 .driver = { 537 .name = "atmel_qspi", 538 .of_match_table = atmel_qspi_dt_ids, 539 .pm = &atmel_qspi_pm_ops, 540 }, 541 .probe = atmel_qspi_probe, 542 .remove = atmel_qspi_remove, 543 }; 544 module_platform_driver(atmel_qspi_driver); 545 546 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>"); 547 MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com"); 548 MODULE_DESCRIPTION("Atmel QSPI Controller driver"); 549 MODULE_LICENSE("GPL v2"); 550