1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // Copyright(c) 2023 Intel Corporation 3 4 /* 5 * Soundwire Intel ops for LunarLake 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/cleanup.h> 10 #include <linux/device.h> 11 #include <linux/soundwire/sdw_registers.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_intel.h> 14 #include <linux/string_choices.h> 15 #include <sound/hdaudio.h> 16 #include <sound/hda-mlink.h> 17 #include <sound/hda-sdw-bpt.h> 18 #include <sound/hda_register.h> 19 #include <sound/pcm_params.h> 20 #include "cadence_master.h" 21 #include "bus.h" 22 #include "intel.h" 23 24 static int sdw_slave_bpt_stream_add(struct sdw_slave *slave, struct sdw_stream_runtime *stream) 25 { 26 struct sdw_stream_config sconfig = {0}; 27 struct sdw_port_config pconfig = {0}; 28 int ret; 29 30 /* arbitrary configuration */ 31 sconfig.frame_rate = 16000; 32 sconfig.ch_count = 1; 33 sconfig.bps = 32; /* this is required for BPT/BRA */ 34 sconfig.direction = SDW_DATA_DIR_RX; 35 sconfig.type = SDW_STREAM_BPT; 36 37 pconfig.num = 0; 38 pconfig.ch_mask = BIT(0); 39 40 ret = sdw_stream_add_slave(slave, &sconfig, &pconfig, 1, stream); 41 if (ret) 42 dev_err(&slave->dev, "%s: failed: %d\n", __func__, ret); 43 44 return ret; 45 } 46 47 #define READ_PDI1_MIN_SIZE 12 48 49 static int intel_ace2x_bpt_open_stream(struct sdw_intel *sdw, struct sdw_slave *slave, 50 struct sdw_bpt_msg *msg) 51 { 52 struct sdw_cdns *cdns = &sdw->cdns; 53 struct sdw_bus *bus = &cdns->bus; 54 struct sdw_master_prop *prop = &bus->prop; 55 struct sdw_stream_runtime *stream; 56 struct sdw_stream_config sconfig; 57 struct sdw_port_config *pconfig; 58 unsigned int pdi0_buf_size_pre_frame; 59 unsigned int pdi1_buf_size_pre_frame; 60 unsigned int max_data_per_frame; 61 unsigned int pdi0_buffer_size_; 62 unsigned int pdi1_buffer_size_; 63 unsigned int pdi0_buffer_size; 64 unsigned int tx_dma_bandwidth; 65 unsigned int pdi1_buffer_size; 66 unsigned int rx_dma_bandwidth; 67 unsigned int fake_num_frames; 68 unsigned int data_per_frame; 69 unsigned int tx_total_bytes; 70 struct sdw_cdns_pdi *pdi0; 71 struct sdw_cdns_pdi *pdi1; 72 unsigned int rx_alignment; 73 unsigned int tx_alignment; 74 unsigned int num_frames_; 75 unsigned int num_frames; 76 unsigned int fake_size; 77 unsigned int tx_pad; 78 unsigned int rx_pad; 79 int command; 80 int ret1; 81 int ret; 82 int dir; 83 int len; 84 int i; 85 86 if (cdns->bus.bpt_stream) { 87 dev_err(cdns->dev, "%s: BPT stream already exists\n", __func__); 88 return -EAGAIN; 89 } 90 91 stream = sdw_alloc_stream("BPT", SDW_STREAM_BPT); 92 if (!stream) 93 return -ENOMEM; 94 95 cdns->bus.bpt_stream = stream; 96 97 ret = sdw_slave_bpt_stream_add(slave, stream); 98 if (ret < 0) 99 goto release_stream; 100 101 /* handle PDI0 first */ 102 dir = SDW_DATA_DIR_TX; 103 104 pdi0 = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, 1, dir, 0); 105 if (!pdi0) { 106 dev_err(cdns->dev, "%s: sdw_cdns_alloc_pdi0 failed\n", __func__); 107 ret = -EINVAL; 108 goto remove_slave; 109 } 110 111 sdw_cdns_config_stream(cdns, 1, dir, pdi0); 112 113 /* handle PDI1 */ 114 dir = SDW_DATA_DIR_RX; 115 116 pdi1 = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, 1, dir, 1); 117 if (!pdi1) { 118 dev_err(cdns->dev, "%s: sdw_cdns_alloc_pdi1 failed\n", __func__); 119 ret = -EINVAL; 120 goto remove_slave; 121 } 122 123 sdw_cdns_config_stream(cdns, 1, dir, pdi1); 124 125 /* 126 * the port config direction, number of channels and frame 127 * rate is totally arbitrary 128 */ 129 sconfig.direction = dir; 130 sconfig.ch_count = 1; 131 sconfig.frame_rate = 16000; 132 sconfig.type = SDW_STREAM_BPT; 133 sconfig.bps = 32; /* this is required for BPT/BRA */ 134 135 /* Port configuration */ 136 pconfig = kzalloc_objs(*pconfig, 2); 137 if (!pconfig) { 138 ret = -ENOMEM; 139 goto remove_slave; 140 } 141 142 for (i = 0; i < 2 /* num_pdi */; i++) { 143 pconfig[i].num = i; 144 pconfig[i].ch_mask = 1; 145 } 146 147 ret = sdw_stream_add_master(&cdns->bus, &sconfig, pconfig, 2, stream); 148 kfree(pconfig); 149 150 if (ret < 0) { 151 dev_err(cdns->dev, "add master to stream failed:%d\n", ret); 152 goto remove_slave; 153 } 154 155 ret = sdw_prepare_stream(cdns->bus.bpt_stream); 156 if (ret < 0) 157 goto remove_master; 158 159 command = (msg->flags & SDW_MSG_FLAG_WRITE) ? 0 : 1; 160 161 ret = sdw_cdns_bpt_find_bandwidth(command, cdns->bus.params.row, 162 cdns->bus.params.col, 163 prop->default_frame_rate, 164 &tx_dma_bandwidth, &rx_dma_bandwidth); 165 if (ret < 0) 166 goto deprepare_stream; 167 168 len = 0; 169 pdi0_buffer_size = 0; 170 pdi1_buffer_size = 0; 171 num_frames = 0; 172 173 if (slave->prop.bra_max_data_per_frame) { 174 max_data_per_frame = slave->prop.bra_max_data_per_frame; 175 if (max_data_per_frame > SDW_BRA_MAX_BYTES_PER_FRAME) { 176 dev_warn(&slave->dev, 177 "BRA max_data_per_frame %u exceeds limit %u, clamping\n", 178 max_data_per_frame, SDW_BRA_MAX_BYTES_PER_FRAME); 179 max_data_per_frame = SDW_BRA_MAX_BYTES_PER_FRAME; 180 } 181 } else { 182 max_data_per_frame = SDW_BRA_MAX_BYTES_PER_FRAME; 183 } 184 185 /* Add up pdi buffer size and frame numbers of each BPT sections */ 186 for (i = 0; i < msg->sections; i++) { 187 ret = sdw_cdns_bpt_find_buffer_sizes(command, cdns->bus.params.row, 188 cdns->bus.params.col, 189 msg->sec[i].len, max_data_per_frame, 190 slave->prop.bra_block_alignment, 191 &data_per_frame, &pdi0_buffer_size_, 192 &pdi1_buffer_size_, &num_frames_); 193 if (ret < 0) 194 goto deprepare_stream; 195 196 len += msg->sec[i].len; 197 pdi0_buffer_size += pdi0_buffer_size_; 198 pdi1_buffer_size += pdi1_buffer_size_; 199 num_frames += num_frames_; 200 } 201 202 sdw->bpt_ctx.pdi0_buffer_size = pdi0_buffer_size; 203 sdw->bpt_ctx.pdi1_buffer_size = pdi1_buffer_size; 204 sdw->bpt_ctx.num_frames = num_frames; 205 sdw->bpt_ctx.data_per_frame = data_per_frame; 206 207 rx_alignment = hda_sdw_bpt_get_buf_size_alignment(rx_dma_bandwidth); 208 tx_alignment = hda_sdw_bpt_get_buf_size_alignment(tx_dma_bandwidth); 209 210 if (command) { /* read */ 211 /* Get buffer size of a full frame */ 212 ret = sdw_cdns_bpt_find_buffer_sizes(command, cdns->bus.params.row, 213 cdns->bus.params.col, 214 data_per_frame, max_data_per_frame, 215 slave->prop.bra_block_alignment, 216 &data_per_frame, &pdi0_buf_size_pre_frame, 217 &pdi1_buf_size_pre_frame, &fake_num_frames); 218 if (ret < 0) 219 goto deprepare_stream; 220 221 /* find fake pdi1 buffer size */ 222 rx_pad = rx_alignment - (pdi1_buffer_size % rx_alignment); 223 while (rx_pad <= READ_PDI1_MIN_SIZE) 224 rx_pad += rx_alignment; 225 226 pdi1_buffer_size += rx_pad; 227 /* It is fine if we request more than enough byte to read */ 228 fake_num_frames = DIV_ROUND_UP(rx_pad, pdi1_buf_size_pre_frame); 229 fake_size = fake_num_frames * data_per_frame; 230 231 /* find fake pdi0 buffer size */ 232 pdi0_buffer_size += (fake_num_frames * pdi0_buf_size_pre_frame); 233 tx_pad = tx_alignment - (pdi0_buffer_size % tx_alignment); 234 pdi0_buffer_size += tx_pad; 235 } else { /* write */ 236 /* 237 * For the write command, the rx data block is 4, and the rx buffer size of a frame 238 * is 8. So the rx buffer size (pdi0_buffer_size) is always a multiple of rx 239 * alignment. 240 */ 241 tx_pad = tx_alignment - (pdi0_buffer_size % tx_alignment); 242 pdi0_buffer_size += tx_pad; 243 } 244 245 dev_dbg(cdns->dev, "Message len %d transferred in %d frames (%d per frame)\n", 246 len, num_frames, data_per_frame); 247 dev_dbg(cdns->dev, "sizes pdi0 %d pdi1 %d tx_bandwidth %d rx_bandwidth %d\n", 248 pdi0_buffer_size, pdi1_buffer_size, tx_dma_bandwidth, rx_dma_bandwidth); 249 250 ret = hda_sdw_bpt_open(cdns->dev->parent, /* PCI device */ 251 sdw->instance, &sdw->bpt_ctx.bpt_tx_stream, 252 &sdw->bpt_ctx.dmab_tx_bdl, pdi0_buffer_size, tx_dma_bandwidth, 253 &sdw->bpt_ctx.bpt_rx_stream, &sdw->bpt_ctx.dmab_rx_bdl, 254 pdi1_buffer_size, rx_dma_bandwidth); 255 if (ret < 0) { 256 dev_err(cdns->dev, "%s: hda_sdw_bpt_open failed %d\n", __func__, ret); 257 goto deprepare_stream; 258 } 259 260 if (!command) { 261 ret = sdw_cdns_prepare_write_dma_buffer(msg->dev_num, msg->sec, msg->sections, 262 data_per_frame, 263 sdw->bpt_ctx.dmab_tx_bdl.area, 264 pdi0_buffer_size, &tx_total_bytes); 265 } else { 266 ret = sdw_cdns_prepare_read_dma_buffer(msg->dev_num, msg->sec, msg->sections, 267 data_per_frame, 268 sdw->bpt_ctx.dmab_tx_bdl.area, 269 pdi0_buffer_size, &tx_total_bytes, 270 fake_size); 271 } 272 273 if (!ret) 274 return 0; 275 276 dev_err(cdns->dev, "%s: sdw_prepare_%s_dma_buffer failed %d\n", 277 __func__, str_read_write(command), ret); 278 279 ret1 = hda_sdw_bpt_close(cdns->dev->parent, /* PCI device */ 280 sdw->instance, 281 sdw->bpt_ctx.bpt_tx_stream, &sdw->bpt_ctx.dmab_tx_bdl, 282 sdw->bpt_ctx.bpt_rx_stream, &sdw->bpt_ctx.dmab_rx_bdl); 283 if (ret1 < 0) 284 dev_err(cdns->dev, "%s: hda_sdw_bpt_close failed: ret %d\n", 285 __func__, ret1); 286 287 deprepare_stream: 288 sdw_deprepare_stream(cdns->bus.bpt_stream); 289 290 remove_master: 291 ret1 = sdw_stream_remove_master(&cdns->bus, cdns->bus.bpt_stream); 292 if (ret1 < 0) 293 dev_err(cdns->dev, "%s: remove master failed: %d\n", 294 __func__, ret1); 295 296 remove_slave: 297 ret1 = sdw_stream_remove_slave(slave, cdns->bus.bpt_stream); 298 if (ret1 < 0) 299 dev_err(cdns->dev, "%s: remove slave failed: %d\n", 300 __func__, ret1); 301 302 release_stream: 303 sdw_release_stream(cdns->bus.bpt_stream); 304 cdns->bus.bpt_stream = NULL; 305 306 return ret; 307 } 308 309 static void intel_ace2x_bpt_close_stream(struct sdw_intel *sdw, struct sdw_slave *slave, 310 struct sdw_bpt_msg *msg) 311 { 312 struct sdw_cdns *cdns = &sdw->cdns; 313 int ret; 314 315 ret = hda_sdw_bpt_close(cdns->dev->parent /* PCI device */, sdw->instance, 316 sdw->bpt_ctx.bpt_tx_stream, 317 &sdw->bpt_ctx.dmab_tx_bdl, sdw->bpt_ctx.bpt_rx_stream, 318 &sdw->bpt_ctx.dmab_rx_bdl); 319 if (ret < 0) 320 dev_err(cdns->dev, "%s: hda_sdw_bpt_close failed: ret %d\n", 321 __func__, ret); 322 323 ret = sdw_deprepare_stream(cdns->bus.bpt_stream); 324 if (ret < 0) 325 dev_err(cdns->dev, "%s: sdw_deprepare_stream failed: ret %d\n", 326 __func__, ret); 327 328 ret = sdw_stream_remove_master(&cdns->bus, cdns->bus.bpt_stream); 329 if (ret < 0) 330 dev_err(cdns->dev, "%s: remove master failed: %d\n", 331 __func__, ret); 332 333 ret = sdw_stream_remove_slave(slave, cdns->bus.bpt_stream); 334 if (ret < 0) 335 dev_err(cdns->dev, "%s: remove slave failed: %d\n", 336 __func__, ret); 337 338 sdw_release_stream(cdns->bus.bpt_stream); 339 cdns->bus.bpt_stream = NULL; 340 } 341 342 #define INTEL_BPT_MSG_BYTE_MIN 16 343 344 static int intel_ace2x_bpt_send_async(struct sdw_intel *sdw, struct sdw_slave *slave, 345 struct sdw_bpt_msg *msg) 346 { 347 struct sdw_cdns *cdns = &sdw->cdns; 348 int len = 0; 349 int ret; 350 int i; 351 352 for (i = 0; i < msg->sections; i++) 353 len += msg->sec[i].len; 354 355 if (len < INTEL_BPT_MSG_BYTE_MIN) { 356 dev_err(cdns->dev, "BPT message length %d is less than the minimum bytes %d\n", 357 len, INTEL_BPT_MSG_BYTE_MIN); 358 return -EINVAL; 359 } 360 361 dev_dbg(cdns->dev, "BPT Transfer start\n"); 362 363 ret = intel_ace2x_bpt_open_stream(sdw, slave, msg); 364 if (ret < 0) 365 return ret; 366 367 ret = hda_sdw_bpt_send_async(cdns->dev->parent, /* PCI device */ 368 sdw->bpt_ctx.bpt_tx_stream, sdw->bpt_ctx.bpt_rx_stream); 369 if (ret < 0) { 370 dev_err(cdns->dev, "%s: hda_sdw_bpt_send_async failed: %d\n", 371 __func__, ret); 372 373 intel_ace2x_bpt_close_stream(sdw, slave, msg); 374 375 return ret; 376 } 377 378 ret = sdw_enable_stream(cdns->bus.bpt_stream); 379 if (ret < 0) { 380 dev_err(cdns->dev, "%s: sdw_stream_enable failed: %d\n", 381 __func__, ret); 382 intel_ace2x_bpt_close_stream(sdw, slave, msg); 383 } 384 385 return ret; 386 } 387 388 static int intel_ace2x_bpt_wait(struct sdw_intel *sdw, struct sdw_slave *slave, 389 struct sdw_bpt_msg *msg) 390 { 391 struct sdw_cdns *cdns = &sdw->cdns; 392 int ret; 393 394 dev_dbg(cdns->dev, "BPT Transfer wait\n"); 395 396 ret = hda_sdw_bpt_wait(cdns->dev->parent, /* PCI device */ 397 sdw->bpt_ctx.bpt_tx_stream, sdw->bpt_ctx.bpt_rx_stream); 398 if (ret < 0) 399 dev_err(cdns->dev, "%s: hda_sdw_bpt_wait failed: %d\n", __func__, ret); 400 401 ret = sdw_disable_stream(cdns->bus.bpt_stream); 402 if (ret < 0) { 403 dev_err(cdns->dev, "%s: sdw_stream_enable failed: %d\n", 404 __func__, ret); 405 goto err; 406 } 407 408 if (msg->flags & SDW_MSG_FLAG_WRITE) { 409 ret = sdw_cdns_check_write_response(cdns->dev, sdw->bpt_ctx.dmab_rx_bdl.area, 410 sdw->bpt_ctx.pdi1_buffer_size, 411 sdw->bpt_ctx.num_frames); 412 if (ret < 0) 413 dev_err(cdns->dev, "%s: BPT Write failed %d\n", __func__, ret); 414 } else { 415 ret = sdw_cdns_check_read_response(cdns->dev, sdw->bpt_ctx.dmab_rx_bdl.area, 416 sdw->bpt_ctx.pdi1_buffer_size, 417 msg->sec, msg->sections, sdw->bpt_ctx.num_frames, 418 sdw->bpt_ctx.data_per_frame); 419 if (ret < 0) 420 dev_err(cdns->dev, "%s: BPT Read failed %d\n", __func__, ret); 421 } 422 423 err: 424 intel_ace2x_bpt_close_stream(sdw, slave, msg); 425 426 return ret; 427 } 428 429 /* 430 * shim vendor-specific (vs) ops 431 */ 432 433 static void intel_shim_vs_init(struct sdw_intel *sdw) 434 { 435 void __iomem *shim_vs = sdw->link_res->shim_vs; 436 struct sdw_bus *bus = &sdw->cdns.bus; 437 struct sdw_intel_prop *intel_prop; 438 u16 clde; 439 u16 doaise2; 440 u16 dodse2; 441 u16 clds; 442 u16 clss; 443 u16 doaise; 444 u16 doais; 445 u16 dodse; 446 u16 dods; 447 u16 act; 448 449 intel_prop = bus->vendor_specific_prop; 450 clde = intel_prop->clde; 451 doaise2 = intel_prop->doaise2; 452 dodse2 = intel_prop->dodse2; 453 clds = intel_prop->clds; 454 clss = intel_prop->clss; 455 doaise = intel_prop->doaise; 456 doais = intel_prop->doais; 457 dodse = intel_prop->dodse; 458 dods = intel_prop->dods; 459 460 act = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL); 461 u16p_replace_bits(&act, clde, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE); 462 u16p_replace_bits(&act, doaise2, SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2); 463 u16p_replace_bits(&act, dodse2, SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2); 464 u16p_replace_bits(&act, clds, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS); 465 u16p_replace_bits(&act, clss, SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS); 466 u16p_replace_bits(&act, doaise, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE); 467 u16p_replace_bits(&act, doais, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS); 468 u16p_replace_bits(&act, dodse, SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE); 469 u16p_replace_bits(&act, dods, SDW_SHIM2_INTEL_VS_ACTMCTL_DODS); 470 act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE; 471 intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL, act); 472 usleep_range(10, 15); 473 } 474 475 static void intel_shim_vs_set_clock_source(struct sdw_intel *sdw, u32 source) 476 { 477 void __iomem *shim_vs = sdw->link_res->shim_vs; 478 u32 val; 479 480 val = intel_readl(shim_vs, SDW_SHIM2_INTEL_VS_LVSCTL); 481 482 u32p_replace_bits(&val, source, SDW_SHIM2_INTEL_VS_LVSCTL_MLCS); 483 484 intel_writel(shim_vs, SDW_SHIM2_INTEL_VS_LVSCTL, val); 485 486 dev_dbg(sdw->cdns.dev, "clock source %d LVSCTL %#x\n", source, val); 487 } 488 489 static int intel_shim_check_wake(struct sdw_intel *sdw) 490 { 491 /* 492 * We follow the HDaudio example and resume unconditionally 493 * without checking the WAKESTS bit for that specific link 494 */ 495 496 return 1; 497 } 498 499 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) 500 { 501 u16 lsdiid = 0; 502 u16 wake_en; 503 u16 wake_sts; 504 int ret; 505 506 mutex_lock(sdw->link_res->shim_lock); 507 508 ret = hdac_bus_eml_sdw_get_lsdiid_unlocked(sdw->link_res->hbus, sdw->instance, &lsdiid); 509 if (ret < 0) 510 goto unlock; 511 512 wake_en = snd_hdac_chip_readw(sdw->link_res->hbus, WAKEEN); 513 514 if (wake_enable) { 515 /* Enable the wakeup */ 516 wake_en |= lsdiid; 517 518 snd_hdac_chip_writew(sdw->link_res->hbus, WAKEEN, wake_en); 519 } else { 520 /* Disable the wake up interrupt */ 521 wake_en &= ~lsdiid; 522 snd_hdac_chip_writew(sdw->link_res->hbus, WAKEEN, wake_en); 523 524 /* Clear wake status (W1C) */ 525 wake_sts = snd_hdac_chip_readw(sdw->link_res->hbus, STATESTS); 526 wake_sts |= lsdiid; 527 snd_hdac_chip_writew(sdw->link_res->hbus, STATESTS, wake_sts); 528 } 529 unlock: 530 mutex_unlock(sdw->link_res->shim_lock); 531 } 532 533 static int intel_link_power_up(struct sdw_intel *sdw) 534 { 535 struct sdw_bus *bus = &sdw->cdns.bus; 536 struct sdw_master_prop *prop = &bus->prop; 537 u32 *shim_mask = sdw->link_res->shim_mask; 538 unsigned int link_id = sdw->instance; 539 u32 clock_source; 540 u32 syncprd; 541 int ret; 542 543 if (prop->mclk_freq % 6000000) { 544 if (prop->mclk_freq % 2400000) { 545 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24_576; 546 clock_source = SDW_SHIM2_MLCS_CARDINAL_CLK; 547 } else { 548 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; 549 clock_source = SDW_SHIM2_MLCS_XTAL_CLK; 550 } 551 } else { 552 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_96; 553 clock_source = SDW_SHIM2_MLCS_AUDIO_PLL_CLK; 554 } 555 556 mutex_lock(sdw->link_res->shim_lock); 557 558 ret = hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, link_id); 559 if (ret < 0) { 560 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_up failed: %d\n", 561 __func__, ret); 562 goto out; 563 } 564 565 intel_shim_vs_set_clock_source(sdw, clock_source); 566 567 if (!*shim_mask) { 568 /* we first need to program the SyncPRD/CPU registers */ 569 dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n"); 570 571 ret = hdac_bus_eml_sdw_set_syncprd_unlocked(sdw->link_res->hbus, syncprd); 572 if (ret < 0) { 573 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_set_syncprd failed: %d\n", 574 __func__, ret); 575 goto out; 576 } 577 578 /* SYNCPU will change once link is active */ 579 ret = hdac_bus_eml_sdw_wait_syncpu_unlocked(sdw->link_res->hbus); 580 if (ret < 0) { 581 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_wait_syncpu failed: %d\n", 582 __func__, ret); 583 goto out; 584 } 585 586 hdac_bus_eml_enable_interrupt_unlocked(sdw->link_res->hbus, true, 587 AZX_REG_ML_LEPTR_ID_SDW, true); 588 } 589 590 *shim_mask |= BIT(link_id); 591 592 sdw->cdns.link_up = true; 593 594 intel_shim_vs_init(sdw); 595 596 out: 597 mutex_unlock(sdw->link_res->shim_lock); 598 599 return ret; 600 } 601 602 static int intel_link_power_down(struct sdw_intel *sdw) 603 { 604 u32 *shim_mask = sdw->link_res->shim_mask; 605 unsigned int link_id = sdw->instance; 606 int ret; 607 608 mutex_lock(sdw->link_res->shim_lock); 609 610 sdw->cdns.link_up = false; 611 612 *shim_mask &= ~BIT(link_id); 613 614 if (!*shim_mask) 615 hdac_bus_eml_enable_interrupt_unlocked(sdw->link_res->hbus, true, 616 AZX_REG_ML_LEPTR_ID_SDW, false); 617 618 ret = hdac_bus_eml_sdw_power_down_unlocked(sdw->link_res->hbus, link_id); 619 if (ret < 0) { 620 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_down failed: %d\n", 621 __func__, ret); 622 623 /* 624 * we leave the sdw->cdns.link_up flag as false since we've disabled 625 * the link at this point and cannot handle interrupts any longer. 626 */ 627 } 628 629 mutex_unlock(sdw->link_res->shim_lock); 630 631 return ret; 632 } 633 634 static void intel_sync_arm(struct sdw_intel *sdw) 635 { 636 unsigned int link_id = sdw->instance; 637 638 mutex_lock(sdw->link_res->shim_lock); 639 640 hdac_bus_eml_sdw_sync_arm_unlocked(sdw->link_res->hbus, link_id); 641 642 mutex_unlock(sdw->link_res->shim_lock); 643 } 644 645 static int intel_sync_go_unlocked(struct sdw_intel *sdw) 646 { 647 int ret; 648 649 ret = hdac_bus_eml_sdw_sync_go_unlocked(sdw->link_res->hbus); 650 if (ret < 0) 651 dev_err(sdw->cdns.dev, "%s: SyncGO clear failed: %d\n", __func__, ret); 652 653 return ret; 654 } 655 656 static int intel_sync_go(struct sdw_intel *sdw) 657 { 658 int ret; 659 660 mutex_lock(sdw->link_res->shim_lock); 661 662 ret = intel_sync_go_unlocked(sdw); 663 664 mutex_unlock(sdw->link_res->shim_lock); 665 666 return ret; 667 } 668 669 static bool intel_check_cmdsync_unlocked(struct sdw_intel *sdw) 670 { 671 return hdac_bus_eml_sdw_check_cmdsync_unlocked(sdw->link_res->hbus); 672 } 673 674 /* DAI callbacks */ 675 static int intel_params_stream(struct sdw_intel *sdw, 676 struct snd_pcm_substream *substream, 677 struct snd_soc_dai *dai, 678 struct snd_pcm_hw_params *hw_params, 679 int link_id, int alh_stream_id) 680 { 681 struct sdw_intel_link_res *res = sdw->link_res; 682 struct sdw_intel_stream_params_data params_data; 683 684 params_data.substream = substream; 685 params_data.dai = dai; 686 params_data.hw_params = hw_params; 687 params_data.link_id = link_id; 688 params_data.alh_stream_id = alh_stream_id; 689 690 if (res->ops && res->ops->params_stream && res->dev) 691 return res->ops->params_stream(res->dev, 692 ¶ms_data); 693 return -EIO; 694 } 695 696 static int intel_free_stream(struct sdw_intel *sdw, 697 struct snd_pcm_substream *substream, 698 struct snd_soc_dai *dai, 699 int link_id) 700 701 { 702 struct sdw_intel_link_res *res = sdw->link_res; 703 struct sdw_intel_stream_free_data free_data; 704 705 free_data.substream = substream; 706 free_data.dai = dai; 707 free_data.link_id = link_id; 708 709 if (res->ops && res->ops->free_stream && res->dev) 710 return res->ops->free_stream(res->dev, 711 &free_data); 712 713 return 0; 714 } 715 716 /* 717 * DAI operations 718 */ 719 static int intel_hw_params(struct snd_pcm_substream *substream, 720 struct snd_pcm_hw_params *params, 721 struct snd_soc_dai *dai) 722 { 723 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 724 struct sdw_intel *sdw = cdns_to_intel(cdns); 725 struct sdw_cdns_dai_runtime *dai_runtime; 726 struct sdw_cdns_pdi *pdi; 727 struct sdw_stream_config sconfig; 728 int ch, dir; 729 int ret; 730 731 dai_runtime = cdns->dai_runtime_array[dai->id]; 732 if (!dai_runtime) 733 return -EIO; 734 735 ch = params_channels(params); 736 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 737 dir = SDW_DATA_DIR_RX; 738 else 739 dir = SDW_DATA_DIR_TX; 740 741 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id); 742 if (!pdi) 743 return -EINVAL; 744 745 /* use same definitions for alh_id as previous generations */ 746 pdi->intel_alh_id = (sdw->instance * 16) + pdi->num + 3; 747 if (pdi->num >= 2) 748 pdi->intel_alh_id += 2; 749 750 /* the SHIM will be configured in the callback functions */ 751 752 sdw_cdns_config_stream(cdns, ch, dir, pdi); 753 754 /* store pdi and state, may be needed in prepare step */ 755 dai_runtime->paused = false; 756 dai_runtime->suspended = false; 757 dai_runtime->pdi = pdi; 758 759 /* Inform DSP about PDI stream number */ 760 ret = intel_params_stream(sdw, substream, dai, params, 761 sdw->instance, 762 pdi->intel_alh_id); 763 if (ret) 764 return ret; 765 766 sconfig.direction = dir; 767 sconfig.ch_count = ch; 768 sconfig.frame_rate = params_rate(params); 769 sconfig.type = dai_runtime->stream_type; 770 771 sconfig.bps = snd_pcm_format_width(params_format(params)); 772 773 /* Port configuration */ 774 struct sdw_port_config *pconfig __free(kfree) = kzalloc_obj(*pconfig); 775 if (!pconfig) 776 return -ENOMEM; 777 778 pconfig->num = pdi->num; 779 pconfig->ch_mask = (1 << ch) - 1; 780 781 ret = sdw_stream_add_master(&cdns->bus, &sconfig, 782 pconfig, 1, dai_runtime->stream); 783 if (ret) 784 dev_err(cdns->dev, "add master to stream failed:%d\n", ret); 785 786 return ret; 787 } 788 789 static int intel_prepare(struct snd_pcm_substream *substream, 790 struct snd_soc_dai *dai) 791 { 792 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 793 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 794 struct sdw_intel *sdw = cdns_to_intel(cdns); 795 struct sdw_cdns_dai_runtime *dai_runtime; 796 struct snd_pcm_hw_params *hw_params; 797 int ch, dir; 798 799 dai_runtime = cdns->dai_runtime_array[dai->id]; 800 if (!dai_runtime) { 801 dev_err(dai->dev, "failed to get dai runtime in %s\n", 802 __func__); 803 return -EIO; 804 } 805 806 hw_params = &rtd->dpcm[substream->stream].hw_params; 807 if (dai_runtime->suspended) { 808 dai_runtime->suspended = false; 809 810 /* 811 * .prepare() is called after system resume, where we 812 * need to reinitialize the SHIM/ALH/Cadence IP. 813 * .prepare() is also called to deal with underflows, 814 * but in those cases we cannot touch ALH/SHIM 815 * registers 816 */ 817 818 /* configure stream */ 819 ch = params_channels(hw_params); 820 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 821 dir = SDW_DATA_DIR_RX; 822 else 823 dir = SDW_DATA_DIR_TX; 824 825 /* the SHIM will be configured in the callback functions */ 826 827 sdw_cdns_config_stream(cdns, ch, dir, dai_runtime->pdi); 828 } 829 830 /* Inform DSP about PDI stream number */ 831 return intel_params_stream(sdw, substream, dai, hw_params, sdw->instance, 832 dai_runtime->pdi->intel_alh_id); 833 } 834 835 static int 836 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 837 { 838 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 839 struct sdw_intel *sdw = cdns_to_intel(cdns); 840 struct sdw_cdns_dai_runtime *dai_runtime; 841 int ret; 842 843 dai_runtime = cdns->dai_runtime_array[dai->id]; 844 if (!dai_runtime) 845 return -EIO; 846 847 /* 848 * The sdw stream state will transition to RELEASED when stream-> 849 * master_list is empty. So the stream state will transition to 850 * DEPREPARED for the first cpu-dai and to RELEASED for the last 851 * cpu-dai. 852 */ 853 ret = sdw_stream_remove_master(&cdns->bus, dai_runtime->stream); 854 if (ret < 0) { 855 dev_err(dai->dev, "remove master from stream %s failed: %d\n", 856 dai_runtime->stream->name, ret); 857 return ret; 858 } 859 860 ret = intel_free_stream(sdw, substream, dai, sdw->instance); 861 if (ret < 0) { 862 dev_err(dai->dev, "intel_free_stream: failed %d\n", ret); 863 return ret; 864 } 865 866 dai_runtime->pdi = NULL; 867 868 return 0; 869 } 870 871 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, 872 void *stream, int direction) 873 { 874 return cdns_set_sdw_stream(dai, stream, direction); 875 } 876 877 static void *intel_get_sdw_stream(struct snd_soc_dai *dai, 878 int direction) 879 { 880 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 881 struct sdw_cdns_dai_runtime *dai_runtime; 882 883 dai_runtime = cdns->dai_runtime_array[dai->id]; 884 if (!dai_runtime) 885 return ERR_PTR(-EINVAL); 886 887 return dai_runtime->stream; 888 } 889 890 static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) 891 { 892 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 893 struct sdw_intel *sdw = cdns_to_intel(cdns); 894 struct sdw_intel_link_res *res = sdw->link_res; 895 struct sdw_cdns_dai_runtime *dai_runtime; 896 int ret = 0; 897 898 /* 899 * The .trigger callback is used to program HDaudio DMA and send required IPC to audio 900 * firmware. 901 */ 902 if (res->ops && res->ops->trigger) { 903 ret = res->ops->trigger(substream, cmd, dai); 904 if (ret < 0) 905 return ret; 906 } 907 908 dai_runtime = cdns->dai_runtime_array[dai->id]; 909 if (!dai_runtime) { 910 dev_err(dai->dev, "failed to get dai runtime in %s\n", 911 __func__); 912 return -EIO; 913 } 914 915 switch (cmd) { 916 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 917 dai_runtime->paused = true; 918 break; 919 case SNDRV_PCM_TRIGGER_STOP: 920 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 921 dai_runtime->paused = false; 922 break; 923 default: 924 break; 925 } 926 927 return ret; 928 } 929 930 static const struct snd_soc_dai_ops intel_pcm_dai_ops = { 931 .hw_params = intel_hw_params, 932 .prepare = intel_prepare, 933 .hw_free = intel_hw_free, 934 .trigger = intel_trigger, 935 .set_stream = intel_pcm_set_sdw_stream, 936 .get_stream = intel_get_sdw_stream, 937 }; 938 939 static int intel_component_dais_suspend(struct snd_soc_component *component) 940 { 941 struct snd_soc_dai *dai; 942 943 /* 944 * Mark all open streams as suspended. 945 * Open streams at this point can be in SUSPENDED, PAUSED or STOPPED 946 * state and during prepare the DMAs and SHIM registers need to be 947 * initialized for them. 948 * The STOPPED state is a special corner case which can happen if audio 949 * experiences xrun at suspend time. 950 */ 951 for_each_component_dais(component, dai) { 952 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 953 struct sdw_cdns_dai_runtime *dai_runtime; 954 955 dai_runtime = cdns->dai_runtime_array[dai->id]; 956 957 if (dai_runtime) 958 dai_runtime->suspended = true; 959 } 960 961 return 0; 962 } 963 964 static const struct snd_soc_component_driver dai_component = { 965 .name = "soundwire", 966 .suspend = intel_component_dais_suspend, 967 }; 968 969 /* 970 * PDI routines 971 */ 972 static void intel_pdi_init(struct sdw_intel *sdw, 973 struct sdw_cdns_stream_config *config) 974 { 975 void __iomem *shim = sdw->link_res->shim; 976 int pcm_cap; 977 978 /* PCM Stream Capability */ 979 pcm_cap = intel_readw(shim, SDW_SHIM2_PCMSCAP); 980 981 config->pcm_bd = FIELD_GET(SDW_SHIM2_PCMSCAP_BSS, pcm_cap); 982 config->pcm_in = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap); 983 config->pcm_out = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap); 984 985 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", 986 config->pcm_bd, config->pcm_in, config->pcm_out); 987 } 988 989 static int 990 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num) 991 { 992 void __iomem *shim = sdw->link_res->shim; 993 994 /* zero based values for channel count in register */ 995 return intel_readw(shim, SDW_SHIM2_PCMSYCHC(pdi_num)) + 1; 996 } 997 998 static void intel_pdi_get_ch_update(struct sdw_intel *sdw, 999 struct sdw_cdns_pdi *pdi, 1000 unsigned int num_pdi, 1001 unsigned int *num_ch) 1002 { 1003 int ch_count = 0; 1004 int i; 1005 1006 for (i = 0; i < num_pdi; i++) { 1007 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num); 1008 ch_count += pdi->ch_count; 1009 pdi++; 1010 } 1011 1012 *num_ch = ch_count; 1013 } 1014 1015 static void intel_pdi_stream_ch_update(struct sdw_intel *sdw, 1016 struct sdw_cdns_streams *stream) 1017 { 1018 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, 1019 &stream->num_ch_bd); 1020 1021 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, 1022 &stream->num_ch_in); 1023 1024 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, 1025 &stream->num_ch_out); 1026 } 1027 1028 static int intel_create_dai(struct sdw_cdns *cdns, 1029 struct snd_soc_dai_driver *dais, 1030 enum intel_pdi_type type, 1031 u32 num, u32 off, u32 max_ch) 1032 { 1033 int i; 1034 1035 if (!num) 1036 return 0; 1037 1038 for (i = off; i < (off + num); i++) { 1039 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL, 1040 "SDW%d Pin%d", 1041 cdns->instance, i); 1042 if (!dais[i].name) 1043 return -ENOMEM; 1044 1045 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { 1046 dais[i].playback.channels_min = 1; 1047 dais[i].playback.channels_max = max_ch; 1048 } 1049 1050 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { 1051 dais[i].capture.channels_min = 1; 1052 dais[i].capture.channels_max = max_ch; 1053 } 1054 1055 dais[i].ops = &intel_pcm_dai_ops; 1056 } 1057 1058 return 0; 1059 } 1060 1061 static int intel_register_dai(struct sdw_intel *sdw) 1062 { 1063 struct sdw_cdns_dai_runtime **dai_runtime_array; 1064 struct sdw_cdns_stream_config config; 1065 struct sdw_cdns *cdns = &sdw->cdns; 1066 struct sdw_cdns_streams *stream; 1067 struct snd_soc_dai_driver *dais; 1068 int num_dai; 1069 int ret; 1070 int off = 0; 1071 1072 /* Read the PDI config and initialize cadence PDI */ 1073 intel_pdi_init(sdw, &config); 1074 ret = sdw_cdns_pdi_init(cdns, config); 1075 if (ret) 1076 return ret; 1077 1078 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm); 1079 1080 /* DAIs are created based on total number of PDIs supported */ 1081 num_dai = cdns->pcm.num_pdi; 1082 1083 dai_runtime_array = devm_kcalloc(cdns->dev, num_dai, 1084 sizeof(struct sdw_cdns_dai_runtime *), 1085 GFP_KERNEL); 1086 if (!dai_runtime_array) 1087 return -ENOMEM; 1088 cdns->dai_runtime_array = dai_runtime_array; 1089 1090 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); 1091 if (!dais) 1092 return -ENOMEM; 1093 1094 /* Create PCM DAIs */ 1095 stream = &cdns->pcm; 1096 1097 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in, 1098 off, stream->num_ch_in); 1099 if (ret) 1100 return ret; 1101 1102 off += cdns->pcm.num_in; 1103 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, 1104 off, stream->num_ch_out); 1105 if (ret) 1106 return ret; 1107 1108 off += cdns->pcm.num_out; 1109 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, 1110 off, stream->num_ch_bd); 1111 if (ret) 1112 return ret; 1113 1114 return devm_snd_soc_register_component(cdns->dev, &dai_component, 1115 dais, num_dai); 1116 } 1117 1118 static void intel_program_sdi(struct sdw_intel *sdw, int dev_num) 1119 { 1120 int ret; 1121 1122 ret = hdac_bus_eml_sdw_set_lsdiid(sdw->link_res->hbus, sdw->instance, dev_num); 1123 if (ret < 0) 1124 dev_err(sdw->cdns.dev, "%s: could not set lsdiid for link %d %d\n", 1125 __func__, sdw->instance, dev_num); 1126 } 1127 1128 static int intel_get_link_count(struct sdw_intel *sdw) 1129 { 1130 int ret; 1131 1132 ret = hdac_bus_eml_get_count(sdw->link_res->hbus, true, AZX_REG_ML_LEPTR_ID_SDW); 1133 if (!ret) { 1134 dev_err(sdw->cdns.dev, "%s: could not retrieve link count\n", __func__); 1135 return -ENODEV; 1136 } 1137 1138 if (ret > SDW_INTEL_MAX_LINKS) { 1139 dev_err(sdw->cdns.dev, "%s: link count %d exceed max %d\n", __func__, ret, SDW_INTEL_MAX_LINKS); 1140 return -EINVAL; 1141 } 1142 1143 return ret; 1144 } 1145 1146 const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops = { 1147 .debugfs_init = intel_ace2x_debugfs_init, 1148 .debugfs_exit = intel_ace2x_debugfs_exit, 1149 1150 .get_link_count = intel_get_link_count, 1151 1152 .register_dai = intel_register_dai, 1153 1154 .check_clock_stop = intel_check_clock_stop, 1155 .start_bus = intel_start_bus, 1156 .start_bus_after_reset = intel_start_bus_after_reset, 1157 .start_bus_after_clock_stop = intel_start_bus_after_clock_stop, 1158 .stop_bus = intel_stop_bus, 1159 1160 .link_power_up = intel_link_power_up, 1161 .link_power_down = intel_link_power_down, 1162 1163 .shim_check_wake = intel_shim_check_wake, 1164 .shim_wake = intel_shim_wake, 1165 1166 .pre_bank_switch = intel_pre_bank_switch, 1167 .post_bank_switch = intel_post_bank_switch, 1168 1169 .sync_arm = intel_sync_arm, 1170 .sync_go_unlocked = intel_sync_go_unlocked, 1171 .sync_go = intel_sync_go, 1172 .sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked, 1173 1174 .program_sdi = intel_program_sdi, 1175 1176 .bpt_send_async = intel_ace2x_bpt_send_async, 1177 .bpt_wait = intel_ace2x_bpt_wait, 1178 }; 1179 EXPORT_SYMBOL_NS(sdw_intel_lnl_hw_ops, "SOUNDWIRE_INTEL"); 1180 1181 MODULE_IMPORT_NS("SND_SOC_SOF_HDA_MLINK"); 1182 MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_HDA_SDW_BPT"); 1183