1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // Copyright(c) 2023 Intel Corporation 3 4 /* 5 * Soundwire Intel ops for LunarLake 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/cleanup.h> 10 #include <linux/device.h> 11 #include <linux/soundwire/sdw_registers.h> 12 #include <linux/soundwire/sdw.h> 13 #include <linux/soundwire/sdw_intel.h> 14 #include <linux/string_choices.h> 15 #include <sound/hdaudio.h> 16 #include <sound/hda-mlink.h> 17 #include <sound/hda-sdw-bpt.h> 18 #include <sound/hda_register.h> 19 #include <sound/pcm_params.h> 20 #include "cadence_master.h" 21 #include "bus.h" 22 #include "intel.h" 23 24 static int sdw_slave_bpt_stream_add(struct sdw_slave *slave, struct sdw_stream_runtime *stream) 25 { 26 struct sdw_stream_config sconfig = {0}; 27 struct sdw_port_config pconfig = {0}; 28 int ret; 29 30 /* arbitrary configuration */ 31 sconfig.frame_rate = 16000; 32 sconfig.ch_count = 1; 33 sconfig.bps = 32; /* this is required for BPT/BRA */ 34 sconfig.direction = SDW_DATA_DIR_RX; 35 sconfig.type = SDW_STREAM_BPT; 36 37 pconfig.num = 0; 38 pconfig.ch_mask = BIT(0); 39 40 ret = sdw_stream_add_slave(slave, &sconfig, &pconfig, 1, stream); 41 if (ret) 42 dev_err(&slave->dev, "%s: failed: %d\n", __func__, ret); 43 44 return ret; 45 } 46 47 #define READ_PDI1_MIN_SIZE 12 48 49 static int intel_ace2x_bpt_open_stream(struct sdw_intel *sdw, struct sdw_slave *slave, 50 struct sdw_bpt_msg *msg) 51 { 52 struct sdw_cdns *cdns = &sdw->cdns; 53 struct sdw_bus *bus = &cdns->bus; 54 struct sdw_master_prop *prop = &bus->prop; 55 struct sdw_stream_runtime *stream; 56 struct sdw_stream_config sconfig; 57 struct sdw_port_config *pconfig; 58 unsigned int pdi0_buf_size_pre_frame; 59 unsigned int pdi1_buf_size_pre_frame; 60 unsigned int pdi0_buffer_size_; 61 unsigned int pdi1_buffer_size_; 62 unsigned int pdi0_buffer_size; 63 unsigned int tx_dma_bandwidth; 64 unsigned int pdi1_buffer_size; 65 unsigned int rx_dma_bandwidth; 66 unsigned int fake_num_frames; 67 unsigned int data_per_frame; 68 unsigned int tx_total_bytes; 69 struct sdw_cdns_pdi *pdi0; 70 struct sdw_cdns_pdi *pdi1; 71 unsigned int rx_alignment; 72 unsigned int tx_alignment; 73 unsigned int num_frames_; 74 unsigned int num_frames; 75 unsigned int fake_size; 76 unsigned int tx_pad; 77 unsigned int rx_pad; 78 int command; 79 int ret1; 80 int ret; 81 int dir; 82 int len; 83 int i; 84 85 if (cdns->bus.bpt_stream) { 86 dev_err(cdns->dev, "%s: BPT stream already exists\n", __func__); 87 return -EAGAIN; 88 } 89 90 stream = sdw_alloc_stream("BPT", SDW_STREAM_BPT); 91 if (!stream) 92 return -ENOMEM; 93 94 cdns->bus.bpt_stream = stream; 95 96 ret = sdw_slave_bpt_stream_add(slave, stream); 97 if (ret < 0) 98 goto release_stream; 99 100 /* handle PDI0 first */ 101 dir = SDW_DATA_DIR_TX; 102 103 pdi0 = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, 1, dir, 0); 104 if (!pdi0) { 105 dev_err(cdns->dev, "%s: sdw_cdns_alloc_pdi0 failed\n", __func__); 106 ret = -EINVAL; 107 goto remove_slave; 108 } 109 110 sdw_cdns_config_stream(cdns, 1, dir, pdi0); 111 112 /* handle PDI1 */ 113 dir = SDW_DATA_DIR_RX; 114 115 pdi1 = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, 1, dir, 1); 116 if (!pdi1) { 117 dev_err(cdns->dev, "%s: sdw_cdns_alloc_pdi1 failed\n", __func__); 118 ret = -EINVAL; 119 goto remove_slave; 120 } 121 122 sdw_cdns_config_stream(cdns, 1, dir, pdi1); 123 124 /* 125 * the port config direction, number of channels and frame 126 * rate is totally arbitrary 127 */ 128 sconfig.direction = dir; 129 sconfig.ch_count = 1; 130 sconfig.frame_rate = 16000; 131 sconfig.type = SDW_STREAM_BPT; 132 sconfig.bps = 32; /* this is required for BPT/BRA */ 133 134 /* Port configuration */ 135 pconfig = kzalloc_objs(*pconfig, 2); 136 if (!pconfig) { 137 ret = -ENOMEM; 138 goto remove_slave; 139 } 140 141 for (i = 0; i < 2 /* num_pdi */; i++) { 142 pconfig[i].num = i; 143 pconfig[i].ch_mask = 1; 144 } 145 146 ret = sdw_stream_add_master(&cdns->bus, &sconfig, pconfig, 2, stream); 147 kfree(pconfig); 148 149 if (ret < 0) { 150 dev_err(cdns->dev, "add master to stream failed:%d\n", ret); 151 goto remove_slave; 152 } 153 154 ret = sdw_prepare_stream(cdns->bus.bpt_stream); 155 if (ret < 0) 156 goto remove_master; 157 158 command = (msg->flags & SDW_MSG_FLAG_WRITE) ? 0 : 1; 159 160 ret = sdw_cdns_bpt_find_bandwidth(command, cdns->bus.params.row, 161 cdns->bus.params.col, 162 prop->default_frame_rate, 163 &tx_dma_bandwidth, &rx_dma_bandwidth); 164 if (ret < 0) 165 goto deprepare_stream; 166 167 len = 0; 168 pdi0_buffer_size = 0; 169 pdi1_buffer_size = 0; 170 num_frames = 0; 171 /* Add up pdi buffer size and frame numbers of each BPT sections */ 172 for (i = 0; i < msg->sections; i++) { 173 ret = sdw_cdns_bpt_find_buffer_sizes(command, cdns->bus.params.row, 174 cdns->bus.params.col, 175 msg->sec[i].len, SDW_BPT_MSG_MAX_BYTES, 176 &data_per_frame, &pdi0_buffer_size_, 177 &pdi1_buffer_size_, &num_frames_); 178 if (ret < 0) 179 goto deprepare_stream; 180 181 len += msg->sec[i].len; 182 pdi0_buffer_size += pdi0_buffer_size_; 183 pdi1_buffer_size += pdi1_buffer_size_; 184 num_frames += num_frames_; 185 } 186 187 sdw->bpt_ctx.pdi0_buffer_size = pdi0_buffer_size; 188 sdw->bpt_ctx.pdi1_buffer_size = pdi1_buffer_size; 189 sdw->bpt_ctx.num_frames = num_frames; 190 sdw->bpt_ctx.data_per_frame = data_per_frame; 191 192 rx_alignment = hda_sdw_bpt_get_buf_size_alignment(rx_dma_bandwidth); 193 tx_alignment = hda_sdw_bpt_get_buf_size_alignment(tx_dma_bandwidth); 194 195 if (command) { /* read */ 196 /* Get buffer size of a full frame */ 197 ret = sdw_cdns_bpt_find_buffer_sizes(command, cdns->bus.params.row, 198 cdns->bus.params.col, 199 data_per_frame, SDW_BPT_MSG_MAX_BYTES, 200 &data_per_frame, &pdi0_buf_size_pre_frame, 201 &pdi1_buf_size_pre_frame, &fake_num_frames); 202 if (ret < 0) 203 goto deprepare_stream; 204 205 /* find fake pdi1 buffer size */ 206 rx_pad = rx_alignment - (pdi1_buffer_size % rx_alignment); 207 while (rx_pad <= READ_PDI1_MIN_SIZE) 208 rx_pad += rx_alignment; 209 210 pdi1_buffer_size += rx_pad; 211 /* It is fine if we request more than enough byte to read */ 212 fake_num_frames = DIV_ROUND_UP(rx_pad, pdi1_buf_size_pre_frame); 213 fake_size = fake_num_frames * data_per_frame; 214 215 /* find fake pdi0 buffer size */ 216 pdi0_buffer_size += (fake_num_frames * pdi0_buf_size_pre_frame); 217 tx_pad = tx_alignment - (pdi0_buffer_size % tx_alignment); 218 pdi0_buffer_size += tx_pad; 219 } else { /* write */ 220 /* 221 * For the write command, the rx data block is 4, and the rx buffer size of a frame 222 * is 8. So the rx buffer size (pdi0_buffer_size) is always a multiple of rx 223 * alignment. 224 */ 225 tx_pad = tx_alignment - (pdi0_buffer_size % tx_alignment); 226 pdi0_buffer_size += tx_pad; 227 } 228 229 dev_dbg(cdns->dev, "Message len %d transferred in %d frames (%d per frame)\n", 230 len, num_frames, data_per_frame); 231 dev_dbg(cdns->dev, "sizes pdi0 %d pdi1 %d tx_bandwidth %d rx_bandwidth %d\n", 232 pdi0_buffer_size, pdi1_buffer_size, tx_dma_bandwidth, rx_dma_bandwidth); 233 234 ret = hda_sdw_bpt_open(cdns->dev->parent, /* PCI device */ 235 sdw->instance, &sdw->bpt_ctx.bpt_tx_stream, 236 &sdw->bpt_ctx.dmab_tx_bdl, pdi0_buffer_size, tx_dma_bandwidth, 237 &sdw->bpt_ctx.bpt_rx_stream, &sdw->bpt_ctx.dmab_rx_bdl, 238 pdi1_buffer_size, rx_dma_bandwidth); 239 if (ret < 0) { 240 dev_err(cdns->dev, "%s: hda_sdw_bpt_open failed %d\n", __func__, ret); 241 goto deprepare_stream; 242 } 243 244 if (!command) { 245 ret = sdw_cdns_prepare_write_dma_buffer(msg->dev_num, msg->sec, msg->sections, 246 data_per_frame, 247 sdw->bpt_ctx.dmab_tx_bdl.area, 248 pdi0_buffer_size, &tx_total_bytes); 249 } else { 250 ret = sdw_cdns_prepare_read_dma_buffer(msg->dev_num, msg->sec, msg->sections, 251 data_per_frame, 252 sdw->bpt_ctx.dmab_tx_bdl.area, 253 pdi0_buffer_size, &tx_total_bytes, 254 fake_size); 255 } 256 257 if (!ret) 258 return 0; 259 260 dev_err(cdns->dev, "%s: sdw_prepare_%s_dma_buffer failed %d\n", 261 __func__, str_read_write(command), ret); 262 263 ret1 = hda_sdw_bpt_close(cdns->dev->parent, /* PCI device */ 264 sdw->instance, 265 sdw->bpt_ctx.bpt_tx_stream, &sdw->bpt_ctx.dmab_tx_bdl, 266 sdw->bpt_ctx.bpt_rx_stream, &sdw->bpt_ctx.dmab_rx_bdl); 267 if (ret1 < 0) 268 dev_err(cdns->dev, "%s: hda_sdw_bpt_close failed: ret %d\n", 269 __func__, ret1); 270 271 deprepare_stream: 272 sdw_deprepare_stream(cdns->bus.bpt_stream); 273 274 remove_master: 275 ret1 = sdw_stream_remove_master(&cdns->bus, cdns->bus.bpt_stream); 276 if (ret1 < 0) 277 dev_err(cdns->dev, "%s: remove master failed: %d\n", 278 __func__, ret1); 279 280 remove_slave: 281 ret1 = sdw_stream_remove_slave(slave, cdns->bus.bpt_stream); 282 if (ret1 < 0) 283 dev_err(cdns->dev, "%s: remove slave failed: %d\n", 284 __func__, ret1); 285 286 release_stream: 287 sdw_release_stream(cdns->bus.bpt_stream); 288 cdns->bus.bpt_stream = NULL; 289 290 return ret; 291 } 292 293 static void intel_ace2x_bpt_close_stream(struct sdw_intel *sdw, struct sdw_slave *slave, 294 struct sdw_bpt_msg *msg) 295 { 296 struct sdw_cdns *cdns = &sdw->cdns; 297 int ret; 298 299 ret = hda_sdw_bpt_close(cdns->dev->parent /* PCI device */, sdw->instance, 300 sdw->bpt_ctx.bpt_tx_stream, 301 &sdw->bpt_ctx.dmab_tx_bdl, sdw->bpt_ctx.bpt_rx_stream, 302 &sdw->bpt_ctx.dmab_rx_bdl); 303 if (ret < 0) 304 dev_err(cdns->dev, "%s: hda_sdw_bpt_close failed: ret %d\n", 305 __func__, ret); 306 307 ret = sdw_deprepare_stream(cdns->bus.bpt_stream); 308 if (ret < 0) 309 dev_err(cdns->dev, "%s: sdw_deprepare_stream failed: ret %d\n", 310 __func__, ret); 311 312 ret = sdw_stream_remove_master(&cdns->bus, cdns->bus.bpt_stream); 313 if (ret < 0) 314 dev_err(cdns->dev, "%s: remove master failed: %d\n", 315 __func__, ret); 316 317 ret = sdw_stream_remove_slave(slave, cdns->bus.bpt_stream); 318 if (ret < 0) 319 dev_err(cdns->dev, "%s: remove slave failed: %d\n", 320 __func__, ret); 321 322 sdw_release_stream(cdns->bus.bpt_stream); 323 cdns->bus.bpt_stream = NULL; 324 } 325 326 #define INTEL_BPT_MSG_BYTE_MIN 16 327 328 static int intel_ace2x_bpt_send_async(struct sdw_intel *sdw, struct sdw_slave *slave, 329 struct sdw_bpt_msg *msg) 330 { 331 struct sdw_cdns *cdns = &sdw->cdns; 332 int len = 0; 333 int ret; 334 int i; 335 336 for (i = 0; i < msg->sections; i++) 337 len += msg->sec[i].len; 338 339 if (len < INTEL_BPT_MSG_BYTE_MIN) { 340 dev_err(cdns->dev, "BPT message length %d is less than the minimum bytes %d\n", 341 len, INTEL_BPT_MSG_BYTE_MIN); 342 return -EINVAL; 343 } 344 345 dev_dbg(cdns->dev, "BPT Transfer start\n"); 346 347 ret = intel_ace2x_bpt_open_stream(sdw, slave, msg); 348 if (ret < 0) 349 return ret; 350 351 ret = hda_sdw_bpt_send_async(cdns->dev->parent, /* PCI device */ 352 sdw->bpt_ctx.bpt_tx_stream, sdw->bpt_ctx.bpt_rx_stream); 353 if (ret < 0) { 354 dev_err(cdns->dev, "%s: hda_sdw_bpt_send_async failed: %d\n", 355 __func__, ret); 356 357 intel_ace2x_bpt_close_stream(sdw, slave, msg); 358 359 return ret; 360 } 361 362 ret = sdw_enable_stream(cdns->bus.bpt_stream); 363 if (ret < 0) { 364 dev_err(cdns->dev, "%s: sdw_stream_enable failed: %d\n", 365 __func__, ret); 366 intel_ace2x_bpt_close_stream(sdw, slave, msg); 367 } 368 369 return ret; 370 } 371 372 static int intel_ace2x_bpt_wait(struct sdw_intel *sdw, struct sdw_slave *slave, 373 struct sdw_bpt_msg *msg) 374 { 375 struct sdw_cdns *cdns = &sdw->cdns; 376 int ret; 377 378 dev_dbg(cdns->dev, "BPT Transfer wait\n"); 379 380 ret = hda_sdw_bpt_wait(cdns->dev->parent, /* PCI device */ 381 sdw->bpt_ctx.bpt_tx_stream, sdw->bpt_ctx.bpt_rx_stream); 382 if (ret < 0) 383 dev_err(cdns->dev, "%s: hda_sdw_bpt_wait failed: %d\n", __func__, ret); 384 385 ret = sdw_disable_stream(cdns->bus.bpt_stream); 386 if (ret < 0) { 387 dev_err(cdns->dev, "%s: sdw_stream_enable failed: %d\n", 388 __func__, ret); 389 goto err; 390 } 391 392 if (msg->flags & SDW_MSG_FLAG_WRITE) { 393 ret = sdw_cdns_check_write_response(cdns->dev, sdw->bpt_ctx.dmab_rx_bdl.area, 394 sdw->bpt_ctx.pdi1_buffer_size, 395 sdw->bpt_ctx.num_frames); 396 if (ret < 0) 397 dev_err(cdns->dev, "%s: BPT Write failed %d\n", __func__, ret); 398 } else { 399 ret = sdw_cdns_check_read_response(cdns->dev, sdw->bpt_ctx.dmab_rx_bdl.area, 400 sdw->bpt_ctx.pdi1_buffer_size, 401 msg->sec, msg->sections, sdw->bpt_ctx.num_frames, 402 sdw->bpt_ctx.data_per_frame); 403 if (ret < 0) 404 dev_err(cdns->dev, "%s: BPT Read failed %d\n", __func__, ret); 405 } 406 407 err: 408 intel_ace2x_bpt_close_stream(sdw, slave, msg); 409 410 return ret; 411 } 412 413 /* 414 * shim vendor-specific (vs) ops 415 */ 416 417 static void intel_shim_vs_init(struct sdw_intel *sdw) 418 { 419 void __iomem *shim_vs = sdw->link_res->shim_vs; 420 struct sdw_bus *bus = &sdw->cdns.bus; 421 struct sdw_intel_prop *intel_prop; 422 u16 clde; 423 u16 doaise2; 424 u16 dodse2; 425 u16 clds; 426 u16 clss; 427 u16 doaise; 428 u16 doais; 429 u16 dodse; 430 u16 dods; 431 u16 act; 432 433 intel_prop = bus->vendor_specific_prop; 434 clde = intel_prop->clde; 435 doaise2 = intel_prop->doaise2; 436 dodse2 = intel_prop->dodse2; 437 clds = intel_prop->clds; 438 clss = intel_prop->clss; 439 doaise = intel_prop->doaise; 440 doais = intel_prop->doais; 441 dodse = intel_prop->dodse; 442 dods = intel_prop->dods; 443 444 act = intel_readw(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL); 445 u16p_replace_bits(&act, clde, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE); 446 u16p_replace_bits(&act, doaise2, SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2); 447 u16p_replace_bits(&act, dodse2, SDW_SHIM3_INTEL_VS_ACTMCTL_DODSE2); 448 u16p_replace_bits(&act, clds, SDW_SHIM3_INTEL_VS_ACTMCTL_CLDS); 449 u16p_replace_bits(&act, clss, SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS); 450 u16p_replace_bits(&act, doaise, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE); 451 u16p_replace_bits(&act, doais, SDW_SHIM2_INTEL_VS_ACTMCTL_DOAIS); 452 u16p_replace_bits(&act, dodse, SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE); 453 u16p_replace_bits(&act, dods, SDW_SHIM2_INTEL_VS_ACTMCTL_DODS); 454 act |= SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE; 455 intel_writew(shim_vs, SDW_SHIM2_INTEL_VS_ACTMCTL, act); 456 usleep_range(10, 15); 457 } 458 459 static void intel_shim_vs_set_clock_source(struct sdw_intel *sdw, u32 source) 460 { 461 void __iomem *shim_vs = sdw->link_res->shim_vs; 462 u32 val; 463 464 val = intel_readl(shim_vs, SDW_SHIM2_INTEL_VS_LVSCTL); 465 466 u32p_replace_bits(&val, source, SDW_SHIM2_INTEL_VS_LVSCTL_MLCS); 467 468 intel_writel(shim_vs, SDW_SHIM2_INTEL_VS_LVSCTL, val); 469 470 dev_dbg(sdw->cdns.dev, "clock source %d LVSCTL %#x\n", source, val); 471 } 472 473 static int intel_shim_check_wake(struct sdw_intel *sdw) 474 { 475 /* 476 * We follow the HDaudio example and resume unconditionally 477 * without checking the WAKESTS bit for that specific link 478 */ 479 480 return 1; 481 } 482 483 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) 484 { 485 u16 lsdiid = 0; 486 u16 wake_en; 487 u16 wake_sts; 488 int ret; 489 490 mutex_lock(sdw->link_res->shim_lock); 491 492 ret = hdac_bus_eml_sdw_get_lsdiid_unlocked(sdw->link_res->hbus, sdw->instance, &lsdiid); 493 if (ret < 0) 494 goto unlock; 495 496 wake_en = snd_hdac_chip_readw(sdw->link_res->hbus, WAKEEN); 497 498 if (wake_enable) { 499 /* Enable the wakeup */ 500 wake_en |= lsdiid; 501 502 snd_hdac_chip_writew(sdw->link_res->hbus, WAKEEN, wake_en); 503 } else { 504 /* Disable the wake up interrupt */ 505 wake_en &= ~lsdiid; 506 snd_hdac_chip_writew(sdw->link_res->hbus, WAKEEN, wake_en); 507 508 /* Clear wake status (W1C) */ 509 wake_sts = snd_hdac_chip_readw(sdw->link_res->hbus, STATESTS); 510 wake_sts |= lsdiid; 511 snd_hdac_chip_writew(sdw->link_res->hbus, STATESTS, wake_sts); 512 } 513 unlock: 514 mutex_unlock(sdw->link_res->shim_lock); 515 } 516 517 static int intel_link_power_up(struct sdw_intel *sdw) 518 { 519 struct sdw_bus *bus = &sdw->cdns.bus; 520 struct sdw_master_prop *prop = &bus->prop; 521 u32 *shim_mask = sdw->link_res->shim_mask; 522 unsigned int link_id = sdw->instance; 523 u32 clock_source; 524 u32 syncprd; 525 int ret; 526 527 if (prop->mclk_freq % 6000000) { 528 if (prop->mclk_freq % 2400000) { 529 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24_576; 530 clock_source = SDW_SHIM2_MLCS_CARDINAL_CLK; 531 } else { 532 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; 533 clock_source = SDW_SHIM2_MLCS_XTAL_CLK; 534 } 535 } else { 536 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_96; 537 clock_source = SDW_SHIM2_MLCS_AUDIO_PLL_CLK; 538 } 539 540 mutex_lock(sdw->link_res->shim_lock); 541 542 ret = hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, link_id); 543 if (ret < 0) { 544 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_up failed: %d\n", 545 __func__, ret); 546 goto out; 547 } 548 549 intel_shim_vs_set_clock_source(sdw, clock_source); 550 551 if (!*shim_mask) { 552 /* we first need to program the SyncPRD/CPU registers */ 553 dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n"); 554 555 ret = hdac_bus_eml_sdw_set_syncprd_unlocked(sdw->link_res->hbus, syncprd); 556 if (ret < 0) { 557 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_set_syncprd failed: %d\n", 558 __func__, ret); 559 goto out; 560 } 561 562 /* SYNCPU will change once link is active */ 563 ret = hdac_bus_eml_sdw_wait_syncpu_unlocked(sdw->link_res->hbus); 564 if (ret < 0) { 565 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_wait_syncpu failed: %d\n", 566 __func__, ret); 567 goto out; 568 } 569 570 hdac_bus_eml_enable_interrupt_unlocked(sdw->link_res->hbus, true, 571 AZX_REG_ML_LEPTR_ID_SDW, true); 572 } 573 574 *shim_mask |= BIT(link_id); 575 576 sdw->cdns.link_up = true; 577 578 intel_shim_vs_init(sdw); 579 580 out: 581 mutex_unlock(sdw->link_res->shim_lock); 582 583 return ret; 584 } 585 586 static int intel_link_power_down(struct sdw_intel *sdw) 587 { 588 u32 *shim_mask = sdw->link_res->shim_mask; 589 unsigned int link_id = sdw->instance; 590 int ret; 591 592 mutex_lock(sdw->link_res->shim_lock); 593 594 sdw->cdns.link_up = false; 595 596 *shim_mask &= ~BIT(link_id); 597 598 if (!*shim_mask) 599 hdac_bus_eml_enable_interrupt_unlocked(sdw->link_res->hbus, true, 600 AZX_REG_ML_LEPTR_ID_SDW, false); 601 602 ret = hdac_bus_eml_sdw_power_down_unlocked(sdw->link_res->hbus, link_id); 603 if (ret < 0) { 604 dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_down failed: %d\n", 605 __func__, ret); 606 607 /* 608 * we leave the sdw->cdns.link_up flag as false since we've disabled 609 * the link at this point and cannot handle interrupts any longer. 610 */ 611 } 612 613 mutex_unlock(sdw->link_res->shim_lock); 614 615 return ret; 616 } 617 618 static void intel_sync_arm(struct sdw_intel *sdw) 619 { 620 unsigned int link_id = sdw->instance; 621 622 mutex_lock(sdw->link_res->shim_lock); 623 624 hdac_bus_eml_sdw_sync_arm_unlocked(sdw->link_res->hbus, link_id); 625 626 mutex_unlock(sdw->link_res->shim_lock); 627 } 628 629 static int intel_sync_go_unlocked(struct sdw_intel *sdw) 630 { 631 int ret; 632 633 ret = hdac_bus_eml_sdw_sync_go_unlocked(sdw->link_res->hbus); 634 if (ret < 0) 635 dev_err(sdw->cdns.dev, "%s: SyncGO clear failed: %d\n", __func__, ret); 636 637 return ret; 638 } 639 640 static int intel_sync_go(struct sdw_intel *sdw) 641 { 642 int ret; 643 644 mutex_lock(sdw->link_res->shim_lock); 645 646 ret = intel_sync_go_unlocked(sdw); 647 648 mutex_unlock(sdw->link_res->shim_lock); 649 650 return ret; 651 } 652 653 static bool intel_check_cmdsync_unlocked(struct sdw_intel *sdw) 654 { 655 return hdac_bus_eml_sdw_check_cmdsync_unlocked(sdw->link_res->hbus); 656 } 657 658 /* DAI callbacks */ 659 static int intel_params_stream(struct sdw_intel *sdw, 660 struct snd_pcm_substream *substream, 661 struct snd_soc_dai *dai, 662 struct snd_pcm_hw_params *hw_params, 663 int link_id, int alh_stream_id) 664 { 665 struct sdw_intel_link_res *res = sdw->link_res; 666 struct sdw_intel_stream_params_data params_data; 667 668 params_data.substream = substream; 669 params_data.dai = dai; 670 params_data.hw_params = hw_params; 671 params_data.link_id = link_id; 672 params_data.alh_stream_id = alh_stream_id; 673 674 if (res->ops && res->ops->params_stream && res->dev) 675 return res->ops->params_stream(res->dev, 676 ¶ms_data); 677 return -EIO; 678 } 679 680 static int intel_free_stream(struct sdw_intel *sdw, 681 struct snd_pcm_substream *substream, 682 struct snd_soc_dai *dai, 683 int link_id) 684 685 { 686 struct sdw_intel_link_res *res = sdw->link_res; 687 struct sdw_intel_stream_free_data free_data; 688 689 free_data.substream = substream; 690 free_data.dai = dai; 691 free_data.link_id = link_id; 692 693 if (res->ops && res->ops->free_stream && res->dev) 694 return res->ops->free_stream(res->dev, 695 &free_data); 696 697 return 0; 698 } 699 700 /* 701 * DAI operations 702 */ 703 static int intel_hw_params(struct snd_pcm_substream *substream, 704 struct snd_pcm_hw_params *params, 705 struct snd_soc_dai *dai) 706 { 707 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 708 struct sdw_intel *sdw = cdns_to_intel(cdns); 709 struct sdw_cdns_dai_runtime *dai_runtime; 710 struct sdw_cdns_pdi *pdi; 711 struct sdw_stream_config sconfig; 712 int ch, dir; 713 int ret; 714 715 dai_runtime = cdns->dai_runtime_array[dai->id]; 716 if (!dai_runtime) 717 return -EIO; 718 719 ch = params_channels(params); 720 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 721 dir = SDW_DATA_DIR_RX; 722 else 723 dir = SDW_DATA_DIR_TX; 724 725 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id); 726 if (!pdi) 727 return -EINVAL; 728 729 /* use same definitions for alh_id as previous generations */ 730 pdi->intel_alh_id = (sdw->instance * 16) + pdi->num + 3; 731 if (pdi->num >= 2) 732 pdi->intel_alh_id += 2; 733 734 /* the SHIM will be configured in the callback functions */ 735 736 sdw_cdns_config_stream(cdns, ch, dir, pdi); 737 738 /* store pdi and state, may be needed in prepare step */ 739 dai_runtime->paused = false; 740 dai_runtime->suspended = false; 741 dai_runtime->pdi = pdi; 742 743 /* Inform DSP about PDI stream number */ 744 ret = intel_params_stream(sdw, substream, dai, params, 745 sdw->instance, 746 pdi->intel_alh_id); 747 if (ret) 748 return ret; 749 750 sconfig.direction = dir; 751 sconfig.ch_count = ch; 752 sconfig.frame_rate = params_rate(params); 753 sconfig.type = dai_runtime->stream_type; 754 755 sconfig.bps = snd_pcm_format_width(params_format(params)); 756 757 /* Port configuration */ 758 struct sdw_port_config *pconfig __free(kfree) = kzalloc_obj(*pconfig); 759 if (!pconfig) 760 return -ENOMEM; 761 762 pconfig->num = pdi->num; 763 pconfig->ch_mask = (1 << ch) - 1; 764 765 ret = sdw_stream_add_master(&cdns->bus, &sconfig, 766 pconfig, 1, dai_runtime->stream); 767 if (ret) 768 dev_err(cdns->dev, "add master to stream failed:%d\n", ret); 769 770 return ret; 771 } 772 773 static int intel_prepare(struct snd_pcm_substream *substream, 774 struct snd_soc_dai *dai) 775 { 776 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 777 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 778 struct sdw_intel *sdw = cdns_to_intel(cdns); 779 struct sdw_cdns_dai_runtime *dai_runtime; 780 struct snd_pcm_hw_params *hw_params; 781 int ch, dir; 782 783 dai_runtime = cdns->dai_runtime_array[dai->id]; 784 if (!dai_runtime) { 785 dev_err(dai->dev, "failed to get dai runtime in %s\n", 786 __func__); 787 return -EIO; 788 } 789 790 hw_params = &rtd->dpcm[substream->stream].hw_params; 791 if (dai_runtime->suspended) { 792 dai_runtime->suspended = false; 793 794 /* 795 * .prepare() is called after system resume, where we 796 * need to reinitialize the SHIM/ALH/Cadence IP. 797 * .prepare() is also called to deal with underflows, 798 * but in those cases we cannot touch ALH/SHIM 799 * registers 800 */ 801 802 /* configure stream */ 803 ch = params_channels(hw_params); 804 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 805 dir = SDW_DATA_DIR_RX; 806 else 807 dir = SDW_DATA_DIR_TX; 808 809 /* the SHIM will be configured in the callback functions */ 810 811 sdw_cdns_config_stream(cdns, ch, dir, dai_runtime->pdi); 812 } 813 814 /* Inform DSP about PDI stream number */ 815 return intel_params_stream(sdw, substream, dai, hw_params, sdw->instance, 816 dai_runtime->pdi->intel_alh_id); 817 } 818 819 static int 820 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 821 { 822 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 823 struct sdw_intel *sdw = cdns_to_intel(cdns); 824 struct sdw_cdns_dai_runtime *dai_runtime; 825 int ret; 826 827 dai_runtime = cdns->dai_runtime_array[dai->id]; 828 if (!dai_runtime) 829 return -EIO; 830 831 /* 832 * The sdw stream state will transition to RELEASED when stream-> 833 * master_list is empty. So the stream state will transition to 834 * DEPREPARED for the first cpu-dai and to RELEASED for the last 835 * cpu-dai. 836 */ 837 ret = sdw_stream_remove_master(&cdns->bus, dai_runtime->stream); 838 if (ret < 0) { 839 dev_err(dai->dev, "remove master from stream %s failed: %d\n", 840 dai_runtime->stream->name, ret); 841 return ret; 842 } 843 844 ret = intel_free_stream(sdw, substream, dai, sdw->instance); 845 if (ret < 0) { 846 dev_err(dai->dev, "intel_free_stream: failed %d\n", ret); 847 return ret; 848 } 849 850 dai_runtime->pdi = NULL; 851 852 return 0; 853 } 854 855 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, 856 void *stream, int direction) 857 { 858 return cdns_set_sdw_stream(dai, stream, direction); 859 } 860 861 static void *intel_get_sdw_stream(struct snd_soc_dai *dai, 862 int direction) 863 { 864 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 865 struct sdw_cdns_dai_runtime *dai_runtime; 866 867 dai_runtime = cdns->dai_runtime_array[dai->id]; 868 if (!dai_runtime) 869 return ERR_PTR(-EINVAL); 870 871 return dai_runtime->stream; 872 } 873 874 static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) 875 { 876 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 877 struct sdw_intel *sdw = cdns_to_intel(cdns); 878 struct sdw_intel_link_res *res = sdw->link_res; 879 struct sdw_cdns_dai_runtime *dai_runtime; 880 int ret = 0; 881 882 /* 883 * The .trigger callback is used to program HDaudio DMA and send required IPC to audio 884 * firmware. 885 */ 886 if (res->ops && res->ops->trigger) { 887 ret = res->ops->trigger(substream, cmd, dai); 888 if (ret < 0) 889 return ret; 890 } 891 892 dai_runtime = cdns->dai_runtime_array[dai->id]; 893 if (!dai_runtime) { 894 dev_err(dai->dev, "failed to get dai runtime in %s\n", 895 __func__); 896 return -EIO; 897 } 898 899 switch (cmd) { 900 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 901 dai_runtime->paused = true; 902 break; 903 case SNDRV_PCM_TRIGGER_STOP: 904 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 905 dai_runtime->paused = false; 906 break; 907 default: 908 break; 909 } 910 911 return ret; 912 } 913 914 static const struct snd_soc_dai_ops intel_pcm_dai_ops = { 915 .hw_params = intel_hw_params, 916 .prepare = intel_prepare, 917 .hw_free = intel_hw_free, 918 .trigger = intel_trigger, 919 .set_stream = intel_pcm_set_sdw_stream, 920 .get_stream = intel_get_sdw_stream, 921 }; 922 923 static int intel_component_dais_suspend(struct snd_soc_component *component) 924 { 925 struct snd_soc_dai *dai; 926 927 /* 928 * Mark all open streams as suspended. 929 * Open streams at this point can be in SUSPENDED, PAUSED or STOPPED 930 * state and during prepare the DMAs and SHIM registers need to be 931 * initialized for them. 932 * The STOPPED state is a special corner case which can happen if audio 933 * experiences xrun at suspend time. 934 */ 935 for_each_component_dais(component, dai) { 936 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 937 struct sdw_cdns_dai_runtime *dai_runtime; 938 939 dai_runtime = cdns->dai_runtime_array[dai->id]; 940 941 if (dai_runtime) 942 dai_runtime->suspended = true; 943 } 944 945 return 0; 946 } 947 948 static const struct snd_soc_component_driver dai_component = { 949 .name = "soundwire", 950 .suspend = intel_component_dais_suspend, 951 }; 952 953 /* 954 * PDI routines 955 */ 956 static void intel_pdi_init(struct sdw_intel *sdw, 957 struct sdw_cdns_stream_config *config) 958 { 959 void __iomem *shim = sdw->link_res->shim; 960 int pcm_cap; 961 962 /* PCM Stream Capability */ 963 pcm_cap = intel_readw(shim, SDW_SHIM2_PCMSCAP); 964 965 config->pcm_bd = FIELD_GET(SDW_SHIM2_PCMSCAP_BSS, pcm_cap); 966 config->pcm_in = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap); 967 config->pcm_out = FIELD_GET(SDW_SHIM2_PCMSCAP_ISS, pcm_cap); 968 969 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", 970 config->pcm_bd, config->pcm_in, config->pcm_out); 971 } 972 973 static int 974 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num) 975 { 976 void __iomem *shim = sdw->link_res->shim; 977 978 /* zero based values for channel count in register */ 979 return intel_readw(shim, SDW_SHIM2_PCMSYCHC(pdi_num)) + 1; 980 } 981 982 static void intel_pdi_get_ch_update(struct sdw_intel *sdw, 983 struct sdw_cdns_pdi *pdi, 984 unsigned int num_pdi, 985 unsigned int *num_ch) 986 { 987 int ch_count = 0; 988 int i; 989 990 for (i = 0; i < num_pdi; i++) { 991 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num); 992 ch_count += pdi->ch_count; 993 pdi++; 994 } 995 996 *num_ch = ch_count; 997 } 998 999 static void intel_pdi_stream_ch_update(struct sdw_intel *sdw, 1000 struct sdw_cdns_streams *stream) 1001 { 1002 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, 1003 &stream->num_ch_bd); 1004 1005 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, 1006 &stream->num_ch_in); 1007 1008 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, 1009 &stream->num_ch_out); 1010 } 1011 1012 static int intel_create_dai(struct sdw_cdns *cdns, 1013 struct snd_soc_dai_driver *dais, 1014 enum intel_pdi_type type, 1015 u32 num, u32 off, u32 max_ch) 1016 { 1017 int i; 1018 1019 if (!num) 1020 return 0; 1021 1022 for (i = off; i < (off + num); i++) { 1023 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL, 1024 "SDW%d Pin%d", 1025 cdns->instance, i); 1026 if (!dais[i].name) 1027 return -ENOMEM; 1028 1029 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { 1030 dais[i].playback.channels_min = 1; 1031 dais[i].playback.channels_max = max_ch; 1032 } 1033 1034 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { 1035 dais[i].capture.channels_min = 1; 1036 dais[i].capture.channels_max = max_ch; 1037 } 1038 1039 dais[i].ops = &intel_pcm_dai_ops; 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int intel_register_dai(struct sdw_intel *sdw) 1046 { 1047 struct sdw_cdns_dai_runtime **dai_runtime_array; 1048 struct sdw_cdns_stream_config config; 1049 struct sdw_cdns *cdns = &sdw->cdns; 1050 struct sdw_cdns_streams *stream; 1051 struct snd_soc_dai_driver *dais; 1052 int num_dai; 1053 int ret; 1054 int off = 0; 1055 1056 /* Read the PDI config and initialize cadence PDI */ 1057 intel_pdi_init(sdw, &config); 1058 ret = sdw_cdns_pdi_init(cdns, config); 1059 if (ret) 1060 return ret; 1061 1062 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm); 1063 1064 /* DAIs are created based on total number of PDIs supported */ 1065 num_dai = cdns->pcm.num_pdi; 1066 1067 dai_runtime_array = devm_kcalloc(cdns->dev, num_dai, 1068 sizeof(struct sdw_cdns_dai_runtime *), 1069 GFP_KERNEL); 1070 if (!dai_runtime_array) 1071 return -ENOMEM; 1072 cdns->dai_runtime_array = dai_runtime_array; 1073 1074 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); 1075 if (!dais) 1076 return -ENOMEM; 1077 1078 /* Create PCM DAIs */ 1079 stream = &cdns->pcm; 1080 1081 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in, 1082 off, stream->num_ch_in); 1083 if (ret) 1084 return ret; 1085 1086 off += cdns->pcm.num_in; 1087 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, 1088 off, stream->num_ch_out); 1089 if (ret) 1090 return ret; 1091 1092 off += cdns->pcm.num_out; 1093 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, 1094 off, stream->num_ch_bd); 1095 if (ret) 1096 return ret; 1097 1098 return devm_snd_soc_register_component(cdns->dev, &dai_component, 1099 dais, num_dai); 1100 } 1101 1102 static void intel_program_sdi(struct sdw_intel *sdw, int dev_num) 1103 { 1104 int ret; 1105 1106 ret = hdac_bus_eml_sdw_set_lsdiid(sdw->link_res->hbus, sdw->instance, dev_num); 1107 if (ret < 0) 1108 dev_err(sdw->cdns.dev, "%s: could not set lsdiid for link %d %d\n", 1109 __func__, sdw->instance, dev_num); 1110 } 1111 1112 static int intel_get_link_count(struct sdw_intel *sdw) 1113 { 1114 int ret; 1115 1116 ret = hdac_bus_eml_get_count(sdw->link_res->hbus, true, AZX_REG_ML_LEPTR_ID_SDW); 1117 if (!ret) { 1118 dev_err(sdw->cdns.dev, "%s: could not retrieve link count\n", __func__); 1119 return -ENODEV; 1120 } 1121 1122 if (ret > SDW_INTEL_MAX_LINKS) { 1123 dev_err(sdw->cdns.dev, "%s: link count %d exceed max %d\n", __func__, ret, SDW_INTEL_MAX_LINKS); 1124 return -EINVAL; 1125 } 1126 1127 return ret; 1128 } 1129 1130 const struct sdw_intel_hw_ops sdw_intel_lnl_hw_ops = { 1131 .debugfs_init = intel_ace2x_debugfs_init, 1132 .debugfs_exit = intel_ace2x_debugfs_exit, 1133 1134 .get_link_count = intel_get_link_count, 1135 1136 .register_dai = intel_register_dai, 1137 1138 .check_clock_stop = intel_check_clock_stop, 1139 .start_bus = intel_start_bus, 1140 .start_bus_after_reset = intel_start_bus_after_reset, 1141 .start_bus_after_clock_stop = intel_start_bus_after_clock_stop, 1142 .stop_bus = intel_stop_bus, 1143 1144 .link_power_up = intel_link_power_up, 1145 .link_power_down = intel_link_power_down, 1146 1147 .shim_check_wake = intel_shim_check_wake, 1148 .shim_wake = intel_shim_wake, 1149 1150 .pre_bank_switch = intel_pre_bank_switch, 1151 .post_bank_switch = intel_post_bank_switch, 1152 1153 .sync_arm = intel_sync_arm, 1154 .sync_go_unlocked = intel_sync_go_unlocked, 1155 .sync_go = intel_sync_go, 1156 .sync_check_cmdsync_unlocked = intel_check_cmdsync_unlocked, 1157 1158 .program_sdi = intel_program_sdi, 1159 1160 .bpt_send_async = intel_ace2x_bpt_send_async, 1161 .bpt_wait = intel_ace2x_bpt_wait, 1162 }; 1163 EXPORT_SYMBOL_NS(sdw_intel_lnl_hw_ops, "SOUNDWIRE_INTEL"); 1164 1165 MODULE_IMPORT_NS("SND_SOC_SOF_HDA_MLINK"); 1166 MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_HDA_SDW_BPT"); 1167