1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * SoundWire AMD Manager driver 4 * 5 * Copyright 2023-24 Advanced Micro Devices, Inc. 6 */ 7 8 #include <linux/completion.h> 9 #include <linux/cleanup.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/jiffies.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/soundwire/sdw.h> 17 #include <linux/soundwire/sdw_registers.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/wait.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include "bus.h" 23 #include "amd_init.h" 24 #include "amd_manager.h" 25 26 #define DRV_NAME "amd_sdw_manager" 27 28 #define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus) 29 30 static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager) 31 { 32 u32 val; 33 int ret; 34 35 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 36 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 37 AMD_SDW_TIMEOUT); 38 if (ret) 39 return ret; 40 41 /* SoundWire manager bus reset */ 42 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 43 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, 44 (val & AMD_SDW_BUS_RESET_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT); 45 if (ret) 46 return ret; 47 48 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 49 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val, 50 ACP_DELAY_US, AMD_SDW_TIMEOUT); 51 if (ret) { 52 dev_err(amd_manager->dev, "Failed to reset SoundWire manager instance%d\n", 53 amd_manager->instance); 54 return ret; 55 } 56 57 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 58 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 59 AMD_SDW_TIMEOUT); 60 } 61 62 static int amd_enable_sdw_manager(struct amd_sdw_manager *amd_manager) 63 { 64 u32 val; 65 66 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 67 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 68 AMD_SDW_TIMEOUT); 69 } 70 71 static int amd_disable_sdw_manager(struct amd_sdw_manager *amd_manager) 72 { 73 u32 val; 74 75 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 76 /* 77 * After invoking manager disable sequence, check whether 78 * manager has executed clock stop sequence. In this case, 79 * manager should ignore checking enable status register. 80 */ 81 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 82 if (val) 83 return 0; 84 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 85 AMD_SDW_TIMEOUT); 86 } 87 88 static void amd_enable_sdw_interrupts(struct amd_sdw_manager *amd_manager) 89 { 90 u32 val; 91 92 mutex_lock(amd_manager->acp_sdw_lock); 93 val = sdw_manager_reg_mask_array[amd_manager->instance]; 94 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), val, val); 95 mutex_unlock(amd_manager->acp_sdw_lock); 96 97 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio + 98 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 99 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio + 100 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 101 writel(AMD_SDW_IRQ_ERROR_MASK, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK); 102 } 103 104 static void amd_disable_sdw_interrupts(struct amd_sdw_manager *amd_manager) 105 { 106 u32 irq_mask; 107 108 mutex_lock(amd_manager->acp_sdw_lock); 109 irq_mask = sdw_manager_reg_mask_array[amd_manager->instance]; 110 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), 111 irq_mask, 0); 112 mutex_unlock(amd_manager->acp_sdw_lock); 113 114 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 115 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 116 writel(0x00, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK); 117 } 118 119 static int amd_deinit_sdw_manager(struct amd_sdw_manager *amd_manager) 120 { 121 amd_disable_sdw_interrupts(amd_manager); 122 return amd_disable_sdw_manager(amd_manager); 123 } 124 125 static void amd_sdw_set_frameshape(struct amd_sdw_manager *amd_manager) 126 { 127 u32 frame_size; 128 129 frame_size = (amd_manager->rows_index << 3) | amd_manager->cols_index; 130 writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE); 131 } 132 133 static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable) 134 { 135 u32 wake_ctrl; 136 137 wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 138 if (enable) 139 wake_ctrl |= AMD_SDW_WAKE_INTR_MASK; 140 else 141 wake_ctrl &= ~AMD_SDW_WAKE_INTR_MASK; 142 143 writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 144 } 145 146 static int amd_sdw_set_device_state(struct amd_sdw_manager *amd_manager, u32 target_device_state) 147 { 148 u32 sdw_dev_state; 149 150 sdw_dev_state = readl(amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE); 151 switch (amd_manager->instance) { 152 case ACP_SDW0: 153 u32p_replace_bits(&sdw_dev_state, target_device_state, 154 AMD_SDW0_DEVICE_STATE_MASK); 155 break; 156 case ACP_SDW1: 157 u32p_replace_bits(&sdw_dev_state, target_device_state, 158 AMD_SDW1_DEVICE_STATE_MASK); 159 break; 160 default: 161 return -EINVAL; 162 } 163 writel(sdw_dev_state, amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE); 164 sdw_dev_state = readl(amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE); 165 dev_dbg(amd_manager->dev, "AMD_SDW_DEVICE_STATE:0x%x\n", sdw_dev_state); 166 return 0; 167 } 168 169 static int amd_sdw_host_wake_enable(struct amd_sdw_manager *amd_manager, bool enable) 170 { 171 u32 intr_cntl1; 172 u32 sdw_host_wake_irq_mask; 173 174 if (!amd_manager->wake_en_mask) 175 return 0; 176 177 switch (amd_manager->instance) { 178 case ACP_SDW0: 179 sdw_host_wake_irq_mask = AMD_SDW0_HOST_WAKE_INTR_MASK; 180 break; 181 case ACP_SDW1: 182 sdw_host_wake_irq_mask = AMD_SDW1_HOST_WAKE_INTR_MASK; 183 break; 184 default: 185 return -EINVAL; 186 } 187 188 intr_cntl1 = readl(amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(ACP_SDW1)); 189 if (enable) 190 intr_cntl1 |= sdw_host_wake_irq_mask; 191 else 192 intr_cntl1 &= ~sdw_host_wake_irq_mask; 193 writel(intr_cntl1, amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(ACP_SDW1)); 194 return 0; 195 } 196 197 static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg, 198 int cmd_offset) 199 { 200 u32 upper_data; 201 u32 lower_data = 0; 202 u16 addr; 203 u8 upper_addr, lower_addr; 204 u8 data = 0; 205 206 addr = msg->addr + cmd_offset; 207 upper_addr = (addr & 0xFF00) >> 8; 208 lower_addr = addr & 0xFF; 209 210 if (msg->flags == SDW_MSG_FLAG_WRITE) 211 data = msg->buf[cmd_offset]; 212 213 upper_data = FIELD_PREP(AMD_SDW_MCP_CMD_DEV_ADDR, msg->dev_num); 214 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_COMMAND, msg->flags + 2); 215 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_HIGH, upper_addr); 216 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_LOW, lower_addr); 217 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_DATA, data); 218 219 *upper_word = upper_data; 220 *lower_word = lower_data; 221 } 222 223 static u64 amd_sdw_send_cmd_get_resp(struct amd_sdw_manager *amd_manager, u32 lower_data, 224 u32 upper_data) 225 { 226 u64 resp; 227 u32 lower_resp, upper_resp; 228 u32 sts; 229 int ret; 230 231 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 232 !(sts & AMD_SDW_IMM_CMD_BUSY), ACP_DELAY_US, AMD_SDW_TIMEOUT); 233 if (ret) { 234 dev_err(amd_manager->dev, "SDW%x previous cmd status clear failed\n", 235 amd_manager->instance); 236 return ret; 237 } 238 239 if (sts & AMD_SDW_IMM_RES_VALID) { 240 dev_err(amd_manager->dev, "SDW%x manager is in bad state\n", amd_manager->instance); 241 writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS); 242 } 243 writel(upper_data, amd_manager->mmio + ACP_SW_IMM_CMD_UPPER_WORD); 244 writel(lower_data, amd_manager->mmio + ACP_SW_IMM_CMD_LOWER_QWORD); 245 246 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 247 (sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT); 248 if (ret) { 249 dev_err(amd_manager->dev, "SDW%x cmd response timeout occurred\n", 250 amd_manager->instance); 251 return ret; 252 } 253 upper_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_UPPER_WORD); 254 lower_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_LOWER_QWORD); 255 256 writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS); 257 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 258 !(sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT); 259 if (ret) { 260 dev_err(amd_manager->dev, "SDW%x cmd status retry failed\n", 261 amd_manager->instance); 262 return ret; 263 } 264 resp = upper_resp; 265 resp = (resp << 32) | lower_resp; 266 return resp; 267 } 268 269 static enum sdw_command_response 270 amd_program_scp_addr(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg) 271 { 272 struct sdw_msg scp_msg = {0}; 273 u64 response_buf[2] = {0}; 274 u32 upper_data = 0, lower_data = 0; 275 int index; 276 277 scp_msg.dev_num = msg->dev_num; 278 scp_msg.addr = SDW_SCP_ADDRPAGE1; 279 scp_msg.buf = &msg->addr_page1; 280 scp_msg.flags = SDW_MSG_FLAG_WRITE; 281 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0); 282 response_buf[0] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 283 scp_msg.addr = SDW_SCP_ADDRPAGE2; 284 scp_msg.buf = &msg->addr_page2; 285 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0); 286 response_buf[1] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 287 288 for (index = 0; index < 2; index++) { 289 if (response_buf[index] == -ETIMEDOUT) { 290 dev_err_ratelimited(amd_manager->dev, 291 "SCP_addrpage command timeout for Slave %d\n", 292 msg->dev_num); 293 return SDW_CMD_TIMEOUT; 294 } else if (!(response_buf[index] & AMD_SDW_MCP_RESP_ACK)) { 295 if (response_buf[index] & AMD_SDW_MCP_RESP_NACK) { 296 dev_err_ratelimited(amd_manager->dev, 297 "SCP_addrpage NACKed for Slave %d\n", 298 msg->dev_num); 299 return SDW_CMD_FAIL; 300 } 301 dev_dbg_ratelimited(amd_manager->dev, "SCP_addrpage ignored for Slave %d\n", 302 msg->dev_num); 303 return SDW_CMD_IGNORED; 304 } 305 } 306 return SDW_CMD_OK; 307 } 308 309 static int amd_prep_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg) 310 { 311 int ret; 312 313 if (msg->page) { 314 ret = amd_program_scp_addr(amd_manager, msg); 315 if (ret) { 316 msg->len = 0; 317 return ret; 318 } 319 } 320 switch (msg->flags) { 321 case SDW_MSG_FLAG_READ: 322 case SDW_MSG_FLAG_WRITE: 323 break; 324 default: 325 dev_err(amd_manager->dev, "Invalid msg cmd: %d\n", msg->flags); 326 return -EINVAL; 327 } 328 return 0; 329 } 330 331 static enum sdw_command_response amd_sdw_fill_msg_resp(struct amd_sdw_manager *amd_manager, 332 struct sdw_msg *msg, u64 response, 333 int offset) 334 { 335 if (response & AMD_SDW_MCP_RESP_ACK) { 336 if (msg->flags == SDW_MSG_FLAG_READ) 337 msg->buf[offset] = FIELD_GET(AMD_SDW_MCP_RESP_RDATA, response); 338 } else { 339 if (response == -ETIMEDOUT) { 340 dev_err_ratelimited(amd_manager->dev, "command timeout for Slave %d\n", 341 msg->dev_num); 342 return SDW_CMD_TIMEOUT; 343 } else if (response & AMD_SDW_MCP_RESP_NACK) { 344 dev_err_ratelimited(amd_manager->dev, 345 "command response NACK received for Slave %d\n", 346 msg->dev_num); 347 return SDW_CMD_FAIL; 348 } 349 dev_dbg_ratelimited(amd_manager->dev, "command is ignored for Slave %d\n", 350 msg->dev_num); 351 return SDW_CMD_IGNORED; 352 } 353 return SDW_CMD_OK; 354 } 355 356 static unsigned int _amd_sdw_xfer_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg, 357 int cmd_offset) 358 { 359 u64 response; 360 u32 upper_data = 0, lower_data = 0; 361 362 amd_sdw_ctl_word_prep(&lower_data, &upper_data, msg, cmd_offset); 363 response = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 364 return amd_sdw_fill_msg_resp(amd_manager, msg, response, cmd_offset); 365 } 366 367 static enum sdw_command_response amd_sdw_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg) 368 { 369 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 370 int ret, i; 371 372 ret = amd_prep_msg(amd_manager, msg); 373 if (ret) 374 return SDW_CMD_FAIL_OTHER; 375 for (i = 0; i < msg->len; i++) { 376 ret = _amd_sdw_xfer_msg(amd_manager, msg, i); 377 if (ret) 378 return ret; 379 } 380 return SDW_CMD_OK; 381 } 382 383 static void amd_sdw_fill_slave_status(struct amd_sdw_manager *amd_manager, u16 index, u32 status) 384 { 385 switch (status) { 386 case SDW_SLAVE_ATTACHED: 387 case SDW_SLAVE_UNATTACHED: 388 case SDW_SLAVE_ALERT: 389 amd_manager->status[index] = status; 390 break; 391 default: 392 amd_manager->status[index] = SDW_SLAVE_RESERVED; 393 break; 394 } 395 } 396 397 static void amd_sdw_process_ping_status(u64 response, struct amd_sdw_manager *amd_manager) 398 { 399 u64 slave_stat; 400 u32 val; 401 u16 dev_index; 402 403 /* slave status response */ 404 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response); 405 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8; 406 dev_dbg(amd_manager->dev, "slave_stat:0x%llx\n", slave_stat); 407 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) { 408 val = (slave_stat >> (dev_index * 2)) & AMD_SDW_MCP_SLAVE_STATUS_MASK; 409 dev_dbg(amd_manager->dev, "val:0x%x\n", val); 410 amd_sdw_fill_slave_status(amd_manager, dev_index, val); 411 } 412 } 413 414 static void amd_sdw_read_and_process_ping_status(struct amd_sdw_manager *amd_manager) 415 { 416 u64 response; 417 418 mutex_lock(&amd_manager->bus.msg_lock); 419 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0); 420 mutex_unlock(&amd_manager->bus.msg_lock); 421 amd_sdw_process_ping_status(response, amd_manager); 422 } 423 424 static u32 amd_sdw_read_ping_status(struct sdw_bus *bus) 425 { 426 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 427 u64 response; 428 u32 slave_stat; 429 430 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0); 431 /* slave status from ping response */ 432 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response); 433 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8; 434 dev_dbg(amd_manager->dev, "slave_stat:0x%x\n", slave_stat); 435 return slave_stat; 436 } 437 438 static int amd_sdw_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream) 439 { 440 struct sdw_transport_data t_data = {0}; 441 struct sdw_master_runtime *m_rt; 442 struct sdw_port_runtime *p_rt; 443 struct sdw_bus_params *b_params = &bus->params; 444 int port_bo, hstart, hstop, sample_int; 445 unsigned int rate, bps; 446 447 port_bo = 0; 448 hstart = 1; 449 hstop = bus->params.col - 1; 450 t_data.hstop = hstop; 451 t_data.hstart = hstart; 452 453 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 454 rate = m_rt->stream->params.rate; 455 bps = m_rt->stream->params.bps; 456 sample_int = (bus->params.curr_dr_freq / rate); 457 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 458 port_bo = (p_rt->num * 64) + 1; 459 dev_dbg(bus->dev, "p_rt->num=%d hstart=%d hstop=%d port_bo=%d\n", 460 p_rt->num, hstart, hstop, port_bo); 461 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, 462 false, SDW_BLK_GRP_CNT_1, sample_int, 463 port_bo, port_bo >> 8, hstart, hstop, 464 SDW_BLK_PKG_PER_PORT, p_rt->lane); 465 466 sdw_fill_port_params(&p_rt->port_params, 467 p_rt->num, bps, 468 SDW_PORT_FLOW_MODE_ISOCH, 469 b_params->m_data_mode); 470 t_data.hstart = hstart; 471 t_data.hstop = hstop; 472 t_data.block_offset = port_bo; 473 t_data.sub_block_offset = 0; 474 } 475 sdw_compute_slave_ports(m_rt, &t_data); 476 } 477 return 0; 478 } 479 480 static int amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_params, 481 unsigned int bank) 482 { 483 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 484 u32 frame_fmt_reg, dpn_frame_fmt; 485 486 dev_dbg(amd_manager->dev, "p_params->num:0x%x\n", p_params->num); 487 switch (amd_manager->acp_rev) { 488 case ACP63_PCI_REV_ID: 489 switch (amd_manager->instance) { 490 case ACP_SDW0: 491 frame_fmt_reg = acp63_sdw0_dp_reg[p_params->num].frame_fmt_reg; 492 break; 493 case ACP_SDW1: 494 frame_fmt_reg = acp63_sdw1_dp_reg[p_params->num].frame_fmt_reg; 495 break; 496 default: 497 return -EINVAL; 498 } 499 break; 500 case ACP70_PCI_REV_ID: 501 case ACP71_PCI_REV_ID: 502 case ACP72_PCI_REV_ID: 503 frame_fmt_reg = acp70_sdw_dp_reg[p_params->num].frame_fmt_reg; 504 break; 505 default: 506 return -EINVAL; 507 } 508 509 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg); 510 u32p_replace_bits(&dpn_frame_fmt, p_params->flow_mode, AMD_DPN_FRAME_FMT_PFM); 511 u32p_replace_bits(&dpn_frame_fmt, p_params->data_mode, AMD_DPN_FRAME_FMT_PDM); 512 u32p_replace_bits(&dpn_frame_fmt, p_params->bps - 1, AMD_DPN_FRAME_FMT_WORD_LEN); 513 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg); 514 return 0; 515 } 516 517 static int amd_sdw_transport_params(struct sdw_bus *bus, 518 struct sdw_transport_params *params, 519 enum sdw_reg_bank bank) 520 { 521 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 522 u32 dpn_frame_fmt; 523 u32 dpn_sampleinterval; 524 u32 dpn_hctrl; 525 u32 dpn_offsetctrl; 526 u32 dpn_lanectrl; 527 u32 frame_fmt_reg, sample_int_reg, hctrl_dp0_reg; 528 u32 offset_reg, lane_ctrl_ch_en_reg; 529 530 switch (amd_manager->acp_rev) { 531 case ACP63_PCI_REV_ID: 532 switch (amd_manager->instance) { 533 case ACP_SDW0: 534 frame_fmt_reg = acp63_sdw0_dp_reg[params->port_num].frame_fmt_reg; 535 sample_int_reg = acp63_sdw0_dp_reg[params->port_num].sample_int_reg; 536 hctrl_dp0_reg = acp63_sdw0_dp_reg[params->port_num].hctrl_dp0_reg; 537 offset_reg = acp63_sdw0_dp_reg[params->port_num].offset_reg; 538 lane_ctrl_ch_en_reg = 539 acp63_sdw0_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 540 break; 541 case ACP_SDW1: 542 frame_fmt_reg = acp63_sdw1_dp_reg[params->port_num].frame_fmt_reg; 543 sample_int_reg = acp63_sdw1_dp_reg[params->port_num].sample_int_reg; 544 hctrl_dp0_reg = acp63_sdw1_dp_reg[params->port_num].hctrl_dp0_reg; 545 offset_reg = acp63_sdw1_dp_reg[params->port_num].offset_reg; 546 lane_ctrl_ch_en_reg = 547 acp63_sdw1_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 548 break; 549 default: 550 return -EINVAL; 551 } 552 break; 553 case ACP70_PCI_REV_ID: 554 case ACP71_PCI_REV_ID: 555 case ACP72_PCI_REV_ID: 556 frame_fmt_reg = acp70_sdw_dp_reg[params->port_num].frame_fmt_reg; 557 sample_int_reg = acp70_sdw_dp_reg[params->port_num].sample_int_reg; 558 hctrl_dp0_reg = acp70_sdw_dp_reg[params->port_num].hctrl_dp0_reg; 559 offset_reg = acp70_sdw_dp_reg[params->port_num].offset_reg; 560 lane_ctrl_ch_en_reg = acp70_sdw_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 561 break; 562 default: 563 return -EINVAL; 564 } 565 writel(AMD_SDW_SSP_COUNTER_VAL, amd_manager->mmio + ACP_SW_SSP_COUNTER); 566 567 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg); 568 u32p_replace_bits(&dpn_frame_fmt, params->blk_pkg_mode, AMD_DPN_FRAME_FMT_BLK_PKG_MODE); 569 u32p_replace_bits(&dpn_frame_fmt, params->blk_grp_ctrl, AMD_DPN_FRAME_FMT_BLK_GRP_CTRL); 570 u32p_replace_bits(&dpn_frame_fmt, SDW_STREAM_PCM, AMD_DPN_FRAME_FMT_PCM_OR_PDM); 571 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg); 572 573 dpn_sampleinterval = params->sample_interval - 1; 574 writel(dpn_sampleinterval, amd_manager->mmio + sample_int_reg); 575 576 dpn_hctrl = FIELD_PREP(AMD_DPN_HCTRL_HSTOP, params->hstop); 577 dpn_hctrl |= FIELD_PREP(AMD_DPN_HCTRL_HSTART, params->hstart); 578 writel(dpn_hctrl, amd_manager->mmio + hctrl_dp0_reg); 579 580 dpn_offsetctrl = FIELD_PREP(AMD_DPN_OFFSET_CTRL_1, params->offset1); 581 dpn_offsetctrl |= FIELD_PREP(AMD_DPN_OFFSET_CTRL_2, params->offset2); 582 writel(dpn_offsetctrl, amd_manager->mmio + offset_reg); 583 584 /* 585 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask 586 * parameters. 587 */ 588 dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); 589 u32p_replace_bits(&dpn_lanectrl, params->lane_ctrl, AMD_DPN_CH_EN_LCTRL); 590 writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg); 591 return 0; 592 } 593 594 static int amd_sdw_port_enable(struct sdw_bus *bus, 595 struct sdw_enable_ch *enable_ch, 596 unsigned int bank) 597 { 598 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 599 u32 dpn_ch_enable; 600 u32 lane_ctrl_ch_en_reg; 601 602 switch (amd_manager->acp_rev) { 603 case ACP63_PCI_REV_ID: 604 switch (amd_manager->instance) { 605 case ACP_SDW0: 606 lane_ctrl_ch_en_reg = 607 acp63_sdw0_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 608 break; 609 case ACP_SDW1: 610 lane_ctrl_ch_en_reg = 611 acp63_sdw1_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 612 break; 613 default: 614 return -EINVAL; 615 } 616 break; 617 case ACP70_PCI_REV_ID: 618 case ACP71_PCI_REV_ID: 619 case ACP72_PCI_REV_ID: 620 lane_ctrl_ch_en_reg = acp70_sdw_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 621 break; 622 default: 623 return -EINVAL; 624 } 625 626 /* 627 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask 628 * parameters. 629 */ 630 dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); 631 u32p_replace_bits(&dpn_ch_enable, enable_ch->ch_mask, AMD_DPN_CH_EN_CHMASK); 632 if (enable_ch->enable) 633 writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg); 634 else 635 writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg); 636 return 0; 637 } 638 639 static int sdw_master_read_amd_prop(struct sdw_bus *bus) 640 { 641 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 642 struct fwnode_handle *link; 643 struct sdw_master_prop *prop; 644 u32 quirk_mask = 0; 645 u32 wake_en_mask = 0; 646 u32 power_mode_mask = 0; 647 char name[32]; 648 649 prop = &bus->prop; 650 /* Find manager handle */ 651 snprintf(name, sizeof(name), "mipi-sdw-link-%d-subproperties", bus->link_id); 652 link = device_get_named_child_node(bus->dev, name); 653 if (!link) { 654 dev_err(bus->dev, "Manager node %s not found\n", name); 655 return -EIO; 656 } 657 fwnode_property_read_u32(link, "amd-sdw-enable", &quirk_mask); 658 if (!(quirk_mask & AMD_SDW_QUIRK_MASK_BUS_ENABLE)) 659 prop->hw_disabled = true; 660 prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH | 661 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY; 662 663 fwnode_property_read_u32(link, "amd-sdw-wakeup-enable", &wake_en_mask); 664 amd_manager->wake_en_mask = wake_en_mask; 665 fwnode_property_read_u32(link, "amd-sdw-power-mode", &power_mode_mask); 666 amd_manager->power_mode_mask = power_mode_mask; 667 668 fwnode_handle_put(link); 669 670 return 0; 671 } 672 673 static int amd_prop_read(struct sdw_bus *bus) 674 { 675 sdw_master_read_prop(bus); 676 sdw_master_read_amd_prop(bus); 677 return 0; 678 } 679 680 static const struct sdw_master_port_ops amd_sdw_port_ops = { 681 .dpn_set_port_params = amd_sdw_port_params, 682 .dpn_set_port_transport_params = amd_sdw_transport_params, 683 .dpn_port_enable_ch = amd_sdw_port_enable, 684 }; 685 686 static const struct sdw_master_ops amd_sdw_ops = { 687 .read_prop = amd_prop_read, 688 .xfer_msg = amd_sdw_xfer_msg, 689 .read_ping_status = amd_sdw_read_ping_status, 690 }; 691 692 static int amd_sdw_hw_params(struct snd_pcm_substream *substream, 693 struct snd_pcm_hw_params *params, 694 struct snd_soc_dai *dai) 695 { 696 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 697 struct sdw_amd_dai_runtime *dai_runtime; 698 struct sdw_stream_config sconfig; 699 int ch, dir; 700 int ret; 701 702 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 703 if (!dai_runtime) 704 return -EIO; 705 706 ch = params_channels(params); 707 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 708 dir = SDW_DATA_DIR_RX; 709 else 710 dir = SDW_DATA_DIR_TX; 711 dev_dbg(amd_manager->dev, "dir:%d dai->id:0x%x\n", dir, dai->id); 712 713 sconfig.direction = dir; 714 sconfig.ch_count = ch; 715 sconfig.frame_rate = params_rate(params); 716 sconfig.type = dai_runtime->stream_type; 717 718 sconfig.bps = snd_pcm_format_width(params_format(params)); 719 720 /* Port configuration */ 721 struct sdw_port_config *pconfig __free(kfree) = kzalloc_obj(*pconfig); 722 if (!pconfig) 723 return -ENOMEM; 724 725 pconfig->num = dai->id; 726 pconfig->ch_mask = (1 << ch) - 1; 727 ret = sdw_stream_add_master(&amd_manager->bus, &sconfig, 728 pconfig, 1, dai_runtime->stream); 729 if (ret) 730 dev_err(amd_manager->dev, "add manager to stream failed:%d\n", ret); 731 732 return ret; 733 } 734 735 static int amd_sdw_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 736 { 737 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 738 struct sdw_amd_dai_runtime *dai_runtime; 739 int ret; 740 741 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 742 if (!dai_runtime) 743 return -EIO; 744 745 ret = sdw_stream_remove_master(&amd_manager->bus, dai_runtime->stream); 746 if (ret < 0) 747 dev_err(dai->dev, "remove manager from stream %s failed: %d\n", 748 dai_runtime->stream->name, ret); 749 return ret; 750 } 751 752 static int amd_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) 753 { 754 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 755 struct sdw_amd_dai_runtime *dai_runtime; 756 757 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 758 if (stream) { 759 /* first paranoia check */ 760 if (dai_runtime) { 761 dev_err(dai->dev, "dai_runtime already allocated for dai %s\n", dai->name); 762 return -EINVAL; 763 } 764 765 /* allocate and set dai_runtime info */ 766 dai_runtime = kzalloc_obj(*dai_runtime); 767 if (!dai_runtime) 768 return -ENOMEM; 769 770 dai_runtime->stream_type = SDW_STREAM_PCM; 771 dai_runtime->bus = &amd_manager->bus; 772 dai_runtime->stream = stream; 773 amd_manager->dai_runtime_array[dai->id] = dai_runtime; 774 } else { 775 /* second paranoia check */ 776 if (!dai_runtime) { 777 dev_err(dai->dev, "dai_runtime not allocated for dai %s\n", dai->name); 778 return -EINVAL; 779 } 780 781 /* for NULL stream we release allocated dai_runtime */ 782 kfree(dai_runtime); 783 amd_manager->dai_runtime_array[dai->id] = NULL; 784 } 785 return 0; 786 } 787 788 static int amd_pcm_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) 789 { 790 return amd_set_sdw_stream(dai, stream, direction); 791 } 792 793 static void *amd_get_sdw_stream(struct snd_soc_dai *dai, int direction) 794 { 795 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 796 struct sdw_amd_dai_runtime *dai_runtime; 797 798 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 799 if (!dai_runtime) 800 return ERR_PTR(-EINVAL); 801 802 return dai_runtime->stream; 803 } 804 805 static const struct snd_soc_dai_ops amd_sdw_dai_ops = { 806 .hw_params = amd_sdw_hw_params, 807 .hw_free = amd_sdw_hw_free, 808 .set_stream = amd_pcm_set_sdw_stream, 809 .get_stream = amd_get_sdw_stream, 810 }; 811 812 static const struct snd_soc_component_driver amd_sdw_dai_component = { 813 .name = "soundwire", 814 }; 815 816 static int amd_sdw_register_dais(struct amd_sdw_manager *amd_manager) 817 { 818 struct sdw_amd_dai_runtime **dai_runtime_array; 819 struct snd_soc_dai_driver *dais; 820 struct snd_soc_pcm_stream *stream; 821 struct device *dev; 822 int i, num_dais; 823 824 dev = amd_manager->dev; 825 num_dais = amd_manager->num_dout_ports + amd_manager->num_din_ports; 826 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); 827 if (!dais) 828 return -ENOMEM; 829 830 dai_runtime_array = devm_kcalloc(dev, num_dais, 831 sizeof(struct sdw_amd_dai_runtime *), 832 GFP_KERNEL); 833 if (!dai_runtime_array) 834 return -ENOMEM; 835 amd_manager->dai_runtime_array = dai_runtime_array; 836 for (i = 0; i < num_dais; i++) { 837 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW%d Pin%d", amd_manager->instance, 838 i); 839 if (!dais[i].name) 840 return -ENOMEM; 841 if (i < amd_manager->num_dout_ports) 842 stream = &dais[i].playback; 843 else 844 stream = &dais[i].capture; 845 846 stream->channels_min = 2; 847 stream->channels_max = 2; 848 stream->rates = SNDRV_PCM_RATE_48000; 849 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; 850 851 dais[i].ops = &amd_sdw_dai_ops; 852 dais[i].id = i; 853 } 854 855 return devm_snd_soc_register_component(dev, &amd_sdw_dai_component, 856 dais, num_dais); 857 } 858 859 static void amd_sdw_update_slave_status_work(struct work_struct *work) 860 { 861 struct amd_sdw_manager *amd_manager = 862 container_of(work, struct amd_sdw_manager, amd_sdw_work); 863 int retry_count = 0; 864 865 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) { 866 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 867 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 868 } 869 870 update_status: 871 sdw_handle_slave_status(&amd_manager->bus, amd_manager->status); 872 /* 873 * During the peripheral enumeration sequence, the SoundWire manager interrupts 874 * are masked. Once the device number programming is done for all peripherals, 875 * interrupts will be unmasked. Read the peripheral device status from ping command 876 * and process the response. This sequence will ensure all peripheral devices enumerated 877 * and initialized properly. 878 */ 879 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) { 880 if (retry_count++ < SDW_MAX_DEVICES) { 881 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio + 882 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 883 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio + 884 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 885 amd_sdw_read_and_process_ping_status(amd_manager); 886 goto update_status; 887 } else { 888 dev_err_ratelimited(amd_manager->dev, 889 "Device0 detected after %d iterations\n", 890 retry_count); 891 } 892 } 893 } 894 895 static void amd_sdw_update_slave_status(u32 status_change_0to7, u32 status_change_8to11, 896 struct amd_sdw_manager *amd_manager) 897 { 898 u64 slave_stat; 899 u32 val; 900 int dev_index; 901 902 if (status_change_0to7 == AMD_SDW_SLAVE_0_ATTACHED) 903 memset(amd_manager->status, 0, sizeof(amd_manager->status)); 904 slave_stat = status_change_0to7; 905 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STATUS_8TO_11, status_change_8to11) << 32; 906 dev_dbg(amd_manager->dev, "status_change_0to7:0x%x status_change_8to11:0x%x\n", 907 status_change_0to7, status_change_8to11); 908 if (slave_stat) { 909 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) { 910 if (slave_stat & AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(dev_index)) { 911 val = (slave_stat >> AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(dev_index)) & 912 AMD_SDW_MCP_SLAVE_STATUS_MASK; 913 amd_sdw_fill_slave_status(amd_manager, dev_index, val); 914 } 915 } 916 } 917 } 918 919 static void amd_sdw_process_wake_event(struct amd_sdw_manager *amd_manager) 920 { 921 dev_dbg(amd_manager->dev, "SoundWire Wake event reported\n"); 922 pm_request_resume(amd_manager->dev); 923 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 924 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 925 } 926 927 static void amd_sdw_irq_thread(struct work_struct *work) 928 { 929 struct amd_sdw_manager *amd_manager = 930 container_of(work, struct amd_sdw_manager, amd_sdw_irq_thread); 931 u32 status_change_8to11; 932 u32 status_change_0to7; 933 934 status_change_8to11 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 935 status_change_0to7 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); 936 if (!status_change_0to7 && !status_change_8to11) 937 return; 938 939 dev_dbg(amd_manager->dev, "[SDW%d] SDW INT: 0to7=0x%x, 8to11=0x%x\n", 940 amd_manager->instance, status_change_0to7, status_change_8to11); 941 if (status_change_8to11 & AMD_SDW_WAKE_STAT_MASK) 942 return amd_sdw_process_wake_event(amd_manager); 943 944 if (status_change_8to11 & AMD_SDW_PREQ_INTR_STAT) { 945 amd_sdw_read_and_process_ping_status(amd_manager); 946 } else { 947 /* Check for the updated status on peripheral device */ 948 amd_sdw_update_slave_status(status_change_0to7, status_change_8to11, amd_manager); 949 } 950 if (status_change_8to11 || status_change_0to7) 951 schedule_work(&amd_manager->amd_sdw_work); 952 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 953 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); 954 } 955 956 int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager) 957 { 958 struct sdw_master_prop *prop; 959 int ret; 960 961 prop = &amd_manager->bus.prop; 962 if (!prop->hw_disabled) { 963 ret = amd_init_sdw_manager(amd_manager); 964 if (ret) 965 return ret; 966 amd_enable_sdw_interrupts(amd_manager); 967 ret = amd_enable_sdw_manager(amd_manager); 968 if (ret) 969 return ret; 970 amd_sdw_set_frameshape(amd_manager); 971 } 972 /* Enable runtime PM */ 973 pm_runtime_set_autosuspend_delay(amd_manager->dev, AMD_SDW_MASTER_SUSPEND_DELAY_MS); 974 pm_runtime_use_autosuspend(amd_manager->dev); 975 pm_runtime_mark_last_busy(amd_manager->dev); 976 pm_runtime_set_active(amd_manager->dev); 977 pm_runtime_enable(amd_manager->dev); 978 return 0; 979 } 980 981 static int amd_sdw_manager_probe(struct platform_device *pdev) 982 { 983 const struct acp_sdw_pdata *pdata = pdev->dev.platform_data; 984 struct resource *res; 985 struct device *dev = &pdev->dev; 986 struct sdw_master_prop *prop; 987 struct sdw_bus_params *params; 988 struct amd_sdw_manager *amd_manager; 989 int ret; 990 991 amd_manager = devm_kzalloc(dev, sizeof(struct amd_sdw_manager), GFP_KERNEL); 992 if (!amd_manager) 993 return -ENOMEM; 994 995 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 996 if (!res) 997 return -ENOMEM; 998 999 amd_manager->acp_mmio = devm_ioremap(dev, res->start, resource_size(res)); 1000 if (!amd_manager->acp_mmio) { 1001 dev_err(dev, "mmio not found\n"); 1002 return -ENOMEM; 1003 } 1004 amd_manager->instance = pdata->instance; 1005 amd_manager->mmio = amd_manager->acp_mmio + 1006 (amd_manager->instance * SDW_MANAGER_REG_OFFSET); 1007 amd_manager->acp_sdw_lock = pdata->acp_sdw_lock; 1008 amd_manager->acp_rev = pdata->acp_rev; 1009 amd_manager->cols_index = sdw_find_col_index(AMD_SDW_DEFAULT_COLUMNS); 1010 amd_manager->rows_index = sdw_find_row_index(AMD_SDW_DEFAULT_ROWS); 1011 amd_manager->dev = dev; 1012 amd_manager->bus.ops = &amd_sdw_ops; 1013 amd_manager->bus.port_ops = &amd_sdw_port_ops; 1014 amd_manager->bus.compute_params = &amd_sdw_compute_params; 1015 amd_manager->bus.clk_stop_timeout = 200; 1016 amd_manager->bus.link_id = amd_manager->instance; 1017 1018 /* 1019 * Due to BIOS compatibility, the two links are exposed within 1020 * the scope of a single controller. If this changes, the 1021 * controller_id will have to be updated with drv_data 1022 * information. 1023 */ 1024 amd_manager->bus.controller_id = 0; 1025 dev_dbg(dev, "acp_rev:0x%x\n", amd_manager->acp_rev); 1026 switch (amd_manager->acp_rev) { 1027 case ACP63_PCI_REV_ID: 1028 switch (amd_manager->instance) { 1029 case ACP_SDW0: 1030 amd_manager->num_dout_ports = AMD_ACP63_SDW0_MAX_TX_PORTS; 1031 amd_manager->num_din_ports = AMD_ACP63_SDW0_MAX_RX_PORTS; 1032 break; 1033 case ACP_SDW1: 1034 amd_manager->num_dout_ports = AMD_ACP63_SDW1_MAX_TX_PORTS; 1035 amd_manager->num_din_ports = AMD_ACP63_SDW1_MAX_RX_PORTS; 1036 break; 1037 default: 1038 return -EINVAL; 1039 } 1040 break; 1041 case ACP70_PCI_REV_ID: 1042 case ACP71_PCI_REV_ID: 1043 case ACP72_PCI_REV_ID: 1044 amd_manager->num_dout_ports = AMD_ACP70_SDW_MAX_TX_PORTS; 1045 amd_manager->num_din_ports = AMD_ACP70_SDW_MAX_RX_PORTS; 1046 break; 1047 default: 1048 return -EINVAL; 1049 } 1050 1051 params = &amd_manager->bus.params; 1052 1053 params->col = AMD_SDW_DEFAULT_COLUMNS; 1054 params->row = AMD_SDW_DEFAULT_ROWS; 1055 prop = &amd_manager->bus.prop; 1056 prop->clk_freq = &amd_sdw_freq_tbl[0]; 1057 prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ; 1058 prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ; 1059 1060 ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode); 1061 if (ret) { 1062 dev_err(dev, "Failed to register SoundWire manager(%d)\n", ret); 1063 return ret; 1064 } 1065 ret = amd_sdw_register_dais(amd_manager); 1066 if (ret) { 1067 dev_err(dev, "CPU DAI registration failed\n"); 1068 sdw_bus_master_delete(&amd_manager->bus); 1069 return ret; 1070 } 1071 dev_set_drvdata(dev, amd_manager); 1072 INIT_WORK(&amd_manager->amd_sdw_irq_thread, amd_sdw_irq_thread); 1073 INIT_WORK(&amd_manager->amd_sdw_work, amd_sdw_update_slave_status_work); 1074 return 0; 1075 } 1076 1077 static void amd_sdw_manager_remove(struct platform_device *pdev) 1078 { 1079 struct amd_sdw_manager *amd_manager = dev_get_drvdata(&pdev->dev); 1080 int ret; 1081 1082 pm_runtime_disable(&pdev->dev); 1083 cancel_work_sync(&amd_manager->amd_sdw_work); 1084 amd_disable_sdw_interrupts(amd_manager); 1085 sdw_bus_master_delete(&amd_manager->bus); 1086 ret = amd_disable_sdw_manager(amd_manager); 1087 if (ret) 1088 dev_err(&pdev->dev, "Failed to disable device (%pe)\n", ERR_PTR(ret)); 1089 } 1090 1091 static int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager) 1092 { 1093 u32 val; 1094 int ret; 1095 1096 ret = sdw_bus_prep_clk_stop(&amd_manager->bus); 1097 if (ret < 0 && ret != -ENODATA) { 1098 dev_err(amd_manager->dev, "prepare clock stop failed %d", ret); 1099 return 0; 1100 } 1101 ret = sdw_bus_clk_stop(&amd_manager->bus); 1102 if (ret < 0 && ret != -ENODATA) { 1103 dev_err(amd_manager->dev, "bus clock stop failed %d", ret); 1104 return 0; 1105 } 1106 1107 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1108 (val & AMD_SDW_CLK_STOP_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT); 1109 if (ret) { 1110 dev_err(amd_manager->dev, "SDW%x clock stop failed\n", amd_manager->instance); 1111 return 0; 1112 } 1113 1114 amd_manager->clk_stopped = true; 1115 if (amd_manager->wake_en_mask) 1116 writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 1117 1118 dev_dbg(amd_manager->dev, "SDW%x clock stop successful\n", amd_manager->instance); 1119 return 0; 1120 } 1121 1122 static int amd_sdw_clock_stop_exit(struct amd_sdw_manager *amd_manager) 1123 { 1124 int ret; 1125 u32 val; 1126 1127 if (amd_manager->clk_stopped) { 1128 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1129 val |= AMD_SDW_CLK_RESUME_REQ; 1130 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1131 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1132 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US, 1133 AMD_SDW_TIMEOUT); 1134 if (val & AMD_SDW_CLK_RESUME_DONE) { 1135 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1136 ret = sdw_bus_exit_clk_stop(&amd_manager->bus); 1137 if (ret < 0) 1138 dev_err(amd_manager->dev, "bus failed to exit clock stop %d\n", 1139 ret); 1140 amd_manager->clk_stopped = false; 1141 } 1142 } 1143 if (amd_manager->clk_stopped) { 1144 dev_err(amd_manager->dev, "SDW%x clock stop exit failed\n", amd_manager->instance); 1145 return 0; 1146 } 1147 dev_dbg(amd_manager->dev, "SDW%x clock stop exit successful\n", amd_manager->instance); 1148 return 0; 1149 } 1150 1151 static int amd_resume_child_device(struct device *dev, void *data) 1152 { 1153 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1154 int ret; 1155 1156 if (!slave->probed) { 1157 dev_dbg(dev, "skipping device, no probed driver\n"); 1158 return 0; 1159 } 1160 if (!slave->dev_num_sticky) { 1161 dev_dbg(dev, "skipping device, never detected on bus\n"); 1162 return 0; 1163 } 1164 ret = pm_request_resume(dev); 1165 if (ret < 0) { 1166 dev_err(dev, "pm_request_resume failed: %d\n", ret); 1167 return ret; 1168 } 1169 return 0; 1170 } 1171 1172 static int __maybe_unused amd_pm_prepare(struct device *dev) 1173 { 1174 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1175 struct sdw_bus *bus = &amd_manager->bus; 1176 int ret; 1177 1178 if (bus->prop.hw_disabled) { 1179 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1180 bus->link_id); 1181 return 0; 1182 } 1183 /* 1184 * When multiple peripheral devices connected over the same link, if SoundWire manager 1185 * device is not in runtime suspend state, observed that device alerts are missing 1186 * without pm_prepare on AMD platforms in clockstop mode0. 1187 */ 1188 if (amd_manager->power_mode_mask) { 1189 ret = pm_runtime_resume(dev); 1190 if (ret < 0) { 1191 dev_err(bus->dev, "pm_runtime_resume failed: %d\n", ret); 1192 return 0; 1193 } 1194 } 1195 /* To force peripheral devices to system level suspend state, resume the devices 1196 * from runtime suspend state first. Without that unable to dispatch the alert 1197 * status to peripheral driver during system level resume as they are in runtime 1198 * suspend state. 1199 */ 1200 ret = device_for_each_child(bus->dev, NULL, amd_resume_child_device); 1201 if (ret < 0) 1202 dev_err(dev, "amd_resume_child_device failed: %d\n", ret); 1203 return 0; 1204 } 1205 1206 static int __maybe_unused amd_suspend(struct device *dev) 1207 { 1208 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1209 struct sdw_bus *bus = &amd_manager->bus; 1210 int ret; 1211 1212 if (bus->prop.hw_disabled) { 1213 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1214 bus->link_id); 1215 return 0; 1216 } 1217 1218 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1219 cancel_work_sync(&amd_manager->amd_sdw_work); 1220 amd_sdw_wake_enable(amd_manager, false); 1221 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1222 ret = amd_sdw_host_wake_enable(amd_manager, false); 1223 if (ret) 1224 return ret; 1225 } 1226 ret = amd_sdw_clock_stop(amd_manager); 1227 if (ret) 1228 return ret; 1229 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1230 cancel_work_sync(&amd_manager->amd_sdw_work); 1231 amd_sdw_wake_enable(amd_manager, false); 1232 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1233 ret = amd_sdw_host_wake_enable(amd_manager, false); 1234 if (ret) 1235 return ret; 1236 } 1237 /* 1238 * As per hardware programming sequence on AMD platforms, 1239 * clock stop should be invoked first before powering-off 1240 */ 1241 ret = amd_sdw_clock_stop(amd_manager); 1242 if (ret) 1243 return ret; 1244 ret = amd_deinit_sdw_manager(amd_manager); 1245 if (ret) 1246 return ret; 1247 } 1248 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1249 ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D3); 1250 if (ret) 1251 return ret; 1252 } 1253 return 0; 1254 } 1255 1256 static int __maybe_unused amd_suspend_runtime(struct device *dev) 1257 { 1258 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1259 struct sdw_bus *bus = &amd_manager->bus; 1260 int ret; 1261 u32 val; 1262 1263 if (bus->prop.hw_disabled) { 1264 dev_dbg(bus->dev, "SoundWire manager %d is disabled,\n", 1265 bus->link_id); 1266 return 0; 1267 } 1268 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1269 amd_sdw_wake_enable(amd_manager, true); 1270 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1271 ret = amd_sdw_host_wake_enable(amd_manager, true); 1272 if (ret) 1273 return ret; 1274 } 1275 ret = amd_sdw_clock_stop(amd_manager); 1276 if (ret) 1277 return ret; 1278 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1279 amd_sdw_wake_enable(amd_manager, true); 1280 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1281 ret = amd_sdw_host_wake_enable(amd_manager, true); 1282 if (ret) 1283 return ret; 1284 } 1285 ret = amd_sdw_clock_stop(amd_manager); 1286 if (ret) 1287 return ret; 1288 ret = amd_deinit_sdw_manager(amd_manager); 1289 if (ret) 1290 return ret; 1291 } 1292 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1293 ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D3); 1294 if (ret) 1295 return ret; 1296 if (amd_manager->wake_en_mask) { 1297 val = readl(amd_manager->acp_mmio + ACP_PME_EN); 1298 if (!val) { 1299 writel(1, amd_manager->acp_mmio + ACP_PME_EN); 1300 val = readl(amd_manager->acp_mmio + ACP_PME_EN); 1301 dev_dbg(amd_manager->dev, "ACP_PME_EN:0x%x\n", val); 1302 } 1303 } 1304 } 1305 return 0; 1306 } 1307 1308 static int __maybe_unused amd_resume_runtime(struct device *dev) 1309 { 1310 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1311 struct sdw_bus *bus = &amd_manager->bus; 1312 int ret; 1313 u32 val; 1314 1315 if (bus->prop.hw_disabled) { 1316 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1317 bus->link_id); 1318 return 0; 1319 } 1320 1321 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1322 ret = amd_sdw_clock_stop_exit(amd_manager); 1323 if (ret) 1324 return ret; 1325 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1326 ret = amd_sdw_host_wake_enable(amd_manager, false); 1327 if (ret) 1328 return ret; 1329 } 1330 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1331 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 1332 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1333 ret = amd_sdw_host_wake_enable(amd_manager, false); 1334 if (ret) 1335 return ret; 1336 } 1337 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1338 if (val) { 1339 val |= AMD_SDW_CLK_RESUME_REQ; 1340 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1341 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1342 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US, 1343 AMD_SDW_TIMEOUT); 1344 if (val & AMD_SDW_CLK_RESUME_DONE) { 1345 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1346 amd_manager->clk_stopped = false; 1347 } 1348 } 1349 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1350 amd_init_sdw_manager(amd_manager); 1351 amd_enable_sdw_interrupts(amd_manager); 1352 ret = amd_enable_sdw_manager(amd_manager); 1353 if (ret) 1354 return ret; 1355 amd_sdw_set_frameshape(amd_manager); 1356 } 1357 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1358 ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D0); 1359 if (ret) 1360 return ret; 1361 } 1362 return 0; 1363 } 1364 1365 static const struct dev_pm_ops amd_pm = { 1366 .prepare = amd_pm_prepare, 1367 SET_SYSTEM_SLEEP_PM_OPS(amd_suspend, amd_resume_runtime) 1368 SET_RUNTIME_PM_OPS(amd_suspend_runtime, amd_resume_runtime, NULL) 1369 }; 1370 1371 static struct platform_driver amd_sdw_driver = { 1372 .probe = &amd_sdw_manager_probe, 1373 .remove = &amd_sdw_manager_remove, 1374 .driver = { 1375 .name = "amd_sdw_manager", 1376 .pm = &amd_pm, 1377 } 1378 }; 1379 module_platform_driver(amd_sdw_driver); 1380 1381 MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 1382 MODULE_DESCRIPTION("AMD SoundWire driver"); 1383 MODULE_LICENSE("Dual BSD/GPL"); 1384 MODULE_ALIAS("platform:" DRV_NAME); 1385