1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * SoundWire AMD Manager driver 4 * 5 * Copyright 2023-24 Advanced Micro Devices, Inc. 6 */ 7 8 #include <linux/completion.h> 9 #include <linux/cleanup.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/jiffies.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/soundwire/sdw.h> 17 #include <linux/soundwire/sdw_registers.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/wait.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include "bus.h" 23 #include "amd_init.h" 24 #include "amd_manager.h" 25 26 #define DRV_NAME "amd_sdw_manager" 27 28 #define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus) 29 30 static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager) 31 { 32 u32 val; 33 int ret; 34 35 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 36 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 37 AMD_SDW_TIMEOUT); 38 if (ret) 39 return ret; 40 41 /* SoundWire manager bus reset */ 42 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 43 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, 44 (val & AMD_SDW_BUS_RESET_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT); 45 if (ret) 46 return ret; 47 48 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 49 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val, 50 ACP_DELAY_US, AMD_SDW_TIMEOUT); 51 if (ret) { 52 dev_err(amd_manager->dev, "Failed to reset SoundWire manager instance%d\n", 53 amd_manager->instance); 54 return ret; 55 } 56 57 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 58 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 59 AMD_SDW_TIMEOUT); 60 } 61 62 static int amd_enable_sdw_manager(struct amd_sdw_manager *amd_manager) 63 { 64 u32 val; 65 66 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 67 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 68 AMD_SDW_TIMEOUT); 69 } 70 71 static int amd_disable_sdw_manager(struct amd_sdw_manager *amd_manager) 72 { 73 u32 val; 74 75 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 76 /* 77 * After invoking manager disable sequence, check whether 78 * manager has executed clock stop sequence. In this case, 79 * manager should ignore checking enable status register. 80 */ 81 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 82 if (val) 83 return 0; 84 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 85 AMD_SDW_TIMEOUT); 86 } 87 88 static void amd_enable_sdw_interrupts(struct amd_sdw_manager *amd_manager) 89 { 90 u32 val; 91 92 mutex_lock(amd_manager->acp_sdw_lock); 93 val = sdw_manager_reg_mask_array[amd_manager->instance]; 94 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), val, val); 95 mutex_unlock(amd_manager->acp_sdw_lock); 96 97 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio + 98 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 99 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio + 100 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 101 writel(AMD_SDW_IRQ_ERROR_MASK, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK); 102 } 103 104 static void amd_disable_sdw_interrupts(struct amd_sdw_manager *amd_manager) 105 { 106 u32 irq_mask; 107 108 mutex_lock(amd_manager->acp_sdw_lock); 109 irq_mask = sdw_manager_reg_mask_array[amd_manager->instance]; 110 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), 111 irq_mask, 0); 112 mutex_unlock(amd_manager->acp_sdw_lock); 113 114 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 115 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 116 writel(0x00, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK); 117 } 118 119 static int amd_deinit_sdw_manager(struct amd_sdw_manager *amd_manager) 120 { 121 amd_disable_sdw_interrupts(amd_manager); 122 return amd_disable_sdw_manager(amd_manager); 123 } 124 125 static void amd_sdw_set_frameshape(struct amd_sdw_manager *amd_manager) 126 { 127 u32 frame_size; 128 129 frame_size = (amd_manager->rows_index << 3) | amd_manager->cols_index; 130 writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE); 131 } 132 133 static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable) 134 { 135 u32 wake_ctrl; 136 137 wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 138 if (enable) 139 wake_ctrl |= AMD_SDW_WAKE_INTR_MASK; 140 else 141 wake_ctrl &= ~AMD_SDW_WAKE_INTR_MASK; 142 143 writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 144 } 145 146 static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg, 147 int cmd_offset) 148 { 149 u32 upper_data; 150 u32 lower_data = 0; 151 u16 addr; 152 u8 upper_addr, lower_addr; 153 u8 data = 0; 154 155 addr = msg->addr + cmd_offset; 156 upper_addr = (addr & 0xFF00) >> 8; 157 lower_addr = addr & 0xFF; 158 159 if (msg->flags == SDW_MSG_FLAG_WRITE) 160 data = msg->buf[cmd_offset]; 161 162 upper_data = FIELD_PREP(AMD_SDW_MCP_CMD_DEV_ADDR, msg->dev_num); 163 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_COMMAND, msg->flags + 2); 164 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_HIGH, upper_addr); 165 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_LOW, lower_addr); 166 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_DATA, data); 167 168 *upper_word = upper_data; 169 *lower_word = lower_data; 170 } 171 172 static u64 amd_sdw_send_cmd_get_resp(struct amd_sdw_manager *amd_manager, u32 lower_data, 173 u32 upper_data) 174 { 175 u64 resp; 176 u32 lower_resp, upper_resp; 177 u32 sts; 178 int ret; 179 180 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 181 !(sts & AMD_SDW_IMM_CMD_BUSY), ACP_DELAY_US, AMD_SDW_TIMEOUT); 182 if (ret) { 183 dev_err(amd_manager->dev, "SDW%x previous cmd status clear failed\n", 184 amd_manager->instance); 185 return ret; 186 } 187 188 if (sts & AMD_SDW_IMM_RES_VALID) { 189 dev_err(amd_manager->dev, "SDW%x manager is in bad state\n", amd_manager->instance); 190 writel(0x00, amd_manager->mmio + ACP_SW_IMM_CMD_STS); 191 } 192 writel(upper_data, amd_manager->mmio + ACP_SW_IMM_CMD_UPPER_WORD); 193 writel(lower_data, amd_manager->mmio + ACP_SW_IMM_CMD_LOWER_QWORD); 194 195 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 196 (sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT); 197 if (ret) { 198 dev_err(amd_manager->dev, "SDW%x cmd response timeout occurred\n", 199 amd_manager->instance); 200 return ret; 201 } 202 upper_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_UPPER_WORD); 203 lower_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_LOWER_QWORD); 204 205 writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS); 206 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 207 !(sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT); 208 if (ret) { 209 dev_err(amd_manager->dev, "SDW%x cmd status retry failed\n", 210 amd_manager->instance); 211 return ret; 212 } 213 resp = upper_resp; 214 resp = (resp << 32) | lower_resp; 215 return resp; 216 } 217 218 static enum sdw_command_response 219 amd_program_scp_addr(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg) 220 { 221 struct sdw_msg scp_msg = {0}; 222 u64 response_buf[2] = {0}; 223 u32 upper_data = 0, lower_data = 0; 224 int index; 225 226 scp_msg.dev_num = msg->dev_num; 227 scp_msg.addr = SDW_SCP_ADDRPAGE1; 228 scp_msg.buf = &msg->addr_page1; 229 scp_msg.flags = SDW_MSG_FLAG_WRITE; 230 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0); 231 response_buf[0] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 232 scp_msg.addr = SDW_SCP_ADDRPAGE2; 233 scp_msg.buf = &msg->addr_page2; 234 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0); 235 response_buf[1] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 236 237 for (index = 0; index < 2; index++) { 238 if (response_buf[index] == -ETIMEDOUT) { 239 dev_err_ratelimited(amd_manager->dev, 240 "SCP_addrpage command timeout for Slave %d\n", 241 msg->dev_num); 242 return SDW_CMD_TIMEOUT; 243 } else if (!(response_buf[index] & AMD_SDW_MCP_RESP_ACK)) { 244 if (response_buf[index] & AMD_SDW_MCP_RESP_NACK) { 245 dev_err_ratelimited(amd_manager->dev, 246 "SCP_addrpage NACKed for Slave %d\n", 247 msg->dev_num); 248 return SDW_CMD_FAIL; 249 } 250 dev_dbg_ratelimited(amd_manager->dev, "SCP_addrpage ignored for Slave %d\n", 251 msg->dev_num); 252 return SDW_CMD_IGNORED; 253 } 254 } 255 return SDW_CMD_OK; 256 } 257 258 static int amd_prep_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg) 259 { 260 int ret; 261 262 if (msg->page) { 263 ret = amd_program_scp_addr(amd_manager, msg); 264 if (ret) { 265 msg->len = 0; 266 return ret; 267 } 268 } 269 switch (msg->flags) { 270 case SDW_MSG_FLAG_READ: 271 case SDW_MSG_FLAG_WRITE: 272 break; 273 default: 274 dev_err(amd_manager->dev, "Invalid msg cmd: %d\n", msg->flags); 275 return -EINVAL; 276 } 277 return 0; 278 } 279 280 static enum sdw_command_response amd_sdw_fill_msg_resp(struct amd_sdw_manager *amd_manager, 281 struct sdw_msg *msg, u64 response, 282 int offset) 283 { 284 if (response & AMD_SDW_MCP_RESP_ACK) { 285 if (msg->flags == SDW_MSG_FLAG_READ) 286 msg->buf[offset] = FIELD_GET(AMD_SDW_MCP_RESP_RDATA, response); 287 } else { 288 if (response == -ETIMEDOUT) { 289 dev_err_ratelimited(amd_manager->dev, "command timeout for Slave %d\n", 290 msg->dev_num); 291 return SDW_CMD_TIMEOUT; 292 } else if (response & AMD_SDW_MCP_RESP_NACK) { 293 dev_err_ratelimited(amd_manager->dev, 294 "command response NACK received for Slave %d\n", 295 msg->dev_num); 296 return SDW_CMD_FAIL; 297 } 298 dev_err_ratelimited(amd_manager->dev, "command is ignored for Slave %d\n", 299 msg->dev_num); 300 return SDW_CMD_IGNORED; 301 } 302 return SDW_CMD_OK; 303 } 304 305 static unsigned int _amd_sdw_xfer_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg, 306 int cmd_offset) 307 { 308 u64 response; 309 u32 upper_data = 0, lower_data = 0; 310 311 amd_sdw_ctl_word_prep(&lower_data, &upper_data, msg, cmd_offset); 312 response = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 313 return amd_sdw_fill_msg_resp(amd_manager, msg, response, cmd_offset); 314 } 315 316 static enum sdw_command_response amd_sdw_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg) 317 { 318 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 319 int ret, i; 320 321 ret = amd_prep_msg(amd_manager, msg); 322 if (ret) 323 return SDW_CMD_FAIL_OTHER; 324 for (i = 0; i < msg->len; i++) { 325 ret = _amd_sdw_xfer_msg(amd_manager, msg, i); 326 if (ret) 327 return ret; 328 } 329 return SDW_CMD_OK; 330 } 331 332 static void amd_sdw_fill_slave_status(struct amd_sdw_manager *amd_manager, u16 index, u32 status) 333 { 334 switch (status) { 335 case SDW_SLAVE_ATTACHED: 336 case SDW_SLAVE_UNATTACHED: 337 case SDW_SLAVE_ALERT: 338 amd_manager->status[index] = status; 339 break; 340 default: 341 amd_manager->status[index] = SDW_SLAVE_RESERVED; 342 break; 343 } 344 } 345 346 static void amd_sdw_process_ping_status(u64 response, struct amd_sdw_manager *amd_manager) 347 { 348 u64 slave_stat; 349 u32 val; 350 u16 dev_index; 351 352 /* slave status response */ 353 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response); 354 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8; 355 dev_dbg(amd_manager->dev, "slave_stat:0x%llx\n", slave_stat); 356 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) { 357 val = (slave_stat >> (dev_index * 2)) & AMD_SDW_MCP_SLAVE_STATUS_MASK; 358 dev_dbg(amd_manager->dev, "val:0x%x\n", val); 359 amd_sdw_fill_slave_status(amd_manager, dev_index, val); 360 } 361 } 362 363 static void amd_sdw_read_and_process_ping_status(struct amd_sdw_manager *amd_manager) 364 { 365 u64 response; 366 367 mutex_lock(&amd_manager->bus.msg_lock); 368 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0); 369 mutex_unlock(&amd_manager->bus.msg_lock); 370 amd_sdw_process_ping_status(response, amd_manager); 371 } 372 373 static u32 amd_sdw_read_ping_status(struct sdw_bus *bus) 374 { 375 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 376 u64 response; 377 u32 slave_stat; 378 379 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0); 380 /* slave status from ping response */ 381 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response); 382 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8; 383 dev_dbg(amd_manager->dev, "slave_stat:0x%x\n", slave_stat); 384 return slave_stat; 385 } 386 387 static int amd_sdw_compute_params(struct sdw_bus *bus) 388 { 389 struct sdw_transport_data t_data = {0}; 390 struct sdw_master_runtime *m_rt; 391 struct sdw_port_runtime *p_rt; 392 struct sdw_bus_params *b_params = &bus->params; 393 int port_bo, hstart, hstop, sample_int; 394 unsigned int rate, bps; 395 396 port_bo = 0; 397 hstart = 1; 398 hstop = bus->params.col - 1; 399 t_data.hstop = hstop; 400 t_data.hstart = hstart; 401 402 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 403 rate = m_rt->stream->params.rate; 404 bps = m_rt->stream->params.bps; 405 sample_int = (bus->params.curr_dr_freq / rate); 406 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 407 port_bo = (p_rt->num * 64) + 1; 408 dev_dbg(bus->dev, "p_rt->num=%d hstart=%d hstop=%d port_bo=%d\n", 409 p_rt->num, hstart, hstop, port_bo); 410 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, 411 false, SDW_BLK_GRP_CNT_1, sample_int, 412 port_bo, port_bo >> 8, hstart, hstop, 413 SDW_BLK_PKG_PER_PORT, 0x0); 414 415 sdw_fill_port_params(&p_rt->port_params, 416 p_rt->num, bps, 417 SDW_PORT_FLOW_MODE_ISOCH, 418 b_params->m_data_mode); 419 t_data.hstart = hstart; 420 t_data.hstop = hstop; 421 t_data.block_offset = port_bo; 422 t_data.sub_block_offset = 0; 423 } 424 sdw_compute_slave_ports(m_rt, &t_data); 425 } 426 return 0; 427 } 428 429 static int amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_params, 430 unsigned int bank) 431 { 432 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 433 u32 frame_fmt_reg, dpn_frame_fmt; 434 435 dev_dbg(amd_manager->dev, "p_params->num:0x%x\n", p_params->num); 436 switch (amd_manager->acp_rev) { 437 case ACP63_PCI_REV_ID: 438 switch (amd_manager->instance) { 439 case ACP_SDW0: 440 frame_fmt_reg = acp63_sdw0_dp_reg[p_params->num].frame_fmt_reg; 441 break; 442 case ACP_SDW1: 443 frame_fmt_reg = acp63_sdw1_dp_reg[p_params->num].frame_fmt_reg; 444 break; 445 default: 446 return -EINVAL; 447 } 448 break; 449 default: 450 return -EINVAL; 451 } 452 453 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg); 454 u32p_replace_bits(&dpn_frame_fmt, p_params->flow_mode, AMD_DPN_FRAME_FMT_PFM); 455 u32p_replace_bits(&dpn_frame_fmt, p_params->data_mode, AMD_DPN_FRAME_FMT_PDM); 456 u32p_replace_bits(&dpn_frame_fmt, p_params->bps - 1, AMD_DPN_FRAME_FMT_WORD_LEN); 457 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg); 458 return 0; 459 } 460 461 static int amd_sdw_transport_params(struct sdw_bus *bus, 462 struct sdw_transport_params *params, 463 enum sdw_reg_bank bank) 464 { 465 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 466 u32 dpn_frame_fmt; 467 u32 dpn_sampleinterval; 468 u32 dpn_hctrl; 469 u32 dpn_offsetctrl; 470 u32 dpn_lanectrl; 471 u32 frame_fmt_reg, sample_int_reg, hctrl_dp0_reg; 472 u32 offset_reg, lane_ctrl_ch_en_reg; 473 474 switch (amd_manager->acp_rev) { 475 case ACP63_PCI_REV_ID: 476 switch (amd_manager->instance) { 477 case ACP_SDW0: 478 frame_fmt_reg = acp63_sdw0_dp_reg[params->port_num].frame_fmt_reg; 479 sample_int_reg = acp63_sdw0_dp_reg[params->port_num].sample_int_reg; 480 hctrl_dp0_reg = acp63_sdw0_dp_reg[params->port_num].hctrl_dp0_reg; 481 offset_reg = acp63_sdw0_dp_reg[params->port_num].offset_reg; 482 lane_ctrl_ch_en_reg = 483 acp63_sdw0_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 484 break; 485 case ACP_SDW1: 486 frame_fmt_reg = acp63_sdw1_dp_reg[params->port_num].frame_fmt_reg; 487 sample_int_reg = acp63_sdw1_dp_reg[params->port_num].sample_int_reg; 488 hctrl_dp0_reg = acp63_sdw1_dp_reg[params->port_num].hctrl_dp0_reg; 489 offset_reg = acp63_sdw1_dp_reg[params->port_num].offset_reg; 490 lane_ctrl_ch_en_reg = 491 acp63_sdw1_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 492 break; 493 default: 494 return -EINVAL; 495 } 496 break; 497 default: 498 return -EINVAL; 499 } 500 writel(AMD_SDW_SSP_COUNTER_VAL, amd_manager->mmio + ACP_SW_SSP_COUNTER); 501 502 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg); 503 u32p_replace_bits(&dpn_frame_fmt, params->blk_pkg_mode, AMD_DPN_FRAME_FMT_BLK_PKG_MODE); 504 u32p_replace_bits(&dpn_frame_fmt, params->blk_grp_ctrl, AMD_DPN_FRAME_FMT_BLK_GRP_CTRL); 505 u32p_replace_bits(&dpn_frame_fmt, SDW_STREAM_PCM, AMD_DPN_FRAME_FMT_PCM_OR_PDM); 506 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg); 507 508 dpn_sampleinterval = params->sample_interval - 1; 509 writel(dpn_sampleinterval, amd_manager->mmio + sample_int_reg); 510 511 dpn_hctrl = FIELD_PREP(AMD_DPN_HCTRL_HSTOP, params->hstop); 512 dpn_hctrl |= FIELD_PREP(AMD_DPN_HCTRL_HSTART, params->hstart); 513 writel(dpn_hctrl, amd_manager->mmio + hctrl_dp0_reg); 514 515 dpn_offsetctrl = FIELD_PREP(AMD_DPN_OFFSET_CTRL_1, params->offset1); 516 dpn_offsetctrl |= FIELD_PREP(AMD_DPN_OFFSET_CTRL_2, params->offset2); 517 writel(dpn_offsetctrl, amd_manager->mmio + offset_reg); 518 519 /* 520 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask 521 * parameters. 522 */ 523 dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); 524 u32p_replace_bits(&dpn_lanectrl, params->lane_ctrl, AMD_DPN_CH_EN_LCTRL); 525 writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg); 526 return 0; 527 } 528 529 static int amd_sdw_port_enable(struct sdw_bus *bus, 530 struct sdw_enable_ch *enable_ch, 531 unsigned int bank) 532 { 533 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 534 u32 dpn_ch_enable; 535 u32 lane_ctrl_ch_en_reg; 536 537 switch (amd_manager->acp_rev) { 538 case ACP63_PCI_REV_ID: 539 switch (amd_manager->instance) { 540 case ACP_SDW0: 541 lane_ctrl_ch_en_reg = 542 acp63_sdw0_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 543 break; 544 case ACP_SDW1: 545 lane_ctrl_ch_en_reg = 546 acp63_sdw1_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 547 break; 548 default: 549 return -EINVAL; 550 } 551 break; 552 default: 553 return -EINVAL; 554 } 555 556 /* 557 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask 558 * parameters. 559 */ 560 dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); 561 u32p_replace_bits(&dpn_ch_enable, enable_ch->ch_mask, AMD_DPN_CH_EN_CHMASK); 562 if (enable_ch->enable) 563 writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg); 564 else 565 writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg); 566 return 0; 567 } 568 569 static int sdw_master_read_amd_prop(struct sdw_bus *bus) 570 { 571 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 572 struct fwnode_handle *link; 573 struct sdw_master_prop *prop; 574 u32 quirk_mask = 0; 575 u32 wake_en_mask = 0; 576 u32 power_mode_mask = 0; 577 char name[32]; 578 579 prop = &bus->prop; 580 /* Find manager handle */ 581 snprintf(name, sizeof(name), "mipi-sdw-link-%d-subproperties", bus->link_id); 582 link = device_get_named_child_node(bus->dev, name); 583 if (!link) { 584 dev_err(bus->dev, "Manager node %s not found\n", name); 585 return -EIO; 586 } 587 fwnode_property_read_u32(link, "amd-sdw-enable", &quirk_mask); 588 if (!(quirk_mask & AMD_SDW_QUIRK_MASK_BUS_ENABLE)) 589 prop->hw_disabled = true; 590 prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH | 591 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY; 592 593 fwnode_property_read_u32(link, "amd-sdw-wakeup-enable", &wake_en_mask); 594 amd_manager->wake_en_mask = wake_en_mask; 595 fwnode_property_read_u32(link, "amd-sdw-power-mode", &power_mode_mask); 596 amd_manager->power_mode_mask = power_mode_mask; 597 598 fwnode_handle_put(link); 599 600 return 0; 601 } 602 603 static int amd_prop_read(struct sdw_bus *bus) 604 { 605 sdw_master_read_prop(bus); 606 sdw_master_read_amd_prop(bus); 607 return 0; 608 } 609 610 static const struct sdw_master_port_ops amd_sdw_port_ops = { 611 .dpn_set_port_params = amd_sdw_port_params, 612 .dpn_set_port_transport_params = amd_sdw_transport_params, 613 .dpn_port_enable_ch = amd_sdw_port_enable, 614 }; 615 616 static const struct sdw_master_ops amd_sdw_ops = { 617 .read_prop = amd_prop_read, 618 .xfer_msg = amd_sdw_xfer_msg, 619 .read_ping_status = amd_sdw_read_ping_status, 620 }; 621 622 static int amd_sdw_hw_params(struct snd_pcm_substream *substream, 623 struct snd_pcm_hw_params *params, 624 struct snd_soc_dai *dai) 625 { 626 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 627 struct sdw_amd_dai_runtime *dai_runtime; 628 struct sdw_stream_config sconfig; 629 int ch, dir; 630 int ret; 631 632 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 633 if (!dai_runtime) 634 return -EIO; 635 636 ch = params_channels(params); 637 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 638 dir = SDW_DATA_DIR_RX; 639 else 640 dir = SDW_DATA_DIR_TX; 641 dev_dbg(amd_manager->dev, "dir:%d dai->id:0x%x\n", dir, dai->id); 642 643 sconfig.direction = dir; 644 sconfig.ch_count = ch; 645 sconfig.frame_rate = params_rate(params); 646 sconfig.type = dai_runtime->stream_type; 647 648 sconfig.bps = snd_pcm_format_width(params_format(params)); 649 650 /* Port configuration */ 651 struct sdw_port_config *pconfig __free(kfree) = kzalloc(sizeof(*pconfig), 652 GFP_KERNEL); 653 if (!pconfig) 654 return -ENOMEM; 655 656 pconfig->num = dai->id; 657 pconfig->ch_mask = (1 << ch) - 1; 658 ret = sdw_stream_add_master(&amd_manager->bus, &sconfig, 659 pconfig, 1, dai_runtime->stream); 660 if (ret) 661 dev_err(amd_manager->dev, "add manager to stream failed:%d\n", ret); 662 663 return ret; 664 } 665 666 static int amd_sdw_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 667 { 668 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 669 struct sdw_amd_dai_runtime *dai_runtime; 670 int ret; 671 672 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 673 if (!dai_runtime) 674 return -EIO; 675 676 ret = sdw_stream_remove_master(&amd_manager->bus, dai_runtime->stream); 677 if (ret < 0) 678 dev_err(dai->dev, "remove manager from stream %s failed: %d\n", 679 dai_runtime->stream->name, ret); 680 return ret; 681 } 682 683 static int amd_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) 684 { 685 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 686 struct sdw_amd_dai_runtime *dai_runtime; 687 688 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 689 if (stream) { 690 /* first paranoia check */ 691 if (dai_runtime) { 692 dev_err(dai->dev, "dai_runtime already allocated for dai %s\n", dai->name); 693 return -EINVAL; 694 } 695 696 /* allocate and set dai_runtime info */ 697 dai_runtime = kzalloc(sizeof(*dai_runtime), GFP_KERNEL); 698 if (!dai_runtime) 699 return -ENOMEM; 700 701 dai_runtime->stream_type = SDW_STREAM_PCM; 702 dai_runtime->bus = &amd_manager->bus; 703 dai_runtime->stream = stream; 704 amd_manager->dai_runtime_array[dai->id] = dai_runtime; 705 } else { 706 /* second paranoia check */ 707 if (!dai_runtime) { 708 dev_err(dai->dev, "dai_runtime not allocated for dai %s\n", dai->name); 709 return -EINVAL; 710 } 711 712 /* for NULL stream we release allocated dai_runtime */ 713 kfree(dai_runtime); 714 amd_manager->dai_runtime_array[dai->id] = NULL; 715 } 716 return 0; 717 } 718 719 static int amd_pcm_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) 720 { 721 return amd_set_sdw_stream(dai, stream, direction); 722 } 723 724 static void *amd_get_sdw_stream(struct snd_soc_dai *dai, int direction) 725 { 726 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 727 struct sdw_amd_dai_runtime *dai_runtime; 728 729 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 730 if (!dai_runtime) 731 return ERR_PTR(-EINVAL); 732 733 return dai_runtime->stream; 734 } 735 736 static const struct snd_soc_dai_ops amd_sdw_dai_ops = { 737 .hw_params = amd_sdw_hw_params, 738 .hw_free = amd_sdw_hw_free, 739 .set_stream = amd_pcm_set_sdw_stream, 740 .get_stream = amd_get_sdw_stream, 741 }; 742 743 static const struct snd_soc_component_driver amd_sdw_dai_component = { 744 .name = "soundwire", 745 }; 746 747 static int amd_sdw_register_dais(struct amd_sdw_manager *amd_manager) 748 { 749 struct sdw_amd_dai_runtime **dai_runtime_array; 750 struct snd_soc_dai_driver *dais; 751 struct snd_soc_pcm_stream *stream; 752 struct device *dev; 753 int i, num_dais; 754 755 dev = amd_manager->dev; 756 num_dais = amd_manager->num_dout_ports + amd_manager->num_din_ports; 757 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); 758 if (!dais) 759 return -ENOMEM; 760 761 dai_runtime_array = devm_kcalloc(dev, num_dais, 762 sizeof(struct sdw_amd_dai_runtime *), 763 GFP_KERNEL); 764 if (!dai_runtime_array) 765 return -ENOMEM; 766 amd_manager->dai_runtime_array = dai_runtime_array; 767 for (i = 0; i < num_dais; i++) { 768 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW%d Pin%d", amd_manager->instance, 769 i); 770 if (!dais[i].name) 771 return -ENOMEM; 772 if (i < amd_manager->num_dout_ports) 773 stream = &dais[i].playback; 774 else 775 stream = &dais[i].capture; 776 777 stream->channels_min = 2; 778 stream->channels_max = 2; 779 stream->rates = SNDRV_PCM_RATE_48000; 780 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; 781 782 dais[i].ops = &amd_sdw_dai_ops; 783 dais[i].id = i; 784 } 785 786 return devm_snd_soc_register_component(dev, &amd_sdw_dai_component, 787 dais, num_dais); 788 } 789 790 static void amd_sdw_update_slave_status_work(struct work_struct *work) 791 { 792 struct amd_sdw_manager *amd_manager = 793 container_of(work, struct amd_sdw_manager, amd_sdw_work); 794 int retry_count = 0; 795 796 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) { 797 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 798 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 799 } 800 801 update_status: 802 sdw_handle_slave_status(&amd_manager->bus, amd_manager->status); 803 /* 804 * During the peripheral enumeration sequence, the SoundWire manager interrupts 805 * are masked. Once the device number programming is done for all peripherals, 806 * interrupts will be unmasked. Read the peripheral device status from ping command 807 * and process the response. This sequence will ensure all peripheral devices enumerated 808 * and initialized properly. 809 */ 810 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) { 811 if (retry_count++ < SDW_MAX_DEVICES) { 812 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio + 813 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 814 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio + 815 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 816 amd_sdw_read_and_process_ping_status(amd_manager); 817 goto update_status; 818 } else { 819 dev_err_ratelimited(amd_manager->dev, 820 "Device0 detected after %d iterations\n", 821 retry_count); 822 } 823 } 824 } 825 826 static void amd_sdw_update_slave_status(u32 status_change_0to7, u32 status_change_8to11, 827 struct amd_sdw_manager *amd_manager) 828 { 829 u64 slave_stat; 830 u32 val; 831 int dev_index; 832 833 if (status_change_0to7 == AMD_SDW_SLAVE_0_ATTACHED) 834 memset(amd_manager->status, 0, sizeof(amd_manager->status)); 835 slave_stat = status_change_0to7; 836 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STATUS_8TO_11, status_change_8to11) << 32; 837 dev_dbg(amd_manager->dev, "status_change_0to7:0x%x status_change_8to11:0x%x\n", 838 status_change_0to7, status_change_8to11); 839 if (slave_stat) { 840 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) { 841 if (slave_stat & AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(dev_index)) { 842 val = (slave_stat >> AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(dev_index)) & 843 AMD_SDW_MCP_SLAVE_STATUS_MASK; 844 amd_sdw_fill_slave_status(amd_manager, dev_index, val); 845 } 846 } 847 } 848 } 849 850 static void amd_sdw_process_wake_event(struct amd_sdw_manager *amd_manager) 851 { 852 pm_request_resume(amd_manager->dev); 853 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 854 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 855 } 856 857 static void amd_sdw_irq_thread(struct work_struct *work) 858 { 859 struct amd_sdw_manager *amd_manager = 860 container_of(work, struct amd_sdw_manager, amd_sdw_irq_thread); 861 u32 status_change_8to11; 862 u32 status_change_0to7; 863 864 status_change_8to11 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 865 status_change_0to7 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); 866 dev_dbg(amd_manager->dev, "[SDW%d] SDW INT: 0to7=0x%x, 8to11=0x%x\n", 867 amd_manager->instance, status_change_0to7, status_change_8to11); 868 if (status_change_8to11 & AMD_SDW_WAKE_STAT_MASK) 869 return amd_sdw_process_wake_event(amd_manager); 870 871 if (status_change_8to11 & AMD_SDW_PREQ_INTR_STAT) { 872 amd_sdw_read_and_process_ping_status(amd_manager); 873 } else { 874 /* Check for the updated status on peripheral device */ 875 amd_sdw_update_slave_status(status_change_0to7, status_change_8to11, amd_manager); 876 } 877 if (status_change_8to11 || status_change_0to7) 878 schedule_work(&amd_manager->amd_sdw_work); 879 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 880 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); 881 } 882 883 int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager) 884 { 885 struct sdw_master_prop *prop; 886 int ret; 887 888 prop = &amd_manager->bus.prop; 889 if (!prop->hw_disabled) { 890 ret = amd_init_sdw_manager(amd_manager); 891 if (ret) 892 return ret; 893 amd_enable_sdw_interrupts(amd_manager); 894 ret = amd_enable_sdw_manager(amd_manager); 895 if (ret) 896 return ret; 897 amd_sdw_set_frameshape(amd_manager); 898 } 899 /* Enable runtime PM */ 900 pm_runtime_set_autosuspend_delay(amd_manager->dev, AMD_SDW_MASTER_SUSPEND_DELAY_MS); 901 pm_runtime_use_autosuspend(amd_manager->dev); 902 pm_runtime_mark_last_busy(amd_manager->dev); 903 pm_runtime_set_active(amd_manager->dev); 904 pm_runtime_enable(amd_manager->dev); 905 return 0; 906 } 907 908 static int amd_sdw_manager_probe(struct platform_device *pdev) 909 { 910 const struct acp_sdw_pdata *pdata = pdev->dev.platform_data; 911 struct resource *res; 912 struct device *dev = &pdev->dev; 913 struct sdw_master_prop *prop; 914 struct sdw_bus_params *params; 915 struct amd_sdw_manager *amd_manager; 916 int ret; 917 918 amd_manager = devm_kzalloc(dev, sizeof(struct amd_sdw_manager), GFP_KERNEL); 919 if (!amd_manager) 920 return -ENOMEM; 921 922 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 923 if (!res) 924 return -ENOMEM; 925 926 amd_manager->acp_mmio = devm_ioremap(dev, res->start, resource_size(res)); 927 if (!amd_manager->acp_mmio) { 928 dev_err(dev, "mmio not found\n"); 929 return -ENOMEM; 930 } 931 amd_manager->instance = pdata->instance; 932 amd_manager->mmio = amd_manager->acp_mmio + 933 (amd_manager->instance * SDW_MANAGER_REG_OFFSET); 934 amd_manager->acp_sdw_lock = pdata->acp_sdw_lock; 935 amd_manager->acp_rev = pdata->acp_rev; 936 amd_manager->cols_index = sdw_find_col_index(AMD_SDW_DEFAULT_COLUMNS); 937 amd_manager->rows_index = sdw_find_row_index(AMD_SDW_DEFAULT_ROWS); 938 amd_manager->dev = dev; 939 amd_manager->bus.ops = &amd_sdw_ops; 940 amd_manager->bus.port_ops = &amd_sdw_port_ops; 941 amd_manager->bus.compute_params = &amd_sdw_compute_params; 942 amd_manager->bus.clk_stop_timeout = 200; 943 amd_manager->bus.link_id = amd_manager->instance; 944 945 /* 946 * Due to BIOS compatibility, the two links are exposed within 947 * the scope of a single controller. If this changes, the 948 * controller_id will have to be updated with drv_data 949 * information. 950 */ 951 amd_manager->bus.controller_id = 0; 952 dev_dbg(dev, "acp_rev:0x%x\n", amd_manager->acp_rev); 953 switch (amd_manager->acp_rev) { 954 case ACP63_PCI_REV_ID: 955 switch (amd_manager->instance) { 956 case ACP_SDW0: 957 amd_manager->num_dout_ports = AMD_ACP63_SDW0_MAX_TX_PORTS; 958 amd_manager->num_din_ports = AMD_ACP63_SDW0_MAX_RX_PORTS; 959 break; 960 case ACP_SDW1: 961 amd_manager->num_dout_ports = AMD_ACP63_SDW1_MAX_TX_PORTS; 962 amd_manager->num_din_ports = AMD_ACP63_SDW1_MAX_RX_PORTS; 963 break; 964 default: 965 return -EINVAL; 966 } 967 break; 968 default: 969 return -EINVAL; 970 } 971 972 params = &amd_manager->bus.params; 973 974 params->col = AMD_SDW_DEFAULT_COLUMNS; 975 params->row = AMD_SDW_DEFAULT_ROWS; 976 prop = &amd_manager->bus.prop; 977 prop->clk_freq = &amd_sdw_freq_tbl[0]; 978 prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ; 979 prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ; 980 981 ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode); 982 if (ret) { 983 dev_err(dev, "Failed to register SoundWire manager(%d)\n", ret); 984 return ret; 985 } 986 ret = amd_sdw_register_dais(amd_manager); 987 if (ret) { 988 dev_err(dev, "CPU DAI registration failed\n"); 989 sdw_bus_master_delete(&amd_manager->bus); 990 return ret; 991 } 992 dev_set_drvdata(dev, amd_manager); 993 INIT_WORK(&amd_manager->amd_sdw_irq_thread, amd_sdw_irq_thread); 994 INIT_WORK(&amd_manager->amd_sdw_work, amd_sdw_update_slave_status_work); 995 return 0; 996 } 997 998 static void amd_sdw_manager_remove(struct platform_device *pdev) 999 { 1000 struct amd_sdw_manager *amd_manager = dev_get_drvdata(&pdev->dev); 1001 int ret; 1002 1003 pm_runtime_disable(&pdev->dev); 1004 amd_disable_sdw_interrupts(amd_manager); 1005 sdw_bus_master_delete(&amd_manager->bus); 1006 ret = amd_disable_sdw_manager(amd_manager); 1007 if (ret) 1008 dev_err(&pdev->dev, "Failed to disable device (%pe)\n", ERR_PTR(ret)); 1009 } 1010 1011 static int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager) 1012 { 1013 u32 val; 1014 int ret; 1015 1016 ret = sdw_bus_prep_clk_stop(&amd_manager->bus); 1017 if (ret < 0 && ret != -ENODATA) { 1018 dev_err(amd_manager->dev, "prepare clock stop failed %d", ret); 1019 return 0; 1020 } 1021 ret = sdw_bus_clk_stop(&amd_manager->bus); 1022 if (ret < 0 && ret != -ENODATA) { 1023 dev_err(amd_manager->dev, "bus clock stop failed %d", ret); 1024 return 0; 1025 } 1026 1027 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1028 (val & AMD_SDW_CLK_STOP_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT); 1029 if (ret) { 1030 dev_err(amd_manager->dev, "SDW%x clock stop failed\n", amd_manager->instance); 1031 return 0; 1032 } 1033 1034 amd_manager->clk_stopped = true; 1035 if (amd_manager->wake_en_mask) 1036 writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 1037 1038 dev_dbg(amd_manager->dev, "SDW%x clock stop successful\n", amd_manager->instance); 1039 return 0; 1040 } 1041 1042 static int amd_sdw_clock_stop_exit(struct amd_sdw_manager *amd_manager) 1043 { 1044 int ret; 1045 u32 val; 1046 1047 if (amd_manager->clk_stopped) { 1048 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1049 val |= AMD_SDW_CLK_RESUME_REQ; 1050 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1051 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1052 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US, 1053 AMD_SDW_TIMEOUT); 1054 if (val & AMD_SDW_CLK_RESUME_DONE) { 1055 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1056 ret = sdw_bus_exit_clk_stop(&amd_manager->bus); 1057 if (ret < 0) 1058 dev_err(amd_manager->dev, "bus failed to exit clock stop %d\n", 1059 ret); 1060 amd_manager->clk_stopped = false; 1061 } 1062 } 1063 if (amd_manager->clk_stopped) { 1064 dev_err(amd_manager->dev, "SDW%x clock stop exit failed\n", amd_manager->instance); 1065 return 0; 1066 } 1067 dev_dbg(amd_manager->dev, "SDW%x clock stop exit successful\n", amd_manager->instance); 1068 return 0; 1069 } 1070 1071 static int amd_resume_child_device(struct device *dev, void *data) 1072 { 1073 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1074 int ret; 1075 1076 if (!slave->probed) { 1077 dev_dbg(dev, "skipping device, no probed driver\n"); 1078 return 0; 1079 } 1080 if (!slave->dev_num_sticky) { 1081 dev_dbg(dev, "skipping device, never detected on bus\n"); 1082 return 0; 1083 } 1084 ret = pm_request_resume(dev); 1085 if (ret < 0) { 1086 dev_err(dev, "pm_request_resume failed: %d\n", ret); 1087 return ret; 1088 } 1089 return 0; 1090 } 1091 1092 static int __maybe_unused amd_pm_prepare(struct device *dev) 1093 { 1094 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1095 struct sdw_bus *bus = &amd_manager->bus; 1096 int ret; 1097 1098 if (bus->prop.hw_disabled) { 1099 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1100 bus->link_id); 1101 return 0; 1102 } 1103 /* 1104 * When multiple peripheral devices connected over the same link, if SoundWire manager 1105 * device is not in runtime suspend state, observed that device alerts are missing 1106 * without pm_prepare on AMD platforms in clockstop mode0. 1107 */ 1108 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1109 ret = pm_request_resume(dev); 1110 if (ret < 0) { 1111 dev_err(bus->dev, "pm_request_resume failed: %d\n", ret); 1112 return 0; 1113 } 1114 } 1115 /* To force peripheral devices to system level suspend state, resume the devices 1116 * from runtime suspend state first. Without that unable to dispatch the alert 1117 * status to peripheral driver during system level resume as they are in runtime 1118 * suspend state. 1119 */ 1120 ret = device_for_each_child(bus->dev, NULL, amd_resume_child_device); 1121 if (ret < 0) 1122 dev_err(dev, "amd_resume_child_device failed: %d\n", ret); 1123 return 0; 1124 } 1125 1126 static int __maybe_unused amd_suspend(struct device *dev) 1127 { 1128 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1129 struct sdw_bus *bus = &amd_manager->bus; 1130 int ret; 1131 1132 if (bus->prop.hw_disabled) { 1133 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1134 bus->link_id); 1135 return 0; 1136 } 1137 1138 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1139 amd_sdw_wake_enable(amd_manager, false); 1140 return amd_sdw_clock_stop(amd_manager); 1141 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1142 /* 1143 * As per hardware programming sequence on AMD platforms, 1144 * clock stop should be invoked first before powering-off 1145 */ 1146 ret = amd_sdw_clock_stop(amd_manager); 1147 if (ret) 1148 return ret; 1149 return amd_deinit_sdw_manager(amd_manager); 1150 } 1151 return 0; 1152 } 1153 1154 static int __maybe_unused amd_suspend_runtime(struct device *dev) 1155 { 1156 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1157 struct sdw_bus *bus = &amd_manager->bus; 1158 int ret; 1159 1160 if (bus->prop.hw_disabled) { 1161 dev_dbg(bus->dev, "SoundWire manager %d is disabled,\n", 1162 bus->link_id); 1163 return 0; 1164 } 1165 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1166 amd_sdw_wake_enable(amd_manager, true); 1167 return amd_sdw_clock_stop(amd_manager); 1168 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1169 ret = amd_sdw_clock_stop(amd_manager); 1170 if (ret) 1171 return ret; 1172 return amd_deinit_sdw_manager(amd_manager); 1173 } 1174 return 0; 1175 } 1176 1177 static int __maybe_unused amd_resume_runtime(struct device *dev) 1178 { 1179 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1180 struct sdw_bus *bus = &amd_manager->bus; 1181 int ret; 1182 u32 val; 1183 1184 if (bus->prop.hw_disabled) { 1185 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1186 bus->link_id); 1187 return 0; 1188 } 1189 1190 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1191 return amd_sdw_clock_stop_exit(amd_manager); 1192 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1193 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1194 if (val) { 1195 val |= AMD_SDW_CLK_RESUME_REQ; 1196 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1197 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1198 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US, 1199 AMD_SDW_TIMEOUT); 1200 if (val & AMD_SDW_CLK_RESUME_DONE) { 1201 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1202 amd_manager->clk_stopped = false; 1203 } 1204 } 1205 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1206 amd_init_sdw_manager(amd_manager); 1207 amd_enable_sdw_interrupts(amd_manager); 1208 ret = amd_enable_sdw_manager(amd_manager); 1209 if (ret) 1210 return ret; 1211 amd_sdw_set_frameshape(amd_manager); 1212 } 1213 return 0; 1214 } 1215 1216 static const struct dev_pm_ops amd_pm = { 1217 .prepare = amd_pm_prepare, 1218 SET_SYSTEM_SLEEP_PM_OPS(amd_suspend, amd_resume_runtime) 1219 SET_RUNTIME_PM_OPS(amd_suspend_runtime, amd_resume_runtime, NULL) 1220 }; 1221 1222 static struct platform_driver amd_sdw_driver = { 1223 .probe = &amd_sdw_manager_probe, 1224 .remove_new = &amd_sdw_manager_remove, 1225 .driver = { 1226 .name = "amd_sdw_manager", 1227 .pm = &amd_pm, 1228 } 1229 }; 1230 module_platform_driver(amd_sdw_driver); 1231 1232 MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 1233 MODULE_DESCRIPTION("AMD SoundWire driver"); 1234 MODULE_LICENSE("Dual BSD/GPL"); 1235 MODULE_ALIAS("platform:" DRV_NAME); 1236