1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * SoundWire AMD Manager driver 4 * 5 * Copyright 2023-24 Advanced Micro Devices, Inc. 6 */ 7 8 #include <linux/completion.h> 9 #include <linux/cleanup.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/jiffies.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/soundwire/sdw.h> 17 #include <linux/soundwire/sdw_registers.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/wait.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include "bus.h" 23 #include "amd_init.h" 24 #include "amd_manager.h" 25 26 #define DRV_NAME "amd_sdw_manager" 27 28 #define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus) 29 30 static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager) 31 { 32 u32 val; 33 int ret; 34 35 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 36 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 37 AMD_SDW_TIMEOUT); 38 if (ret) 39 return ret; 40 41 /* SoundWire manager bus reset */ 42 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 43 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, 44 (val & AMD_SDW_BUS_RESET_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT); 45 if (ret) 46 return ret; 47 48 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 49 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val, 50 ACP_DELAY_US, AMD_SDW_TIMEOUT); 51 if (ret) { 52 dev_err(amd_manager->dev, "Failed to reset SoundWire manager instance%d\n", 53 amd_manager->instance); 54 return ret; 55 } 56 57 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 58 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 59 AMD_SDW_TIMEOUT); 60 } 61 62 static int amd_enable_sdw_manager(struct amd_sdw_manager *amd_manager) 63 { 64 u32 val; 65 66 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 67 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 68 AMD_SDW_TIMEOUT); 69 } 70 71 static int amd_disable_sdw_manager(struct amd_sdw_manager *amd_manager) 72 { 73 u32 val; 74 75 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 76 /* 77 * After invoking manager disable sequence, check whether 78 * manager has executed clock stop sequence. In this case, 79 * manager should ignore checking enable status register. 80 */ 81 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 82 if (val) 83 return 0; 84 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 85 AMD_SDW_TIMEOUT); 86 } 87 88 static void amd_enable_sdw_interrupts(struct amd_sdw_manager *amd_manager) 89 { 90 u32 val; 91 92 mutex_lock(amd_manager->acp_sdw_lock); 93 val = sdw_manager_reg_mask_array[amd_manager->instance]; 94 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), val, val); 95 mutex_unlock(amd_manager->acp_sdw_lock); 96 97 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio + 98 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 99 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio + 100 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 101 writel(AMD_SDW_IRQ_ERROR_MASK, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK); 102 } 103 104 static void amd_disable_sdw_interrupts(struct amd_sdw_manager *amd_manager) 105 { 106 u32 irq_mask; 107 108 mutex_lock(amd_manager->acp_sdw_lock); 109 irq_mask = sdw_manager_reg_mask_array[amd_manager->instance]; 110 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), 111 irq_mask, 0); 112 mutex_unlock(amd_manager->acp_sdw_lock); 113 114 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 115 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 116 writel(0x00, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK); 117 } 118 119 static int amd_deinit_sdw_manager(struct amd_sdw_manager *amd_manager) 120 { 121 amd_disable_sdw_interrupts(amd_manager); 122 return amd_disable_sdw_manager(amd_manager); 123 } 124 125 static void amd_sdw_set_frameshape(struct amd_sdw_manager *amd_manager) 126 { 127 u32 frame_size; 128 129 frame_size = (amd_manager->rows_index << 3) | amd_manager->cols_index; 130 writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE); 131 } 132 133 static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable) 134 { 135 u32 wake_ctrl; 136 137 wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 138 if (enable) 139 wake_ctrl |= AMD_SDW_WAKE_INTR_MASK; 140 else 141 wake_ctrl &= ~AMD_SDW_WAKE_INTR_MASK; 142 143 writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 144 } 145 146 static int amd_sdw_set_device_state(struct amd_sdw_manager *amd_manager, u32 target_device_state) 147 { 148 u32 sdw_dev_state; 149 150 sdw_dev_state = readl(amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE); 151 switch (amd_manager->instance) { 152 case ACP_SDW0: 153 u32p_replace_bits(&sdw_dev_state, target_device_state, 154 AMD_SDW0_DEVICE_STATE_MASK); 155 break; 156 case ACP_SDW1: 157 u32p_replace_bits(&sdw_dev_state, target_device_state, 158 AMD_SDW1_DEVICE_STATE_MASK); 159 break; 160 default: 161 return -EINVAL; 162 } 163 writel(sdw_dev_state, amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE); 164 sdw_dev_state = readl(amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE); 165 dev_dbg(amd_manager->dev, "AMD_SDW_DEVICE_STATE:0x%x\n", sdw_dev_state); 166 return 0; 167 } 168 169 static int amd_sdw_host_wake_enable(struct amd_sdw_manager *amd_manager, bool enable) 170 { 171 u32 intr_cntl1; 172 u32 sdw_host_wake_irq_mask; 173 174 if (!amd_manager->wake_en_mask) 175 return 0; 176 177 switch (amd_manager->instance) { 178 case ACP_SDW0: 179 sdw_host_wake_irq_mask = AMD_SDW0_HOST_WAKE_INTR_MASK; 180 break; 181 case ACP_SDW1: 182 sdw_host_wake_irq_mask = AMD_SDW1_HOST_WAKE_INTR_MASK; 183 break; 184 default: 185 return -EINVAL; 186 } 187 188 intr_cntl1 = readl(amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(ACP_SDW1)); 189 if (enable) 190 intr_cntl1 |= sdw_host_wake_irq_mask; 191 else 192 intr_cntl1 &= ~sdw_host_wake_irq_mask; 193 writel(intr_cntl1, amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(ACP_SDW1)); 194 return 0; 195 } 196 197 static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg, 198 int cmd_offset) 199 { 200 u32 upper_data; 201 u32 lower_data = 0; 202 u16 addr; 203 u8 upper_addr, lower_addr; 204 u8 data = 0; 205 206 addr = msg->addr + cmd_offset; 207 upper_addr = (addr & 0xFF00) >> 8; 208 lower_addr = addr & 0xFF; 209 210 if (msg->flags == SDW_MSG_FLAG_WRITE) 211 data = msg->buf[cmd_offset]; 212 213 upper_data = FIELD_PREP(AMD_SDW_MCP_CMD_DEV_ADDR, msg->dev_num); 214 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_COMMAND, msg->flags + 2); 215 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_HIGH, upper_addr); 216 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_LOW, lower_addr); 217 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_DATA, data); 218 219 *upper_word = upper_data; 220 *lower_word = lower_data; 221 } 222 223 static u64 amd_sdw_send_cmd_get_resp(struct amd_sdw_manager *amd_manager, u32 lower_data, 224 u32 upper_data) 225 { 226 u64 resp; 227 u32 lower_resp, upper_resp; 228 u32 sts; 229 int ret; 230 231 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 232 !(sts & AMD_SDW_IMM_CMD_BUSY), ACP_DELAY_US, AMD_SDW_TIMEOUT); 233 if (ret) { 234 dev_err(amd_manager->dev, "SDW%x previous cmd status clear failed\n", 235 amd_manager->instance); 236 return ret; 237 } 238 239 if (sts & AMD_SDW_IMM_RES_VALID) { 240 dev_err(amd_manager->dev, "SDW%x manager is in bad state\n", amd_manager->instance); 241 writel(0x00, amd_manager->mmio + ACP_SW_IMM_CMD_STS); 242 } 243 writel(upper_data, amd_manager->mmio + ACP_SW_IMM_CMD_UPPER_WORD); 244 writel(lower_data, amd_manager->mmio + ACP_SW_IMM_CMD_LOWER_QWORD); 245 246 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 247 (sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT); 248 if (ret) { 249 dev_err(amd_manager->dev, "SDW%x cmd response timeout occurred\n", 250 amd_manager->instance); 251 return ret; 252 } 253 upper_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_UPPER_WORD); 254 lower_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_LOWER_QWORD); 255 256 writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS); 257 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 258 !(sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT); 259 if (ret) { 260 dev_err(amd_manager->dev, "SDW%x cmd status retry failed\n", 261 amd_manager->instance); 262 return ret; 263 } 264 resp = upper_resp; 265 resp = (resp << 32) | lower_resp; 266 return resp; 267 } 268 269 static enum sdw_command_response 270 amd_program_scp_addr(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg) 271 { 272 struct sdw_msg scp_msg = {0}; 273 u64 response_buf[2] = {0}; 274 u32 upper_data = 0, lower_data = 0; 275 int index; 276 277 scp_msg.dev_num = msg->dev_num; 278 scp_msg.addr = SDW_SCP_ADDRPAGE1; 279 scp_msg.buf = &msg->addr_page1; 280 scp_msg.flags = SDW_MSG_FLAG_WRITE; 281 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0); 282 response_buf[0] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 283 scp_msg.addr = SDW_SCP_ADDRPAGE2; 284 scp_msg.buf = &msg->addr_page2; 285 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0); 286 response_buf[1] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 287 288 for (index = 0; index < 2; index++) { 289 if (response_buf[index] == -ETIMEDOUT) { 290 dev_err_ratelimited(amd_manager->dev, 291 "SCP_addrpage command timeout for Slave %d\n", 292 msg->dev_num); 293 return SDW_CMD_TIMEOUT; 294 } else if (!(response_buf[index] & AMD_SDW_MCP_RESP_ACK)) { 295 if (response_buf[index] & AMD_SDW_MCP_RESP_NACK) { 296 dev_err_ratelimited(amd_manager->dev, 297 "SCP_addrpage NACKed for Slave %d\n", 298 msg->dev_num); 299 return SDW_CMD_FAIL; 300 } 301 dev_dbg_ratelimited(amd_manager->dev, "SCP_addrpage ignored for Slave %d\n", 302 msg->dev_num); 303 return SDW_CMD_IGNORED; 304 } 305 } 306 return SDW_CMD_OK; 307 } 308 309 static int amd_prep_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg) 310 { 311 int ret; 312 313 if (msg->page) { 314 ret = amd_program_scp_addr(amd_manager, msg); 315 if (ret) { 316 msg->len = 0; 317 return ret; 318 } 319 } 320 switch (msg->flags) { 321 case SDW_MSG_FLAG_READ: 322 case SDW_MSG_FLAG_WRITE: 323 break; 324 default: 325 dev_err(amd_manager->dev, "Invalid msg cmd: %d\n", msg->flags); 326 return -EINVAL; 327 } 328 return 0; 329 } 330 331 static enum sdw_command_response amd_sdw_fill_msg_resp(struct amd_sdw_manager *amd_manager, 332 struct sdw_msg *msg, u64 response, 333 int offset) 334 { 335 if (response & AMD_SDW_MCP_RESP_ACK) { 336 if (msg->flags == SDW_MSG_FLAG_READ) 337 msg->buf[offset] = FIELD_GET(AMD_SDW_MCP_RESP_RDATA, response); 338 } else { 339 if (response == -ETIMEDOUT) { 340 dev_err_ratelimited(amd_manager->dev, "command timeout for Slave %d\n", 341 msg->dev_num); 342 return SDW_CMD_TIMEOUT; 343 } else if (response & AMD_SDW_MCP_RESP_NACK) { 344 dev_err_ratelimited(amd_manager->dev, 345 "command response NACK received for Slave %d\n", 346 msg->dev_num); 347 return SDW_CMD_FAIL; 348 } 349 dev_dbg_ratelimited(amd_manager->dev, "command is ignored for Slave %d\n", 350 msg->dev_num); 351 return SDW_CMD_IGNORED; 352 } 353 return SDW_CMD_OK; 354 } 355 356 static unsigned int _amd_sdw_xfer_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg, 357 int cmd_offset) 358 { 359 u64 response; 360 u32 upper_data = 0, lower_data = 0; 361 362 amd_sdw_ctl_word_prep(&lower_data, &upper_data, msg, cmd_offset); 363 response = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 364 return amd_sdw_fill_msg_resp(amd_manager, msg, response, cmd_offset); 365 } 366 367 static enum sdw_command_response amd_sdw_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg) 368 { 369 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 370 int ret, i; 371 372 ret = amd_prep_msg(amd_manager, msg); 373 if (ret) 374 return SDW_CMD_FAIL_OTHER; 375 for (i = 0; i < msg->len; i++) { 376 ret = _amd_sdw_xfer_msg(amd_manager, msg, i); 377 if (ret) 378 return ret; 379 } 380 return SDW_CMD_OK; 381 } 382 383 static void amd_sdw_fill_slave_status(struct amd_sdw_manager *amd_manager, u16 index, u32 status) 384 { 385 switch (status) { 386 case SDW_SLAVE_ATTACHED: 387 case SDW_SLAVE_UNATTACHED: 388 case SDW_SLAVE_ALERT: 389 amd_manager->status[index] = status; 390 break; 391 default: 392 amd_manager->status[index] = SDW_SLAVE_RESERVED; 393 break; 394 } 395 } 396 397 static void amd_sdw_process_ping_status(u64 response, struct amd_sdw_manager *amd_manager) 398 { 399 u64 slave_stat; 400 u32 val; 401 u16 dev_index; 402 403 /* slave status response */ 404 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response); 405 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8; 406 dev_dbg(amd_manager->dev, "slave_stat:0x%llx\n", slave_stat); 407 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) { 408 val = (slave_stat >> (dev_index * 2)) & AMD_SDW_MCP_SLAVE_STATUS_MASK; 409 dev_dbg(amd_manager->dev, "val:0x%x\n", val); 410 amd_sdw_fill_slave_status(amd_manager, dev_index, val); 411 } 412 } 413 414 static void amd_sdw_read_and_process_ping_status(struct amd_sdw_manager *amd_manager) 415 { 416 u64 response; 417 418 mutex_lock(&amd_manager->bus.msg_lock); 419 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0); 420 mutex_unlock(&amd_manager->bus.msg_lock); 421 amd_sdw_process_ping_status(response, amd_manager); 422 } 423 424 static u32 amd_sdw_read_ping_status(struct sdw_bus *bus) 425 { 426 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 427 u64 response; 428 u32 slave_stat; 429 430 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0); 431 /* slave status from ping response */ 432 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response); 433 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8; 434 dev_dbg(amd_manager->dev, "slave_stat:0x%x\n", slave_stat); 435 return slave_stat; 436 } 437 438 static int amd_sdw_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream) 439 { 440 struct sdw_transport_data t_data = {0}; 441 struct sdw_master_runtime *m_rt; 442 struct sdw_port_runtime *p_rt; 443 struct sdw_bus_params *b_params = &bus->params; 444 int port_bo, hstart, hstop, sample_int; 445 unsigned int rate, bps; 446 447 port_bo = 0; 448 hstart = 1; 449 hstop = bus->params.col - 1; 450 t_data.hstop = hstop; 451 t_data.hstart = hstart; 452 453 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 454 rate = m_rt->stream->params.rate; 455 bps = m_rt->stream->params.bps; 456 sample_int = (bus->params.curr_dr_freq / rate); 457 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 458 port_bo = (p_rt->num * 64) + 1; 459 dev_dbg(bus->dev, "p_rt->num=%d hstart=%d hstop=%d port_bo=%d\n", 460 p_rt->num, hstart, hstop, port_bo); 461 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, 462 false, SDW_BLK_GRP_CNT_1, sample_int, 463 port_bo, port_bo >> 8, hstart, hstop, 464 SDW_BLK_PKG_PER_PORT, p_rt->lane); 465 466 sdw_fill_port_params(&p_rt->port_params, 467 p_rt->num, bps, 468 SDW_PORT_FLOW_MODE_ISOCH, 469 b_params->m_data_mode); 470 t_data.hstart = hstart; 471 t_data.hstop = hstop; 472 t_data.block_offset = port_bo; 473 t_data.sub_block_offset = 0; 474 } 475 sdw_compute_slave_ports(m_rt, &t_data); 476 } 477 return 0; 478 } 479 480 static int amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_params, 481 unsigned int bank) 482 { 483 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 484 u32 frame_fmt_reg, dpn_frame_fmt; 485 486 dev_dbg(amd_manager->dev, "p_params->num:0x%x\n", p_params->num); 487 switch (amd_manager->acp_rev) { 488 case ACP63_PCI_REV_ID: 489 switch (amd_manager->instance) { 490 case ACP_SDW0: 491 frame_fmt_reg = acp63_sdw0_dp_reg[p_params->num].frame_fmt_reg; 492 break; 493 case ACP_SDW1: 494 frame_fmt_reg = acp63_sdw1_dp_reg[p_params->num].frame_fmt_reg; 495 break; 496 default: 497 return -EINVAL; 498 } 499 break; 500 case ACP70_PCI_REV_ID: 501 case ACP71_PCI_REV_ID: 502 frame_fmt_reg = acp70_sdw_dp_reg[p_params->num].frame_fmt_reg; 503 break; 504 default: 505 return -EINVAL; 506 } 507 508 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg); 509 u32p_replace_bits(&dpn_frame_fmt, p_params->flow_mode, AMD_DPN_FRAME_FMT_PFM); 510 u32p_replace_bits(&dpn_frame_fmt, p_params->data_mode, AMD_DPN_FRAME_FMT_PDM); 511 u32p_replace_bits(&dpn_frame_fmt, p_params->bps - 1, AMD_DPN_FRAME_FMT_WORD_LEN); 512 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg); 513 return 0; 514 } 515 516 static int amd_sdw_transport_params(struct sdw_bus *bus, 517 struct sdw_transport_params *params, 518 enum sdw_reg_bank bank) 519 { 520 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 521 u32 dpn_frame_fmt; 522 u32 dpn_sampleinterval; 523 u32 dpn_hctrl; 524 u32 dpn_offsetctrl; 525 u32 dpn_lanectrl; 526 u32 frame_fmt_reg, sample_int_reg, hctrl_dp0_reg; 527 u32 offset_reg, lane_ctrl_ch_en_reg; 528 529 switch (amd_manager->acp_rev) { 530 case ACP63_PCI_REV_ID: 531 switch (amd_manager->instance) { 532 case ACP_SDW0: 533 frame_fmt_reg = acp63_sdw0_dp_reg[params->port_num].frame_fmt_reg; 534 sample_int_reg = acp63_sdw0_dp_reg[params->port_num].sample_int_reg; 535 hctrl_dp0_reg = acp63_sdw0_dp_reg[params->port_num].hctrl_dp0_reg; 536 offset_reg = acp63_sdw0_dp_reg[params->port_num].offset_reg; 537 lane_ctrl_ch_en_reg = 538 acp63_sdw0_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 539 break; 540 case ACP_SDW1: 541 frame_fmt_reg = acp63_sdw1_dp_reg[params->port_num].frame_fmt_reg; 542 sample_int_reg = acp63_sdw1_dp_reg[params->port_num].sample_int_reg; 543 hctrl_dp0_reg = acp63_sdw1_dp_reg[params->port_num].hctrl_dp0_reg; 544 offset_reg = acp63_sdw1_dp_reg[params->port_num].offset_reg; 545 lane_ctrl_ch_en_reg = 546 acp63_sdw1_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 547 break; 548 default: 549 return -EINVAL; 550 } 551 break; 552 case ACP70_PCI_REV_ID: 553 case ACP71_PCI_REV_ID: 554 frame_fmt_reg = acp70_sdw_dp_reg[params->port_num].frame_fmt_reg; 555 sample_int_reg = acp70_sdw_dp_reg[params->port_num].sample_int_reg; 556 hctrl_dp0_reg = acp70_sdw_dp_reg[params->port_num].hctrl_dp0_reg; 557 offset_reg = acp70_sdw_dp_reg[params->port_num].offset_reg; 558 lane_ctrl_ch_en_reg = acp70_sdw_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 559 break; 560 default: 561 return -EINVAL; 562 } 563 writel(AMD_SDW_SSP_COUNTER_VAL, amd_manager->mmio + ACP_SW_SSP_COUNTER); 564 565 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg); 566 u32p_replace_bits(&dpn_frame_fmt, params->blk_pkg_mode, AMD_DPN_FRAME_FMT_BLK_PKG_MODE); 567 u32p_replace_bits(&dpn_frame_fmt, params->blk_grp_ctrl, AMD_DPN_FRAME_FMT_BLK_GRP_CTRL); 568 u32p_replace_bits(&dpn_frame_fmt, SDW_STREAM_PCM, AMD_DPN_FRAME_FMT_PCM_OR_PDM); 569 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg); 570 571 dpn_sampleinterval = params->sample_interval - 1; 572 writel(dpn_sampleinterval, amd_manager->mmio + sample_int_reg); 573 574 dpn_hctrl = FIELD_PREP(AMD_DPN_HCTRL_HSTOP, params->hstop); 575 dpn_hctrl |= FIELD_PREP(AMD_DPN_HCTRL_HSTART, params->hstart); 576 writel(dpn_hctrl, amd_manager->mmio + hctrl_dp0_reg); 577 578 dpn_offsetctrl = FIELD_PREP(AMD_DPN_OFFSET_CTRL_1, params->offset1); 579 dpn_offsetctrl |= FIELD_PREP(AMD_DPN_OFFSET_CTRL_2, params->offset2); 580 writel(dpn_offsetctrl, amd_manager->mmio + offset_reg); 581 582 /* 583 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask 584 * parameters. 585 */ 586 dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); 587 u32p_replace_bits(&dpn_lanectrl, params->lane_ctrl, AMD_DPN_CH_EN_LCTRL); 588 writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg); 589 return 0; 590 } 591 592 static int amd_sdw_port_enable(struct sdw_bus *bus, 593 struct sdw_enable_ch *enable_ch, 594 unsigned int bank) 595 { 596 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 597 u32 dpn_ch_enable; 598 u32 lane_ctrl_ch_en_reg; 599 600 switch (amd_manager->acp_rev) { 601 case ACP63_PCI_REV_ID: 602 switch (amd_manager->instance) { 603 case ACP_SDW0: 604 lane_ctrl_ch_en_reg = 605 acp63_sdw0_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 606 break; 607 case ACP_SDW1: 608 lane_ctrl_ch_en_reg = 609 acp63_sdw1_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 610 break; 611 default: 612 return -EINVAL; 613 } 614 break; 615 case ACP70_PCI_REV_ID: 616 case ACP71_PCI_REV_ID: 617 lane_ctrl_ch_en_reg = acp70_sdw_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 618 break; 619 default: 620 return -EINVAL; 621 } 622 623 /* 624 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask 625 * parameters. 626 */ 627 dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); 628 u32p_replace_bits(&dpn_ch_enable, enable_ch->ch_mask, AMD_DPN_CH_EN_CHMASK); 629 if (enable_ch->enable) 630 writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg); 631 else 632 writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg); 633 return 0; 634 } 635 636 static int sdw_master_read_amd_prop(struct sdw_bus *bus) 637 { 638 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 639 struct fwnode_handle *link; 640 struct sdw_master_prop *prop; 641 u32 quirk_mask = 0; 642 u32 wake_en_mask = 0; 643 u32 power_mode_mask = 0; 644 char name[32]; 645 646 prop = &bus->prop; 647 /* Find manager handle */ 648 snprintf(name, sizeof(name), "mipi-sdw-link-%d-subproperties", bus->link_id); 649 link = device_get_named_child_node(bus->dev, name); 650 if (!link) { 651 dev_err(bus->dev, "Manager node %s not found\n", name); 652 return -EIO; 653 } 654 fwnode_property_read_u32(link, "amd-sdw-enable", &quirk_mask); 655 if (!(quirk_mask & AMD_SDW_QUIRK_MASK_BUS_ENABLE)) 656 prop->hw_disabled = true; 657 prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH | 658 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY; 659 660 fwnode_property_read_u32(link, "amd-sdw-wakeup-enable", &wake_en_mask); 661 amd_manager->wake_en_mask = wake_en_mask; 662 fwnode_property_read_u32(link, "amd-sdw-power-mode", &power_mode_mask); 663 amd_manager->power_mode_mask = power_mode_mask; 664 665 fwnode_handle_put(link); 666 667 return 0; 668 } 669 670 static int amd_prop_read(struct sdw_bus *bus) 671 { 672 sdw_master_read_prop(bus); 673 sdw_master_read_amd_prop(bus); 674 return 0; 675 } 676 677 static const struct sdw_master_port_ops amd_sdw_port_ops = { 678 .dpn_set_port_params = amd_sdw_port_params, 679 .dpn_set_port_transport_params = amd_sdw_transport_params, 680 .dpn_port_enable_ch = amd_sdw_port_enable, 681 }; 682 683 static const struct sdw_master_ops amd_sdw_ops = { 684 .read_prop = amd_prop_read, 685 .xfer_msg = amd_sdw_xfer_msg, 686 .read_ping_status = amd_sdw_read_ping_status, 687 }; 688 689 static int amd_sdw_hw_params(struct snd_pcm_substream *substream, 690 struct snd_pcm_hw_params *params, 691 struct snd_soc_dai *dai) 692 { 693 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 694 struct sdw_amd_dai_runtime *dai_runtime; 695 struct sdw_stream_config sconfig; 696 int ch, dir; 697 int ret; 698 699 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 700 if (!dai_runtime) 701 return -EIO; 702 703 ch = params_channels(params); 704 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 705 dir = SDW_DATA_DIR_RX; 706 else 707 dir = SDW_DATA_DIR_TX; 708 dev_dbg(amd_manager->dev, "dir:%d dai->id:0x%x\n", dir, dai->id); 709 710 sconfig.direction = dir; 711 sconfig.ch_count = ch; 712 sconfig.frame_rate = params_rate(params); 713 sconfig.type = dai_runtime->stream_type; 714 715 sconfig.bps = snd_pcm_format_width(params_format(params)); 716 717 /* Port configuration */ 718 struct sdw_port_config *pconfig __free(kfree) = kzalloc(sizeof(*pconfig), 719 GFP_KERNEL); 720 if (!pconfig) 721 return -ENOMEM; 722 723 pconfig->num = dai->id; 724 pconfig->ch_mask = (1 << ch) - 1; 725 ret = sdw_stream_add_master(&amd_manager->bus, &sconfig, 726 pconfig, 1, dai_runtime->stream); 727 if (ret) 728 dev_err(amd_manager->dev, "add manager to stream failed:%d\n", ret); 729 730 return ret; 731 } 732 733 static int amd_sdw_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 734 { 735 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 736 struct sdw_amd_dai_runtime *dai_runtime; 737 int ret; 738 739 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 740 if (!dai_runtime) 741 return -EIO; 742 743 ret = sdw_stream_remove_master(&amd_manager->bus, dai_runtime->stream); 744 if (ret < 0) 745 dev_err(dai->dev, "remove manager from stream %s failed: %d\n", 746 dai_runtime->stream->name, ret); 747 return ret; 748 } 749 750 static int amd_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) 751 { 752 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 753 struct sdw_amd_dai_runtime *dai_runtime; 754 755 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 756 if (stream) { 757 /* first paranoia check */ 758 if (dai_runtime) { 759 dev_err(dai->dev, "dai_runtime already allocated for dai %s\n", dai->name); 760 return -EINVAL; 761 } 762 763 /* allocate and set dai_runtime info */ 764 dai_runtime = kzalloc(sizeof(*dai_runtime), GFP_KERNEL); 765 if (!dai_runtime) 766 return -ENOMEM; 767 768 dai_runtime->stream_type = SDW_STREAM_PCM; 769 dai_runtime->bus = &amd_manager->bus; 770 dai_runtime->stream = stream; 771 amd_manager->dai_runtime_array[dai->id] = dai_runtime; 772 } else { 773 /* second paranoia check */ 774 if (!dai_runtime) { 775 dev_err(dai->dev, "dai_runtime not allocated for dai %s\n", dai->name); 776 return -EINVAL; 777 } 778 779 /* for NULL stream we release allocated dai_runtime */ 780 kfree(dai_runtime); 781 amd_manager->dai_runtime_array[dai->id] = NULL; 782 } 783 return 0; 784 } 785 786 static int amd_pcm_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) 787 { 788 return amd_set_sdw_stream(dai, stream, direction); 789 } 790 791 static void *amd_get_sdw_stream(struct snd_soc_dai *dai, int direction) 792 { 793 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 794 struct sdw_amd_dai_runtime *dai_runtime; 795 796 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 797 if (!dai_runtime) 798 return ERR_PTR(-EINVAL); 799 800 return dai_runtime->stream; 801 } 802 803 static const struct snd_soc_dai_ops amd_sdw_dai_ops = { 804 .hw_params = amd_sdw_hw_params, 805 .hw_free = amd_sdw_hw_free, 806 .set_stream = amd_pcm_set_sdw_stream, 807 .get_stream = amd_get_sdw_stream, 808 }; 809 810 static const struct snd_soc_component_driver amd_sdw_dai_component = { 811 .name = "soundwire", 812 }; 813 814 static int amd_sdw_register_dais(struct amd_sdw_manager *amd_manager) 815 { 816 struct sdw_amd_dai_runtime **dai_runtime_array; 817 struct snd_soc_dai_driver *dais; 818 struct snd_soc_pcm_stream *stream; 819 struct device *dev; 820 int i, num_dais; 821 822 dev = amd_manager->dev; 823 num_dais = amd_manager->num_dout_ports + amd_manager->num_din_ports; 824 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); 825 if (!dais) 826 return -ENOMEM; 827 828 dai_runtime_array = devm_kcalloc(dev, num_dais, 829 sizeof(struct sdw_amd_dai_runtime *), 830 GFP_KERNEL); 831 if (!dai_runtime_array) 832 return -ENOMEM; 833 amd_manager->dai_runtime_array = dai_runtime_array; 834 for (i = 0; i < num_dais; i++) { 835 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW%d Pin%d", amd_manager->instance, 836 i); 837 if (!dais[i].name) 838 return -ENOMEM; 839 if (i < amd_manager->num_dout_ports) 840 stream = &dais[i].playback; 841 else 842 stream = &dais[i].capture; 843 844 stream->channels_min = 2; 845 stream->channels_max = 2; 846 stream->rates = SNDRV_PCM_RATE_48000; 847 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; 848 849 dais[i].ops = &amd_sdw_dai_ops; 850 dais[i].id = i; 851 } 852 853 return devm_snd_soc_register_component(dev, &amd_sdw_dai_component, 854 dais, num_dais); 855 } 856 857 static void amd_sdw_update_slave_status_work(struct work_struct *work) 858 { 859 struct amd_sdw_manager *amd_manager = 860 container_of(work, struct amd_sdw_manager, amd_sdw_work); 861 int retry_count = 0; 862 863 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) { 864 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 865 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 866 } 867 868 update_status: 869 sdw_handle_slave_status(&amd_manager->bus, amd_manager->status); 870 /* 871 * During the peripheral enumeration sequence, the SoundWire manager interrupts 872 * are masked. Once the device number programming is done for all peripherals, 873 * interrupts will be unmasked. Read the peripheral device status from ping command 874 * and process the response. This sequence will ensure all peripheral devices enumerated 875 * and initialized properly. 876 */ 877 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) { 878 if (retry_count++ < SDW_MAX_DEVICES) { 879 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio + 880 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 881 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio + 882 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 883 amd_sdw_read_and_process_ping_status(amd_manager); 884 goto update_status; 885 } else { 886 dev_err_ratelimited(amd_manager->dev, 887 "Device0 detected after %d iterations\n", 888 retry_count); 889 } 890 } 891 } 892 893 static void amd_sdw_update_slave_status(u32 status_change_0to7, u32 status_change_8to11, 894 struct amd_sdw_manager *amd_manager) 895 { 896 u64 slave_stat; 897 u32 val; 898 int dev_index; 899 900 if (status_change_0to7 == AMD_SDW_SLAVE_0_ATTACHED) 901 memset(amd_manager->status, 0, sizeof(amd_manager->status)); 902 slave_stat = status_change_0to7; 903 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STATUS_8TO_11, status_change_8to11) << 32; 904 dev_dbg(amd_manager->dev, "status_change_0to7:0x%x status_change_8to11:0x%x\n", 905 status_change_0to7, status_change_8to11); 906 if (slave_stat) { 907 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) { 908 if (slave_stat & AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(dev_index)) { 909 val = (slave_stat >> AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(dev_index)) & 910 AMD_SDW_MCP_SLAVE_STATUS_MASK; 911 amd_sdw_fill_slave_status(amd_manager, dev_index, val); 912 } 913 } 914 } 915 } 916 917 static void amd_sdw_process_wake_event(struct amd_sdw_manager *amd_manager) 918 { 919 dev_dbg(amd_manager->dev, "SoundWire Wake event reported\n"); 920 pm_request_resume(amd_manager->dev); 921 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 922 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 923 } 924 925 static void amd_sdw_irq_thread(struct work_struct *work) 926 { 927 struct amd_sdw_manager *amd_manager = 928 container_of(work, struct amd_sdw_manager, amd_sdw_irq_thread); 929 u32 status_change_8to11; 930 u32 status_change_0to7; 931 932 status_change_8to11 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 933 status_change_0to7 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); 934 dev_dbg(amd_manager->dev, "[SDW%d] SDW INT: 0to7=0x%x, 8to11=0x%x\n", 935 amd_manager->instance, status_change_0to7, status_change_8to11); 936 if (status_change_8to11 & AMD_SDW_WAKE_STAT_MASK) 937 return amd_sdw_process_wake_event(amd_manager); 938 939 if (status_change_8to11 & AMD_SDW_PREQ_INTR_STAT) { 940 amd_sdw_read_and_process_ping_status(amd_manager); 941 } else { 942 /* Check for the updated status on peripheral device */ 943 amd_sdw_update_slave_status(status_change_0to7, status_change_8to11, amd_manager); 944 } 945 if (status_change_8to11 || status_change_0to7) 946 schedule_work(&amd_manager->amd_sdw_work); 947 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 948 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); 949 } 950 951 int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager) 952 { 953 struct sdw_master_prop *prop; 954 int ret; 955 956 prop = &amd_manager->bus.prop; 957 if (!prop->hw_disabled) { 958 ret = amd_init_sdw_manager(amd_manager); 959 if (ret) 960 return ret; 961 amd_enable_sdw_interrupts(amd_manager); 962 ret = amd_enable_sdw_manager(amd_manager); 963 if (ret) 964 return ret; 965 amd_sdw_set_frameshape(amd_manager); 966 } 967 /* Enable runtime PM */ 968 pm_runtime_set_autosuspend_delay(amd_manager->dev, AMD_SDW_MASTER_SUSPEND_DELAY_MS); 969 pm_runtime_use_autosuspend(amd_manager->dev); 970 pm_runtime_mark_last_busy(amd_manager->dev); 971 pm_runtime_set_active(amd_manager->dev); 972 pm_runtime_enable(amd_manager->dev); 973 return 0; 974 } 975 976 static int amd_sdw_manager_probe(struct platform_device *pdev) 977 { 978 const struct acp_sdw_pdata *pdata = pdev->dev.platform_data; 979 struct resource *res; 980 struct device *dev = &pdev->dev; 981 struct sdw_master_prop *prop; 982 struct sdw_bus_params *params; 983 struct amd_sdw_manager *amd_manager; 984 int ret; 985 986 amd_manager = devm_kzalloc(dev, sizeof(struct amd_sdw_manager), GFP_KERNEL); 987 if (!amd_manager) 988 return -ENOMEM; 989 990 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 991 if (!res) 992 return -ENOMEM; 993 994 amd_manager->acp_mmio = devm_ioremap(dev, res->start, resource_size(res)); 995 if (!amd_manager->acp_mmio) { 996 dev_err(dev, "mmio not found\n"); 997 return -ENOMEM; 998 } 999 amd_manager->instance = pdata->instance; 1000 amd_manager->mmio = amd_manager->acp_mmio + 1001 (amd_manager->instance * SDW_MANAGER_REG_OFFSET); 1002 amd_manager->acp_sdw_lock = pdata->acp_sdw_lock; 1003 amd_manager->acp_rev = pdata->acp_rev; 1004 amd_manager->cols_index = sdw_find_col_index(AMD_SDW_DEFAULT_COLUMNS); 1005 amd_manager->rows_index = sdw_find_row_index(AMD_SDW_DEFAULT_ROWS); 1006 amd_manager->dev = dev; 1007 amd_manager->bus.ops = &amd_sdw_ops; 1008 amd_manager->bus.port_ops = &amd_sdw_port_ops; 1009 amd_manager->bus.compute_params = &amd_sdw_compute_params; 1010 amd_manager->bus.clk_stop_timeout = 200; 1011 amd_manager->bus.link_id = amd_manager->instance; 1012 1013 /* 1014 * Due to BIOS compatibility, the two links are exposed within 1015 * the scope of a single controller. If this changes, the 1016 * controller_id will have to be updated with drv_data 1017 * information. 1018 */ 1019 amd_manager->bus.controller_id = 0; 1020 dev_dbg(dev, "acp_rev:0x%x\n", amd_manager->acp_rev); 1021 switch (amd_manager->acp_rev) { 1022 case ACP63_PCI_REV_ID: 1023 switch (amd_manager->instance) { 1024 case ACP_SDW0: 1025 amd_manager->num_dout_ports = AMD_ACP63_SDW0_MAX_TX_PORTS; 1026 amd_manager->num_din_ports = AMD_ACP63_SDW0_MAX_RX_PORTS; 1027 break; 1028 case ACP_SDW1: 1029 amd_manager->num_dout_ports = AMD_ACP63_SDW1_MAX_TX_PORTS; 1030 amd_manager->num_din_ports = AMD_ACP63_SDW1_MAX_RX_PORTS; 1031 break; 1032 default: 1033 return -EINVAL; 1034 } 1035 break; 1036 case ACP70_PCI_REV_ID: 1037 case ACP71_PCI_REV_ID: 1038 amd_manager->num_dout_ports = AMD_ACP70_SDW_MAX_TX_PORTS; 1039 amd_manager->num_din_ports = AMD_ACP70_SDW_MAX_RX_PORTS; 1040 break; 1041 default: 1042 return -EINVAL; 1043 } 1044 1045 params = &amd_manager->bus.params; 1046 1047 params->col = AMD_SDW_DEFAULT_COLUMNS; 1048 params->row = AMD_SDW_DEFAULT_ROWS; 1049 prop = &amd_manager->bus.prop; 1050 prop->clk_freq = &amd_sdw_freq_tbl[0]; 1051 prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ; 1052 prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ; 1053 1054 ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode); 1055 if (ret) { 1056 dev_err(dev, "Failed to register SoundWire manager(%d)\n", ret); 1057 return ret; 1058 } 1059 ret = amd_sdw_register_dais(amd_manager); 1060 if (ret) { 1061 dev_err(dev, "CPU DAI registration failed\n"); 1062 sdw_bus_master_delete(&amd_manager->bus); 1063 return ret; 1064 } 1065 dev_set_drvdata(dev, amd_manager); 1066 INIT_WORK(&amd_manager->amd_sdw_irq_thread, amd_sdw_irq_thread); 1067 INIT_WORK(&amd_manager->amd_sdw_work, amd_sdw_update_slave_status_work); 1068 return 0; 1069 } 1070 1071 static void amd_sdw_manager_remove(struct platform_device *pdev) 1072 { 1073 struct amd_sdw_manager *amd_manager = dev_get_drvdata(&pdev->dev); 1074 int ret; 1075 1076 pm_runtime_disable(&pdev->dev); 1077 amd_disable_sdw_interrupts(amd_manager); 1078 sdw_bus_master_delete(&amd_manager->bus); 1079 ret = amd_disable_sdw_manager(amd_manager); 1080 if (ret) 1081 dev_err(&pdev->dev, "Failed to disable device (%pe)\n", ERR_PTR(ret)); 1082 } 1083 1084 static int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager) 1085 { 1086 u32 val; 1087 int ret; 1088 1089 ret = sdw_bus_prep_clk_stop(&amd_manager->bus); 1090 if (ret < 0 && ret != -ENODATA) { 1091 dev_err(amd_manager->dev, "prepare clock stop failed %d", ret); 1092 return 0; 1093 } 1094 ret = sdw_bus_clk_stop(&amd_manager->bus); 1095 if (ret < 0 && ret != -ENODATA) { 1096 dev_err(amd_manager->dev, "bus clock stop failed %d", ret); 1097 return 0; 1098 } 1099 1100 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1101 (val & AMD_SDW_CLK_STOP_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT); 1102 if (ret) { 1103 dev_err(amd_manager->dev, "SDW%x clock stop failed\n", amd_manager->instance); 1104 return 0; 1105 } 1106 1107 amd_manager->clk_stopped = true; 1108 if (amd_manager->wake_en_mask) 1109 writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 1110 1111 dev_dbg(amd_manager->dev, "SDW%x clock stop successful\n", amd_manager->instance); 1112 return 0; 1113 } 1114 1115 static int amd_sdw_clock_stop_exit(struct amd_sdw_manager *amd_manager) 1116 { 1117 int ret; 1118 u32 val; 1119 1120 if (amd_manager->clk_stopped) { 1121 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1122 val |= AMD_SDW_CLK_RESUME_REQ; 1123 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1124 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1125 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US, 1126 AMD_SDW_TIMEOUT); 1127 if (val & AMD_SDW_CLK_RESUME_DONE) { 1128 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1129 ret = sdw_bus_exit_clk_stop(&amd_manager->bus); 1130 if (ret < 0) 1131 dev_err(amd_manager->dev, "bus failed to exit clock stop %d\n", 1132 ret); 1133 amd_manager->clk_stopped = false; 1134 } 1135 } 1136 if (amd_manager->clk_stopped) { 1137 dev_err(amd_manager->dev, "SDW%x clock stop exit failed\n", amd_manager->instance); 1138 return 0; 1139 } 1140 dev_dbg(amd_manager->dev, "SDW%x clock stop exit successful\n", amd_manager->instance); 1141 return 0; 1142 } 1143 1144 static int amd_resume_child_device(struct device *dev, void *data) 1145 { 1146 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1147 int ret; 1148 1149 if (!slave->probed) { 1150 dev_dbg(dev, "skipping device, no probed driver\n"); 1151 return 0; 1152 } 1153 if (!slave->dev_num_sticky) { 1154 dev_dbg(dev, "skipping device, never detected on bus\n"); 1155 return 0; 1156 } 1157 ret = pm_request_resume(dev); 1158 if (ret < 0) { 1159 dev_err(dev, "pm_request_resume failed: %d\n", ret); 1160 return ret; 1161 } 1162 return 0; 1163 } 1164 1165 static int __maybe_unused amd_pm_prepare(struct device *dev) 1166 { 1167 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1168 struct sdw_bus *bus = &amd_manager->bus; 1169 int ret; 1170 1171 if (bus->prop.hw_disabled) { 1172 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1173 bus->link_id); 1174 return 0; 1175 } 1176 /* 1177 * When multiple peripheral devices connected over the same link, if SoundWire manager 1178 * device is not in runtime suspend state, observed that device alerts are missing 1179 * without pm_prepare on AMD platforms in clockstop mode0. 1180 */ 1181 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1182 ret = pm_request_resume(dev); 1183 if (ret < 0) { 1184 dev_err(bus->dev, "pm_request_resume failed: %d\n", ret); 1185 return 0; 1186 } 1187 } 1188 /* To force peripheral devices to system level suspend state, resume the devices 1189 * from runtime suspend state first. Without that unable to dispatch the alert 1190 * status to peripheral driver during system level resume as they are in runtime 1191 * suspend state. 1192 */ 1193 ret = device_for_each_child(bus->dev, NULL, amd_resume_child_device); 1194 if (ret < 0) 1195 dev_err(dev, "amd_resume_child_device failed: %d\n", ret); 1196 return 0; 1197 } 1198 1199 static int __maybe_unused amd_suspend(struct device *dev) 1200 { 1201 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1202 struct sdw_bus *bus = &amd_manager->bus; 1203 int ret; 1204 1205 if (bus->prop.hw_disabled) { 1206 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1207 bus->link_id); 1208 return 0; 1209 } 1210 1211 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1212 amd_sdw_wake_enable(amd_manager, false); 1213 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1214 ret = amd_sdw_host_wake_enable(amd_manager, false); 1215 if (ret) 1216 return ret; 1217 } 1218 ret = amd_sdw_clock_stop(amd_manager); 1219 if (ret) 1220 return ret; 1221 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1222 amd_sdw_wake_enable(amd_manager, false); 1223 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1224 ret = amd_sdw_host_wake_enable(amd_manager, false); 1225 if (ret) 1226 return ret; 1227 } 1228 /* 1229 * As per hardware programming sequence on AMD platforms, 1230 * clock stop should be invoked first before powering-off 1231 */ 1232 ret = amd_sdw_clock_stop(amd_manager); 1233 if (ret) 1234 return ret; 1235 ret = amd_deinit_sdw_manager(amd_manager); 1236 if (ret) 1237 return ret; 1238 } 1239 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1240 ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D3); 1241 if (ret) 1242 return ret; 1243 } 1244 return 0; 1245 } 1246 1247 static int __maybe_unused amd_suspend_runtime(struct device *dev) 1248 { 1249 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1250 struct sdw_bus *bus = &amd_manager->bus; 1251 int ret; 1252 u32 val; 1253 1254 if (bus->prop.hw_disabled) { 1255 dev_dbg(bus->dev, "SoundWire manager %d is disabled,\n", 1256 bus->link_id); 1257 return 0; 1258 } 1259 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1260 amd_sdw_wake_enable(amd_manager, true); 1261 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1262 ret = amd_sdw_host_wake_enable(amd_manager, true); 1263 if (ret) 1264 return ret; 1265 } 1266 ret = amd_sdw_clock_stop(amd_manager); 1267 if (ret) 1268 return ret; 1269 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1270 amd_sdw_wake_enable(amd_manager, true); 1271 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1272 ret = amd_sdw_host_wake_enable(amd_manager, true); 1273 if (ret) 1274 return ret; 1275 } 1276 ret = amd_sdw_clock_stop(amd_manager); 1277 if (ret) 1278 return ret; 1279 ret = amd_deinit_sdw_manager(amd_manager); 1280 if (ret) 1281 return ret; 1282 } 1283 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1284 ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D3); 1285 if (ret) 1286 return ret; 1287 if (amd_manager->wake_en_mask) { 1288 val = readl(amd_manager->acp_mmio + ACP_PME_EN); 1289 if (!val) { 1290 writel(1, amd_manager->acp_mmio + ACP_PME_EN); 1291 val = readl(amd_manager->acp_mmio + ACP_PME_EN); 1292 dev_dbg(amd_manager->dev, "ACP_PME_EN:0x%x\n", val); 1293 } 1294 } 1295 } 1296 return 0; 1297 } 1298 1299 static int __maybe_unused amd_resume_runtime(struct device *dev) 1300 { 1301 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1302 struct sdw_bus *bus = &amd_manager->bus; 1303 int ret; 1304 u32 val; 1305 1306 if (bus->prop.hw_disabled) { 1307 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1308 bus->link_id); 1309 return 0; 1310 } 1311 1312 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1313 ret = amd_sdw_clock_stop_exit(amd_manager); 1314 if (ret) 1315 return ret; 1316 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1317 ret = amd_sdw_host_wake_enable(amd_manager, false); 1318 if (ret) 1319 return ret; 1320 } 1321 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1322 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 1323 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1324 ret = amd_sdw_host_wake_enable(amd_manager, false); 1325 if (ret) 1326 return ret; 1327 } 1328 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1329 if (val) { 1330 val |= AMD_SDW_CLK_RESUME_REQ; 1331 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1332 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1333 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US, 1334 AMD_SDW_TIMEOUT); 1335 if (val & AMD_SDW_CLK_RESUME_DONE) { 1336 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1337 amd_manager->clk_stopped = false; 1338 } 1339 } 1340 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1341 amd_init_sdw_manager(amd_manager); 1342 amd_enable_sdw_interrupts(amd_manager); 1343 ret = amd_enable_sdw_manager(amd_manager); 1344 if (ret) 1345 return ret; 1346 amd_sdw_set_frameshape(amd_manager); 1347 } 1348 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1349 ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D0); 1350 if (ret) 1351 return ret; 1352 } 1353 return 0; 1354 } 1355 1356 static const struct dev_pm_ops amd_pm = { 1357 .prepare = amd_pm_prepare, 1358 SET_SYSTEM_SLEEP_PM_OPS(amd_suspend, amd_resume_runtime) 1359 SET_RUNTIME_PM_OPS(amd_suspend_runtime, amd_resume_runtime, NULL) 1360 }; 1361 1362 static struct platform_driver amd_sdw_driver = { 1363 .probe = &amd_sdw_manager_probe, 1364 .remove = &amd_sdw_manager_remove, 1365 .driver = { 1366 .name = "amd_sdw_manager", 1367 .pm = &amd_pm, 1368 } 1369 }; 1370 module_platform_driver(amd_sdw_driver); 1371 1372 MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 1373 MODULE_DESCRIPTION("AMD SoundWire driver"); 1374 MODULE_LICENSE("Dual BSD/GPL"); 1375 MODULE_ALIAS("platform:" DRV_NAME); 1376