1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * SoundWire AMD Manager driver 4 * 5 * Copyright 2023-24 Advanced Micro Devices, Inc. 6 */ 7 8 #include <linux/completion.h> 9 #include <linux/cleanup.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/jiffies.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/soundwire/sdw.h> 17 #include <linux/soundwire/sdw_registers.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/wait.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include "bus.h" 23 #include "amd_init.h" 24 #include "amd_manager.h" 25 26 #define DRV_NAME "amd_sdw_manager" 27 28 #define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus) 29 30 static int amd_sdw_clk_init_ctrl(struct amd_sdw_manager *amd_manager) 31 { 32 struct sdw_bus *bus = &amd_manager->bus; 33 struct sdw_master_prop *prop = &bus->prop; 34 u32 divider; 35 36 dev_dbg(amd_manager->dev, "mclk %d max %d row %d col %d frame_rate:%d\n", 37 prop->mclk_freq, prop->max_clk_freq, prop->default_row, 38 prop->default_col, prop->default_frame_rate); 39 40 if (!prop->default_frame_rate || !prop->default_row) { 41 dev_err(amd_manager->dev, "Default frame_rate %d or row %d is invalid\n", 42 prop->default_frame_rate, prop->default_row); 43 return -EINVAL; 44 } 45 46 /* Set clock divider */ 47 divider = (prop->mclk_freq / bus->params.curr_dr_freq); 48 writel(divider, amd_manager->mmio + ACP_SW_CLK_FREQUENCY_CTRL); 49 50 /* Set frame shape base on the actual bus frequency. */ 51 prop->default_col = bus->params.curr_dr_freq / 52 prop->default_frame_rate / prop->default_row; 53 amd_manager->cols_index = sdw_find_col_index(prop->default_col); 54 amd_manager->rows_index = sdw_find_row_index(prop->default_row); 55 bus->params.col = prop->default_col; 56 bus->params.row = prop->default_row; 57 return 0; 58 } 59 60 static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager) 61 { 62 u32 val; 63 int ret; 64 65 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 66 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 67 AMD_SDW_TIMEOUT); 68 if (ret) 69 return ret; 70 71 /* SoundWire manager bus reset */ 72 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 73 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, 74 (val & AMD_SDW_BUS_RESET_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT); 75 if (ret) 76 return ret; 77 78 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL); 79 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val, 80 ACP_DELAY_US, AMD_SDW_TIMEOUT); 81 if (ret) { 82 dev_err(amd_manager->dev, "Failed to reset SoundWire manager instance%d\n", 83 amd_manager->instance); 84 return ret; 85 } 86 87 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 88 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 89 AMD_SDW_TIMEOUT); 90 } 91 92 static int amd_enable_sdw_manager(struct amd_sdw_manager *amd_manager) 93 { 94 u32 val; 95 96 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN); 97 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US, 98 AMD_SDW_TIMEOUT); 99 } 100 101 static int amd_disable_sdw_manager(struct amd_sdw_manager *amd_manager) 102 { 103 u32 val; 104 105 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN); 106 /* 107 * After invoking manager disable sequence, check whether 108 * manager has executed clock stop sequence. In this case, 109 * manager should ignore checking enable status register. 110 */ 111 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 112 if (val) 113 return 0; 114 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US, 115 AMD_SDW_TIMEOUT); 116 } 117 118 static void amd_enable_sdw_interrupts(struct amd_sdw_manager *amd_manager) 119 { 120 u32 val; 121 122 mutex_lock(amd_manager->acp_sdw_lock); 123 val = sdw_manager_reg_mask_array[amd_manager->instance]; 124 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), val, val); 125 mutex_unlock(amd_manager->acp_sdw_lock); 126 127 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio + 128 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 129 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio + 130 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 131 writel(AMD_SDW_IRQ_ERROR_MASK, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK); 132 } 133 134 static void amd_disable_sdw_interrupts(struct amd_sdw_manager *amd_manager) 135 { 136 u32 irq_mask; 137 138 mutex_lock(amd_manager->acp_sdw_lock); 139 irq_mask = sdw_manager_reg_mask_array[amd_manager->instance]; 140 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), 141 irq_mask, 0); 142 mutex_unlock(amd_manager->acp_sdw_lock); 143 144 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 145 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 146 writel(0x00, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK); 147 } 148 149 static int amd_deinit_sdw_manager(struct amd_sdw_manager *amd_manager) 150 { 151 amd_disable_sdw_interrupts(amd_manager); 152 return amd_disable_sdw_manager(amd_manager); 153 } 154 155 static void amd_sdw_set_frameshape(struct amd_sdw_manager *amd_manager) 156 { 157 u32 frame_size; 158 159 frame_size = (amd_manager->rows_index << 3) | amd_manager->cols_index; 160 writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE); 161 } 162 163 static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable) 164 { 165 u32 wake_ctrl; 166 167 wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 168 if (enable) 169 wake_ctrl |= AMD_SDW_WAKE_INTR_MASK; 170 else 171 wake_ctrl &= ~AMD_SDW_WAKE_INTR_MASK; 172 173 writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 174 } 175 176 static int amd_sdw_set_device_state(struct amd_sdw_manager *amd_manager, u32 target_device_state) 177 { 178 u32 sdw_dev_state; 179 180 sdw_dev_state = readl(amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE); 181 switch (amd_manager->instance) { 182 case ACP_SDW0: 183 u32p_replace_bits(&sdw_dev_state, target_device_state, 184 AMD_SDW0_DEVICE_STATE_MASK); 185 break; 186 case ACP_SDW1: 187 u32p_replace_bits(&sdw_dev_state, target_device_state, 188 AMD_SDW1_DEVICE_STATE_MASK); 189 break; 190 default: 191 return -EINVAL; 192 } 193 writel(sdw_dev_state, amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE); 194 sdw_dev_state = readl(amd_manager->acp_mmio + AMD_SDW_DEVICE_STATE); 195 dev_dbg(amd_manager->dev, "AMD_SDW_DEVICE_STATE:0x%x\n", sdw_dev_state); 196 return 0; 197 } 198 199 static int amd_sdw_host_wake_enable(struct amd_sdw_manager *amd_manager, bool enable) 200 { 201 u32 intr_cntl1; 202 u32 sdw_host_wake_irq_mask; 203 204 if (!amd_manager->wake_en_mask) 205 return 0; 206 207 switch (amd_manager->instance) { 208 case ACP_SDW0: 209 sdw_host_wake_irq_mask = AMD_SDW0_HOST_WAKE_INTR_MASK; 210 break; 211 case ACP_SDW1: 212 sdw_host_wake_irq_mask = AMD_SDW1_HOST_WAKE_INTR_MASK; 213 break; 214 default: 215 return -EINVAL; 216 } 217 218 intr_cntl1 = readl(amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(ACP_SDW1)); 219 if (enable) 220 intr_cntl1 |= sdw_host_wake_irq_mask; 221 else 222 intr_cntl1 &= ~sdw_host_wake_irq_mask; 223 writel(intr_cntl1, amd_manager->acp_mmio + ACP_EXTERNAL_INTR_CNTL(ACP_SDW1)); 224 return 0; 225 } 226 227 static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg, 228 int cmd_offset) 229 { 230 u32 upper_data; 231 u32 lower_data = 0; 232 u16 addr; 233 u8 upper_addr, lower_addr; 234 u8 data = 0; 235 236 addr = msg->addr + cmd_offset; 237 upper_addr = (addr & 0xFF00) >> 8; 238 lower_addr = addr & 0xFF; 239 240 if (msg->flags == SDW_MSG_FLAG_WRITE) 241 data = msg->buf[cmd_offset]; 242 243 upper_data = FIELD_PREP(AMD_SDW_MCP_CMD_DEV_ADDR, msg->dev_num); 244 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_COMMAND, msg->flags + 2); 245 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_HIGH, upper_addr); 246 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_LOW, lower_addr); 247 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_DATA, data); 248 249 *upper_word = upper_data; 250 *lower_word = lower_data; 251 } 252 253 static u64 amd_sdw_send_cmd_get_resp(struct amd_sdw_manager *amd_manager, u32 lower_data, 254 u32 upper_data) 255 { 256 u64 resp; 257 u32 lower_resp, upper_resp; 258 u32 sts; 259 int ret; 260 261 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 262 !(sts & AMD_SDW_IMM_CMD_BUSY), ACP_DELAY_US, AMD_SDW_TIMEOUT); 263 if (ret) { 264 dev_err(amd_manager->dev, "SDW%x previous cmd status clear failed\n", 265 amd_manager->instance); 266 return ret; 267 } 268 269 if (sts & AMD_SDW_IMM_RES_VALID) { 270 dev_err(amd_manager->dev, "SDW%x manager is in bad state\n", amd_manager->instance); 271 writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS); 272 } 273 writel(upper_data, amd_manager->mmio + ACP_SW_IMM_CMD_UPPER_WORD); 274 writel(lower_data, amd_manager->mmio + ACP_SW_IMM_CMD_LOWER_QWORD); 275 276 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 277 (sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT); 278 if (ret) { 279 dev_err(amd_manager->dev, "SDW%x cmd response timeout occurred\n", 280 amd_manager->instance); 281 return ret; 282 } 283 upper_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_UPPER_WORD); 284 lower_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_LOWER_QWORD); 285 286 writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS); 287 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts, 288 !(sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT); 289 if (ret) { 290 dev_err(amd_manager->dev, "SDW%x cmd status retry failed\n", 291 amd_manager->instance); 292 return ret; 293 } 294 resp = upper_resp; 295 resp = (resp << 32) | lower_resp; 296 return resp; 297 } 298 299 static enum sdw_command_response 300 amd_program_scp_addr(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg) 301 { 302 struct sdw_msg scp_msg = {0}; 303 u64 response_buf[2] = {0}; 304 u32 upper_data = 0, lower_data = 0; 305 int index; 306 307 scp_msg.dev_num = msg->dev_num; 308 scp_msg.addr = SDW_SCP_ADDRPAGE1; 309 scp_msg.buf = &msg->addr_page1; 310 scp_msg.flags = SDW_MSG_FLAG_WRITE; 311 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0); 312 response_buf[0] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 313 scp_msg.addr = SDW_SCP_ADDRPAGE2; 314 scp_msg.buf = &msg->addr_page2; 315 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0); 316 response_buf[1] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 317 318 for (index = 0; index < 2; index++) { 319 if (response_buf[index] == -ETIMEDOUT) { 320 dev_err_ratelimited(amd_manager->dev, 321 "SCP_addrpage command timeout for Slave %d\n", 322 msg->dev_num); 323 return SDW_CMD_TIMEOUT; 324 } else if (!(response_buf[index] & AMD_SDW_MCP_RESP_ACK)) { 325 if (response_buf[index] & AMD_SDW_MCP_RESP_NACK) { 326 dev_err_ratelimited(amd_manager->dev, 327 "SCP_addrpage NACKed for Slave %d\n", 328 msg->dev_num); 329 return SDW_CMD_FAIL; 330 } 331 dev_dbg_ratelimited(amd_manager->dev, "SCP_addrpage ignored for Slave %d\n", 332 msg->dev_num); 333 return SDW_CMD_IGNORED; 334 } 335 } 336 return SDW_CMD_OK; 337 } 338 339 static int amd_prep_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg) 340 { 341 int ret; 342 343 if (msg->page) { 344 ret = amd_program_scp_addr(amd_manager, msg); 345 if (ret) { 346 msg->len = 0; 347 return ret; 348 } 349 } 350 switch (msg->flags) { 351 case SDW_MSG_FLAG_READ: 352 case SDW_MSG_FLAG_WRITE: 353 break; 354 default: 355 dev_err(amd_manager->dev, "Invalid msg cmd: %d\n", msg->flags); 356 return -EINVAL; 357 } 358 return 0; 359 } 360 361 static enum sdw_command_response amd_sdw_fill_msg_resp(struct amd_sdw_manager *amd_manager, 362 struct sdw_msg *msg, u64 response, 363 int offset) 364 { 365 if (response & AMD_SDW_MCP_RESP_ACK) { 366 if (msg->flags == SDW_MSG_FLAG_READ) 367 msg->buf[offset] = FIELD_GET(AMD_SDW_MCP_RESP_RDATA, response); 368 } else { 369 if (response == -ETIMEDOUT) { 370 dev_err_ratelimited(amd_manager->dev, "command timeout for Slave %d\n", 371 msg->dev_num); 372 return SDW_CMD_TIMEOUT; 373 } else if (response & AMD_SDW_MCP_RESP_NACK) { 374 dev_err_ratelimited(amd_manager->dev, 375 "command response NACK received for Slave %d\n", 376 msg->dev_num); 377 return SDW_CMD_FAIL; 378 } 379 dev_dbg_ratelimited(amd_manager->dev, "command is ignored for Slave %d\n", 380 msg->dev_num); 381 return SDW_CMD_IGNORED; 382 } 383 return SDW_CMD_OK; 384 } 385 386 static unsigned int _amd_sdw_xfer_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg, 387 int cmd_offset) 388 { 389 u64 response; 390 u32 upper_data = 0, lower_data = 0; 391 392 amd_sdw_ctl_word_prep(&lower_data, &upper_data, msg, cmd_offset); 393 response = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data); 394 return amd_sdw_fill_msg_resp(amd_manager, msg, response, cmd_offset); 395 } 396 397 static enum sdw_command_response amd_sdw_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg) 398 { 399 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 400 int ret, i; 401 402 ret = amd_prep_msg(amd_manager, msg); 403 if (ret) 404 return SDW_CMD_FAIL_OTHER; 405 for (i = 0; i < msg->len; i++) { 406 ret = _amd_sdw_xfer_msg(amd_manager, msg, i); 407 if (ret) 408 return ret; 409 } 410 return SDW_CMD_OK; 411 } 412 413 static void amd_sdw_fill_slave_status(struct amd_sdw_manager *amd_manager, u16 index, u32 status) 414 { 415 switch (status) { 416 case SDW_SLAVE_ATTACHED: 417 case SDW_SLAVE_UNATTACHED: 418 case SDW_SLAVE_ALERT: 419 amd_manager->status[index] = status; 420 break; 421 default: 422 amd_manager->status[index] = SDW_SLAVE_RESERVED; 423 break; 424 } 425 } 426 427 static void amd_sdw_process_ping_status(u64 response, struct amd_sdw_manager *amd_manager) 428 { 429 u64 slave_stat; 430 u32 val; 431 u16 dev_index; 432 433 /* slave status response */ 434 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response); 435 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8; 436 dev_dbg(amd_manager->dev, "slave_stat:0x%llx\n", slave_stat); 437 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) { 438 val = (slave_stat >> (dev_index * 2)) & AMD_SDW_MCP_SLAVE_STATUS_MASK; 439 dev_dbg(amd_manager->dev, "val:0x%x\n", val); 440 amd_sdw_fill_slave_status(amd_manager, dev_index, val); 441 } 442 } 443 444 static void amd_sdw_read_and_process_ping_status(struct amd_sdw_manager *amd_manager) 445 { 446 u64 response; 447 448 mutex_lock(&amd_manager->bus.msg_lock); 449 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0); 450 mutex_unlock(&amd_manager->bus.msg_lock); 451 amd_sdw_process_ping_status(response, amd_manager); 452 } 453 454 static u32 amd_sdw_read_ping_status(struct sdw_bus *bus) 455 { 456 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 457 u64 response; 458 u32 slave_stat; 459 460 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0); 461 /* slave status from ping response */ 462 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response); 463 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8; 464 dev_dbg(amd_manager->dev, "slave_stat:0x%x\n", slave_stat); 465 return slave_stat; 466 } 467 468 static int amd_sdw_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream) 469 { 470 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 471 struct sdw_transport_data t_data = {0}; 472 struct sdw_master_runtime *m_rt; 473 struct sdw_port_runtime *p_rt; 474 struct sdw_bus_params *b_params = &bus->params; 475 int port_bo, hstart, hstop, sample_int; 476 unsigned int rate, bps, channels; 477 unsigned int stream_slot_size, max_slots; 478 static unsigned int next_offset[AMD_SDW_MAX_MANAGER_COUNT] = {1}; 479 unsigned int inst_id = amd_manager->instance; 480 481 port_bo = 0; 482 hstart = 1; 483 hstop = bus->params.col - 1; 484 t_data.hstop = hstop; 485 t_data.hstart = hstart; 486 487 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 488 rate = m_rt->stream->params.rate; 489 bps = m_rt->stream->params.bps; 490 channels = m_rt->stream->params.ch_count; 491 sample_int = (bus->params.curr_dr_freq / rate); 492 493 /* Compute slots required for this stream dynamically */ 494 stream_slot_size = bps * channels; 495 496 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 497 if (p_rt->num >= amd_manager->max_ports) { 498 dev_err(bus->dev, "Port %d exceeds max ports %d\n", 499 p_rt->num, amd_manager->max_ports); 500 return -EINVAL; 501 } 502 503 if (!amd_manager->port_offset_map[p_rt->num]) { 504 /* 505 * port block offset calculation for 6MHz bus clock frequency with 506 * different frame sizes 50 x 10 and 125 x 2 507 */ 508 if (bus->params.curr_dr_freq == 12000000) { 509 max_slots = bus->params.row * (bus->params.col - 1); 510 if (next_offset[inst_id] + stream_slot_size <= 511 (max_slots - 1)) { 512 amd_manager->port_offset_map[p_rt->num] = 513 next_offset[inst_id]; 514 next_offset[inst_id] += stream_slot_size; 515 } else { 516 dev_err(bus->dev, 517 "No space for port %d\n", p_rt->num); 518 return -ENOMEM; 519 } 520 } else { 521 /* 522 * port block offset calculation for 12MHz bus clock 523 * frequency 524 */ 525 amd_manager->port_offset_map[p_rt->num] = 526 (p_rt->num * 64) + 1; 527 } 528 } 529 port_bo = amd_manager->port_offset_map[p_rt->num]; 530 dev_dbg(bus->dev, 531 "Port=%d hstart=%d hstop=%d port_bo=%d slots=%d max_ports=%d\n", 532 p_rt->num, hstart, hstop, port_bo, stream_slot_size, 533 amd_manager->max_ports); 534 535 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, 536 false, SDW_BLK_GRP_CNT_1, sample_int, 537 port_bo, port_bo >> 8, hstart, hstop, 538 SDW_BLK_PKG_PER_PORT, p_rt->lane); 539 540 sdw_fill_port_params(&p_rt->port_params, 541 p_rt->num, bps, 542 SDW_PORT_FLOW_MODE_ISOCH, 543 b_params->m_data_mode); 544 t_data.hstart = hstart; 545 t_data.hstop = hstop; 546 t_data.block_offset = port_bo; 547 t_data.sub_block_offset = 0; 548 } 549 sdw_compute_slave_ports(m_rt, &t_data); 550 } 551 return 0; 552 } 553 554 static int amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_params, 555 unsigned int bank) 556 { 557 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 558 u32 frame_fmt_reg, dpn_frame_fmt; 559 560 dev_dbg(amd_manager->dev, "p_params->num:0x%x\n", p_params->num); 561 switch (amd_manager->acp_rev) { 562 case ACP63_PCI_REV_ID: 563 switch (amd_manager->instance) { 564 case ACP_SDW0: 565 frame_fmt_reg = acp63_sdw0_dp_reg[p_params->num].frame_fmt_reg; 566 break; 567 case ACP_SDW1: 568 frame_fmt_reg = acp63_sdw1_dp_reg[p_params->num].frame_fmt_reg; 569 break; 570 default: 571 return -EINVAL; 572 } 573 break; 574 case ACP70_PCI_REV_ID: 575 case ACP71_PCI_REV_ID: 576 case ACP72_PCI_REV_ID: 577 frame_fmt_reg = acp70_sdw_dp_reg[p_params->num].frame_fmt_reg; 578 break; 579 default: 580 return -EINVAL; 581 } 582 583 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg); 584 u32p_replace_bits(&dpn_frame_fmt, p_params->flow_mode, AMD_DPN_FRAME_FMT_PFM); 585 u32p_replace_bits(&dpn_frame_fmt, p_params->data_mode, AMD_DPN_FRAME_FMT_PDM); 586 u32p_replace_bits(&dpn_frame_fmt, p_params->bps - 1, AMD_DPN_FRAME_FMT_WORD_LEN); 587 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg); 588 return 0; 589 } 590 591 static int amd_sdw_transport_params(struct sdw_bus *bus, 592 struct sdw_transport_params *params, 593 enum sdw_reg_bank bank) 594 { 595 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 596 u32 dpn_frame_fmt; 597 u32 dpn_sampleinterval; 598 u32 dpn_hctrl; 599 u32 dpn_offsetctrl; 600 u32 dpn_lanectrl; 601 u32 frame_fmt_reg, sample_int_reg, hctrl_dp0_reg; 602 u32 offset_reg, lane_ctrl_ch_en_reg; 603 604 switch (amd_manager->acp_rev) { 605 case ACP63_PCI_REV_ID: 606 switch (amd_manager->instance) { 607 case ACP_SDW0: 608 frame_fmt_reg = acp63_sdw0_dp_reg[params->port_num].frame_fmt_reg; 609 sample_int_reg = acp63_sdw0_dp_reg[params->port_num].sample_int_reg; 610 hctrl_dp0_reg = acp63_sdw0_dp_reg[params->port_num].hctrl_dp0_reg; 611 offset_reg = acp63_sdw0_dp_reg[params->port_num].offset_reg; 612 lane_ctrl_ch_en_reg = 613 acp63_sdw0_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 614 break; 615 case ACP_SDW1: 616 frame_fmt_reg = acp63_sdw1_dp_reg[params->port_num].frame_fmt_reg; 617 sample_int_reg = acp63_sdw1_dp_reg[params->port_num].sample_int_reg; 618 hctrl_dp0_reg = acp63_sdw1_dp_reg[params->port_num].hctrl_dp0_reg; 619 offset_reg = acp63_sdw1_dp_reg[params->port_num].offset_reg; 620 lane_ctrl_ch_en_reg = 621 acp63_sdw1_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 622 break; 623 default: 624 return -EINVAL; 625 } 626 break; 627 case ACP70_PCI_REV_ID: 628 case ACP71_PCI_REV_ID: 629 case ACP72_PCI_REV_ID: 630 frame_fmt_reg = acp70_sdw_dp_reg[params->port_num].frame_fmt_reg; 631 sample_int_reg = acp70_sdw_dp_reg[params->port_num].sample_int_reg; 632 hctrl_dp0_reg = acp70_sdw_dp_reg[params->port_num].hctrl_dp0_reg; 633 offset_reg = acp70_sdw_dp_reg[params->port_num].offset_reg; 634 lane_ctrl_ch_en_reg = acp70_sdw_dp_reg[params->port_num].lane_ctrl_ch_en_reg; 635 break; 636 default: 637 return -EINVAL; 638 } 639 writel(AMD_SDW_SSP_COUNTER_VAL, amd_manager->mmio + ACP_SW_SSP_COUNTER); 640 641 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg); 642 u32p_replace_bits(&dpn_frame_fmt, params->blk_pkg_mode, AMD_DPN_FRAME_FMT_BLK_PKG_MODE); 643 u32p_replace_bits(&dpn_frame_fmt, params->blk_grp_ctrl, AMD_DPN_FRAME_FMT_BLK_GRP_CTRL); 644 u32p_replace_bits(&dpn_frame_fmt, SDW_STREAM_PCM, AMD_DPN_FRAME_FMT_PCM_OR_PDM); 645 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg); 646 647 dpn_sampleinterval = params->sample_interval - 1; 648 writel(dpn_sampleinterval, amd_manager->mmio + sample_int_reg); 649 650 dpn_hctrl = FIELD_PREP(AMD_DPN_HCTRL_HSTOP, params->hstop); 651 dpn_hctrl |= FIELD_PREP(AMD_DPN_HCTRL_HSTART, params->hstart); 652 writel(dpn_hctrl, amd_manager->mmio + hctrl_dp0_reg); 653 654 dpn_offsetctrl = FIELD_PREP(AMD_DPN_OFFSET_CTRL_1, params->offset1); 655 dpn_offsetctrl |= FIELD_PREP(AMD_DPN_OFFSET_CTRL_2, params->offset2); 656 writel(dpn_offsetctrl, amd_manager->mmio + offset_reg); 657 658 /* 659 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask 660 * parameters. 661 */ 662 dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); 663 u32p_replace_bits(&dpn_lanectrl, params->lane_ctrl, AMD_DPN_CH_EN_LCTRL); 664 writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg); 665 return 0; 666 } 667 668 static int amd_sdw_port_enable(struct sdw_bus *bus, 669 struct sdw_enable_ch *enable_ch, 670 unsigned int bank) 671 { 672 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 673 u32 dpn_ch_enable; 674 u32 lane_ctrl_ch_en_reg; 675 676 switch (amd_manager->acp_rev) { 677 case ACP63_PCI_REV_ID: 678 switch (amd_manager->instance) { 679 case ACP_SDW0: 680 lane_ctrl_ch_en_reg = 681 acp63_sdw0_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 682 break; 683 case ACP_SDW1: 684 lane_ctrl_ch_en_reg = 685 acp63_sdw1_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 686 break; 687 default: 688 return -EINVAL; 689 } 690 break; 691 case ACP70_PCI_REV_ID: 692 case ACP71_PCI_REV_ID: 693 case ACP72_PCI_REV_ID: 694 lane_ctrl_ch_en_reg = acp70_sdw_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; 695 break; 696 default: 697 return -EINVAL; 698 } 699 700 /* 701 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask 702 * parameters. 703 */ 704 dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); 705 u32p_replace_bits(&dpn_ch_enable, enable_ch->ch_mask, AMD_DPN_CH_EN_CHMASK); 706 if (enable_ch->enable) 707 writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg); 708 else 709 writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg); 710 return 0; 711 } 712 713 static int sdw_master_read_amd_prop(struct sdw_bus *bus) 714 { 715 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus); 716 struct fwnode_handle *link; 717 struct sdw_master_prop *prop; 718 u32 quirk_mask = 0; 719 u32 wake_en_mask = 0; 720 u32 power_mode_mask = 0; 721 char name[32]; 722 723 prop = &bus->prop; 724 /* Find manager handle */ 725 snprintf(name, sizeof(name), "mipi-sdw-link-%d-subproperties", bus->link_id); 726 link = device_get_named_child_node(bus->dev, name); 727 if (!link) { 728 dev_err(bus->dev, "Manager node %s not found\n", name); 729 return -EIO; 730 } 731 fwnode_property_read_u32(link, "amd-sdw-enable", &quirk_mask); 732 if (!(quirk_mask & AMD_SDW_QUIRK_MASK_BUS_ENABLE)) 733 prop->hw_disabled = true; 734 prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH | 735 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY; 736 737 fwnode_property_read_u32(link, "amd-sdw-wakeup-enable", &wake_en_mask); 738 amd_manager->wake_en_mask = wake_en_mask; 739 fwnode_property_read_u32(link, "amd-sdw-power-mode", &power_mode_mask); 740 amd_manager->power_mode_mask = power_mode_mask; 741 742 fwnode_handle_put(link); 743 744 return 0; 745 } 746 747 static int amd_prop_read(struct sdw_bus *bus) 748 { 749 sdw_master_read_prop(bus); 750 sdw_master_read_amd_prop(bus); 751 return 0; 752 } 753 754 static const struct sdw_master_port_ops amd_sdw_port_ops = { 755 .dpn_set_port_params = amd_sdw_port_params, 756 .dpn_set_port_transport_params = amd_sdw_transport_params, 757 .dpn_port_enable_ch = amd_sdw_port_enable, 758 }; 759 760 static const struct sdw_master_ops amd_sdw_ops = { 761 .read_prop = amd_prop_read, 762 .xfer_msg = amd_sdw_xfer_msg, 763 .read_ping_status = amd_sdw_read_ping_status, 764 }; 765 766 static int amd_sdw_hw_params(struct snd_pcm_substream *substream, 767 struct snd_pcm_hw_params *params, 768 struct snd_soc_dai *dai) 769 { 770 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 771 struct sdw_amd_dai_runtime *dai_runtime; 772 struct sdw_stream_config sconfig; 773 int ch, dir; 774 int ret; 775 776 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 777 if (!dai_runtime) 778 return -EIO; 779 780 ch = params_channels(params); 781 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 782 dir = SDW_DATA_DIR_RX; 783 else 784 dir = SDW_DATA_DIR_TX; 785 dev_dbg(amd_manager->dev, "dir:%d dai->id:0x%x\n", dir, dai->id); 786 787 sconfig.direction = dir; 788 sconfig.ch_count = ch; 789 sconfig.frame_rate = params_rate(params); 790 sconfig.type = dai_runtime->stream_type; 791 792 sconfig.bps = snd_pcm_format_width(params_format(params)); 793 794 /* Port configuration */ 795 struct sdw_port_config *pconfig __free(kfree) = kzalloc_obj(*pconfig); 796 if (!pconfig) 797 return -ENOMEM; 798 799 pconfig->num = dai->id; 800 pconfig->ch_mask = (1 << ch) - 1; 801 ret = sdw_stream_add_master(&amd_manager->bus, &sconfig, 802 pconfig, 1, dai_runtime->stream); 803 if (ret) 804 dev_err(amd_manager->dev, "add manager to stream failed:%d\n", ret); 805 806 return ret; 807 } 808 809 static int amd_sdw_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 810 { 811 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 812 struct sdw_amd_dai_runtime *dai_runtime; 813 int ret; 814 815 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 816 if (!dai_runtime) 817 return -EIO; 818 819 ret = sdw_stream_remove_master(&amd_manager->bus, dai_runtime->stream); 820 if (ret < 0) 821 dev_err(dai->dev, "remove manager from stream %s failed: %d\n", 822 dai_runtime->stream->name, ret); 823 return ret; 824 } 825 826 static int amd_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) 827 { 828 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 829 struct sdw_amd_dai_runtime *dai_runtime; 830 831 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 832 if (stream) { 833 /* first paranoia check */ 834 if (dai_runtime) { 835 dev_err(dai->dev, "dai_runtime already allocated for dai %s\n", dai->name); 836 return -EINVAL; 837 } 838 839 /* allocate and set dai_runtime info */ 840 dai_runtime = kzalloc_obj(*dai_runtime); 841 if (!dai_runtime) 842 return -ENOMEM; 843 844 dai_runtime->stream_type = SDW_STREAM_PCM; 845 dai_runtime->bus = &amd_manager->bus; 846 dai_runtime->stream = stream; 847 amd_manager->dai_runtime_array[dai->id] = dai_runtime; 848 } else { 849 /* second paranoia check */ 850 if (!dai_runtime) { 851 dev_err(dai->dev, "dai_runtime not allocated for dai %s\n", dai->name); 852 return -EINVAL; 853 } 854 855 /* for NULL stream we release allocated dai_runtime */ 856 kfree(dai_runtime); 857 amd_manager->dai_runtime_array[dai->id] = NULL; 858 } 859 return 0; 860 } 861 862 static int amd_pcm_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction) 863 { 864 return amd_set_sdw_stream(dai, stream, direction); 865 } 866 867 static void *amd_get_sdw_stream(struct snd_soc_dai *dai, int direction) 868 { 869 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai); 870 struct sdw_amd_dai_runtime *dai_runtime; 871 872 dai_runtime = amd_manager->dai_runtime_array[dai->id]; 873 if (!dai_runtime) 874 return ERR_PTR(-EINVAL); 875 876 return dai_runtime->stream; 877 } 878 879 static const struct snd_soc_dai_ops amd_sdw_dai_ops = { 880 .hw_params = amd_sdw_hw_params, 881 .hw_free = amd_sdw_hw_free, 882 .set_stream = amd_pcm_set_sdw_stream, 883 .get_stream = amd_get_sdw_stream, 884 }; 885 886 static const struct snd_soc_component_driver amd_sdw_dai_component = { 887 .name = "soundwire", 888 }; 889 890 static int amd_sdw_register_dais(struct amd_sdw_manager *amd_manager) 891 { 892 struct sdw_amd_dai_runtime **dai_runtime_array; 893 struct snd_soc_dai_driver *dais; 894 struct snd_soc_pcm_stream *stream; 895 struct device *dev; 896 int i, num_dais; 897 898 dev = amd_manager->dev; 899 num_dais = amd_manager->num_dout_ports + amd_manager->num_din_ports; 900 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); 901 if (!dais) 902 return -ENOMEM; 903 904 dai_runtime_array = devm_kcalloc(dev, num_dais, 905 sizeof(struct sdw_amd_dai_runtime *), 906 GFP_KERNEL); 907 if (!dai_runtime_array) 908 return -ENOMEM; 909 amd_manager->dai_runtime_array = dai_runtime_array; 910 for (i = 0; i < num_dais; i++) { 911 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW%d Pin%d", amd_manager->instance, 912 i); 913 if (!dais[i].name) 914 return -ENOMEM; 915 if (i < amd_manager->num_dout_ports) 916 stream = &dais[i].playback; 917 else 918 stream = &dais[i].capture; 919 920 stream->channels_min = 2; 921 stream->channels_max = 2; 922 stream->rates = SNDRV_PCM_RATE_48000; 923 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; 924 925 dais[i].ops = &amd_sdw_dai_ops; 926 dais[i].id = i; 927 } 928 929 return devm_snd_soc_register_component(dev, &amd_sdw_dai_component, 930 dais, num_dais); 931 } 932 933 static void amd_sdw_update_slave_status_work(struct work_struct *work) 934 { 935 struct amd_sdw_manager *amd_manager = 936 container_of(work, struct amd_sdw_manager, amd_sdw_work); 937 int retry_count = 0; 938 939 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) { 940 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 941 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 942 } 943 944 update_status: 945 sdw_handle_slave_status(&amd_manager->bus, amd_manager->status); 946 /* 947 * During the peripheral enumeration sequence, the SoundWire manager interrupts 948 * are masked. Once the device number programming is done for all peripherals, 949 * interrupts will be unmasked. Read the peripheral device status from ping command 950 * and process the response. This sequence will ensure all peripheral devices enumerated 951 * and initialized properly. 952 */ 953 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) { 954 if (retry_count++ < SDW_MAX_DEVICES) { 955 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio + 956 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7); 957 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio + 958 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11); 959 amd_sdw_read_and_process_ping_status(amd_manager); 960 goto update_status; 961 } else { 962 dev_err_ratelimited(amd_manager->dev, 963 "Device0 detected after %d iterations\n", 964 retry_count); 965 } 966 } 967 } 968 969 static void amd_sdw_update_slave_status(u32 status_change_0to7, u32 status_change_8to11, 970 struct amd_sdw_manager *amd_manager) 971 { 972 u64 slave_stat; 973 u32 val; 974 int dev_index; 975 976 if (status_change_0to7 == AMD_SDW_SLAVE_0_ATTACHED) 977 memset(amd_manager->status, 0, sizeof(amd_manager->status)); 978 slave_stat = status_change_0to7; 979 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STATUS_8TO_11, status_change_8to11) << 32; 980 dev_dbg(amd_manager->dev, "status_change_0to7:0x%x status_change_8to11:0x%x\n", 981 status_change_0to7, status_change_8to11); 982 if (slave_stat) { 983 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) { 984 if (slave_stat & AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(dev_index)) { 985 val = (slave_stat >> AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(dev_index)) & 986 AMD_SDW_MCP_SLAVE_STATUS_MASK; 987 amd_sdw_fill_slave_status(amd_manager, dev_index, val); 988 } 989 } 990 } 991 } 992 993 static void amd_sdw_process_wake_event(struct amd_sdw_manager *amd_manager) 994 { 995 dev_dbg(amd_manager->dev, "SoundWire Wake event reported\n"); 996 pm_request_resume(amd_manager->dev); 997 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 998 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 999 } 1000 1001 static void amd_sdw_irq_thread(struct work_struct *work) 1002 { 1003 struct amd_sdw_manager *amd_manager = 1004 container_of(work, struct amd_sdw_manager, amd_sdw_irq_thread); 1005 u32 status_change_8to11; 1006 u32 status_change_0to7; 1007 1008 status_change_8to11 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 1009 status_change_0to7 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); 1010 if (!status_change_0to7 && !status_change_8to11) 1011 return; 1012 1013 dev_dbg(amd_manager->dev, "[SDW%d] SDW INT: 0to7=0x%x, 8to11=0x%x\n", 1014 amd_manager->instance, status_change_0to7, status_change_8to11); 1015 if (status_change_8to11 & AMD_SDW_WAKE_STAT_MASK) 1016 return amd_sdw_process_wake_event(amd_manager); 1017 1018 if (status_change_8to11 & AMD_SDW_PREQ_INTR_STAT) { 1019 amd_sdw_read_and_process_ping_status(amd_manager); 1020 } else { 1021 /* Check for the updated status on peripheral device */ 1022 amd_sdw_update_slave_status(status_change_0to7, status_change_8to11, amd_manager); 1023 } 1024 if (status_change_8to11 || status_change_0to7) 1025 schedule_work(&amd_manager->amd_sdw_work); 1026 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11); 1027 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7); 1028 } 1029 1030 int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager) 1031 { 1032 struct sdw_master_prop *prop; 1033 int ret; 1034 1035 prop = &amd_manager->bus.prop; 1036 if (!prop->hw_disabled) { 1037 ret = amd_sdw_clk_init_ctrl(amd_manager); 1038 if (ret) 1039 return ret; 1040 ret = amd_init_sdw_manager(amd_manager); 1041 if (ret) 1042 return ret; 1043 amd_enable_sdw_interrupts(amd_manager); 1044 ret = amd_enable_sdw_manager(amd_manager); 1045 if (ret) 1046 return ret; 1047 amd_sdw_set_frameshape(amd_manager); 1048 } 1049 /* Enable runtime PM */ 1050 pm_runtime_set_autosuspend_delay(amd_manager->dev, AMD_SDW_MASTER_SUSPEND_DELAY_MS); 1051 pm_runtime_use_autosuspend(amd_manager->dev); 1052 pm_runtime_mark_last_busy(amd_manager->dev); 1053 pm_runtime_set_active(amd_manager->dev); 1054 pm_runtime_enable(amd_manager->dev); 1055 return 0; 1056 } 1057 1058 static int amd_sdw_manager_probe(struct platform_device *pdev) 1059 { 1060 const struct acp_sdw_pdata *pdata = pdev->dev.platform_data; 1061 struct resource *res; 1062 struct device *dev = &pdev->dev; 1063 struct sdw_master_prop *prop; 1064 struct amd_sdw_manager *amd_manager; 1065 int ret; 1066 1067 amd_manager = devm_kzalloc(dev, sizeof(struct amd_sdw_manager), GFP_KERNEL); 1068 if (!amd_manager) 1069 return -ENOMEM; 1070 1071 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1072 if (!res) 1073 return -ENOMEM; 1074 1075 amd_manager->acp_mmio = devm_ioremap(dev, res->start, resource_size(res)); 1076 if (!amd_manager->acp_mmio) { 1077 dev_err(dev, "mmio not found\n"); 1078 return -ENOMEM; 1079 } 1080 amd_manager->instance = pdata->instance; 1081 amd_manager->mmio = amd_manager->acp_mmio + 1082 (amd_manager->instance * SDW_MANAGER_REG_OFFSET); 1083 amd_manager->acp_sdw_lock = pdata->acp_sdw_lock; 1084 amd_manager->acp_rev = pdata->acp_rev; 1085 amd_manager->cols_index = sdw_find_col_index(AMD_SDW_DEFAULT_COLUMNS); 1086 amd_manager->rows_index = sdw_find_row_index(AMD_SDW_DEFAULT_ROWS); 1087 amd_manager->dev = dev; 1088 amd_manager->bus.ops = &amd_sdw_ops; 1089 amd_manager->bus.port_ops = &amd_sdw_port_ops; 1090 amd_manager->bus.compute_params = &amd_sdw_compute_params; 1091 amd_manager->bus.clk_stop_timeout = 200; 1092 amd_manager->bus.link_id = amd_manager->instance; 1093 1094 /* 1095 * Due to BIOS compatibility, the two links are exposed within 1096 * the scope of a single controller. If this changes, the 1097 * controller_id will have to be updated with drv_data 1098 * information. 1099 */ 1100 amd_manager->bus.controller_id = 0; 1101 dev_dbg(dev, "acp_rev:0x%x\n", amd_manager->acp_rev); 1102 switch (amd_manager->acp_rev) { 1103 case ACP63_PCI_REV_ID: 1104 switch (amd_manager->instance) { 1105 case ACP_SDW0: 1106 amd_manager->num_dout_ports = AMD_ACP63_SDW0_MAX_TX_PORTS; 1107 amd_manager->num_din_ports = AMD_ACP63_SDW0_MAX_RX_PORTS; 1108 break; 1109 case ACP_SDW1: 1110 amd_manager->num_dout_ports = AMD_ACP63_SDW1_MAX_TX_PORTS; 1111 amd_manager->num_din_ports = AMD_ACP63_SDW1_MAX_RX_PORTS; 1112 break; 1113 default: 1114 return -EINVAL; 1115 } 1116 break; 1117 case ACP70_PCI_REV_ID: 1118 case ACP71_PCI_REV_ID: 1119 case ACP72_PCI_REV_ID: 1120 amd_manager->num_dout_ports = AMD_ACP70_SDW_MAX_TX_PORTS; 1121 amd_manager->num_din_ports = AMD_ACP70_SDW_MAX_RX_PORTS; 1122 break; 1123 default: 1124 return -EINVAL; 1125 } 1126 amd_manager->max_ports = amd_manager->num_dout_ports + amd_manager->num_din_ports; 1127 amd_manager->port_offset_map = devm_kcalloc(dev, amd_manager->max_ports, 1128 sizeof(int), GFP_KERNEL); 1129 if (!amd_manager->port_offset_map) 1130 return -ENOMEM; 1131 1132 prop = &amd_manager->bus.prop; 1133 prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ; 1134 1135 ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode); 1136 if (ret) { 1137 dev_err(dev, "Failed to register SoundWire manager(%d)\n", ret); 1138 return ret; 1139 } 1140 ret = amd_sdw_register_dais(amd_manager); 1141 if (ret) { 1142 dev_err(dev, "CPU DAI registration failed\n"); 1143 sdw_bus_master_delete(&amd_manager->bus); 1144 return ret; 1145 } 1146 dev_set_drvdata(dev, amd_manager); 1147 INIT_WORK(&amd_manager->amd_sdw_irq_thread, amd_sdw_irq_thread); 1148 INIT_WORK(&amd_manager->amd_sdw_work, amd_sdw_update_slave_status_work); 1149 return 0; 1150 } 1151 1152 static void amd_sdw_manager_remove(struct platform_device *pdev) 1153 { 1154 struct amd_sdw_manager *amd_manager = dev_get_drvdata(&pdev->dev); 1155 int ret; 1156 1157 pm_runtime_disable(&pdev->dev); 1158 cancel_work_sync(&amd_manager->amd_sdw_work); 1159 amd_disable_sdw_interrupts(amd_manager); 1160 sdw_bus_master_delete(&amd_manager->bus); 1161 ret = amd_disable_sdw_manager(amd_manager); 1162 if (ret) 1163 dev_err(&pdev->dev, "Failed to disable device (%pe)\n", ERR_PTR(ret)); 1164 } 1165 1166 static int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager) 1167 { 1168 u32 val; 1169 int ret; 1170 1171 ret = sdw_bus_prep_clk_stop(&amd_manager->bus); 1172 if (ret < 0 && ret != -ENODATA) { 1173 dev_err(amd_manager->dev, "prepare clock stop failed %d", ret); 1174 return 0; 1175 } 1176 ret = sdw_bus_clk_stop(&amd_manager->bus); 1177 if (ret < 0 && ret != -ENODATA) { 1178 dev_err(amd_manager->dev, "bus clock stop failed %d", ret); 1179 return 0; 1180 } 1181 1182 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1183 (val & AMD_SDW_CLK_STOP_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT); 1184 if (ret) { 1185 dev_err(amd_manager->dev, "SDW%x clock stop failed\n", amd_manager->instance); 1186 return 0; 1187 } 1188 1189 amd_manager->clk_stopped = true; 1190 if (amd_manager->wake_en_mask) 1191 writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 1192 1193 dev_dbg(amd_manager->dev, "SDW%x clock stop successful\n", amd_manager->instance); 1194 return 0; 1195 } 1196 1197 static int amd_sdw_clock_stop_exit(struct amd_sdw_manager *amd_manager) 1198 { 1199 int ret; 1200 u32 val; 1201 1202 if (amd_manager->clk_stopped) { 1203 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1204 val |= AMD_SDW_CLK_RESUME_REQ; 1205 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1206 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1207 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US, 1208 AMD_SDW_TIMEOUT); 1209 if (val & AMD_SDW_CLK_RESUME_DONE) { 1210 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1211 ret = sdw_bus_exit_clk_stop(&amd_manager->bus); 1212 if (ret < 0) 1213 dev_err(amd_manager->dev, "bus failed to exit clock stop %d\n", 1214 ret); 1215 amd_manager->clk_stopped = false; 1216 } 1217 } 1218 if (amd_manager->clk_stopped) { 1219 dev_err(amd_manager->dev, "SDW%x clock stop exit failed\n", amd_manager->instance); 1220 return 0; 1221 } 1222 dev_dbg(amd_manager->dev, "SDW%x clock stop exit successful\n", amd_manager->instance); 1223 return 0; 1224 } 1225 1226 static int amd_resume_child_device(struct device *dev, void *data) 1227 { 1228 struct sdw_slave *slave = dev_to_sdw_dev(dev); 1229 int ret; 1230 1231 if (!slave->probed) { 1232 dev_dbg(dev, "skipping device, no probed driver\n"); 1233 return 0; 1234 } 1235 if (!slave->dev_num_sticky) { 1236 dev_dbg(dev, "skipping device, never detected on bus\n"); 1237 return 0; 1238 } 1239 ret = pm_request_resume(dev); 1240 if (ret < 0) { 1241 dev_err(dev, "pm_request_resume failed: %d\n", ret); 1242 return ret; 1243 } 1244 return 0; 1245 } 1246 1247 static int __maybe_unused amd_pm_prepare(struct device *dev) 1248 { 1249 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1250 struct sdw_bus *bus = &amd_manager->bus; 1251 int ret; 1252 1253 if (bus->prop.hw_disabled) { 1254 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1255 bus->link_id); 1256 return 0; 1257 } 1258 /* 1259 * When multiple peripheral devices connected over the same link, if SoundWire manager 1260 * device is not in runtime suspend state, observed that device alerts are missing 1261 * without pm_prepare on AMD platforms in clockstop mode0. 1262 */ 1263 if (amd_manager->power_mode_mask) { 1264 ret = pm_runtime_resume(dev); 1265 if (ret < 0) { 1266 dev_err(bus->dev, "pm_runtime_resume failed: %d\n", ret); 1267 return 0; 1268 } 1269 } 1270 /* To force peripheral devices to system level suspend state, resume the devices 1271 * from runtime suspend state first. Without that unable to dispatch the alert 1272 * status to peripheral driver during system level resume as they are in runtime 1273 * suspend state. 1274 */ 1275 ret = device_for_each_child(bus->dev, NULL, amd_resume_child_device); 1276 if (ret < 0) 1277 dev_err(dev, "amd_resume_child_device failed: %d\n", ret); 1278 return 0; 1279 } 1280 1281 static int __maybe_unused amd_suspend(struct device *dev) 1282 { 1283 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1284 struct sdw_bus *bus = &amd_manager->bus; 1285 int ret; 1286 1287 if (bus->prop.hw_disabled) { 1288 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1289 bus->link_id); 1290 return 0; 1291 } 1292 1293 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1294 cancel_work_sync(&amd_manager->amd_sdw_work); 1295 amd_sdw_wake_enable(amd_manager, false); 1296 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1297 ret = amd_sdw_host_wake_enable(amd_manager, false); 1298 if (ret) 1299 return ret; 1300 } 1301 ret = amd_sdw_clock_stop(amd_manager); 1302 if (ret) 1303 return ret; 1304 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1305 cancel_work_sync(&amd_manager->amd_sdw_work); 1306 amd_sdw_wake_enable(amd_manager, false); 1307 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1308 ret = amd_sdw_host_wake_enable(amd_manager, false); 1309 if (ret) 1310 return ret; 1311 } 1312 /* 1313 * As per hardware programming sequence on AMD platforms, 1314 * clock stop should be invoked first before powering-off 1315 */ 1316 ret = amd_sdw_clock_stop(amd_manager); 1317 if (ret) 1318 return ret; 1319 ret = amd_deinit_sdw_manager(amd_manager); 1320 if (ret) 1321 return ret; 1322 } 1323 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1324 ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D3); 1325 if (ret) 1326 return ret; 1327 } 1328 return 0; 1329 } 1330 1331 static int __maybe_unused amd_suspend_runtime(struct device *dev) 1332 { 1333 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1334 struct sdw_bus *bus = &amd_manager->bus; 1335 int ret; 1336 u32 val; 1337 1338 if (bus->prop.hw_disabled) { 1339 dev_dbg(bus->dev, "SoundWire manager %d is disabled,\n", 1340 bus->link_id); 1341 return 0; 1342 } 1343 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1344 amd_sdw_wake_enable(amd_manager, true); 1345 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1346 ret = amd_sdw_host_wake_enable(amd_manager, true); 1347 if (ret) 1348 return ret; 1349 } 1350 ret = amd_sdw_clock_stop(amd_manager); 1351 if (ret) 1352 return ret; 1353 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1354 amd_sdw_wake_enable(amd_manager, true); 1355 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1356 ret = amd_sdw_host_wake_enable(amd_manager, true); 1357 if (ret) 1358 return ret; 1359 } 1360 ret = amd_sdw_clock_stop(amd_manager); 1361 if (ret) 1362 return ret; 1363 ret = amd_deinit_sdw_manager(amd_manager); 1364 if (ret) 1365 return ret; 1366 } 1367 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1368 ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D3); 1369 if (ret) 1370 return ret; 1371 if (amd_manager->wake_en_mask) { 1372 val = readl(amd_manager->acp_mmio + ACP_PME_EN); 1373 if (!val) { 1374 writel(1, amd_manager->acp_mmio + ACP_PME_EN); 1375 val = readl(amd_manager->acp_mmio + ACP_PME_EN); 1376 dev_dbg(amd_manager->dev, "ACP_PME_EN:0x%x\n", val); 1377 } 1378 } 1379 } 1380 return 0; 1381 } 1382 1383 static int __maybe_unused amd_resume_runtime(struct device *dev) 1384 { 1385 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); 1386 struct sdw_bus *bus = &amd_manager->bus; 1387 int ret; 1388 u32 val; 1389 1390 if (bus->prop.hw_disabled) { 1391 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n", 1392 bus->link_id); 1393 return 0; 1394 } 1395 1396 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) { 1397 ret = amd_sdw_clock_stop_exit(amd_manager); 1398 if (ret) 1399 return ret; 1400 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1401 ret = amd_sdw_host_wake_enable(amd_manager, false); 1402 if (ret) 1403 return ret; 1404 } 1405 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) { 1406 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance)); 1407 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1408 ret = amd_sdw_host_wake_enable(amd_manager, false); 1409 if (ret) 1410 return ret; 1411 } 1412 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1413 if (val) { 1414 val |= AMD_SDW_CLK_RESUME_REQ; 1415 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1416 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val, 1417 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US, 1418 AMD_SDW_TIMEOUT); 1419 if (val & AMD_SDW_CLK_RESUME_DONE) { 1420 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL); 1421 amd_manager->clk_stopped = false; 1422 } 1423 } 1424 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1425 ret = amd_sdw_clk_init_ctrl(amd_manager); 1426 if (ret) 1427 return ret; 1428 amd_init_sdw_manager(amd_manager); 1429 amd_enable_sdw_interrupts(amd_manager); 1430 ret = amd_enable_sdw_manager(amd_manager); 1431 if (ret) 1432 return ret; 1433 amd_sdw_set_frameshape(amd_manager); 1434 } 1435 if (amd_manager->acp_rev >= ACP70_PCI_REV_ID) { 1436 ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D0); 1437 if (ret) 1438 return ret; 1439 } 1440 return 0; 1441 } 1442 1443 static const struct dev_pm_ops amd_pm = { 1444 .prepare = amd_pm_prepare, 1445 SET_SYSTEM_SLEEP_PM_OPS(amd_suspend, amd_resume_runtime) 1446 SET_RUNTIME_PM_OPS(amd_suspend_runtime, amd_resume_runtime, NULL) 1447 }; 1448 1449 static struct platform_driver amd_sdw_driver = { 1450 .probe = &amd_sdw_manager_probe, 1451 .remove = &amd_sdw_manager_remove, 1452 .driver = { 1453 .name = "amd_sdw_manager", 1454 .pm = &amd_pm, 1455 } 1456 }; 1457 module_platform_driver(amd_sdw_driver); 1458 1459 MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 1460 MODULE_DESCRIPTION("AMD SoundWire driver"); 1461 MODULE_LICENSE("Dual BSD/GPL"); 1462 MODULE_ALIAS("platform:" DRV_NAME); 1463