1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #define pr_fmt(fmt) "tegra-pmc: " fmt 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/clk/tegra.h> 25 #include <linux/debugfs.h> 26 #include <linux/delay.h> 27 #include <linux/err.h> 28 #include <linux/export.h> 29 #include <linux/init.h> 30 #include <linux/io.h> 31 #include <linux/iopoll.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_platform.h> 35 #include <linux/platform_device.h> 36 #include <linux/pm_domain.h> 37 #include <linux/reboot.h> 38 #include <linux/reset.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 43 #include <soc/tegra/common.h> 44 #include <soc/tegra/fuse.h> 45 #include <soc/tegra/pmc.h> 46 47 #define PMC_CNTRL 0x0 48 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 49 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 50 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 51 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 52 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 53 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 54 #define PMC_CNTRL_MAIN_RST BIT(4) 55 56 #define DPD_SAMPLE 0x020 57 #define DPD_SAMPLE_ENABLE BIT(0) 58 #define DPD_SAMPLE_DISABLE (0 << 0) 59 60 #define PWRGATE_TOGGLE 0x30 61 #define PWRGATE_TOGGLE_START BIT(8) 62 63 #define REMOVE_CLAMPING 0x34 64 65 #define PWRGATE_STATUS 0x38 66 67 #define PMC_PWR_DET 0x48 68 69 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 70 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 71 #define PMC_SCRATCH0_MODE_RCM BIT(1) 72 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 73 PMC_SCRATCH0_MODE_BOOTLOADER | \ 74 PMC_SCRATCH0_MODE_RCM) 75 76 #define PMC_CPUPWRGOOD_TIMER 0xc8 77 #define PMC_CPUPWROFF_TIMER 0xcc 78 79 #define PMC_PWR_DET_VALUE 0xe4 80 81 #define PMC_SCRATCH41 0x140 82 83 #define PMC_SENSOR_CTRL 0x1b0 84 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 85 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 86 87 #define PMC_RST_STATUS 0x1b4 88 #define PMC_RST_STATUS_POR 0 89 #define PMC_RST_STATUS_WATCHDOG 1 90 #define PMC_RST_STATUS_SENSOR 2 91 #define PMC_RST_STATUS_SW_MAIN 3 92 #define PMC_RST_STATUS_LP0 4 93 #define PMC_RST_STATUS_AOTAG 5 94 95 #define IO_DPD_REQ 0x1b8 96 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 97 #define IO_DPD_REQ_CODE_OFF (1U << 30) 98 #define IO_DPD_REQ_CODE_ON (2U << 30) 99 #define IO_DPD_REQ_CODE_MASK (3U << 30) 100 101 #define IO_DPD_STATUS 0x1bc 102 #define IO_DPD2_REQ 0x1c0 103 #define IO_DPD2_STATUS 0x1c4 104 #define SEL_DPD_TIM 0x1c8 105 106 #define PMC_SCRATCH54 0x258 107 #define PMC_SCRATCH54_DATA_SHIFT 8 108 #define PMC_SCRATCH54_ADDR_SHIFT 0 109 110 #define PMC_SCRATCH55 0x25c 111 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 112 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 113 #define PMC_SCRATCH55_PINMUX_SHIFT 24 114 #define PMC_SCRATCH55_16BITOP BIT(15) 115 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 116 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 117 118 #define GPU_RG_CNTRL 0x2d4 119 120 /* Tegra186 and later */ 121 #define WAKE_AOWAKE_CTRL 0x4f4 122 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 123 124 struct tegra_powergate { 125 struct generic_pm_domain genpd; 126 struct tegra_pmc *pmc; 127 unsigned int id; 128 struct clk **clks; 129 unsigned int num_clks; 130 struct reset_control *reset; 131 }; 132 133 struct tegra_io_pad_soc { 134 enum tegra_io_pad id; 135 unsigned int dpd; 136 unsigned int voltage; 137 }; 138 139 struct tegra_pmc_regs { 140 unsigned int scratch0; 141 unsigned int dpd_req; 142 unsigned int dpd_status; 143 unsigned int dpd2_req; 144 unsigned int dpd2_status; 145 }; 146 147 struct tegra_pmc_soc { 148 unsigned int num_powergates; 149 const char *const *powergates; 150 unsigned int num_cpu_powergates; 151 const u8 *cpu_powergates; 152 153 bool has_tsense_reset; 154 bool has_gpu_clamps; 155 bool needs_mbist_war; 156 157 const struct tegra_io_pad_soc *io_pads; 158 unsigned int num_io_pads; 159 160 const struct tegra_pmc_regs *regs; 161 void (*init)(struct tegra_pmc *pmc); 162 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 163 struct device_node *np, 164 bool invert); 165 }; 166 167 /** 168 * struct tegra_pmc - NVIDIA Tegra PMC 169 * @dev: pointer to PMC device structure 170 * @base: pointer to I/O remapped register region 171 * @clk: pointer to pclk clock 172 * @soc: pointer to SoC data structure 173 * @debugfs: pointer to debugfs entry 174 * @rate: currently configured rate of pclk 175 * @suspend_mode: lowest suspend mode available 176 * @cpu_good_time: CPU power good time (in microseconds) 177 * @cpu_off_time: CPU power off time (in microsecends) 178 * @core_osc_time: core power good OSC time (in microseconds) 179 * @core_pmu_time: core power good PMU time (in microseconds) 180 * @core_off_time: core power off time (in microseconds) 181 * @corereq_high: core power request is active-high 182 * @sysclkreq_high: system clock request is active-high 183 * @combined_req: combined power request for CPU & core 184 * @cpu_pwr_good_en: CPU power good signal is enabled 185 * @lp0_vec_phys: physical base address of the LP0 warm boot code 186 * @lp0_vec_size: size of the LP0 warm boot code 187 * @powergates_available: Bitmap of available power gates 188 * @powergates_lock: mutex for power gate register access 189 */ 190 struct tegra_pmc { 191 struct device *dev; 192 void __iomem *base; 193 void __iomem *wake; 194 void __iomem *aotag; 195 void __iomem *scratch; 196 struct clk *clk; 197 struct dentry *debugfs; 198 199 const struct tegra_pmc_soc *soc; 200 201 unsigned long rate; 202 203 enum tegra_suspend_mode suspend_mode; 204 u32 cpu_good_time; 205 u32 cpu_off_time; 206 u32 core_osc_time; 207 u32 core_pmu_time; 208 u32 core_off_time; 209 bool corereq_high; 210 bool sysclkreq_high; 211 bool combined_req; 212 bool cpu_pwr_good_en; 213 u32 lp0_vec_phys; 214 u32 lp0_vec_size; 215 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 216 217 struct mutex powergates_lock; 218 }; 219 220 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 221 .base = NULL, 222 .suspend_mode = TEGRA_SUSPEND_NONE, 223 }; 224 225 static inline struct tegra_powergate * 226 to_powergate(struct generic_pm_domain *domain) 227 { 228 return container_of(domain, struct tegra_powergate, genpd); 229 } 230 231 static u32 tegra_pmc_readl(unsigned long offset) 232 { 233 return readl(pmc->base + offset); 234 } 235 236 static void tegra_pmc_writel(u32 value, unsigned long offset) 237 { 238 writel(value, pmc->base + offset); 239 } 240 241 static inline bool tegra_powergate_state(int id) 242 { 243 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 244 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; 245 else 246 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 247 } 248 249 static inline bool tegra_powergate_is_valid(int id) 250 { 251 return (pmc->soc && pmc->soc->powergates[id]); 252 } 253 254 static inline bool tegra_powergate_is_available(int id) 255 { 256 return test_bit(id, pmc->powergates_available); 257 } 258 259 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 260 { 261 unsigned int i; 262 263 if (!pmc || !pmc->soc || !name) 264 return -EINVAL; 265 266 for (i = 0; i < pmc->soc->num_powergates; i++) { 267 if (!tegra_powergate_is_valid(i)) 268 continue; 269 270 if (!strcmp(name, pmc->soc->powergates[i])) 271 return i; 272 } 273 274 return -ENODEV; 275 } 276 277 /** 278 * tegra_powergate_set() - set the state of a partition 279 * @id: partition ID 280 * @new_state: new state of the partition 281 */ 282 static int tegra_powergate_set(unsigned int id, bool new_state) 283 { 284 bool status; 285 int err; 286 287 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 288 return -EINVAL; 289 290 mutex_lock(&pmc->powergates_lock); 291 292 if (tegra_powergate_state(id) == new_state) { 293 mutex_unlock(&pmc->powergates_lock); 294 return 0; 295 } 296 297 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 298 299 err = readx_poll_timeout(tegra_powergate_state, id, status, 300 status == new_state, 10, 100000); 301 302 mutex_unlock(&pmc->powergates_lock); 303 304 return err; 305 } 306 307 static int __tegra_powergate_remove_clamping(unsigned int id) 308 { 309 u32 mask; 310 311 mutex_lock(&pmc->powergates_lock); 312 313 /* 314 * On Tegra124 and later, the clamps for the GPU are controlled by a 315 * separate register (with different semantics). 316 */ 317 if (id == TEGRA_POWERGATE_3D) { 318 if (pmc->soc->has_gpu_clamps) { 319 tegra_pmc_writel(0, GPU_RG_CNTRL); 320 goto out; 321 } 322 } 323 324 /* 325 * Tegra 2 has a bug where PCIE and VDE clamping masks are 326 * swapped relatively to the partition ids 327 */ 328 if (id == TEGRA_POWERGATE_VDEC) 329 mask = (1 << TEGRA_POWERGATE_PCIE); 330 else if (id == TEGRA_POWERGATE_PCIE) 331 mask = (1 << TEGRA_POWERGATE_VDEC); 332 else 333 mask = (1 << id); 334 335 tegra_pmc_writel(mask, REMOVE_CLAMPING); 336 337 out: 338 mutex_unlock(&pmc->powergates_lock); 339 340 return 0; 341 } 342 343 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 344 { 345 unsigned int i; 346 347 for (i = 0; i < pg->num_clks; i++) 348 clk_disable_unprepare(pg->clks[i]); 349 } 350 351 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 352 { 353 unsigned int i; 354 int err; 355 356 for (i = 0; i < pg->num_clks; i++) { 357 err = clk_prepare_enable(pg->clks[i]); 358 if (err) 359 goto out; 360 } 361 362 return 0; 363 364 out: 365 while (i--) 366 clk_disable_unprepare(pg->clks[i]); 367 368 return err; 369 } 370 371 int __weak tegra210_clk_handle_mbist_war(unsigned int id) 372 { 373 return 0; 374 } 375 376 static int tegra_powergate_power_up(struct tegra_powergate *pg, 377 bool disable_clocks) 378 { 379 int err; 380 381 err = reset_control_assert(pg->reset); 382 if (err) 383 return err; 384 385 usleep_range(10, 20); 386 387 err = tegra_powergate_set(pg->id, true); 388 if (err < 0) 389 return err; 390 391 usleep_range(10, 20); 392 393 err = tegra_powergate_enable_clocks(pg); 394 if (err) 395 goto disable_clks; 396 397 usleep_range(10, 20); 398 399 err = __tegra_powergate_remove_clamping(pg->id); 400 if (err) 401 goto disable_clks; 402 403 usleep_range(10, 20); 404 405 err = reset_control_deassert(pg->reset); 406 if (err) 407 goto powergate_off; 408 409 usleep_range(10, 20); 410 411 if (pg->pmc->soc->needs_mbist_war) 412 err = tegra210_clk_handle_mbist_war(pg->id); 413 if (err) 414 goto disable_clks; 415 416 if (disable_clocks) 417 tegra_powergate_disable_clocks(pg); 418 419 return 0; 420 421 disable_clks: 422 tegra_powergate_disable_clocks(pg); 423 usleep_range(10, 20); 424 425 powergate_off: 426 tegra_powergate_set(pg->id, false); 427 428 return err; 429 } 430 431 static int tegra_powergate_power_down(struct tegra_powergate *pg) 432 { 433 int err; 434 435 err = tegra_powergate_enable_clocks(pg); 436 if (err) 437 return err; 438 439 usleep_range(10, 20); 440 441 err = reset_control_assert(pg->reset); 442 if (err) 443 goto disable_clks; 444 445 usleep_range(10, 20); 446 447 tegra_powergate_disable_clocks(pg); 448 449 usleep_range(10, 20); 450 451 err = tegra_powergate_set(pg->id, false); 452 if (err) 453 goto assert_resets; 454 455 return 0; 456 457 assert_resets: 458 tegra_powergate_enable_clocks(pg); 459 usleep_range(10, 20); 460 reset_control_deassert(pg->reset); 461 usleep_range(10, 20); 462 463 disable_clks: 464 tegra_powergate_disable_clocks(pg); 465 466 return err; 467 } 468 469 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 470 { 471 struct tegra_powergate *pg = to_powergate(domain); 472 int err; 473 474 err = tegra_powergate_power_up(pg, true); 475 if (err) 476 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name, 477 err); 478 479 return err; 480 } 481 482 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 483 { 484 struct tegra_powergate *pg = to_powergate(domain); 485 int err; 486 487 err = tegra_powergate_power_down(pg); 488 if (err) 489 pr_err("failed to turn off PM domain %s: %d\n", 490 pg->genpd.name, err); 491 492 return err; 493 } 494 495 /** 496 * tegra_powergate_power_on() - power on partition 497 * @id: partition ID 498 */ 499 int tegra_powergate_power_on(unsigned int id) 500 { 501 if (!tegra_powergate_is_available(id)) 502 return -EINVAL; 503 504 return tegra_powergate_set(id, true); 505 } 506 507 /** 508 * tegra_powergate_power_off() - power off partition 509 * @id: partition ID 510 */ 511 int tegra_powergate_power_off(unsigned int id) 512 { 513 if (!tegra_powergate_is_available(id)) 514 return -EINVAL; 515 516 return tegra_powergate_set(id, false); 517 } 518 EXPORT_SYMBOL(tegra_powergate_power_off); 519 520 /** 521 * tegra_powergate_is_powered() - check if partition is powered 522 * @id: partition ID 523 */ 524 int tegra_powergate_is_powered(unsigned int id) 525 { 526 int status; 527 528 if (!tegra_powergate_is_valid(id)) 529 return -EINVAL; 530 531 mutex_lock(&pmc->powergates_lock); 532 status = tegra_powergate_state(id); 533 mutex_unlock(&pmc->powergates_lock); 534 535 return status; 536 } 537 538 /** 539 * tegra_powergate_remove_clamping() - remove power clamps for partition 540 * @id: partition ID 541 */ 542 int tegra_powergate_remove_clamping(unsigned int id) 543 { 544 if (!tegra_powergate_is_available(id)) 545 return -EINVAL; 546 547 return __tegra_powergate_remove_clamping(id); 548 } 549 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 550 551 /** 552 * tegra_powergate_sequence_power_up() - power up partition 553 * @id: partition ID 554 * @clk: clock for partition 555 * @rst: reset for partition 556 * 557 * Must be called with clk disabled, and returns with clk enabled. 558 */ 559 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 560 struct reset_control *rst) 561 { 562 struct tegra_powergate pg; 563 int err; 564 565 if (!tegra_powergate_is_available(id)) 566 return -EINVAL; 567 568 pg.id = id; 569 pg.clks = &clk; 570 pg.num_clks = 1; 571 pg.reset = rst; 572 pg.pmc = pmc; 573 574 err = tegra_powergate_power_up(&pg, false); 575 if (err) 576 pr_err("failed to turn on partition %d: %d\n", id, err); 577 578 return err; 579 } 580 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 581 582 #ifdef CONFIG_SMP 583 /** 584 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 585 * @cpuid: CPU partition ID 586 * 587 * Returns the partition ID corresponding to the CPU partition ID or a 588 * negative error code on failure. 589 */ 590 static int tegra_get_cpu_powergate_id(unsigned int cpuid) 591 { 592 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 593 return pmc->soc->cpu_powergates[cpuid]; 594 595 return -EINVAL; 596 } 597 598 /** 599 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 600 * @cpuid: CPU partition ID 601 */ 602 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 603 { 604 int id; 605 606 id = tegra_get_cpu_powergate_id(cpuid); 607 if (id < 0) 608 return false; 609 610 return tegra_powergate_is_powered(id); 611 } 612 613 /** 614 * tegra_pmc_cpu_power_on() - power on CPU partition 615 * @cpuid: CPU partition ID 616 */ 617 int tegra_pmc_cpu_power_on(unsigned int cpuid) 618 { 619 int id; 620 621 id = tegra_get_cpu_powergate_id(cpuid); 622 if (id < 0) 623 return id; 624 625 return tegra_powergate_set(id, true); 626 } 627 628 /** 629 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 630 * @cpuid: CPU partition ID 631 */ 632 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 633 { 634 int id; 635 636 id = tegra_get_cpu_powergate_id(cpuid); 637 if (id < 0) 638 return id; 639 640 return tegra_powergate_remove_clamping(id); 641 } 642 #endif /* CONFIG_SMP */ 643 644 static int tegra_pmc_restart_notify(struct notifier_block *this, 645 unsigned long action, void *data) 646 { 647 const char *cmd = data; 648 u32 value; 649 650 value = readl(pmc->scratch + pmc->soc->regs->scratch0); 651 value &= ~PMC_SCRATCH0_MODE_MASK; 652 653 if (cmd) { 654 if (strcmp(cmd, "recovery") == 0) 655 value |= PMC_SCRATCH0_MODE_RECOVERY; 656 657 if (strcmp(cmd, "bootloader") == 0) 658 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 659 660 if (strcmp(cmd, "forced-recovery") == 0) 661 value |= PMC_SCRATCH0_MODE_RCM; 662 } 663 664 writel(value, pmc->scratch + pmc->soc->regs->scratch0); 665 666 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 667 value = tegra_pmc_readl(PMC_CNTRL); 668 value |= PMC_CNTRL_MAIN_RST; 669 tegra_pmc_writel(value, PMC_CNTRL); 670 671 return NOTIFY_DONE; 672 } 673 674 static struct notifier_block tegra_pmc_restart_handler = { 675 .notifier_call = tegra_pmc_restart_notify, 676 .priority = 128, 677 }; 678 679 static int powergate_show(struct seq_file *s, void *data) 680 { 681 unsigned int i; 682 int status; 683 684 seq_printf(s, " powergate powered\n"); 685 seq_printf(s, "------------------\n"); 686 687 for (i = 0; i < pmc->soc->num_powergates; i++) { 688 status = tegra_powergate_is_powered(i); 689 if (status < 0) 690 continue; 691 692 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 693 status ? "yes" : "no"); 694 } 695 696 return 0; 697 } 698 699 static int powergate_open(struct inode *inode, struct file *file) 700 { 701 return single_open(file, powergate_show, inode->i_private); 702 } 703 704 static const struct file_operations powergate_fops = { 705 .open = powergate_open, 706 .read = seq_read, 707 .llseek = seq_lseek, 708 .release = single_release, 709 }; 710 711 static int tegra_powergate_debugfs_init(void) 712 { 713 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 714 &powergate_fops); 715 if (!pmc->debugfs) 716 return -ENOMEM; 717 718 return 0; 719 } 720 721 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 722 struct device_node *np) 723 { 724 struct clk *clk; 725 unsigned int i, count; 726 int err; 727 728 count = of_count_phandle_with_args(np, "clocks", "#clock-cells"); 729 if (count == 0) 730 return -ENODEV; 731 732 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 733 if (!pg->clks) 734 return -ENOMEM; 735 736 for (i = 0; i < count; i++) { 737 pg->clks[i] = of_clk_get(np, i); 738 if (IS_ERR(pg->clks[i])) { 739 err = PTR_ERR(pg->clks[i]); 740 goto err; 741 } 742 } 743 744 pg->num_clks = count; 745 746 return 0; 747 748 err: 749 while (i--) 750 clk_put(pg->clks[i]); 751 752 kfree(pg->clks); 753 754 return err; 755 } 756 757 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 758 struct device_node *np, bool off) 759 { 760 int err; 761 762 pg->reset = of_reset_control_array_get_exclusive(np); 763 if (IS_ERR(pg->reset)) { 764 err = PTR_ERR(pg->reset); 765 pr_err("failed to get device resets: %d\n", err); 766 return err; 767 } 768 769 if (off) 770 err = reset_control_assert(pg->reset); 771 else 772 err = reset_control_deassert(pg->reset); 773 774 if (err) 775 reset_control_put(pg->reset); 776 777 return err; 778 } 779 780 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 781 { 782 struct tegra_powergate *pg; 783 int id, err; 784 bool off; 785 786 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 787 if (!pg) 788 return; 789 790 id = tegra_powergate_lookup(pmc, np->name); 791 if (id < 0) { 792 pr_err("powergate lookup failed for %s: %d\n", np->name, id); 793 goto free_mem; 794 } 795 796 /* 797 * Clear the bit for this powergate so it cannot be managed 798 * directly via the legacy APIs for controlling powergates. 799 */ 800 clear_bit(id, pmc->powergates_available); 801 802 pg->id = id; 803 pg->genpd.name = np->name; 804 pg->genpd.power_off = tegra_genpd_power_off; 805 pg->genpd.power_on = tegra_genpd_power_on; 806 pg->pmc = pmc; 807 808 off = !tegra_powergate_is_powered(pg->id); 809 810 err = tegra_powergate_of_get_clks(pg, np); 811 if (err < 0) { 812 pr_err("failed to get clocks for %s: %d\n", np->name, err); 813 goto set_available; 814 } 815 816 err = tegra_powergate_of_get_resets(pg, np, off); 817 if (err < 0) { 818 pr_err("failed to get resets for %s: %d\n", np->name, err); 819 goto remove_clks; 820 } 821 822 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 823 if (off) 824 WARN_ON(tegra_powergate_power_up(pg, true)); 825 826 goto remove_resets; 827 } 828 829 /* 830 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB 831 * host and super-speed partitions. Once the XHCI driver 832 * manages the partitions itself this code can be removed. Note 833 * that we don't register these partitions with the genpd core 834 * to avoid it from powering down the partitions as they appear 835 * to be unused. 836 */ 837 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) && 838 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) { 839 if (off) 840 WARN_ON(tegra_powergate_power_up(pg, true)); 841 842 goto remove_resets; 843 } 844 845 err = pm_genpd_init(&pg->genpd, NULL, off); 846 if (err < 0) { 847 pr_err("failed to initialise PM domain %s: %d\n", np->name, 848 err); 849 goto remove_resets; 850 } 851 852 err = of_genpd_add_provider_simple(np, &pg->genpd); 853 if (err < 0) { 854 pr_err("failed to add PM domain provider for %s: %d\n", 855 np->name, err); 856 goto remove_genpd; 857 } 858 859 pr_debug("added PM domain %s\n", pg->genpd.name); 860 861 return; 862 863 remove_genpd: 864 pm_genpd_remove(&pg->genpd); 865 866 remove_resets: 867 reset_control_put(pg->reset); 868 869 remove_clks: 870 while (pg->num_clks--) 871 clk_put(pg->clks[pg->num_clks]); 872 873 kfree(pg->clks); 874 875 set_available: 876 set_bit(id, pmc->powergates_available); 877 878 free_mem: 879 kfree(pg); 880 } 881 882 static void tegra_powergate_init(struct tegra_pmc *pmc, 883 struct device_node *parent) 884 { 885 struct device_node *np, *child; 886 unsigned int i; 887 888 /* Create a bitmap of the available and valid partitions */ 889 for (i = 0; i < pmc->soc->num_powergates; i++) 890 if (pmc->soc->powergates[i]) 891 set_bit(i, pmc->powergates_available); 892 893 np = of_get_child_by_name(parent, "powergates"); 894 if (!np) 895 return; 896 897 for_each_child_of_node(np, child) 898 tegra_powergate_add(pmc, child); 899 900 of_node_put(np); 901 } 902 903 static const struct tegra_io_pad_soc * 904 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 905 { 906 unsigned int i; 907 908 for (i = 0; i < pmc->soc->num_io_pads; i++) 909 if (pmc->soc->io_pads[i].id == id) 910 return &pmc->soc->io_pads[i]; 911 912 return NULL; 913 } 914 915 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, 916 unsigned long *status, u32 *mask) 917 { 918 const struct tegra_io_pad_soc *pad; 919 unsigned long rate, value; 920 921 pad = tegra_io_pad_find(pmc, id); 922 if (!pad) { 923 pr_err("invalid I/O pad ID %u\n", id); 924 return -ENOENT; 925 } 926 927 if (pad->dpd == UINT_MAX) 928 return -ENOTSUPP; 929 930 *mask = BIT(pad->dpd % 32); 931 932 if (pad->dpd < 32) { 933 *status = pmc->soc->regs->dpd_status; 934 *request = pmc->soc->regs->dpd_req; 935 } else { 936 *status = pmc->soc->regs->dpd2_status; 937 *request = pmc->soc->regs->dpd2_req; 938 } 939 940 if (pmc->clk) { 941 rate = clk_get_rate(pmc->clk); 942 if (!rate) { 943 pr_err("failed to get clock rate\n"); 944 return -ENODEV; 945 } 946 947 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 948 949 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 950 value = DIV_ROUND_UP(1000000000, rate); 951 value = DIV_ROUND_UP(200, value); 952 tegra_pmc_writel(value, SEL_DPD_TIM); 953 } 954 955 return 0; 956 } 957 958 static int tegra_io_pad_poll(unsigned long offset, u32 mask, 959 u32 val, unsigned long timeout) 960 { 961 u32 value; 962 963 timeout = jiffies + msecs_to_jiffies(timeout); 964 965 while (time_after(timeout, jiffies)) { 966 value = tegra_pmc_readl(offset); 967 if ((value & mask) == val) 968 return 0; 969 970 usleep_range(250, 1000); 971 } 972 973 return -ETIMEDOUT; 974 } 975 976 static void tegra_io_pad_unprepare(void) 977 { 978 if (pmc->clk) 979 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 980 } 981 982 /** 983 * tegra_io_pad_power_enable() - enable power to I/O pad 984 * @id: Tegra I/O pad ID for which to enable power 985 * 986 * Returns: 0 on success or a negative error code on failure. 987 */ 988 int tegra_io_pad_power_enable(enum tegra_io_pad id) 989 { 990 unsigned long request, status; 991 u32 mask; 992 int err; 993 994 mutex_lock(&pmc->powergates_lock); 995 996 err = tegra_io_pad_prepare(id, &request, &status, &mask); 997 if (err < 0) { 998 pr_err("failed to prepare I/O pad: %d\n", err); 999 goto unlock; 1000 } 1001 1002 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request); 1003 1004 err = tegra_io_pad_poll(status, mask, 0, 250); 1005 if (err < 0) { 1006 pr_err("failed to enable I/O pad: %d\n", err); 1007 goto unlock; 1008 } 1009 1010 tegra_io_pad_unprepare(); 1011 1012 unlock: 1013 mutex_unlock(&pmc->powergates_lock); 1014 return err; 1015 } 1016 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1017 1018 /** 1019 * tegra_io_pad_power_disable() - disable power to I/O pad 1020 * @id: Tegra I/O pad ID for which to disable power 1021 * 1022 * Returns: 0 on success or a negative error code on failure. 1023 */ 1024 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1025 { 1026 unsigned long request, status; 1027 u32 mask; 1028 int err; 1029 1030 mutex_lock(&pmc->powergates_lock); 1031 1032 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1033 if (err < 0) { 1034 pr_err("failed to prepare I/O pad: %d\n", err); 1035 goto unlock; 1036 } 1037 1038 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request); 1039 1040 err = tegra_io_pad_poll(status, mask, mask, 250); 1041 if (err < 0) { 1042 pr_err("failed to disable I/O pad: %d\n", err); 1043 goto unlock; 1044 } 1045 1046 tegra_io_pad_unprepare(); 1047 1048 unlock: 1049 mutex_unlock(&pmc->powergates_lock); 1050 return err; 1051 } 1052 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1053 1054 int tegra_io_pad_set_voltage(enum tegra_io_pad id, 1055 enum tegra_io_pad_voltage voltage) 1056 { 1057 const struct tegra_io_pad_soc *pad; 1058 u32 value; 1059 1060 pad = tegra_io_pad_find(pmc, id); 1061 if (!pad) 1062 return -ENOENT; 1063 1064 if (pad->voltage == UINT_MAX) 1065 return -ENOTSUPP; 1066 1067 mutex_lock(&pmc->powergates_lock); 1068 1069 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1070 value = tegra_pmc_readl(PMC_PWR_DET); 1071 value |= BIT(pad->voltage); 1072 tegra_pmc_writel(value, PMC_PWR_DET); 1073 1074 /* update I/O voltage */ 1075 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1076 1077 if (voltage == TEGRA_IO_PAD_1800000UV) 1078 value &= ~BIT(pad->voltage); 1079 else 1080 value |= BIT(pad->voltage); 1081 1082 tegra_pmc_writel(value, PMC_PWR_DET_VALUE); 1083 1084 mutex_unlock(&pmc->powergates_lock); 1085 1086 usleep_range(100, 250); 1087 1088 return 0; 1089 } 1090 EXPORT_SYMBOL(tegra_io_pad_set_voltage); 1091 1092 int tegra_io_pad_get_voltage(enum tegra_io_pad id) 1093 { 1094 const struct tegra_io_pad_soc *pad; 1095 u32 value; 1096 1097 pad = tegra_io_pad_find(pmc, id); 1098 if (!pad) 1099 return -ENOENT; 1100 1101 if (pad->voltage == UINT_MAX) 1102 return -ENOTSUPP; 1103 1104 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1105 1106 if ((value & BIT(pad->voltage)) == 0) 1107 return TEGRA_IO_PAD_1800000UV; 1108 1109 return TEGRA_IO_PAD_3300000UV; 1110 } 1111 EXPORT_SYMBOL(tegra_io_pad_get_voltage); 1112 1113 /** 1114 * tegra_io_rail_power_on() - enable power to I/O rail 1115 * @id: Tegra I/O pad ID for which to enable power 1116 * 1117 * See also: tegra_io_pad_power_enable() 1118 */ 1119 int tegra_io_rail_power_on(unsigned int id) 1120 { 1121 return tegra_io_pad_power_enable(id); 1122 } 1123 EXPORT_SYMBOL(tegra_io_rail_power_on); 1124 1125 /** 1126 * tegra_io_rail_power_off() - disable power to I/O rail 1127 * @id: Tegra I/O pad ID for which to disable power 1128 * 1129 * See also: tegra_io_pad_power_disable() 1130 */ 1131 int tegra_io_rail_power_off(unsigned int id) 1132 { 1133 return tegra_io_pad_power_disable(id); 1134 } 1135 EXPORT_SYMBOL(tegra_io_rail_power_off); 1136 1137 #ifdef CONFIG_PM_SLEEP 1138 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1139 { 1140 return pmc->suspend_mode; 1141 } 1142 1143 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1144 { 1145 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1146 return; 1147 1148 pmc->suspend_mode = mode; 1149 } 1150 1151 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1152 { 1153 unsigned long long rate = 0; 1154 u32 value; 1155 1156 switch (mode) { 1157 case TEGRA_SUSPEND_LP1: 1158 rate = 32768; 1159 break; 1160 1161 case TEGRA_SUSPEND_LP2: 1162 rate = clk_get_rate(pmc->clk); 1163 break; 1164 1165 default: 1166 break; 1167 } 1168 1169 if (WARN_ON_ONCE(rate == 0)) 1170 rate = 100000000; 1171 1172 if (rate != pmc->rate) { 1173 u64 ticks; 1174 1175 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1176 do_div(ticks, USEC_PER_SEC); 1177 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 1178 1179 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1180 do_div(ticks, USEC_PER_SEC); 1181 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 1182 1183 wmb(); 1184 1185 pmc->rate = rate; 1186 } 1187 1188 value = tegra_pmc_readl(PMC_CNTRL); 1189 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1190 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1191 tegra_pmc_writel(value, PMC_CNTRL); 1192 } 1193 #endif 1194 1195 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1196 { 1197 u32 value, values[2]; 1198 1199 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1200 } else { 1201 switch (value) { 1202 case 0: 1203 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1204 break; 1205 1206 case 1: 1207 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1208 break; 1209 1210 case 2: 1211 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1212 break; 1213 1214 default: 1215 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1216 break; 1217 } 1218 } 1219 1220 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1221 1222 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1223 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1224 1225 pmc->cpu_good_time = value; 1226 1227 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1228 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1229 1230 pmc->cpu_off_time = value; 1231 1232 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1233 values, ARRAY_SIZE(values))) 1234 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1235 1236 pmc->core_osc_time = values[0]; 1237 pmc->core_pmu_time = values[1]; 1238 1239 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1240 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1241 1242 pmc->core_off_time = value; 1243 1244 pmc->corereq_high = of_property_read_bool(np, 1245 "nvidia,core-power-req-active-high"); 1246 1247 pmc->sysclkreq_high = of_property_read_bool(np, 1248 "nvidia,sys-clock-req-active-high"); 1249 1250 pmc->combined_req = of_property_read_bool(np, 1251 "nvidia,combined-power-req"); 1252 1253 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1254 "nvidia,cpu-pwr-good-en"); 1255 1256 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1257 ARRAY_SIZE(values))) 1258 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1259 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1260 1261 pmc->lp0_vec_phys = values[0]; 1262 pmc->lp0_vec_size = values[1]; 1263 1264 return 0; 1265 } 1266 1267 static void tegra_pmc_init(struct tegra_pmc *pmc) 1268 { 1269 if (pmc->soc->init) 1270 pmc->soc->init(pmc); 1271 } 1272 1273 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1274 { 1275 static const char disabled[] = "emergency thermal reset disabled"; 1276 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1277 struct device *dev = pmc->dev; 1278 struct device_node *np; 1279 u32 value, checksum; 1280 1281 if (!pmc->soc->has_tsense_reset) 1282 return; 1283 1284 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1285 if (!np) { 1286 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1287 return; 1288 } 1289 1290 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1291 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1292 goto out; 1293 } 1294 1295 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1296 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1297 goto out; 1298 } 1299 1300 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1301 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1302 goto out; 1303 } 1304 1305 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1306 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1307 goto out; 1308 } 1309 1310 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1311 pinmux = 0; 1312 1313 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1314 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1315 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1316 1317 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1318 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1319 tegra_pmc_writel(value, PMC_SCRATCH54); 1320 1321 value = PMC_SCRATCH55_RESET_TEGRA; 1322 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1323 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1324 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1325 1326 /* 1327 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1328 * contain the checksum and are currently zero, so they are not added. 1329 */ 1330 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1331 + ((value >> 24) & 0xff); 1332 checksum &= 0xff; 1333 checksum = 0x100 - checksum; 1334 1335 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1336 1337 tegra_pmc_writel(value, PMC_SCRATCH55); 1338 1339 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1340 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1341 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1342 1343 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1344 1345 out: 1346 of_node_put(np); 1347 } 1348 1349 static int tegra_pmc_probe(struct platform_device *pdev) 1350 { 1351 void __iomem *base; 1352 struct resource *res; 1353 int err; 1354 1355 /* 1356 * Early initialisation should have configured an initial 1357 * register mapping and setup the soc data pointer. If these 1358 * are not valid then something went badly wrong! 1359 */ 1360 if (WARN_ON(!pmc->base || !pmc->soc)) 1361 return -ENODEV; 1362 1363 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1364 if (err < 0) 1365 return err; 1366 1367 /* take over the memory region from the early initialization */ 1368 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1369 base = devm_ioremap_resource(&pdev->dev, res); 1370 if (IS_ERR(base)) 1371 return PTR_ERR(base); 1372 1373 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 1374 if (res) { 1375 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 1376 if (IS_ERR(pmc->wake)) 1377 return PTR_ERR(pmc->wake); 1378 } else { 1379 pmc->wake = base; 1380 } 1381 1382 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 1383 if (res) { 1384 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 1385 if (IS_ERR(pmc->aotag)) 1386 return PTR_ERR(pmc->aotag); 1387 } else { 1388 pmc->aotag = base; 1389 } 1390 1391 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 1392 if (res) { 1393 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 1394 if (IS_ERR(pmc->scratch)) 1395 return PTR_ERR(pmc->scratch); 1396 } else { 1397 pmc->scratch = base; 1398 } 1399 1400 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1401 if (IS_ERR(pmc->clk)) { 1402 err = PTR_ERR(pmc->clk); 1403 1404 if (err != -ENOENT) { 1405 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1406 return err; 1407 } 1408 1409 pmc->clk = NULL; 1410 } 1411 1412 pmc->dev = &pdev->dev; 1413 1414 tegra_pmc_init(pmc); 1415 1416 tegra_pmc_init_tsense_reset(pmc); 1417 1418 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1419 err = tegra_powergate_debugfs_init(); 1420 if (err < 0) 1421 return err; 1422 } 1423 1424 err = register_restart_handler(&tegra_pmc_restart_handler); 1425 if (err) { 1426 debugfs_remove(pmc->debugfs); 1427 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 1428 err); 1429 return err; 1430 } 1431 1432 mutex_lock(&pmc->powergates_lock); 1433 iounmap(pmc->base); 1434 pmc->base = base; 1435 mutex_unlock(&pmc->powergates_lock); 1436 1437 return 0; 1438 } 1439 1440 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1441 static int tegra_pmc_suspend(struct device *dev) 1442 { 1443 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 1444 1445 return 0; 1446 } 1447 1448 static int tegra_pmc_resume(struct device *dev) 1449 { 1450 tegra_pmc_writel(0x0, PMC_SCRATCH41); 1451 1452 return 0; 1453 } 1454 1455 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 1456 1457 #endif 1458 1459 static const char * const tegra20_powergates[] = { 1460 [TEGRA_POWERGATE_CPU] = "cpu", 1461 [TEGRA_POWERGATE_3D] = "3d", 1462 [TEGRA_POWERGATE_VENC] = "venc", 1463 [TEGRA_POWERGATE_VDEC] = "vdec", 1464 [TEGRA_POWERGATE_PCIE] = "pcie", 1465 [TEGRA_POWERGATE_L2] = "l2", 1466 [TEGRA_POWERGATE_MPE] = "mpe", 1467 }; 1468 1469 static const struct tegra_pmc_regs tegra20_pmc_regs = { 1470 .scratch0 = 0x50, 1471 .dpd_req = 0x1b8, 1472 .dpd_status = 0x1bc, 1473 .dpd2_req = 0x1c0, 1474 .dpd2_status = 0x1c4, 1475 }; 1476 1477 static void tegra20_pmc_init(struct tegra_pmc *pmc) 1478 { 1479 u32 value; 1480 1481 /* Always enable CPU power request */ 1482 value = tegra_pmc_readl(PMC_CNTRL); 1483 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1484 tegra_pmc_writel(value, PMC_CNTRL); 1485 1486 value = tegra_pmc_readl(PMC_CNTRL); 1487 1488 if (pmc->sysclkreq_high) 1489 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 1490 else 1491 value |= PMC_CNTRL_SYSCLK_POLARITY; 1492 1493 /* configure the output polarity while the request is tristated */ 1494 tegra_pmc_writel(value, PMC_CNTRL); 1495 1496 /* now enable the request */ 1497 value = tegra_pmc_readl(PMC_CNTRL); 1498 value |= PMC_CNTRL_SYSCLK_OE; 1499 tegra_pmc_writel(value, PMC_CNTRL); 1500 } 1501 1502 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1503 struct device_node *np, 1504 bool invert) 1505 { 1506 u32 value; 1507 1508 value = tegra_pmc_readl(PMC_CNTRL); 1509 1510 if (invert) 1511 value |= PMC_CNTRL_INTR_POLARITY; 1512 else 1513 value &= ~PMC_CNTRL_INTR_POLARITY; 1514 1515 tegra_pmc_writel(value, PMC_CNTRL); 1516 } 1517 1518 static const struct tegra_pmc_soc tegra20_pmc_soc = { 1519 .num_powergates = ARRAY_SIZE(tegra20_powergates), 1520 .powergates = tegra20_powergates, 1521 .num_cpu_powergates = 0, 1522 .cpu_powergates = NULL, 1523 .has_tsense_reset = false, 1524 .has_gpu_clamps = false, 1525 .num_io_pads = 0, 1526 .io_pads = NULL, 1527 .regs = &tegra20_pmc_regs, 1528 .init = tegra20_pmc_init, 1529 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1530 }; 1531 1532 static const char * const tegra30_powergates[] = { 1533 [TEGRA_POWERGATE_CPU] = "cpu0", 1534 [TEGRA_POWERGATE_3D] = "3d0", 1535 [TEGRA_POWERGATE_VENC] = "venc", 1536 [TEGRA_POWERGATE_VDEC] = "vdec", 1537 [TEGRA_POWERGATE_PCIE] = "pcie", 1538 [TEGRA_POWERGATE_L2] = "l2", 1539 [TEGRA_POWERGATE_MPE] = "mpe", 1540 [TEGRA_POWERGATE_HEG] = "heg", 1541 [TEGRA_POWERGATE_SATA] = "sata", 1542 [TEGRA_POWERGATE_CPU1] = "cpu1", 1543 [TEGRA_POWERGATE_CPU2] = "cpu2", 1544 [TEGRA_POWERGATE_CPU3] = "cpu3", 1545 [TEGRA_POWERGATE_CELP] = "celp", 1546 [TEGRA_POWERGATE_3D1] = "3d1", 1547 }; 1548 1549 static const u8 tegra30_cpu_powergates[] = { 1550 TEGRA_POWERGATE_CPU, 1551 TEGRA_POWERGATE_CPU1, 1552 TEGRA_POWERGATE_CPU2, 1553 TEGRA_POWERGATE_CPU3, 1554 }; 1555 1556 static const struct tegra_pmc_soc tegra30_pmc_soc = { 1557 .num_powergates = ARRAY_SIZE(tegra30_powergates), 1558 .powergates = tegra30_powergates, 1559 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 1560 .cpu_powergates = tegra30_cpu_powergates, 1561 .has_tsense_reset = true, 1562 .has_gpu_clamps = false, 1563 .num_io_pads = 0, 1564 .io_pads = NULL, 1565 .regs = &tegra20_pmc_regs, 1566 .init = tegra20_pmc_init, 1567 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1568 }; 1569 1570 static const char * const tegra114_powergates[] = { 1571 [TEGRA_POWERGATE_CPU] = "crail", 1572 [TEGRA_POWERGATE_3D] = "3d", 1573 [TEGRA_POWERGATE_VENC] = "venc", 1574 [TEGRA_POWERGATE_VDEC] = "vdec", 1575 [TEGRA_POWERGATE_MPE] = "mpe", 1576 [TEGRA_POWERGATE_HEG] = "heg", 1577 [TEGRA_POWERGATE_CPU1] = "cpu1", 1578 [TEGRA_POWERGATE_CPU2] = "cpu2", 1579 [TEGRA_POWERGATE_CPU3] = "cpu3", 1580 [TEGRA_POWERGATE_CELP] = "celp", 1581 [TEGRA_POWERGATE_CPU0] = "cpu0", 1582 [TEGRA_POWERGATE_C0NC] = "c0nc", 1583 [TEGRA_POWERGATE_C1NC] = "c1nc", 1584 [TEGRA_POWERGATE_DIS] = "dis", 1585 [TEGRA_POWERGATE_DISB] = "disb", 1586 [TEGRA_POWERGATE_XUSBA] = "xusba", 1587 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1588 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1589 }; 1590 1591 static const u8 tegra114_cpu_powergates[] = { 1592 TEGRA_POWERGATE_CPU0, 1593 TEGRA_POWERGATE_CPU1, 1594 TEGRA_POWERGATE_CPU2, 1595 TEGRA_POWERGATE_CPU3, 1596 }; 1597 1598 static const struct tegra_pmc_soc tegra114_pmc_soc = { 1599 .num_powergates = ARRAY_SIZE(tegra114_powergates), 1600 .powergates = tegra114_powergates, 1601 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 1602 .cpu_powergates = tegra114_cpu_powergates, 1603 .has_tsense_reset = true, 1604 .has_gpu_clamps = false, 1605 .num_io_pads = 0, 1606 .io_pads = NULL, 1607 .regs = &tegra20_pmc_regs, 1608 .init = tegra20_pmc_init, 1609 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1610 }; 1611 1612 static const char * const tegra124_powergates[] = { 1613 [TEGRA_POWERGATE_CPU] = "crail", 1614 [TEGRA_POWERGATE_3D] = "3d", 1615 [TEGRA_POWERGATE_VENC] = "venc", 1616 [TEGRA_POWERGATE_PCIE] = "pcie", 1617 [TEGRA_POWERGATE_VDEC] = "vdec", 1618 [TEGRA_POWERGATE_MPE] = "mpe", 1619 [TEGRA_POWERGATE_HEG] = "heg", 1620 [TEGRA_POWERGATE_SATA] = "sata", 1621 [TEGRA_POWERGATE_CPU1] = "cpu1", 1622 [TEGRA_POWERGATE_CPU2] = "cpu2", 1623 [TEGRA_POWERGATE_CPU3] = "cpu3", 1624 [TEGRA_POWERGATE_CELP] = "celp", 1625 [TEGRA_POWERGATE_CPU0] = "cpu0", 1626 [TEGRA_POWERGATE_C0NC] = "c0nc", 1627 [TEGRA_POWERGATE_C1NC] = "c1nc", 1628 [TEGRA_POWERGATE_SOR] = "sor", 1629 [TEGRA_POWERGATE_DIS] = "dis", 1630 [TEGRA_POWERGATE_DISB] = "disb", 1631 [TEGRA_POWERGATE_XUSBA] = "xusba", 1632 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1633 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1634 [TEGRA_POWERGATE_VIC] = "vic", 1635 [TEGRA_POWERGATE_IRAM] = "iram", 1636 }; 1637 1638 static const u8 tegra124_cpu_powergates[] = { 1639 TEGRA_POWERGATE_CPU0, 1640 TEGRA_POWERGATE_CPU1, 1641 TEGRA_POWERGATE_CPU2, 1642 TEGRA_POWERGATE_CPU3, 1643 }; 1644 1645 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 1646 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 1647 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX }, 1648 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX }, 1649 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX }, 1650 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1651 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1652 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, 1653 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1654 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, 1655 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, 1656 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, 1657 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, 1658 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1659 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX }, 1660 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, 1661 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1662 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX }, 1663 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1664 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, 1665 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1666 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 1667 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX }, 1668 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX }, 1669 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX }, 1670 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX }, 1671 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 1672 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1673 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1674 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1675 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1676 }; 1677 1678 static const struct tegra_pmc_soc tegra124_pmc_soc = { 1679 .num_powergates = ARRAY_SIZE(tegra124_powergates), 1680 .powergates = tegra124_powergates, 1681 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 1682 .cpu_powergates = tegra124_cpu_powergates, 1683 .has_tsense_reset = true, 1684 .has_gpu_clamps = true, 1685 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 1686 .io_pads = tegra124_io_pads, 1687 .regs = &tegra20_pmc_regs, 1688 .init = tegra20_pmc_init, 1689 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1690 }; 1691 1692 static const char * const tegra210_powergates[] = { 1693 [TEGRA_POWERGATE_CPU] = "crail", 1694 [TEGRA_POWERGATE_3D] = "3d", 1695 [TEGRA_POWERGATE_VENC] = "venc", 1696 [TEGRA_POWERGATE_PCIE] = "pcie", 1697 [TEGRA_POWERGATE_MPE] = "mpe", 1698 [TEGRA_POWERGATE_SATA] = "sata", 1699 [TEGRA_POWERGATE_CPU1] = "cpu1", 1700 [TEGRA_POWERGATE_CPU2] = "cpu2", 1701 [TEGRA_POWERGATE_CPU3] = "cpu3", 1702 [TEGRA_POWERGATE_CPU0] = "cpu0", 1703 [TEGRA_POWERGATE_C0NC] = "c0nc", 1704 [TEGRA_POWERGATE_SOR] = "sor", 1705 [TEGRA_POWERGATE_DIS] = "dis", 1706 [TEGRA_POWERGATE_DISB] = "disb", 1707 [TEGRA_POWERGATE_XUSBA] = "xusba", 1708 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1709 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1710 [TEGRA_POWERGATE_VIC] = "vic", 1711 [TEGRA_POWERGATE_IRAM] = "iram", 1712 [TEGRA_POWERGATE_NVDEC] = "nvdec", 1713 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 1714 [TEGRA_POWERGATE_AUD] = "aud", 1715 [TEGRA_POWERGATE_DFD] = "dfd", 1716 [TEGRA_POWERGATE_VE2] = "ve2", 1717 }; 1718 1719 static const u8 tegra210_cpu_powergates[] = { 1720 TEGRA_POWERGATE_CPU0, 1721 TEGRA_POWERGATE_CPU1, 1722 TEGRA_POWERGATE_CPU2, 1723 TEGRA_POWERGATE_CPU3, 1724 }; 1725 1726 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 1727 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 }, 1728 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 }, 1729 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 }, 1730 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1731 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1732 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX }, 1733 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX }, 1734 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, 1735 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX }, 1736 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 }, 1737 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX }, 1738 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 }, 1739 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX }, 1740 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1741 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, 1742 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, 1743 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, 1744 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX }, 1745 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX }, 1746 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 }, 1747 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, 1748 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1749 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, 1750 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1751 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1752 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, 1753 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1754 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 }, 1755 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 }, 1756 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 }, 1757 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 }, 1758 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 }, 1759 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 }, 1760 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1761 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1762 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1763 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX }, 1764 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1765 }; 1766 1767 static const struct tegra_pmc_soc tegra210_pmc_soc = { 1768 .num_powergates = ARRAY_SIZE(tegra210_powergates), 1769 .powergates = tegra210_powergates, 1770 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 1771 .cpu_powergates = tegra210_cpu_powergates, 1772 .has_tsense_reset = true, 1773 .has_gpu_clamps = true, 1774 .needs_mbist_war = true, 1775 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 1776 .io_pads = tegra210_io_pads, 1777 .regs = &tegra20_pmc_regs, 1778 .init = tegra20_pmc_init, 1779 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1780 }; 1781 1782 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 1783 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1784 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1785 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1786 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1787 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1788 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, 1789 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1790 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, 1791 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1792 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1793 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1794 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1795 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 1796 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 1797 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1798 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, 1799 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, 1800 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, 1801 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 1802 { .id = TEGRA_IO_PAD_SDMMC2_HV, .dpd = 34, .voltage = UINT_MAX }, 1803 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, 1804 { .id = TEGRA_IO_PAD_CAM, .dpd = 38, .voltage = UINT_MAX }, 1805 { .id = TEGRA_IO_PAD_DSIB, .dpd = 40, .voltage = UINT_MAX }, 1806 { .id = TEGRA_IO_PAD_DSIC, .dpd = 41, .voltage = UINT_MAX }, 1807 { .id = TEGRA_IO_PAD_DSID, .dpd = 42, .voltage = UINT_MAX }, 1808 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, 1809 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, 1810 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, 1811 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, 1812 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, 1813 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, 1814 { .id = TEGRA_IO_PAD_DMIC_HV, .dpd = 52, .voltage = UINT_MAX }, 1815 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, 1816 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, 1817 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, 1818 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, 1819 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, 1820 }; 1821 1822 static const struct tegra_pmc_regs tegra186_pmc_regs = { 1823 .scratch0 = 0x2000, 1824 .dpd_req = 0x74, 1825 .dpd_status = 0x78, 1826 .dpd2_req = 0x7c, 1827 .dpd2_status = 0x80, 1828 }; 1829 1830 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1831 struct device_node *np, 1832 bool invert) 1833 { 1834 struct resource regs; 1835 void __iomem *wake; 1836 u32 value; 1837 int index; 1838 1839 index = of_property_match_string(np, "reg-names", "wake"); 1840 if (index < 0) { 1841 pr_err("failed to find PMC wake registers\n"); 1842 return; 1843 } 1844 1845 of_address_to_resource(np, index, ®s); 1846 1847 wake = ioremap_nocache(regs.start, resource_size(®s)); 1848 if (!wake) { 1849 pr_err("failed to map PMC wake registers\n"); 1850 return; 1851 } 1852 1853 value = readl(wake + WAKE_AOWAKE_CTRL); 1854 1855 if (invert) 1856 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 1857 else 1858 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 1859 1860 writel(value, wake + WAKE_AOWAKE_CTRL); 1861 1862 iounmap(wake); 1863 } 1864 1865 static const struct tegra_pmc_soc tegra186_pmc_soc = { 1866 .num_powergates = 0, 1867 .powergates = NULL, 1868 .num_cpu_powergates = 0, 1869 .cpu_powergates = NULL, 1870 .has_tsense_reset = false, 1871 .has_gpu_clamps = false, 1872 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 1873 .io_pads = tegra186_io_pads, 1874 .regs = &tegra186_pmc_regs, 1875 .init = NULL, 1876 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 1877 }; 1878 1879 static const struct of_device_id tegra_pmc_match[] = { 1880 { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc }, 1881 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 1882 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 1883 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 1884 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 1885 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 1886 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 1887 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 1888 { } 1889 }; 1890 1891 static struct platform_driver tegra_pmc_driver = { 1892 .driver = { 1893 .name = "tegra-pmc", 1894 .suppress_bind_attrs = true, 1895 .of_match_table = tegra_pmc_match, 1896 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1897 .pm = &tegra_pmc_pm_ops, 1898 #endif 1899 }, 1900 .probe = tegra_pmc_probe, 1901 }; 1902 builtin_platform_driver(tegra_pmc_driver); 1903 1904 /* 1905 * Early initialization to allow access to registers in the very early boot 1906 * process. 1907 */ 1908 static int __init tegra_pmc_early_init(void) 1909 { 1910 const struct of_device_id *match; 1911 struct device_node *np; 1912 struct resource regs; 1913 bool invert; 1914 1915 mutex_init(&pmc->powergates_lock); 1916 1917 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 1918 if (!np) { 1919 /* 1920 * Fall back to legacy initialization for 32-bit ARM only. All 1921 * 64-bit ARM device tree files for Tegra are required to have 1922 * a PMC node. 1923 * 1924 * This is for backwards-compatibility with old device trees 1925 * that didn't contain a PMC node. Note that in this case the 1926 * SoC data can't be matched and therefore powergating is 1927 * disabled. 1928 */ 1929 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 1930 pr_warn("DT node not found, powergating disabled\n"); 1931 1932 regs.start = 0x7000e400; 1933 regs.end = 0x7000e7ff; 1934 regs.flags = IORESOURCE_MEM; 1935 1936 pr_warn("Using memory region %pR\n", ®s); 1937 } else { 1938 /* 1939 * At this point we're not running on Tegra, so play 1940 * nice with multi-platform kernels. 1941 */ 1942 return 0; 1943 } 1944 } else { 1945 /* 1946 * Extract information from the device tree if we've found a 1947 * matching node. 1948 */ 1949 if (of_address_to_resource(np, 0, ®s) < 0) { 1950 pr_err("failed to get PMC registers\n"); 1951 of_node_put(np); 1952 return -ENXIO; 1953 } 1954 } 1955 1956 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 1957 if (!pmc->base) { 1958 pr_err("failed to map PMC registers\n"); 1959 of_node_put(np); 1960 return -ENXIO; 1961 } 1962 1963 if (np) { 1964 pmc->soc = match->data; 1965 1966 tegra_powergate_init(pmc, np); 1967 1968 /* 1969 * Invert the interrupt polarity if a PMC device tree node 1970 * exists and contains the nvidia,invert-interrupt property. 1971 */ 1972 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 1973 1974 pmc->soc->setup_irq_polarity(pmc, np, invert); 1975 1976 of_node_put(np); 1977 } 1978 1979 return 0; 1980 } 1981 early_initcall(tegra_pmc_early_init); 1982