1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/arm-smccc.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 20 #include <linux/debugfs.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/io.h> 27 #include <linux/iopoll.h> 28 #include <linux/irqdomain.h> 29 #include <linux/irq.h> 30 #include <linux/kernel.h> 31 #include <linux/of_address.h> 32 #include <linux/of_clk.h> 33 #include <linux/of.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_platform.h> 36 #include <linux/pinctrl/pinconf-generic.h> 37 #include <linux/pinctrl/pinconf.h> 38 #include <linux/pinctrl/pinctrl.h> 39 #include <linux/platform_device.h> 40 #include <linux/pm_domain.h> 41 #include <linux/pm_opp.h> 42 #include <linux/reboot.h> 43 #include <linux/regmap.h> 44 #include <linux/reset.h> 45 #include <linux/seq_file.h> 46 #include <linux/slab.h> 47 #include <linux/spinlock.h> 48 49 #include <soc/tegra/common.h> 50 #include <soc/tegra/fuse.h> 51 #include <soc/tegra/pmc.h> 52 53 #include <dt-bindings/interrupt-controller/arm-gic.h> 54 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 55 #include <dt-bindings/gpio/tegra186-gpio.h> 56 #include <dt-bindings/gpio/tegra194-gpio.h> 57 #include <dt-bindings/gpio/tegra234-gpio.h> 58 #include <dt-bindings/soc/tegra-pmc.h> 59 60 #define PMC_CNTRL 0x0 61 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 62 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 63 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 64 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 65 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 66 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 67 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 68 #define PMC_CNTRL_BLINK_EN 7 69 #define PMC_CNTRL_MAIN_RST BIT(4) 70 71 #define PMC_WAKE_MASK 0x0c 72 #define PMC_WAKE_LEVEL 0x10 73 #define PMC_WAKE_STATUS 0x14 74 #define PMC_SW_WAKE_STATUS 0x18 75 #define PMC_DPD_PADS_ORIDE 0x1c 76 #define PMC_DPD_PADS_ORIDE_BLINK 20 77 78 #define DPD_SAMPLE 0x020 79 #define DPD_SAMPLE_ENABLE BIT(0) 80 #define DPD_SAMPLE_DISABLE (0 << 0) 81 82 #define PWRGATE_TOGGLE 0x30 83 #define PWRGATE_TOGGLE_START BIT(8) 84 85 #define REMOVE_CLAMPING 0x34 86 87 #define PWRGATE_STATUS 0x38 88 89 #define PMC_BLINK_TIMER 0x40 90 #define PMC_IMPL_E_33V_PWR 0x40 91 92 #define PMC_PWR_DET 0x48 93 94 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 95 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 96 #define PMC_SCRATCH0_MODE_RCM BIT(1) 97 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 98 PMC_SCRATCH0_MODE_BOOTLOADER | \ 99 PMC_SCRATCH0_MODE_RCM) 100 101 #define PMC_CPUPWRGOOD_TIMER 0xc8 102 #define PMC_CPUPWROFF_TIMER 0xcc 103 #define PMC_COREPWRGOOD_TIMER 0x3c 104 #define PMC_COREPWROFF_TIMER 0xe0 105 106 #define PMC_PWR_DET_VALUE 0xe4 107 108 #define PMC_USB_DEBOUNCE_DEL 0xec 109 #define PMC_USB_AO 0xf0 110 111 #define PMC_SCRATCH41 0x140 112 113 #define PMC_WAKE2_MASK 0x160 114 #define PMC_WAKE2_LEVEL 0x164 115 #define PMC_WAKE2_STATUS 0x168 116 #define PMC_SW_WAKE2_STATUS 0x16c 117 118 #define PMC_CLK_OUT_CNTRL 0x1a8 119 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 120 #define PMC_SENSOR_CTRL 0x1b0 121 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 122 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 123 124 #define PMC_RST_STATUS_POR 0 125 #define PMC_RST_STATUS_WATCHDOG 1 126 #define PMC_RST_STATUS_SENSOR 2 127 #define PMC_RST_STATUS_SW_MAIN 3 128 #define PMC_RST_STATUS_LP0 4 129 #define PMC_RST_STATUS_AOTAG 5 130 131 #define IO_DPD_REQ 0x1b8 132 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 133 #define IO_DPD_REQ_CODE_OFF (1U << 30) 134 #define IO_DPD_REQ_CODE_ON (2U << 30) 135 #define IO_DPD_REQ_CODE_MASK (3U << 30) 136 137 #define IO_DPD_STATUS 0x1bc 138 #define IO_DPD2_REQ 0x1c0 139 #define IO_DPD2_STATUS 0x1c4 140 #define SEL_DPD_TIM 0x1c8 141 142 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec 143 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0 144 145 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8 146 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc 147 #define PMC_UTMIP_UHSIC_FAKE 0x218 148 149 #define PMC_SCRATCH54 0x258 150 #define PMC_SCRATCH54_DATA_SHIFT 8 151 #define PMC_SCRATCH54_ADDR_SHIFT 0 152 153 #define PMC_SCRATCH55 0x25c 154 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 155 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 156 #define PMC_SCRATCH55_PINMUX_SHIFT 24 157 #define PMC_SCRATCH55_16BITOP BIT(15) 158 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 159 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 160 161 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c 162 163 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270 164 #define PMC_UTMIP_MASTER_CONFIG 0x274 165 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c 166 #define PMC_UTMIP_MASTER2_CONFIG 0x29c 167 168 #define GPU_RG_CNTRL 0x2d4 169 170 #define PMC_UTMIP_PAD_CFG0 0x4c0 171 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0 172 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0 173 /* Tegra186 and later */ 174 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 175 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 176 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 177 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 178 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 179 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 180 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 181 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 182 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 183 184 #define WAKE_AOWAKE_CTRL 0x4f4 185 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 186 187 /* for secure PMC */ 188 #define TEGRA_SMC_PMC 0xc2fffe00 189 #define TEGRA_SMC_PMC_READ 0xaa 190 #define TEGRA_SMC_PMC_WRITE 0xbb 191 192 struct pmc_clk { 193 struct clk_hw hw; 194 unsigned long offs; 195 u32 mux_shift; 196 u32 force_en_shift; 197 }; 198 199 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 200 201 struct pmc_clk_gate { 202 struct clk_hw hw; 203 unsigned long offs; 204 u32 shift; 205 }; 206 207 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 208 209 struct pmc_clk_init_data { 210 char *name; 211 const char *const *parents; 212 int num_parents; 213 int clk_id; 214 u8 mux_shift; 215 u8 force_en_shift; 216 }; 217 218 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 219 "osc_div4", "extern1", 220 }; 221 222 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 223 "osc_div4", "extern2", 224 }; 225 226 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 227 "osc_div4", "extern3", 228 }; 229 230 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 231 { 232 .name = "pmc_clk_out_1", 233 .parents = clk_out1_parents, 234 .num_parents = ARRAY_SIZE(clk_out1_parents), 235 .clk_id = TEGRA_PMC_CLK_OUT_1, 236 .mux_shift = 6, 237 .force_en_shift = 2, 238 }, 239 { 240 .name = "pmc_clk_out_2", 241 .parents = clk_out2_parents, 242 .num_parents = ARRAY_SIZE(clk_out2_parents), 243 .clk_id = TEGRA_PMC_CLK_OUT_2, 244 .mux_shift = 14, 245 .force_en_shift = 10, 246 }, 247 { 248 .name = "pmc_clk_out_3", 249 .parents = clk_out3_parents, 250 .num_parents = ARRAY_SIZE(clk_out3_parents), 251 .clk_id = TEGRA_PMC_CLK_OUT_3, 252 .mux_shift = 22, 253 .force_en_shift = 18, 254 }, 255 }; 256 257 struct tegra_powergate { 258 struct generic_pm_domain genpd; 259 struct tegra_pmc *pmc; 260 unsigned int id; 261 struct clk **clks; 262 unsigned int num_clks; 263 unsigned long *clk_rates; 264 struct reset_control *reset; 265 }; 266 267 struct tegra_io_pad_soc { 268 enum tegra_io_pad id; 269 unsigned int dpd; 270 unsigned int voltage; 271 const char *name; 272 }; 273 274 struct tegra_pmc_regs { 275 unsigned int scratch0; 276 unsigned int dpd_req; 277 unsigned int dpd_status; 278 unsigned int dpd2_req; 279 unsigned int dpd2_status; 280 unsigned int rst_status; 281 unsigned int rst_source_shift; 282 unsigned int rst_source_mask; 283 unsigned int rst_level_shift; 284 unsigned int rst_level_mask; 285 }; 286 287 struct tegra_wake_event { 288 const char *name; 289 unsigned int id; 290 unsigned int irq; 291 struct { 292 unsigned int instance; 293 unsigned int pin; 294 } gpio; 295 }; 296 297 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 298 { \ 299 .name = _name, \ 300 .id = _id, \ 301 .irq = _irq, \ 302 .gpio = { \ 303 .instance = UINT_MAX, \ 304 .pin = UINT_MAX, \ 305 }, \ 306 } 307 308 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 309 { \ 310 .name = _name, \ 311 .id = _id, \ 312 .irq = 0, \ 313 .gpio = { \ 314 .instance = _instance, \ 315 .pin = _pin, \ 316 }, \ 317 } 318 319 struct tegra_pmc_soc { 320 unsigned int num_powergates; 321 const char *const *powergates; 322 unsigned int num_cpu_powergates; 323 const u8 *cpu_powergates; 324 325 bool has_tsense_reset; 326 bool has_gpu_clamps; 327 bool needs_mbist_war; 328 bool has_impl_33v_pwr; 329 bool maybe_tz_only; 330 331 const struct tegra_io_pad_soc *io_pads; 332 unsigned int num_io_pads; 333 334 const struct pinctrl_pin_desc *pin_descs; 335 unsigned int num_pin_descs; 336 337 const struct tegra_pmc_regs *regs; 338 void (*init)(struct tegra_pmc *pmc); 339 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 340 struct device_node *np, 341 bool invert); 342 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 343 int (*irq_set_type)(struct irq_data *data, unsigned int type); 344 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, 345 bool new_state); 346 347 const char * const *reset_sources; 348 unsigned int num_reset_sources; 349 const char * const *reset_levels; 350 unsigned int num_reset_levels; 351 352 /* 353 * These describe events that can wake the system from sleep (i.e. 354 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 355 * are dealt with in the LIC. 356 */ 357 const struct tegra_wake_event *wake_events; 358 unsigned int num_wake_events; 359 360 const struct pmc_clk_init_data *pmc_clks_data; 361 unsigned int num_pmc_clks; 362 bool has_blink_output; 363 bool has_usb_sleepwalk; 364 bool supports_core_domain; 365 }; 366 367 /** 368 * struct tegra_pmc - NVIDIA Tegra PMC 369 * @dev: pointer to PMC device structure 370 * @base: pointer to I/O remapped register region 371 * @wake: pointer to I/O remapped region for WAKE registers 372 * @aotag: pointer to I/O remapped region for AOTAG registers 373 * @scratch: pointer to I/O remapped region for scratch registers 374 * @clk: pointer to pclk clock 375 * @soc: pointer to SoC data structure 376 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 377 * @debugfs: pointer to debugfs entry 378 * @rate: currently configured rate of pclk 379 * @suspend_mode: lowest suspend mode available 380 * @cpu_good_time: CPU power good time (in microseconds) 381 * @cpu_off_time: CPU power off time (in microsecends) 382 * @core_osc_time: core power good OSC time (in microseconds) 383 * @core_pmu_time: core power good PMU time (in microseconds) 384 * @core_off_time: core power off time (in microseconds) 385 * @corereq_high: core power request is active-high 386 * @sysclkreq_high: system clock request is active-high 387 * @combined_req: combined power request for CPU & core 388 * @cpu_pwr_good_en: CPU power good signal is enabled 389 * @lp0_vec_phys: physical base address of the LP0 warm boot code 390 * @lp0_vec_size: size of the LP0 warm boot code 391 * @powergates_available: Bitmap of available power gates 392 * @powergates_lock: mutex for power gate register access 393 * @pctl_dev: pin controller exposed by the PMC 394 * @domain: IRQ domain provided by the PMC 395 * @irq: chip implementation for the IRQ domain 396 * @clk_nb: pclk clock changes handler 397 */ 398 struct tegra_pmc { 399 struct device *dev; 400 void __iomem *base; 401 void __iomem *wake; 402 void __iomem *aotag; 403 void __iomem *scratch; 404 struct clk *clk; 405 struct dentry *debugfs; 406 407 const struct tegra_pmc_soc *soc; 408 bool tz_only; 409 410 unsigned long rate; 411 412 enum tegra_suspend_mode suspend_mode; 413 u32 cpu_good_time; 414 u32 cpu_off_time; 415 u32 core_osc_time; 416 u32 core_pmu_time; 417 u32 core_off_time; 418 bool corereq_high; 419 bool sysclkreq_high; 420 bool combined_req; 421 bool cpu_pwr_good_en; 422 u32 lp0_vec_phys; 423 u32 lp0_vec_size; 424 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 425 426 struct mutex powergates_lock; 427 428 struct pinctrl_dev *pctl_dev; 429 430 struct irq_domain *domain; 431 struct irq_chip irq; 432 433 struct notifier_block clk_nb; 434 435 bool core_domain_state_synced; 436 bool core_domain_registered; 437 }; 438 439 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 440 .base = NULL, 441 .suspend_mode = TEGRA_SUSPEND_NOT_READY, 442 }; 443 444 static inline struct tegra_powergate * 445 to_powergate(struct generic_pm_domain *domain) 446 { 447 return container_of(domain, struct tegra_powergate, genpd); 448 } 449 450 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 451 { 452 struct arm_smccc_res res; 453 454 if (pmc->tz_only) { 455 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 456 0, 0, 0, &res); 457 if (res.a0) { 458 if (pmc->dev) 459 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 460 __func__, res.a0); 461 else 462 pr_warn("%s(): SMC failed: %lu\n", __func__, 463 res.a0); 464 } 465 466 return res.a1; 467 } 468 469 return readl(pmc->base + offset); 470 } 471 472 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 473 unsigned long offset) 474 { 475 struct arm_smccc_res res; 476 477 if (pmc->tz_only) { 478 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 479 value, 0, 0, 0, 0, &res); 480 if (res.a0) { 481 if (pmc->dev) 482 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 483 __func__, res.a0); 484 else 485 pr_warn("%s(): SMC failed: %lu\n", __func__, 486 res.a0); 487 } 488 } else { 489 writel(value, pmc->base + offset); 490 } 491 } 492 493 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 494 { 495 if (pmc->tz_only) 496 return tegra_pmc_readl(pmc, offset); 497 498 return readl(pmc->scratch + offset); 499 } 500 501 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 502 unsigned long offset) 503 { 504 if (pmc->tz_only) 505 tegra_pmc_writel(pmc, value, offset); 506 else 507 writel(value, pmc->scratch + offset); 508 } 509 510 /* 511 * TODO Figure out a way to call this with the struct tegra_pmc * passed in. 512 * This currently doesn't work because readx_poll_timeout() can only operate 513 * on functions that take a single argument. 514 */ 515 static inline bool tegra_powergate_state(int id) 516 { 517 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 518 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 519 else 520 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 521 } 522 523 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 524 { 525 return (pmc->soc && pmc->soc->powergates[id]); 526 } 527 528 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 529 { 530 return test_bit(id, pmc->powergates_available); 531 } 532 533 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 534 { 535 unsigned int i; 536 537 if (!pmc || !pmc->soc || !name) 538 return -EINVAL; 539 540 for (i = 0; i < pmc->soc->num_powergates; i++) { 541 if (!tegra_powergate_is_valid(pmc, i)) 542 continue; 543 544 if (!strcmp(name, pmc->soc->powergates[i])) 545 return i; 546 } 547 548 return -ENODEV; 549 } 550 551 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, 552 bool new_state) 553 { 554 unsigned int retries = 100; 555 bool status; 556 int ret; 557 558 /* 559 * As per TRM documentation, the toggle command will be dropped by PMC 560 * if there is contention with a HW-initiated toggling (i.e. CPU core 561 * power-gated), the command should be retried in that case. 562 */ 563 do { 564 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 565 566 /* wait for PMC to execute the command */ 567 ret = readx_poll_timeout(tegra_powergate_state, id, status, 568 status == new_state, 1, 10); 569 } while (ret == -ETIMEDOUT && retries--); 570 571 return ret; 572 } 573 574 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) 575 { 576 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); 577 } 578 579 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, 580 bool new_state) 581 { 582 bool status; 583 int err; 584 585 /* wait while PMC power gating is contended */ 586 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 587 status == true, 1, 100); 588 if (err) 589 return err; 590 591 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 592 593 /* wait for PMC to accept the command */ 594 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 595 status == true, 1, 100); 596 if (err) 597 return err; 598 599 /* wait for PMC to execute the command */ 600 err = readx_poll_timeout(tegra_powergate_state, id, status, 601 status == new_state, 10, 100000); 602 if (err) 603 return err; 604 605 return 0; 606 } 607 608 /** 609 * tegra_powergate_set() - set the state of a partition 610 * @pmc: power management controller 611 * @id: partition ID 612 * @new_state: new state of the partition 613 */ 614 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 615 bool new_state) 616 { 617 int err; 618 619 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 620 return -EINVAL; 621 622 mutex_lock(&pmc->powergates_lock); 623 624 if (tegra_powergate_state(id) == new_state) { 625 mutex_unlock(&pmc->powergates_lock); 626 return 0; 627 } 628 629 err = pmc->soc->powergate_set(pmc, id, new_state); 630 631 mutex_unlock(&pmc->powergates_lock); 632 633 return err; 634 } 635 636 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 637 unsigned int id) 638 { 639 u32 mask; 640 641 mutex_lock(&pmc->powergates_lock); 642 643 /* 644 * On Tegra124 and later, the clamps for the GPU are controlled by a 645 * separate register (with different semantics). 646 */ 647 if (id == TEGRA_POWERGATE_3D) { 648 if (pmc->soc->has_gpu_clamps) { 649 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 650 goto out; 651 } 652 } 653 654 /* 655 * Tegra 2 has a bug where PCIE and VDE clamping masks are 656 * swapped relatively to the partition ids 657 */ 658 if (id == TEGRA_POWERGATE_VDEC) 659 mask = (1 << TEGRA_POWERGATE_PCIE); 660 else if (id == TEGRA_POWERGATE_PCIE) 661 mask = (1 << TEGRA_POWERGATE_VDEC); 662 else 663 mask = (1 << id); 664 665 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 666 667 out: 668 mutex_unlock(&pmc->powergates_lock); 669 670 return 0; 671 } 672 673 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) 674 { 675 unsigned long safe_rate = 100 * 1000 * 1000; 676 unsigned int i; 677 int err; 678 679 for (i = 0; i < pg->num_clks; i++) { 680 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); 681 682 if (!pg->clk_rates[i]) { 683 err = -EINVAL; 684 goto out; 685 } 686 687 if (pg->clk_rates[i] <= safe_rate) 688 continue; 689 690 /* 691 * We don't know whether voltage state is okay for the 692 * current clock rate, hence it's better to temporally 693 * switch clock to a safe rate which is suitable for 694 * all voltages, before enabling the clock. 695 */ 696 err = clk_set_rate(pg->clks[i], safe_rate); 697 if (err) 698 goto out; 699 } 700 701 return 0; 702 703 out: 704 while (i--) 705 clk_set_rate(pg->clks[i], pg->clk_rates[i]); 706 707 return err; 708 } 709 710 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) 711 { 712 unsigned int i; 713 int err; 714 715 for (i = 0; i < pg->num_clks; i++) { 716 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); 717 if (err) 718 return err; 719 } 720 721 return 0; 722 } 723 724 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 725 { 726 unsigned int i; 727 728 for (i = 0; i < pg->num_clks; i++) 729 clk_disable_unprepare(pg->clks[i]); 730 } 731 732 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 733 { 734 unsigned int i; 735 int err; 736 737 for (i = 0; i < pg->num_clks; i++) { 738 err = clk_prepare_enable(pg->clks[i]); 739 if (err) 740 goto out; 741 } 742 743 return 0; 744 745 out: 746 while (i--) 747 clk_disable_unprepare(pg->clks[i]); 748 749 return err; 750 } 751 752 static int tegra_powergate_power_up(struct tegra_powergate *pg, 753 bool disable_clocks) 754 { 755 int err; 756 757 err = reset_control_assert(pg->reset); 758 if (err) 759 return err; 760 761 usleep_range(10, 20); 762 763 err = tegra_powergate_set(pg->pmc, pg->id, true); 764 if (err < 0) 765 return err; 766 767 usleep_range(10, 20); 768 769 err = tegra_powergate_prepare_clocks(pg); 770 if (err) 771 goto powergate_off; 772 773 err = tegra_powergate_enable_clocks(pg); 774 if (err) 775 goto unprepare_clks; 776 777 usleep_range(10, 20); 778 779 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 780 if (err) 781 goto disable_clks; 782 783 usleep_range(10, 20); 784 785 err = reset_control_deassert(pg->reset); 786 if (err) 787 goto disable_clks; 788 789 usleep_range(10, 20); 790 791 if (pg->pmc->soc->needs_mbist_war) 792 err = tegra210_clk_handle_mbist_war(pg->id); 793 if (err) 794 goto disable_clks; 795 796 if (disable_clocks) 797 tegra_powergate_disable_clocks(pg); 798 799 err = tegra_powergate_unprepare_clocks(pg); 800 if (err) 801 return err; 802 803 return 0; 804 805 disable_clks: 806 tegra_powergate_disable_clocks(pg); 807 usleep_range(10, 20); 808 809 unprepare_clks: 810 tegra_powergate_unprepare_clocks(pg); 811 812 powergate_off: 813 tegra_powergate_set(pg->pmc, pg->id, false); 814 815 return err; 816 } 817 818 static int tegra_powergate_power_down(struct tegra_powergate *pg) 819 { 820 int err; 821 822 err = tegra_powergate_prepare_clocks(pg); 823 if (err) 824 return err; 825 826 err = tegra_powergate_enable_clocks(pg); 827 if (err) 828 goto unprepare_clks; 829 830 usleep_range(10, 20); 831 832 err = reset_control_assert(pg->reset); 833 if (err) 834 goto disable_clks; 835 836 usleep_range(10, 20); 837 838 tegra_powergate_disable_clocks(pg); 839 840 usleep_range(10, 20); 841 842 err = tegra_powergate_set(pg->pmc, pg->id, false); 843 if (err) 844 goto assert_resets; 845 846 err = tegra_powergate_unprepare_clocks(pg); 847 if (err) 848 return err; 849 850 return 0; 851 852 assert_resets: 853 tegra_powergate_enable_clocks(pg); 854 usleep_range(10, 20); 855 reset_control_deassert(pg->reset); 856 usleep_range(10, 20); 857 858 disable_clks: 859 tegra_powergate_disable_clocks(pg); 860 861 unprepare_clks: 862 tegra_powergate_unprepare_clocks(pg); 863 864 return err; 865 } 866 867 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 868 { 869 struct tegra_powergate *pg = to_powergate(domain); 870 struct device *dev = pg->pmc->dev; 871 int err; 872 873 err = tegra_powergate_power_up(pg, true); 874 if (err) { 875 dev_err(dev, "failed to turn on PM domain %s: %d\n", 876 pg->genpd.name, err); 877 goto out; 878 } 879 880 reset_control_release(pg->reset); 881 882 out: 883 return err; 884 } 885 886 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 887 { 888 struct tegra_powergate *pg = to_powergate(domain); 889 struct device *dev = pg->pmc->dev; 890 int err; 891 892 err = reset_control_acquire(pg->reset); 893 if (err < 0) { 894 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", 895 pg->genpd.name, err); 896 return err; 897 } 898 899 err = tegra_powergate_power_down(pg); 900 if (err) { 901 dev_err(dev, "failed to turn off PM domain %s: %d\n", 902 pg->genpd.name, err); 903 reset_control_release(pg->reset); 904 } 905 906 return err; 907 } 908 909 /** 910 * tegra_powergate_power_on() - power on partition 911 * @id: partition ID 912 */ 913 int tegra_powergate_power_on(unsigned int id) 914 { 915 if (!tegra_powergate_is_available(pmc, id)) 916 return -EINVAL; 917 918 return tegra_powergate_set(pmc, id, true); 919 } 920 EXPORT_SYMBOL(tegra_powergate_power_on); 921 922 /** 923 * tegra_powergate_power_off() - power off partition 924 * @id: partition ID 925 */ 926 int tegra_powergate_power_off(unsigned int id) 927 { 928 if (!tegra_powergate_is_available(pmc, id)) 929 return -EINVAL; 930 931 return tegra_powergate_set(pmc, id, false); 932 } 933 EXPORT_SYMBOL(tegra_powergate_power_off); 934 935 /** 936 * tegra_powergate_is_powered() - check if partition is powered 937 * @pmc: power management controller 938 * @id: partition ID 939 */ 940 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 941 { 942 if (!tegra_powergate_is_valid(pmc, id)) 943 return -EINVAL; 944 945 return tegra_powergate_state(id); 946 } 947 948 /** 949 * tegra_powergate_remove_clamping() - remove power clamps for partition 950 * @id: partition ID 951 */ 952 int tegra_powergate_remove_clamping(unsigned int id) 953 { 954 if (!tegra_powergate_is_available(pmc, id)) 955 return -EINVAL; 956 957 return __tegra_powergate_remove_clamping(pmc, id); 958 } 959 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 960 961 /** 962 * tegra_powergate_sequence_power_up() - power up partition 963 * @id: partition ID 964 * @clk: clock for partition 965 * @rst: reset for partition 966 * 967 * Must be called with clk disabled, and returns with clk enabled. 968 */ 969 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 970 struct reset_control *rst) 971 { 972 struct tegra_powergate *pg; 973 int err; 974 975 if (!tegra_powergate_is_available(pmc, id)) 976 return -EINVAL; 977 978 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 979 if (!pg) 980 return -ENOMEM; 981 982 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); 983 if (!pg->clk_rates) { 984 kfree(pg->clks); 985 return -ENOMEM; 986 } 987 988 pg->id = id; 989 pg->clks = &clk; 990 pg->num_clks = 1; 991 pg->reset = rst; 992 pg->pmc = pmc; 993 994 err = tegra_powergate_power_up(pg, false); 995 if (err) 996 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 997 err); 998 999 kfree(pg->clk_rates); 1000 kfree(pg); 1001 1002 return err; 1003 } 1004 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 1005 1006 /** 1007 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 1008 * @pmc: power management controller 1009 * @cpuid: CPU partition ID 1010 * 1011 * Returns the partition ID corresponding to the CPU partition ID or a 1012 * negative error code on failure. 1013 */ 1014 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 1015 unsigned int cpuid) 1016 { 1017 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 1018 return pmc->soc->cpu_powergates[cpuid]; 1019 1020 return -EINVAL; 1021 } 1022 1023 /** 1024 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 1025 * @cpuid: CPU partition ID 1026 */ 1027 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 1028 { 1029 int id; 1030 1031 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1032 if (id < 0) 1033 return false; 1034 1035 return tegra_powergate_is_powered(pmc, id); 1036 } 1037 1038 /** 1039 * tegra_pmc_cpu_power_on() - power on CPU partition 1040 * @cpuid: CPU partition ID 1041 */ 1042 int tegra_pmc_cpu_power_on(unsigned int cpuid) 1043 { 1044 int id; 1045 1046 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1047 if (id < 0) 1048 return id; 1049 1050 return tegra_powergate_set(pmc, id, true); 1051 } 1052 1053 /** 1054 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 1055 * @cpuid: CPU partition ID 1056 */ 1057 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 1058 { 1059 int id; 1060 1061 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1062 if (id < 0) 1063 return id; 1064 1065 return tegra_powergate_remove_clamping(id); 1066 } 1067 1068 static void tegra_pmc_program_reboot_reason(const char *cmd) 1069 { 1070 u32 value; 1071 1072 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 1073 value &= ~PMC_SCRATCH0_MODE_MASK; 1074 1075 if (cmd) { 1076 if (strcmp(cmd, "recovery") == 0) 1077 value |= PMC_SCRATCH0_MODE_RECOVERY; 1078 1079 if (strcmp(cmd, "bootloader") == 0) 1080 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 1081 1082 if (strcmp(cmd, "forced-recovery") == 0) 1083 value |= PMC_SCRATCH0_MODE_RCM; 1084 } 1085 1086 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 1087 } 1088 1089 static int tegra_pmc_reboot_notify(struct notifier_block *this, 1090 unsigned long action, void *data) 1091 { 1092 if (action == SYS_RESTART) 1093 tegra_pmc_program_reboot_reason(data); 1094 1095 return NOTIFY_DONE; 1096 } 1097 1098 static struct notifier_block tegra_pmc_reboot_notifier = { 1099 .notifier_call = tegra_pmc_reboot_notify, 1100 }; 1101 1102 static int tegra_pmc_restart_notify(struct notifier_block *this, 1103 unsigned long action, void *data) 1104 { 1105 u32 value; 1106 1107 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 1108 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1109 value |= PMC_CNTRL_MAIN_RST; 1110 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1111 1112 return NOTIFY_DONE; 1113 } 1114 1115 static struct notifier_block tegra_pmc_restart_handler = { 1116 .notifier_call = tegra_pmc_restart_notify, 1117 .priority = 128, 1118 }; 1119 1120 static int powergate_show(struct seq_file *s, void *data) 1121 { 1122 unsigned int i; 1123 int status; 1124 1125 seq_printf(s, " powergate powered\n"); 1126 seq_printf(s, "------------------\n"); 1127 1128 for (i = 0; i < pmc->soc->num_powergates; i++) { 1129 status = tegra_powergate_is_powered(pmc, i); 1130 if (status < 0) 1131 continue; 1132 1133 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 1134 status ? "yes" : "no"); 1135 } 1136 1137 return 0; 1138 } 1139 1140 DEFINE_SHOW_ATTRIBUTE(powergate); 1141 1142 static int tegra_powergate_debugfs_init(void) 1143 { 1144 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 1145 &powergate_fops); 1146 if (!pmc->debugfs) 1147 return -ENOMEM; 1148 1149 return 0; 1150 } 1151 1152 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1153 struct device_node *np) 1154 { 1155 struct clk *clk; 1156 unsigned int i, count; 1157 int err; 1158 1159 count = of_clk_get_parent_count(np); 1160 if (count == 0) 1161 return -ENODEV; 1162 1163 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 1164 if (!pg->clks) 1165 return -ENOMEM; 1166 1167 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); 1168 if (!pg->clk_rates) { 1169 kfree(pg->clks); 1170 return -ENOMEM; 1171 } 1172 1173 for (i = 0; i < count; i++) { 1174 pg->clks[i] = of_clk_get(np, i); 1175 if (IS_ERR(pg->clks[i])) { 1176 err = PTR_ERR(pg->clks[i]); 1177 goto err; 1178 } 1179 } 1180 1181 pg->num_clks = count; 1182 1183 return 0; 1184 1185 err: 1186 while (i--) 1187 clk_put(pg->clks[i]); 1188 1189 kfree(pg->clk_rates); 1190 kfree(pg->clks); 1191 1192 return err; 1193 } 1194 1195 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1196 struct device_node *np, bool off) 1197 { 1198 struct device *dev = pg->pmc->dev; 1199 int err; 1200 1201 pg->reset = of_reset_control_array_get_exclusive_released(np); 1202 if (IS_ERR(pg->reset)) { 1203 err = PTR_ERR(pg->reset); 1204 dev_err(dev, "failed to get device resets: %d\n", err); 1205 return err; 1206 } 1207 1208 err = reset_control_acquire(pg->reset); 1209 if (err < 0) { 1210 pr_err("failed to acquire resets: %d\n", err); 1211 goto out; 1212 } 1213 1214 if (off) { 1215 err = reset_control_assert(pg->reset); 1216 } else { 1217 err = reset_control_deassert(pg->reset); 1218 if (err < 0) 1219 goto out; 1220 1221 reset_control_release(pg->reset); 1222 } 1223 1224 out: 1225 if (err) { 1226 reset_control_release(pg->reset); 1227 reset_control_put(pg->reset); 1228 } 1229 1230 return err; 1231 } 1232 1233 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1234 { 1235 struct device *dev = pmc->dev; 1236 struct tegra_powergate *pg; 1237 int id, err = 0; 1238 bool off; 1239 1240 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1241 if (!pg) 1242 return -ENOMEM; 1243 1244 id = tegra_powergate_lookup(pmc, np->name); 1245 if (id < 0) { 1246 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1247 err = -ENODEV; 1248 goto free_mem; 1249 } 1250 1251 /* 1252 * Clear the bit for this powergate so it cannot be managed 1253 * directly via the legacy APIs for controlling powergates. 1254 */ 1255 clear_bit(id, pmc->powergates_available); 1256 1257 pg->id = id; 1258 pg->genpd.name = np->name; 1259 pg->genpd.power_off = tegra_genpd_power_off; 1260 pg->genpd.power_on = tegra_genpd_power_on; 1261 pg->pmc = pmc; 1262 1263 off = !tegra_powergate_is_powered(pmc, pg->id); 1264 1265 err = tegra_powergate_of_get_clks(pg, np); 1266 if (err < 0) { 1267 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1268 goto set_available; 1269 } 1270 1271 err = tegra_powergate_of_get_resets(pg, np, off); 1272 if (err < 0) { 1273 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1274 goto remove_clks; 1275 } 1276 1277 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1278 if (off) 1279 WARN_ON(tegra_powergate_power_up(pg, true)); 1280 1281 goto remove_resets; 1282 } 1283 1284 err = pm_genpd_init(&pg->genpd, NULL, off); 1285 if (err < 0) { 1286 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1287 err); 1288 goto remove_resets; 1289 } 1290 1291 err = of_genpd_add_provider_simple(np, &pg->genpd); 1292 if (err < 0) { 1293 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1294 np, err); 1295 goto remove_genpd; 1296 } 1297 1298 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1299 1300 return 0; 1301 1302 remove_genpd: 1303 pm_genpd_remove(&pg->genpd); 1304 1305 remove_resets: 1306 reset_control_put(pg->reset); 1307 1308 remove_clks: 1309 while (pg->num_clks--) 1310 clk_put(pg->clks[pg->num_clks]); 1311 1312 kfree(pg->clks); 1313 1314 set_available: 1315 set_bit(id, pmc->powergates_available); 1316 1317 free_mem: 1318 kfree(pg); 1319 1320 return err; 1321 } 1322 1323 bool tegra_pmc_core_domain_state_synced(void) 1324 { 1325 return pmc->core_domain_state_synced; 1326 } 1327 1328 static int 1329 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, 1330 unsigned int level) 1331 { 1332 struct dev_pm_opp *opp; 1333 int err; 1334 1335 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); 1336 if (IS_ERR(opp)) { 1337 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", 1338 level, opp); 1339 return PTR_ERR(opp); 1340 } 1341 1342 mutex_lock(&pmc->powergates_lock); 1343 err = dev_pm_opp_set_opp(pmc->dev, opp); 1344 mutex_unlock(&pmc->powergates_lock); 1345 1346 dev_pm_opp_put(opp); 1347 1348 if (err) { 1349 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", 1350 level, err); 1351 return err; 1352 } 1353 1354 return 0; 1355 } 1356 1357 static unsigned int 1358 tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd, 1359 struct dev_pm_opp *opp) 1360 { 1361 return dev_pm_opp_get_level(opp); 1362 } 1363 1364 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) 1365 { 1366 struct generic_pm_domain *genpd; 1367 const char *rname = "core"; 1368 int err; 1369 1370 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); 1371 if (!genpd) 1372 return -ENOMEM; 1373 1374 genpd->name = "core"; 1375 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; 1376 genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state; 1377 1378 err = devm_pm_opp_set_regulators(pmc->dev, &rname, 1); 1379 if (err) 1380 return dev_err_probe(pmc->dev, err, 1381 "failed to set core OPP regulator\n"); 1382 1383 err = pm_genpd_init(genpd, NULL, false); 1384 if (err) { 1385 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); 1386 return err; 1387 } 1388 1389 err = of_genpd_add_provider_simple(np, genpd); 1390 if (err) { 1391 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); 1392 goto remove_genpd; 1393 } 1394 1395 pmc->core_domain_registered = true; 1396 1397 return 0; 1398 1399 remove_genpd: 1400 pm_genpd_remove(genpd); 1401 1402 return err; 1403 } 1404 1405 static int tegra_powergate_init(struct tegra_pmc *pmc, 1406 struct device_node *parent) 1407 { 1408 struct of_phandle_args child_args, parent_args; 1409 struct device_node *np, *child; 1410 int err = 0; 1411 1412 /* 1413 * Core power domain is the parent of powergate domains, hence it 1414 * should be registered first. 1415 */ 1416 np = of_get_child_by_name(parent, "core-domain"); 1417 if (np) { 1418 err = tegra_pmc_core_pd_add(pmc, np); 1419 of_node_put(np); 1420 if (err) 1421 return err; 1422 } 1423 1424 np = of_get_child_by_name(parent, "powergates"); 1425 if (!np) 1426 return 0; 1427 1428 for_each_child_of_node(np, child) { 1429 err = tegra_powergate_add(pmc, child); 1430 if (err < 0) { 1431 of_node_put(child); 1432 break; 1433 } 1434 1435 if (of_parse_phandle_with_args(child, "power-domains", 1436 "#power-domain-cells", 1437 0, &parent_args)) 1438 continue; 1439 1440 child_args.np = child; 1441 child_args.args_count = 0; 1442 1443 err = of_genpd_add_subdomain(&parent_args, &child_args); 1444 of_node_put(parent_args.np); 1445 if (err) { 1446 of_node_put(child); 1447 break; 1448 } 1449 } 1450 1451 of_node_put(np); 1452 1453 return err; 1454 } 1455 1456 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1457 { 1458 struct tegra_powergate *pg = to_powergate(genpd); 1459 1460 reset_control_put(pg->reset); 1461 1462 while (pg->num_clks--) 1463 clk_put(pg->clks[pg->num_clks]); 1464 1465 kfree(pg->clks); 1466 1467 set_bit(pg->id, pmc->powergates_available); 1468 1469 kfree(pg); 1470 } 1471 1472 static void tegra_powergate_remove_all(struct device_node *parent) 1473 { 1474 struct generic_pm_domain *genpd; 1475 struct device_node *np, *child; 1476 1477 np = of_get_child_by_name(parent, "powergates"); 1478 if (!np) 1479 return; 1480 1481 for_each_child_of_node(np, child) { 1482 of_genpd_del_provider(child); 1483 1484 genpd = of_genpd_remove_last(child); 1485 if (IS_ERR(genpd)) 1486 continue; 1487 1488 tegra_powergate_remove(genpd); 1489 } 1490 1491 of_node_put(np); 1492 1493 np = of_get_child_by_name(parent, "core-domain"); 1494 if (np) { 1495 of_genpd_del_provider(np); 1496 of_genpd_remove_last(np); 1497 } 1498 } 1499 1500 static const struct tegra_io_pad_soc * 1501 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1502 { 1503 unsigned int i; 1504 1505 for (i = 0; i < pmc->soc->num_io_pads; i++) 1506 if (pmc->soc->io_pads[i].id == id) 1507 return &pmc->soc->io_pads[i]; 1508 1509 return NULL; 1510 } 1511 1512 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, 1513 enum tegra_io_pad id, 1514 unsigned long *request, 1515 unsigned long *status, 1516 u32 *mask) 1517 { 1518 const struct tegra_io_pad_soc *pad; 1519 1520 pad = tegra_io_pad_find(pmc, id); 1521 if (!pad) { 1522 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1523 return -ENOENT; 1524 } 1525 1526 if (pad->dpd == UINT_MAX) 1527 return -ENOTSUPP; 1528 1529 *mask = BIT(pad->dpd % 32); 1530 1531 if (pad->dpd < 32) { 1532 *status = pmc->soc->regs->dpd_status; 1533 *request = pmc->soc->regs->dpd_req; 1534 } else { 1535 *status = pmc->soc->regs->dpd2_status; 1536 *request = pmc->soc->regs->dpd2_req; 1537 } 1538 1539 return 0; 1540 } 1541 1542 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, 1543 unsigned long *request, unsigned long *status, 1544 u32 *mask) 1545 { 1546 unsigned long rate, value; 1547 int err; 1548 1549 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); 1550 if (err) 1551 return err; 1552 1553 if (pmc->clk) { 1554 rate = pmc->rate; 1555 if (!rate) { 1556 dev_err(pmc->dev, "failed to get clock rate\n"); 1557 return -ENODEV; 1558 } 1559 1560 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1561 1562 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1563 value = DIV_ROUND_UP(1000000000, rate); 1564 value = DIV_ROUND_UP(200, value); 1565 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1566 } 1567 1568 return 0; 1569 } 1570 1571 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1572 u32 mask, u32 val, unsigned long timeout) 1573 { 1574 u32 value; 1575 1576 timeout = jiffies + msecs_to_jiffies(timeout); 1577 1578 while (time_after(timeout, jiffies)) { 1579 value = tegra_pmc_readl(pmc, offset); 1580 if ((value & mask) == val) 1581 return 0; 1582 1583 usleep_range(250, 1000); 1584 } 1585 1586 return -ETIMEDOUT; 1587 } 1588 1589 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1590 { 1591 if (pmc->clk) 1592 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1593 } 1594 1595 /** 1596 * tegra_io_pad_power_enable() - enable power to I/O pad 1597 * @id: Tegra I/O pad ID for which to enable power 1598 * 1599 * Returns: 0 on success or a negative error code on failure. 1600 */ 1601 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1602 { 1603 unsigned long request, status; 1604 u32 mask; 1605 int err; 1606 1607 mutex_lock(&pmc->powergates_lock); 1608 1609 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1610 if (err < 0) { 1611 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1612 goto unlock; 1613 } 1614 1615 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1616 1617 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1618 if (err < 0) { 1619 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1620 goto unlock; 1621 } 1622 1623 tegra_io_pad_unprepare(pmc); 1624 1625 unlock: 1626 mutex_unlock(&pmc->powergates_lock); 1627 return err; 1628 } 1629 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1630 1631 /** 1632 * tegra_io_pad_power_disable() - disable power to I/O pad 1633 * @id: Tegra I/O pad ID for which to disable power 1634 * 1635 * Returns: 0 on success or a negative error code on failure. 1636 */ 1637 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1638 { 1639 unsigned long request, status; 1640 u32 mask; 1641 int err; 1642 1643 mutex_lock(&pmc->powergates_lock); 1644 1645 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1646 if (err < 0) { 1647 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1648 goto unlock; 1649 } 1650 1651 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1652 1653 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1654 if (err < 0) { 1655 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1656 goto unlock; 1657 } 1658 1659 tegra_io_pad_unprepare(pmc); 1660 1661 unlock: 1662 mutex_unlock(&pmc->powergates_lock); 1663 return err; 1664 } 1665 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1666 1667 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1668 { 1669 unsigned long request, status; 1670 u32 mask, value; 1671 int err; 1672 1673 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, 1674 &mask); 1675 if (err) 1676 return err; 1677 1678 value = tegra_pmc_readl(pmc, status); 1679 1680 return !(value & mask); 1681 } 1682 1683 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1684 int voltage) 1685 { 1686 const struct tegra_io_pad_soc *pad; 1687 u32 value; 1688 1689 pad = tegra_io_pad_find(pmc, id); 1690 if (!pad) 1691 return -ENOENT; 1692 1693 if (pad->voltage == UINT_MAX) 1694 return -ENOTSUPP; 1695 1696 mutex_lock(&pmc->powergates_lock); 1697 1698 if (pmc->soc->has_impl_33v_pwr) { 1699 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1700 1701 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1702 value &= ~BIT(pad->voltage); 1703 else 1704 value |= BIT(pad->voltage); 1705 1706 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1707 } else { 1708 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1709 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1710 value |= BIT(pad->voltage); 1711 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1712 1713 /* update I/O voltage */ 1714 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1715 1716 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1717 value &= ~BIT(pad->voltage); 1718 else 1719 value |= BIT(pad->voltage); 1720 1721 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1722 } 1723 1724 mutex_unlock(&pmc->powergates_lock); 1725 1726 usleep_range(100, 250); 1727 1728 return 0; 1729 } 1730 1731 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1732 { 1733 const struct tegra_io_pad_soc *pad; 1734 u32 value; 1735 1736 pad = tegra_io_pad_find(pmc, id); 1737 if (!pad) 1738 return -ENOENT; 1739 1740 if (pad->voltage == UINT_MAX) 1741 return -ENOTSUPP; 1742 1743 if (pmc->soc->has_impl_33v_pwr) 1744 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1745 else 1746 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1747 1748 if ((value & BIT(pad->voltage)) == 0) 1749 return TEGRA_IO_PAD_VOLTAGE_1V8; 1750 1751 return TEGRA_IO_PAD_VOLTAGE_3V3; 1752 } 1753 1754 /** 1755 * tegra_io_rail_power_on() - enable power to I/O rail 1756 * @id: Tegra I/O pad ID for which to enable power 1757 * 1758 * See also: tegra_io_pad_power_enable() 1759 */ 1760 int tegra_io_rail_power_on(unsigned int id) 1761 { 1762 return tegra_io_pad_power_enable(id); 1763 } 1764 EXPORT_SYMBOL(tegra_io_rail_power_on); 1765 1766 /** 1767 * tegra_io_rail_power_off() - disable power to I/O rail 1768 * @id: Tegra I/O pad ID for which to disable power 1769 * 1770 * See also: tegra_io_pad_power_disable() 1771 */ 1772 int tegra_io_rail_power_off(unsigned int id) 1773 { 1774 return tegra_io_pad_power_disable(id); 1775 } 1776 EXPORT_SYMBOL(tegra_io_rail_power_off); 1777 1778 #ifdef CONFIG_PM_SLEEP 1779 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1780 { 1781 return pmc->suspend_mode; 1782 } 1783 1784 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1785 { 1786 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1787 return; 1788 1789 pmc->suspend_mode = mode; 1790 } 1791 1792 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1793 { 1794 unsigned long long rate = 0; 1795 u64 ticks; 1796 u32 value; 1797 1798 switch (mode) { 1799 case TEGRA_SUSPEND_LP1: 1800 rate = 32768; 1801 break; 1802 1803 case TEGRA_SUSPEND_LP2: 1804 rate = pmc->rate; 1805 break; 1806 1807 default: 1808 break; 1809 } 1810 1811 if (WARN_ON_ONCE(rate == 0)) 1812 rate = 100000000; 1813 1814 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1815 do_div(ticks, USEC_PER_SEC); 1816 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1817 1818 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1819 do_div(ticks, USEC_PER_SEC); 1820 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1821 1822 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1823 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1824 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1825 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1826 } 1827 #endif 1828 1829 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1830 { 1831 u32 value, values[2]; 1832 1833 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1834 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1835 } else { 1836 switch (value) { 1837 case 0: 1838 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1839 break; 1840 1841 case 1: 1842 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1843 break; 1844 1845 case 2: 1846 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1847 break; 1848 1849 default: 1850 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1851 break; 1852 } 1853 } 1854 1855 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1856 1857 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1858 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1859 1860 pmc->cpu_good_time = value; 1861 1862 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1863 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1864 1865 pmc->cpu_off_time = value; 1866 1867 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1868 values, ARRAY_SIZE(values))) 1869 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1870 1871 pmc->core_osc_time = values[0]; 1872 pmc->core_pmu_time = values[1]; 1873 1874 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1875 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1876 1877 pmc->core_off_time = value; 1878 1879 pmc->corereq_high = of_property_read_bool(np, 1880 "nvidia,core-power-req-active-high"); 1881 1882 pmc->sysclkreq_high = of_property_read_bool(np, 1883 "nvidia,sys-clock-req-active-high"); 1884 1885 pmc->combined_req = of_property_read_bool(np, 1886 "nvidia,combined-power-req"); 1887 1888 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1889 "nvidia,cpu-pwr-good-en"); 1890 1891 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1892 ARRAY_SIZE(values))) 1893 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1894 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1895 1896 pmc->lp0_vec_phys = values[0]; 1897 pmc->lp0_vec_size = values[1]; 1898 1899 return 0; 1900 } 1901 1902 static void tegra_pmc_init(struct tegra_pmc *pmc) 1903 { 1904 if (pmc->soc->init) 1905 pmc->soc->init(pmc); 1906 } 1907 1908 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1909 { 1910 static const char disabled[] = "emergency thermal reset disabled"; 1911 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1912 struct device *dev = pmc->dev; 1913 struct device_node *np; 1914 u32 value, checksum; 1915 1916 if (!pmc->soc->has_tsense_reset) 1917 return; 1918 1919 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1920 if (!np) { 1921 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1922 return; 1923 } 1924 1925 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1926 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1927 goto out; 1928 } 1929 1930 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1931 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1932 goto out; 1933 } 1934 1935 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1936 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1937 goto out; 1938 } 1939 1940 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1941 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1942 goto out; 1943 } 1944 1945 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1946 pinmux = 0; 1947 1948 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1949 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1950 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1951 1952 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1953 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1954 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 1955 1956 value = PMC_SCRATCH55_RESET_TEGRA; 1957 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1958 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1959 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1960 1961 /* 1962 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1963 * contain the checksum and are currently zero, so they are not added. 1964 */ 1965 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1966 + ((value >> 24) & 0xff); 1967 checksum &= 0xff; 1968 checksum = 0x100 - checksum; 1969 1970 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1971 1972 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 1973 1974 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1975 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1976 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1977 1978 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1979 1980 out: 1981 of_node_put(np); 1982 } 1983 1984 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 1985 { 1986 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1987 1988 return pmc->soc->num_io_pads; 1989 } 1990 1991 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 1992 unsigned int group) 1993 { 1994 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 1995 1996 return pmc->soc->io_pads[group].name; 1997 } 1998 1999 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 2000 unsigned int group, 2001 const unsigned int **pins, 2002 unsigned int *num_pins) 2003 { 2004 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2005 2006 *pins = &pmc->soc->io_pads[group].id; 2007 *num_pins = 1; 2008 2009 return 0; 2010 } 2011 2012 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 2013 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 2014 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 2015 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 2016 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2017 .dt_free_map = pinconf_generic_dt_free_map, 2018 }; 2019 2020 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 2021 unsigned int pin, unsigned long *config) 2022 { 2023 enum pin_config_param param = pinconf_to_config_param(*config); 2024 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2025 const struct tegra_io_pad_soc *pad; 2026 int ret; 2027 u32 arg; 2028 2029 pad = tegra_io_pad_find(pmc, pin); 2030 if (!pad) 2031 return -EINVAL; 2032 2033 switch (param) { 2034 case PIN_CONFIG_POWER_SOURCE: 2035 ret = tegra_io_pad_get_voltage(pmc, pad->id); 2036 if (ret < 0) 2037 return ret; 2038 2039 arg = ret; 2040 break; 2041 2042 case PIN_CONFIG_MODE_LOW_POWER: 2043 ret = tegra_io_pad_is_powered(pmc, pad->id); 2044 if (ret < 0) 2045 return ret; 2046 2047 arg = !ret; 2048 break; 2049 2050 default: 2051 return -EINVAL; 2052 } 2053 2054 *config = pinconf_to_config_packed(param, arg); 2055 2056 return 0; 2057 } 2058 2059 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 2060 unsigned int pin, unsigned long *configs, 2061 unsigned int num_configs) 2062 { 2063 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2064 const struct tegra_io_pad_soc *pad; 2065 enum pin_config_param param; 2066 unsigned int i; 2067 int err; 2068 u32 arg; 2069 2070 pad = tegra_io_pad_find(pmc, pin); 2071 if (!pad) 2072 return -EINVAL; 2073 2074 for (i = 0; i < num_configs; ++i) { 2075 param = pinconf_to_config_param(configs[i]); 2076 arg = pinconf_to_config_argument(configs[i]); 2077 2078 switch (param) { 2079 case PIN_CONFIG_MODE_LOW_POWER: 2080 if (arg) 2081 err = tegra_io_pad_power_disable(pad->id); 2082 else 2083 err = tegra_io_pad_power_enable(pad->id); 2084 if (err) 2085 return err; 2086 break; 2087 case PIN_CONFIG_POWER_SOURCE: 2088 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 2089 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 2090 return -EINVAL; 2091 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 2092 if (err) 2093 return err; 2094 break; 2095 default: 2096 return -EINVAL; 2097 } 2098 } 2099 2100 return 0; 2101 } 2102 2103 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 2104 .pin_config_get = tegra_io_pad_pinconf_get, 2105 .pin_config_set = tegra_io_pad_pinconf_set, 2106 .is_generic = true, 2107 }; 2108 2109 static struct pinctrl_desc tegra_pmc_pctl_desc = { 2110 .pctlops = &tegra_io_pad_pinctrl_ops, 2111 .confops = &tegra_io_pad_pinconf_ops, 2112 }; 2113 2114 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 2115 { 2116 int err; 2117 2118 if (!pmc->soc->num_pin_descs) 2119 return 0; 2120 2121 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 2122 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 2123 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 2124 2125 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 2126 pmc); 2127 if (IS_ERR(pmc->pctl_dev)) { 2128 err = PTR_ERR(pmc->pctl_dev); 2129 dev_err(pmc->dev, "failed to register pin controller: %d\n", 2130 err); 2131 return err; 2132 } 2133 2134 return 0; 2135 } 2136 2137 static ssize_t reset_reason_show(struct device *dev, 2138 struct device_attribute *attr, char *buf) 2139 { 2140 u32 value; 2141 2142 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2143 value &= pmc->soc->regs->rst_source_mask; 2144 value >>= pmc->soc->regs->rst_source_shift; 2145 2146 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 2147 return sprintf(buf, "%s\n", "UNKNOWN"); 2148 2149 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 2150 } 2151 2152 static DEVICE_ATTR_RO(reset_reason); 2153 2154 static ssize_t reset_level_show(struct device *dev, 2155 struct device_attribute *attr, char *buf) 2156 { 2157 u32 value; 2158 2159 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2160 value &= pmc->soc->regs->rst_level_mask; 2161 value >>= pmc->soc->regs->rst_level_shift; 2162 2163 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 2164 return sprintf(buf, "%s\n", "UNKNOWN"); 2165 2166 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 2167 } 2168 2169 static DEVICE_ATTR_RO(reset_level); 2170 2171 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 2172 { 2173 struct device *dev = pmc->dev; 2174 int err = 0; 2175 2176 if (pmc->soc->reset_sources) { 2177 err = device_create_file(dev, &dev_attr_reset_reason); 2178 if (err < 0) 2179 dev_warn(dev, 2180 "failed to create attr \"reset_reason\": %d\n", 2181 err); 2182 } 2183 2184 if (pmc->soc->reset_levels) { 2185 err = device_create_file(dev, &dev_attr_reset_level); 2186 if (err < 0) 2187 dev_warn(dev, 2188 "failed to create attr \"reset_level\": %d\n", 2189 err); 2190 } 2191 } 2192 2193 static int tegra_pmc_irq_translate(struct irq_domain *domain, 2194 struct irq_fwspec *fwspec, 2195 unsigned long *hwirq, 2196 unsigned int *type) 2197 { 2198 if (WARN_ON(fwspec->param_count < 2)) 2199 return -EINVAL; 2200 2201 *hwirq = fwspec->param[0]; 2202 *type = fwspec->param[1]; 2203 2204 return 0; 2205 } 2206 2207 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 2208 unsigned int num_irqs, void *data) 2209 { 2210 struct tegra_pmc *pmc = domain->host_data; 2211 const struct tegra_pmc_soc *soc = pmc->soc; 2212 struct irq_fwspec *fwspec = data; 2213 unsigned int i; 2214 int err = 0; 2215 2216 if (WARN_ON(num_irqs > 1)) 2217 return -EINVAL; 2218 2219 for (i = 0; i < soc->num_wake_events; i++) { 2220 const struct tegra_wake_event *event = &soc->wake_events[i]; 2221 2222 if (fwspec->param_count == 2) { 2223 struct irq_fwspec spec; 2224 2225 if (event->id != fwspec->param[0]) 2226 continue; 2227 2228 err = irq_domain_set_hwirq_and_chip(domain, virq, 2229 event->id, 2230 &pmc->irq, pmc); 2231 if (err < 0) 2232 break; 2233 2234 spec.fwnode = &pmc->dev->of_node->fwnode; 2235 spec.param_count = 3; 2236 spec.param[0] = GIC_SPI; 2237 spec.param[1] = event->irq; 2238 spec.param[2] = fwspec->param[1]; 2239 2240 err = irq_domain_alloc_irqs_parent(domain, virq, 2241 num_irqs, &spec); 2242 2243 break; 2244 } 2245 2246 if (fwspec->param_count == 3) { 2247 if (event->gpio.instance != fwspec->param[0] || 2248 event->gpio.pin != fwspec->param[1]) 2249 continue; 2250 2251 err = irq_domain_set_hwirq_and_chip(domain, virq, 2252 event->id, 2253 &pmc->irq, pmc); 2254 2255 /* GPIO hierarchies stop at the PMC level */ 2256 if (!err && domain->parent) 2257 err = irq_domain_disconnect_hierarchy(domain->parent, 2258 virq); 2259 break; 2260 } 2261 } 2262 2263 /* If there is no wake-up event, there is no PMC mapping */ 2264 if (i == soc->num_wake_events) 2265 err = irq_domain_disconnect_hierarchy(domain, virq); 2266 2267 return err; 2268 } 2269 2270 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2271 .translate = tegra_pmc_irq_translate, 2272 .alloc = tegra_pmc_irq_alloc, 2273 }; 2274 2275 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2276 { 2277 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2278 unsigned int offset, bit; 2279 u32 value; 2280 2281 offset = data->hwirq / 32; 2282 bit = data->hwirq % 32; 2283 2284 /* clear wake status */ 2285 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2286 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2287 2288 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2289 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2290 2291 /* enable PMC wake */ 2292 if (data->hwirq >= 32) 2293 offset = PMC_WAKE2_MASK; 2294 else 2295 offset = PMC_WAKE_MASK; 2296 2297 value = tegra_pmc_readl(pmc, offset); 2298 2299 if (on) 2300 value |= BIT(bit); 2301 else 2302 value &= ~BIT(bit); 2303 2304 tegra_pmc_writel(pmc, value, offset); 2305 2306 return 0; 2307 } 2308 2309 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2310 { 2311 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2312 unsigned int offset, bit; 2313 u32 value; 2314 2315 offset = data->hwirq / 32; 2316 bit = data->hwirq % 32; 2317 2318 if (data->hwirq >= 32) 2319 offset = PMC_WAKE2_LEVEL; 2320 else 2321 offset = PMC_WAKE_LEVEL; 2322 2323 value = tegra_pmc_readl(pmc, offset); 2324 2325 switch (type) { 2326 case IRQ_TYPE_EDGE_RISING: 2327 case IRQ_TYPE_LEVEL_HIGH: 2328 value |= BIT(bit); 2329 break; 2330 2331 case IRQ_TYPE_EDGE_FALLING: 2332 case IRQ_TYPE_LEVEL_LOW: 2333 value &= ~BIT(bit); 2334 break; 2335 2336 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2337 value ^= BIT(bit); 2338 break; 2339 2340 default: 2341 return -EINVAL; 2342 } 2343 2344 tegra_pmc_writel(pmc, value, offset); 2345 2346 return 0; 2347 } 2348 2349 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2350 { 2351 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2352 unsigned int offset, bit; 2353 u32 value; 2354 2355 offset = data->hwirq / 32; 2356 bit = data->hwirq % 32; 2357 2358 /* clear wake status */ 2359 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 2360 2361 /* route wake to tier 2 */ 2362 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2363 2364 if (!on) 2365 value &= ~(1 << bit); 2366 else 2367 value |= 1 << bit; 2368 2369 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2370 2371 /* enable wakeup event */ 2372 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 2373 2374 return 0; 2375 } 2376 2377 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2378 { 2379 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2380 u32 value; 2381 2382 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2383 2384 switch (type) { 2385 case IRQ_TYPE_EDGE_RISING: 2386 case IRQ_TYPE_LEVEL_HIGH: 2387 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2388 break; 2389 2390 case IRQ_TYPE_EDGE_FALLING: 2391 case IRQ_TYPE_LEVEL_LOW: 2392 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2393 break; 2394 2395 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2396 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2397 break; 2398 2399 default: 2400 return -EINVAL; 2401 } 2402 2403 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2404 2405 return 0; 2406 } 2407 2408 static void tegra_irq_mask_parent(struct irq_data *data) 2409 { 2410 if (data->parent_data) 2411 irq_chip_mask_parent(data); 2412 } 2413 2414 static void tegra_irq_unmask_parent(struct irq_data *data) 2415 { 2416 if (data->parent_data) 2417 irq_chip_unmask_parent(data); 2418 } 2419 2420 static void tegra_irq_eoi_parent(struct irq_data *data) 2421 { 2422 if (data->parent_data) 2423 irq_chip_eoi_parent(data); 2424 } 2425 2426 static int tegra_irq_set_affinity_parent(struct irq_data *data, 2427 const struct cpumask *dest, 2428 bool force) 2429 { 2430 if (data->parent_data) 2431 return irq_chip_set_affinity_parent(data, dest, force); 2432 2433 return -EINVAL; 2434 } 2435 2436 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2437 { 2438 struct irq_domain *parent = NULL; 2439 struct device_node *np; 2440 2441 np = of_irq_find_parent(pmc->dev->of_node); 2442 if (np) { 2443 parent = irq_find_host(np); 2444 of_node_put(np); 2445 } 2446 2447 if (!parent) 2448 return 0; 2449 2450 pmc->irq.name = dev_name(pmc->dev); 2451 pmc->irq.irq_mask = tegra_irq_mask_parent; 2452 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2453 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2454 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2455 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2456 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2457 2458 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, 2459 &tegra_pmc_irq_domain_ops, pmc); 2460 if (!pmc->domain) { 2461 dev_err(pmc->dev, "failed to allocate domain\n"); 2462 return -ENOMEM; 2463 } 2464 2465 return 0; 2466 } 2467 2468 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2469 unsigned long action, void *ptr) 2470 { 2471 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2472 struct clk_notifier_data *data = ptr; 2473 2474 switch (action) { 2475 case PRE_RATE_CHANGE: 2476 mutex_lock(&pmc->powergates_lock); 2477 break; 2478 2479 case POST_RATE_CHANGE: 2480 pmc->rate = data->new_rate; 2481 fallthrough; 2482 2483 case ABORT_RATE_CHANGE: 2484 mutex_unlock(&pmc->powergates_lock); 2485 break; 2486 2487 default: 2488 WARN_ON_ONCE(1); 2489 return notifier_from_errno(-EINVAL); 2490 } 2491 2492 return NOTIFY_OK; 2493 } 2494 2495 static void pmc_clk_fence_udelay(u32 offset) 2496 { 2497 tegra_pmc_readl(pmc, offset); 2498 /* pmc clk propagation delay 2 us */ 2499 udelay(2); 2500 } 2501 2502 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2503 { 2504 struct pmc_clk *clk = to_pmc_clk(hw); 2505 u32 val; 2506 2507 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; 2508 val &= PMC_CLK_OUT_MUX_MASK; 2509 2510 return val; 2511 } 2512 2513 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2514 { 2515 struct pmc_clk *clk = to_pmc_clk(hw); 2516 u32 val; 2517 2518 val = tegra_pmc_readl(pmc, clk->offs); 2519 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2520 val |= index << clk->mux_shift; 2521 tegra_pmc_writel(pmc, val, clk->offs); 2522 pmc_clk_fence_udelay(clk->offs); 2523 2524 return 0; 2525 } 2526 2527 static int pmc_clk_is_enabled(struct clk_hw *hw) 2528 { 2529 struct pmc_clk *clk = to_pmc_clk(hw); 2530 u32 val; 2531 2532 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); 2533 2534 return val ? 1 : 0; 2535 } 2536 2537 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state) 2538 { 2539 u32 val; 2540 2541 val = tegra_pmc_readl(pmc, offs); 2542 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2543 tegra_pmc_writel(pmc, val, offs); 2544 pmc_clk_fence_udelay(offs); 2545 } 2546 2547 static int pmc_clk_enable(struct clk_hw *hw) 2548 { 2549 struct pmc_clk *clk = to_pmc_clk(hw); 2550 2551 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); 2552 2553 return 0; 2554 } 2555 2556 static void pmc_clk_disable(struct clk_hw *hw) 2557 { 2558 struct pmc_clk *clk = to_pmc_clk(hw); 2559 2560 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); 2561 } 2562 2563 static const struct clk_ops pmc_clk_ops = { 2564 .get_parent = pmc_clk_mux_get_parent, 2565 .set_parent = pmc_clk_mux_set_parent, 2566 .determine_rate = __clk_mux_determine_rate, 2567 .is_enabled = pmc_clk_is_enabled, 2568 .enable = pmc_clk_enable, 2569 .disable = pmc_clk_disable, 2570 }; 2571 2572 static struct clk * 2573 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2574 const struct pmc_clk_init_data *data, 2575 unsigned long offset) 2576 { 2577 struct clk_init_data init; 2578 struct pmc_clk *pmc_clk; 2579 2580 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2581 if (!pmc_clk) 2582 return ERR_PTR(-ENOMEM); 2583 2584 init.name = data->name; 2585 init.ops = &pmc_clk_ops; 2586 init.parent_names = data->parents; 2587 init.num_parents = data->num_parents; 2588 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2589 CLK_SET_PARENT_GATE; 2590 2591 pmc_clk->hw.init = &init; 2592 pmc_clk->offs = offset; 2593 pmc_clk->mux_shift = data->mux_shift; 2594 pmc_clk->force_en_shift = data->force_en_shift; 2595 2596 return clk_register(NULL, &pmc_clk->hw); 2597 } 2598 2599 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2600 { 2601 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2602 2603 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; 2604 } 2605 2606 static int pmc_clk_gate_enable(struct clk_hw *hw) 2607 { 2608 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2609 2610 pmc_clk_set_state(gate->offs, gate->shift, 1); 2611 2612 return 0; 2613 } 2614 2615 static void pmc_clk_gate_disable(struct clk_hw *hw) 2616 { 2617 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2618 2619 pmc_clk_set_state(gate->offs, gate->shift, 0); 2620 } 2621 2622 static const struct clk_ops pmc_clk_gate_ops = { 2623 .is_enabled = pmc_clk_gate_is_enabled, 2624 .enable = pmc_clk_gate_enable, 2625 .disable = pmc_clk_gate_disable, 2626 }; 2627 2628 static struct clk * 2629 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2630 const char *parent_name, unsigned long offset, 2631 u32 shift) 2632 { 2633 struct clk_init_data init; 2634 struct pmc_clk_gate *gate; 2635 2636 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2637 if (!gate) 2638 return ERR_PTR(-ENOMEM); 2639 2640 init.name = name; 2641 init.ops = &pmc_clk_gate_ops; 2642 init.parent_names = &parent_name; 2643 init.num_parents = 1; 2644 init.flags = 0; 2645 2646 gate->hw.init = &init; 2647 gate->offs = offset; 2648 gate->shift = shift; 2649 2650 return clk_register(NULL, &gate->hw); 2651 } 2652 2653 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2654 struct device_node *np) 2655 { 2656 struct clk *clk; 2657 struct clk_onecell_data *clk_data; 2658 unsigned int num_clks; 2659 int i, err; 2660 2661 num_clks = pmc->soc->num_pmc_clks; 2662 if (pmc->soc->has_blink_output) 2663 num_clks += 1; 2664 2665 if (!num_clks) 2666 return; 2667 2668 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2669 if (!clk_data) 2670 return; 2671 2672 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2673 sizeof(*clk_data->clks), GFP_KERNEL); 2674 if (!clk_data->clks) 2675 return; 2676 2677 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2678 2679 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2680 clk_data->clks[i] = ERR_PTR(-ENOENT); 2681 2682 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2683 const struct pmc_clk_init_data *data; 2684 2685 data = pmc->soc->pmc_clks_data + i; 2686 2687 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2688 if (IS_ERR(clk)) { 2689 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2690 data->name, PTR_ERR_OR_ZERO(clk)); 2691 return; 2692 } 2693 2694 err = clk_register_clkdev(clk, data->name, NULL); 2695 if (err) { 2696 dev_warn(pmc->dev, 2697 "unable to register %s clock lookup: %d\n", 2698 data->name, err); 2699 return; 2700 } 2701 2702 clk_data->clks[data->clk_id] = clk; 2703 } 2704 2705 if (pmc->soc->has_blink_output) { 2706 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2707 clk = tegra_pmc_clk_gate_register(pmc, 2708 "pmc_blink_override", 2709 "clk_32k", 2710 PMC_DPD_PADS_ORIDE, 2711 PMC_DPD_PADS_ORIDE_BLINK); 2712 if (IS_ERR(clk)) { 2713 dev_warn(pmc->dev, 2714 "unable to register pmc_blink_override: %d\n", 2715 PTR_ERR_OR_ZERO(clk)); 2716 return; 2717 } 2718 2719 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 2720 "pmc_blink_override", 2721 PMC_CNTRL, 2722 PMC_CNTRL_BLINK_EN); 2723 if (IS_ERR(clk)) { 2724 dev_warn(pmc->dev, 2725 "unable to register pmc_blink: %d\n", 2726 PTR_ERR_OR_ZERO(clk)); 2727 return; 2728 } 2729 2730 err = clk_register_clkdev(clk, "pmc_blink", NULL); 2731 if (err) { 2732 dev_warn(pmc->dev, 2733 "unable to register pmc_blink lookup: %d\n", 2734 err); 2735 return; 2736 } 2737 2738 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 2739 } 2740 2741 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 2742 if (err) 2743 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 2744 err); 2745 } 2746 2747 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = { 2748 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO), 2749 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE), 2750 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE), 2751 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP), 2752 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG), 2753 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG), 2754 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1), 2755 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3), 2756 }; 2757 2758 static const struct regmap_access_table pmc_usb_sleepwalk_table = { 2759 .yes_ranges = pmc_usb_sleepwalk_ranges, 2760 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges), 2761 }; 2762 2763 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) 2764 { 2765 struct tegra_pmc *pmc = context; 2766 2767 *value = tegra_pmc_readl(pmc, offset); 2768 return 0; 2769 } 2770 2771 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) 2772 { 2773 struct tegra_pmc *pmc = context; 2774 2775 tegra_pmc_writel(pmc, value, offset); 2776 return 0; 2777 } 2778 2779 static const struct regmap_config usb_sleepwalk_regmap_config = { 2780 .name = "usb_sleepwalk", 2781 .reg_bits = 32, 2782 .val_bits = 32, 2783 .reg_stride = 4, 2784 .fast_io = true, 2785 .rd_table = &pmc_usb_sleepwalk_table, 2786 .wr_table = &pmc_usb_sleepwalk_table, 2787 .reg_read = tegra_pmc_regmap_readl, 2788 .reg_write = tegra_pmc_regmap_writel, 2789 }; 2790 2791 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) 2792 { 2793 struct regmap *regmap; 2794 int err; 2795 2796 if (pmc->soc->has_usb_sleepwalk) { 2797 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); 2798 if (IS_ERR(regmap)) { 2799 err = PTR_ERR(regmap); 2800 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); 2801 return err; 2802 } 2803 } 2804 2805 return 0; 2806 } 2807 2808 static void tegra_pmc_reset_suspend_mode(void *data) 2809 { 2810 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; 2811 } 2812 2813 static int tegra_pmc_probe(struct platform_device *pdev) 2814 { 2815 void __iomem *base; 2816 struct resource *res; 2817 int err; 2818 2819 /* 2820 * Early initialisation should have configured an initial 2821 * register mapping and setup the soc data pointer. If these 2822 * are not valid then something went badly wrong! 2823 */ 2824 if (WARN_ON(!pmc->base || !pmc->soc)) 2825 return -ENODEV; 2826 2827 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 2828 if (err < 0) 2829 return err; 2830 2831 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, 2832 NULL); 2833 if (err) 2834 return err; 2835 2836 /* take over the memory region from the early initialization */ 2837 base = devm_platform_ioremap_resource(pdev, 0); 2838 if (IS_ERR(base)) 2839 return PTR_ERR(base); 2840 2841 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 2842 if (res) { 2843 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 2844 if (IS_ERR(pmc->wake)) 2845 return PTR_ERR(pmc->wake); 2846 } else { 2847 pmc->wake = base; 2848 } 2849 2850 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 2851 if (res) { 2852 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 2853 if (IS_ERR(pmc->aotag)) 2854 return PTR_ERR(pmc->aotag); 2855 } else { 2856 pmc->aotag = base; 2857 } 2858 2859 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 2860 if (res) { 2861 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 2862 if (IS_ERR(pmc->scratch)) 2863 return PTR_ERR(pmc->scratch); 2864 } else { 2865 pmc->scratch = base; 2866 } 2867 2868 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 2869 if (IS_ERR(pmc->clk)) { 2870 err = PTR_ERR(pmc->clk); 2871 2872 if (err != -ENOENT) { 2873 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 2874 return err; 2875 } 2876 2877 pmc->clk = NULL; 2878 } 2879 2880 /* 2881 * PCLK clock rate can't be retrieved using CLK API because it 2882 * causes lockup if CPU enters LP2 idle state from some other 2883 * CLK notifier, hence we're caching the rate's value locally. 2884 */ 2885 if (pmc->clk) { 2886 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 2887 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); 2888 if (err) { 2889 dev_err(&pdev->dev, 2890 "failed to register clk notifier\n"); 2891 return err; 2892 } 2893 2894 pmc->rate = clk_get_rate(pmc->clk); 2895 } 2896 2897 pmc->dev = &pdev->dev; 2898 2899 tegra_pmc_init(pmc); 2900 2901 tegra_pmc_init_tsense_reset(pmc); 2902 2903 tegra_pmc_reset_sysfs_init(pmc); 2904 2905 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 2906 err = tegra_powergate_debugfs_init(); 2907 if (err < 0) 2908 goto cleanup_sysfs; 2909 } 2910 2911 err = devm_register_reboot_notifier(&pdev->dev, 2912 &tegra_pmc_reboot_notifier); 2913 if (err) { 2914 dev_err(&pdev->dev, "unable to register reboot notifier, %d\n", 2915 err); 2916 goto cleanup_debugfs; 2917 } 2918 2919 err = register_restart_handler(&tegra_pmc_restart_handler); 2920 if (err) { 2921 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 2922 err); 2923 goto cleanup_debugfs; 2924 } 2925 2926 err = tegra_pmc_pinctrl_init(pmc); 2927 if (err) 2928 goto cleanup_restart_handler; 2929 2930 err = tegra_pmc_regmap_init(pmc); 2931 if (err < 0) 2932 goto cleanup_restart_handler; 2933 2934 err = tegra_powergate_init(pmc, pdev->dev.of_node); 2935 if (err < 0) 2936 goto cleanup_powergates; 2937 2938 err = tegra_pmc_irq_init(pmc); 2939 if (err < 0) 2940 goto cleanup_powergates; 2941 2942 mutex_lock(&pmc->powergates_lock); 2943 iounmap(pmc->base); 2944 pmc->base = base; 2945 mutex_unlock(&pmc->powergates_lock); 2946 2947 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 2948 platform_set_drvdata(pdev, pmc); 2949 tegra_pm_init_suspend(); 2950 2951 return 0; 2952 2953 cleanup_powergates: 2954 tegra_powergate_remove_all(pdev->dev.of_node); 2955 cleanup_restart_handler: 2956 unregister_restart_handler(&tegra_pmc_restart_handler); 2957 cleanup_debugfs: 2958 debugfs_remove(pmc->debugfs); 2959 cleanup_sysfs: 2960 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 2961 device_remove_file(&pdev->dev, &dev_attr_reset_level); 2962 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); 2963 2964 return err; 2965 } 2966 2967 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 2968 static int tegra_pmc_suspend(struct device *dev) 2969 { 2970 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2971 2972 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 2973 2974 return 0; 2975 } 2976 2977 static int tegra_pmc_resume(struct device *dev) 2978 { 2979 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2980 2981 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 2982 2983 return 0; 2984 } 2985 2986 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 2987 2988 #endif 2989 2990 static const char * const tegra20_powergates[] = { 2991 [TEGRA_POWERGATE_CPU] = "cpu", 2992 [TEGRA_POWERGATE_3D] = "td", 2993 [TEGRA_POWERGATE_VENC] = "venc", 2994 [TEGRA_POWERGATE_VDEC] = "vdec", 2995 [TEGRA_POWERGATE_PCIE] = "pcie", 2996 [TEGRA_POWERGATE_L2] = "l2", 2997 [TEGRA_POWERGATE_MPE] = "mpe", 2998 }; 2999 3000 static const struct tegra_pmc_regs tegra20_pmc_regs = { 3001 .scratch0 = 0x50, 3002 .dpd_req = 0x1b8, 3003 .dpd_status = 0x1bc, 3004 .dpd2_req = 0x1c0, 3005 .dpd2_status = 0x1c4, 3006 .rst_status = 0x1b4, 3007 .rst_source_shift = 0x0, 3008 .rst_source_mask = 0x7, 3009 .rst_level_shift = 0x0, 3010 .rst_level_mask = 0x0, 3011 }; 3012 3013 static void tegra20_pmc_init(struct tegra_pmc *pmc) 3014 { 3015 u32 value, osc, pmu, off; 3016 3017 /* Always enable CPU power request */ 3018 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3019 value |= PMC_CNTRL_CPU_PWRREQ_OE; 3020 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3021 3022 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3023 3024 if (pmc->sysclkreq_high) 3025 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 3026 else 3027 value |= PMC_CNTRL_SYSCLK_POLARITY; 3028 3029 if (pmc->corereq_high) 3030 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 3031 else 3032 value |= PMC_CNTRL_PWRREQ_POLARITY; 3033 3034 /* configure the output polarity while the request is tristated */ 3035 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3036 3037 /* now enable the request */ 3038 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3039 value |= PMC_CNTRL_SYSCLK_OE; 3040 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3041 3042 /* program core timings which are applicable only for suspend state */ 3043 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 3044 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 3045 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 3046 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 3047 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 3048 PMC_COREPWRGOOD_TIMER); 3049 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 3050 } 3051 } 3052 3053 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3054 struct device_node *np, 3055 bool invert) 3056 { 3057 u32 value; 3058 3059 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3060 3061 if (invert) 3062 value |= PMC_CNTRL_INTR_POLARITY; 3063 else 3064 value &= ~PMC_CNTRL_INTR_POLARITY; 3065 3066 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3067 } 3068 3069 static const struct tegra_pmc_soc tegra20_pmc_soc = { 3070 .supports_core_domain = true, 3071 .num_powergates = ARRAY_SIZE(tegra20_powergates), 3072 .powergates = tegra20_powergates, 3073 .num_cpu_powergates = 0, 3074 .cpu_powergates = NULL, 3075 .has_tsense_reset = false, 3076 .has_gpu_clamps = false, 3077 .needs_mbist_war = false, 3078 .has_impl_33v_pwr = false, 3079 .maybe_tz_only = false, 3080 .num_io_pads = 0, 3081 .io_pads = NULL, 3082 .num_pin_descs = 0, 3083 .pin_descs = NULL, 3084 .regs = &tegra20_pmc_regs, 3085 .init = tegra20_pmc_init, 3086 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3087 .powergate_set = tegra20_powergate_set, 3088 .reset_sources = NULL, 3089 .num_reset_sources = 0, 3090 .reset_levels = NULL, 3091 .num_reset_levels = 0, 3092 .pmc_clks_data = NULL, 3093 .num_pmc_clks = 0, 3094 .has_blink_output = true, 3095 .has_usb_sleepwalk = true, 3096 }; 3097 3098 static const char * const tegra30_powergates[] = { 3099 [TEGRA_POWERGATE_CPU] = "cpu0", 3100 [TEGRA_POWERGATE_3D] = "td", 3101 [TEGRA_POWERGATE_VENC] = "venc", 3102 [TEGRA_POWERGATE_VDEC] = "vdec", 3103 [TEGRA_POWERGATE_PCIE] = "pcie", 3104 [TEGRA_POWERGATE_L2] = "l2", 3105 [TEGRA_POWERGATE_MPE] = "mpe", 3106 [TEGRA_POWERGATE_HEG] = "heg", 3107 [TEGRA_POWERGATE_SATA] = "sata", 3108 [TEGRA_POWERGATE_CPU1] = "cpu1", 3109 [TEGRA_POWERGATE_CPU2] = "cpu2", 3110 [TEGRA_POWERGATE_CPU3] = "cpu3", 3111 [TEGRA_POWERGATE_CELP] = "celp", 3112 [TEGRA_POWERGATE_3D1] = "td2", 3113 }; 3114 3115 static const u8 tegra30_cpu_powergates[] = { 3116 TEGRA_POWERGATE_CPU, 3117 TEGRA_POWERGATE_CPU1, 3118 TEGRA_POWERGATE_CPU2, 3119 TEGRA_POWERGATE_CPU3, 3120 }; 3121 3122 static const char * const tegra30_reset_sources[] = { 3123 "POWER_ON_RESET", 3124 "WATCHDOG", 3125 "SENSOR", 3126 "SW_MAIN", 3127 "LP0" 3128 }; 3129 3130 static const struct tegra_pmc_soc tegra30_pmc_soc = { 3131 .supports_core_domain = true, 3132 .num_powergates = ARRAY_SIZE(tegra30_powergates), 3133 .powergates = tegra30_powergates, 3134 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 3135 .cpu_powergates = tegra30_cpu_powergates, 3136 .has_tsense_reset = true, 3137 .has_gpu_clamps = false, 3138 .needs_mbist_war = false, 3139 .has_impl_33v_pwr = false, 3140 .maybe_tz_only = false, 3141 .num_io_pads = 0, 3142 .io_pads = NULL, 3143 .num_pin_descs = 0, 3144 .pin_descs = NULL, 3145 .regs = &tegra20_pmc_regs, 3146 .init = tegra20_pmc_init, 3147 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3148 .powergate_set = tegra20_powergate_set, 3149 .reset_sources = tegra30_reset_sources, 3150 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3151 .reset_levels = NULL, 3152 .num_reset_levels = 0, 3153 .pmc_clks_data = tegra_pmc_clks_data, 3154 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3155 .has_blink_output = true, 3156 .has_usb_sleepwalk = true, 3157 }; 3158 3159 static const char * const tegra114_powergates[] = { 3160 [TEGRA_POWERGATE_CPU] = "crail", 3161 [TEGRA_POWERGATE_3D] = "td", 3162 [TEGRA_POWERGATE_VENC] = "venc", 3163 [TEGRA_POWERGATE_VDEC] = "vdec", 3164 [TEGRA_POWERGATE_MPE] = "mpe", 3165 [TEGRA_POWERGATE_HEG] = "heg", 3166 [TEGRA_POWERGATE_CPU1] = "cpu1", 3167 [TEGRA_POWERGATE_CPU2] = "cpu2", 3168 [TEGRA_POWERGATE_CPU3] = "cpu3", 3169 [TEGRA_POWERGATE_CELP] = "celp", 3170 [TEGRA_POWERGATE_CPU0] = "cpu0", 3171 [TEGRA_POWERGATE_C0NC] = "c0nc", 3172 [TEGRA_POWERGATE_C1NC] = "c1nc", 3173 [TEGRA_POWERGATE_DIS] = "dis", 3174 [TEGRA_POWERGATE_DISB] = "disb", 3175 [TEGRA_POWERGATE_XUSBA] = "xusba", 3176 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3177 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3178 }; 3179 3180 static const u8 tegra114_cpu_powergates[] = { 3181 TEGRA_POWERGATE_CPU0, 3182 TEGRA_POWERGATE_CPU1, 3183 TEGRA_POWERGATE_CPU2, 3184 TEGRA_POWERGATE_CPU3, 3185 }; 3186 3187 static const struct tegra_pmc_soc tegra114_pmc_soc = { 3188 .supports_core_domain = false, 3189 .num_powergates = ARRAY_SIZE(tegra114_powergates), 3190 .powergates = tegra114_powergates, 3191 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 3192 .cpu_powergates = tegra114_cpu_powergates, 3193 .has_tsense_reset = true, 3194 .has_gpu_clamps = false, 3195 .needs_mbist_war = false, 3196 .has_impl_33v_pwr = false, 3197 .maybe_tz_only = false, 3198 .num_io_pads = 0, 3199 .io_pads = NULL, 3200 .num_pin_descs = 0, 3201 .pin_descs = NULL, 3202 .regs = &tegra20_pmc_regs, 3203 .init = tegra20_pmc_init, 3204 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3205 .powergate_set = tegra114_powergate_set, 3206 .reset_sources = tegra30_reset_sources, 3207 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3208 .reset_levels = NULL, 3209 .num_reset_levels = 0, 3210 .pmc_clks_data = tegra_pmc_clks_data, 3211 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3212 .has_blink_output = true, 3213 .has_usb_sleepwalk = true, 3214 }; 3215 3216 static const char * const tegra124_powergates[] = { 3217 [TEGRA_POWERGATE_CPU] = "crail", 3218 [TEGRA_POWERGATE_3D] = "3d", 3219 [TEGRA_POWERGATE_VENC] = "venc", 3220 [TEGRA_POWERGATE_PCIE] = "pcie", 3221 [TEGRA_POWERGATE_VDEC] = "vdec", 3222 [TEGRA_POWERGATE_MPE] = "mpe", 3223 [TEGRA_POWERGATE_HEG] = "heg", 3224 [TEGRA_POWERGATE_SATA] = "sata", 3225 [TEGRA_POWERGATE_CPU1] = "cpu1", 3226 [TEGRA_POWERGATE_CPU2] = "cpu2", 3227 [TEGRA_POWERGATE_CPU3] = "cpu3", 3228 [TEGRA_POWERGATE_CELP] = "celp", 3229 [TEGRA_POWERGATE_CPU0] = "cpu0", 3230 [TEGRA_POWERGATE_C0NC] = "c0nc", 3231 [TEGRA_POWERGATE_C1NC] = "c1nc", 3232 [TEGRA_POWERGATE_SOR] = "sor", 3233 [TEGRA_POWERGATE_DIS] = "dis", 3234 [TEGRA_POWERGATE_DISB] = "disb", 3235 [TEGRA_POWERGATE_XUSBA] = "xusba", 3236 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3237 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3238 [TEGRA_POWERGATE_VIC] = "vic", 3239 [TEGRA_POWERGATE_IRAM] = "iram", 3240 }; 3241 3242 static const u8 tegra124_cpu_powergates[] = { 3243 TEGRA_POWERGATE_CPU0, 3244 TEGRA_POWERGATE_CPU1, 3245 TEGRA_POWERGATE_CPU2, 3246 TEGRA_POWERGATE_CPU3, 3247 }; 3248 3249 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ 3250 ((struct tegra_io_pad_soc) { \ 3251 .id = (_id), \ 3252 .dpd = (_dpd), \ 3253 .voltage = (_voltage), \ 3254 .name = (_name), \ 3255 }) 3256 3257 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ 3258 ((struct pinctrl_pin_desc) { \ 3259 .number = (_id), \ 3260 .name = (_name) \ 3261 }) 3262 3263 #define TEGRA124_IO_PAD_TABLE(_pad) \ 3264 /* .id .dpd .voltage .name */ \ 3265 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3266 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ 3267 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ 3268 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ 3269 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3270 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ 3271 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ 3272 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3273 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 3274 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 3275 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 3276 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 3277 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3278 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ 3279 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 3280 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3281 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ 3282 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 3283 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 3284 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3285 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3286 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ 3287 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ 3288 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ 3289 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ 3290 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3291 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3292 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3293 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3294 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") 3295 3296 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 3297 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) 3298 }; 3299 3300 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 3301 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3302 }; 3303 3304 static const struct tegra_pmc_soc tegra124_pmc_soc = { 3305 .supports_core_domain = false, 3306 .num_powergates = ARRAY_SIZE(tegra124_powergates), 3307 .powergates = tegra124_powergates, 3308 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 3309 .cpu_powergates = tegra124_cpu_powergates, 3310 .has_tsense_reset = true, 3311 .has_gpu_clamps = true, 3312 .needs_mbist_war = false, 3313 .has_impl_33v_pwr = false, 3314 .maybe_tz_only = false, 3315 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 3316 .io_pads = tegra124_io_pads, 3317 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 3318 .pin_descs = tegra124_pin_descs, 3319 .regs = &tegra20_pmc_regs, 3320 .init = tegra20_pmc_init, 3321 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3322 .powergate_set = tegra114_powergate_set, 3323 .reset_sources = tegra30_reset_sources, 3324 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3325 .reset_levels = NULL, 3326 .num_reset_levels = 0, 3327 .pmc_clks_data = tegra_pmc_clks_data, 3328 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3329 .has_blink_output = true, 3330 .has_usb_sleepwalk = true, 3331 }; 3332 3333 static const char * const tegra210_powergates[] = { 3334 [TEGRA_POWERGATE_CPU] = "crail", 3335 [TEGRA_POWERGATE_3D] = "3d", 3336 [TEGRA_POWERGATE_VENC] = "venc", 3337 [TEGRA_POWERGATE_PCIE] = "pcie", 3338 [TEGRA_POWERGATE_MPE] = "mpe", 3339 [TEGRA_POWERGATE_SATA] = "sata", 3340 [TEGRA_POWERGATE_CPU1] = "cpu1", 3341 [TEGRA_POWERGATE_CPU2] = "cpu2", 3342 [TEGRA_POWERGATE_CPU3] = "cpu3", 3343 [TEGRA_POWERGATE_CPU0] = "cpu0", 3344 [TEGRA_POWERGATE_C0NC] = "c0nc", 3345 [TEGRA_POWERGATE_SOR] = "sor", 3346 [TEGRA_POWERGATE_DIS] = "dis", 3347 [TEGRA_POWERGATE_DISB] = "disb", 3348 [TEGRA_POWERGATE_XUSBA] = "xusba", 3349 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3350 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3351 [TEGRA_POWERGATE_VIC] = "vic", 3352 [TEGRA_POWERGATE_IRAM] = "iram", 3353 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3354 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3355 [TEGRA_POWERGATE_AUD] = "aud", 3356 [TEGRA_POWERGATE_DFD] = "dfd", 3357 [TEGRA_POWERGATE_VE2] = "ve2", 3358 }; 3359 3360 static const u8 tegra210_cpu_powergates[] = { 3361 TEGRA_POWERGATE_CPU0, 3362 TEGRA_POWERGATE_CPU1, 3363 TEGRA_POWERGATE_CPU2, 3364 TEGRA_POWERGATE_CPU3, 3365 }; 3366 3367 #define TEGRA210_IO_PAD_TABLE(_pad) \ 3368 /* .id .dpd .voltage .name */ \ 3369 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ 3370 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ 3371 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ 3372 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3373 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3374 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ 3375 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ 3376 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ 3377 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ 3378 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ 3379 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ 3380 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ 3381 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ 3382 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3383 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 3384 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 3385 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 3386 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ 3387 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ 3388 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ 3389 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 3390 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3391 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 3392 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3393 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 3394 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 3395 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3396 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ 3397 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ 3398 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ 3399 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ 3400 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ 3401 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ 3402 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3403 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3404 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3405 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ 3406 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") 3407 3408 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3409 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) 3410 }; 3411 3412 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3413 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3414 }; 3415 3416 static const char * const tegra210_reset_sources[] = { 3417 "POWER_ON_RESET", 3418 "WATCHDOG", 3419 "SENSOR", 3420 "SW_MAIN", 3421 "LP0", 3422 "AOTAG" 3423 }; 3424 3425 static const struct tegra_wake_event tegra210_wake_events[] = { 3426 TEGRA_WAKE_IRQ("rtc", 16, 2), 3427 TEGRA_WAKE_IRQ("pmu", 51, 86), 3428 }; 3429 3430 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3431 .supports_core_domain = false, 3432 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3433 .powergates = tegra210_powergates, 3434 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3435 .cpu_powergates = tegra210_cpu_powergates, 3436 .has_tsense_reset = true, 3437 .has_gpu_clamps = true, 3438 .needs_mbist_war = true, 3439 .has_impl_33v_pwr = false, 3440 .maybe_tz_only = true, 3441 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3442 .io_pads = tegra210_io_pads, 3443 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3444 .pin_descs = tegra210_pin_descs, 3445 .regs = &tegra20_pmc_regs, 3446 .init = tegra20_pmc_init, 3447 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3448 .powergate_set = tegra114_powergate_set, 3449 .irq_set_wake = tegra210_pmc_irq_set_wake, 3450 .irq_set_type = tegra210_pmc_irq_set_type, 3451 .reset_sources = tegra210_reset_sources, 3452 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3453 .reset_levels = NULL, 3454 .num_reset_levels = 0, 3455 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3456 .wake_events = tegra210_wake_events, 3457 .pmc_clks_data = tegra_pmc_clks_data, 3458 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3459 .has_blink_output = true, 3460 .has_usb_sleepwalk = true, 3461 }; 3462 3463 #define TEGRA186_IO_PAD_TABLE(_pad) \ 3464 /* .id .dpd .voltage .name */ \ 3465 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3466 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3467 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3468 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3469 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 3470 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 3471 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3472 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 3473 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3474 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3475 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3476 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ 3477 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3478 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3479 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3480 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 3481 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 3482 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 3483 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3484 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ 3485 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 3486 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 3487 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ 3488 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ 3489 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ 3490 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 3491 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 3492 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 3493 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 3494 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 3495 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 3496 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ 3497 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 3498 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 3499 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 3500 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 3501 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 3502 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 3503 3504 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3505 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) 3506 }; 3507 3508 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 3509 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3510 }; 3511 3512 static const struct tegra_pmc_regs tegra186_pmc_regs = { 3513 .scratch0 = 0x2000, 3514 .dpd_req = 0x74, 3515 .dpd_status = 0x78, 3516 .dpd2_req = 0x7c, 3517 .dpd2_status = 0x80, 3518 .rst_status = 0x70, 3519 .rst_source_shift = 0x2, 3520 .rst_source_mask = 0x3c, 3521 .rst_level_shift = 0x0, 3522 .rst_level_mask = 0x3, 3523 }; 3524 3525 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3526 struct device_node *np, 3527 bool invert) 3528 { 3529 struct resource regs; 3530 void __iomem *wake; 3531 u32 value; 3532 int index; 3533 3534 index = of_property_match_string(np, "reg-names", "wake"); 3535 if (index < 0) { 3536 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 3537 return; 3538 } 3539 3540 of_address_to_resource(np, index, ®s); 3541 3542 wake = ioremap(regs.start, resource_size(®s)); 3543 if (!wake) { 3544 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 3545 return; 3546 } 3547 3548 value = readl(wake + WAKE_AOWAKE_CTRL); 3549 3550 if (invert) 3551 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 3552 else 3553 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 3554 3555 writel(value, wake + WAKE_AOWAKE_CTRL); 3556 3557 iounmap(wake); 3558 } 3559 3560 static const char * const tegra186_reset_sources[] = { 3561 "SYS_RESET", 3562 "AOWDT", 3563 "MCCPLEXWDT", 3564 "BPMPWDT", 3565 "SCEWDT", 3566 "SPEWDT", 3567 "APEWDT", 3568 "BCCPLEXWDT", 3569 "SENSOR", 3570 "AOTAG", 3571 "VFSENSOR", 3572 "SWREST", 3573 "SC7", 3574 "HSM", 3575 "CORESIGHT" 3576 }; 3577 3578 static const char * const tegra186_reset_levels[] = { 3579 "L0", "L1", "L2", "WARM" 3580 }; 3581 3582 static const struct tegra_wake_event tegra186_wake_events[] = { 3583 TEGRA_WAKE_IRQ("pmu", 24, 209), 3584 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 3585 TEGRA_WAKE_IRQ("rtc", 73, 10), 3586 }; 3587 3588 static const struct tegra_pmc_soc tegra186_pmc_soc = { 3589 .supports_core_domain = false, 3590 .num_powergates = 0, 3591 .powergates = NULL, 3592 .num_cpu_powergates = 0, 3593 .cpu_powergates = NULL, 3594 .has_tsense_reset = false, 3595 .has_gpu_clamps = false, 3596 .needs_mbist_war = false, 3597 .has_impl_33v_pwr = true, 3598 .maybe_tz_only = false, 3599 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 3600 .io_pads = tegra186_io_pads, 3601 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 3602 .pin_descs = tegra186_pin_descs, 3603 .regs = &tegra186_pmc_regs, 3604 .init = NULL, 3605 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3606 .irq_set_wake = tegra186_pmc_irq_set_wake, 3607 .irq_set_type = tegra186_pmc_irq_set_type, 3608 .reset_sources = tegra186_reset_sources, 3609 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 3610 .reset_levels = tegra186_reset_levels, 3611 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3612 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 3613 .wake_events = tegra186_wake_events, 3614 .pmc_clks_data = NULL, 3615 .num_pmc_clks = 0, 3616 .has_blink_output = false, 3617 .has_usb_sleepwalk = false, 3618 }; 3619 3620 #define TEGRA194_IO_PAD_TABLE(_pad) \ 3621 /* .id .dpd .voltage .name */ \ 3622 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3623 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3624 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3625 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 3626 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 3627 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3628 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 3629 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \ 3630 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \ 3631 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \ 3632 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \ 3633 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \ 3634 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3635 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \ 3636 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \ 3637 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3638 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \ 3639 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \ 3640 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \ 3641 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \ 3642 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \ 3643 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \ 3644 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \ 3645 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 3646 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \ 3647 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \ 3648 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 3649 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 3650 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3651 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \ 3652 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \ 3653 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \ 3654 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 3655 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \ 3656 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 3657 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 3658 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 3659 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 3660 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 3661 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 3662 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 3663 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \ 3664 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \ 3665 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 3666 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 3667 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 3668 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 3669 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 3670 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 3671 3672 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 3673 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD) 3674 }; 3675 3676 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 3677 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3678 }; 3679 3680 static const struct tegra_pmc_regs tegra194_pmc_regs = { 3681 .scratch0 = 0x2000, 3682 .dpd_req = 0x74, 3683 .dpd_status = 0x78, 3684 .dpd2_req = 0x7c, 3685 .dpd2_status = 0x80, 3686 .rst_status = 0x70, 3687 .rst_source_shift = 0x2, 3688 .rst_source_mask = 0x7c, 3689 .rst_level_shift = 0x0, 3690 .rst_level_mask = 0x3, 3691 }; 3692 3693 static const char * const tegra194_reset_sources[] = { 3694 "SYS_RESET_N", 3695 "AOWDT", 3696 "BCCPLEXWDT", 3697 "BPMPWDT", 3698 "SCEWDT", 3699 "SPEWDT", 3700 "APEWDT", 3701 "LCCPLEXWDT", 3702 "SENSOR", 3703 "AOTAG", 3704 "VFSENSOR", 3705 "MAINSWRST", 3706 "SC7", 3707 "HSM", 3708 "CSITE", 3709 "RCEWDT", 3710 "PVA0WDT", 3711 "PVA1WDT", 3712 "L1A_ASYNC", 3713 "BPMPBOOT", 3714 "FUSECRC", 3715 }; 3716 3717 static const struct tegra_wake_event tegra194_wake_events[] = { 3718 TEGRA_WAKE_IRQ("pmu", 24, 209), 3719 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 3720 TEGRA_WAKE_IRQ("rtc", 73, 10), 3721 }; 3722 3723 static const struct tegra_pmc_soc tegra194_pmc_soc = { 3724 .supports_core_domain = false, 3725 .num_powergates = 0, 3726 .powergates = NULL, 3727 .num_cpu_powergates = 0, 3728 .cpu_powergates = NULL, 3729 .has_tsense_reset = false, 3730 .has_gpu_clamps = false, 3731 .needs_mbist_war = false, 3732 .has_impl_33v_pwr = true, 3733 .maybe_tz_only = false, 3734 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 3735 .io_pads = tegra194_io_pads, 3736 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 3737 .pin_descs = tegra194_pin_descs, 3738 .regs = &tegra194_pmc_regs, 3739 .init = NULL, 3740 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3741 .irq_set_wake = tegra186_pmc_irq_set_wake, 3742 .irq_set_type = tegra186_pmc_irq_set_type, 3743 .reset_sources = tegra194_reset_sources, 3744 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 3745 .reset_levels = tegra186_reset_levels, 3746 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3747 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 3748 .wake_events = tegra194_wake_events, 3749 .pmc_clks_data = NULL, 3750 .num_pmc_clks = 0, 3751 .has_blink_output = false, 3752 .has_usb_sleepwalk = false, 3753 }; 3754 3755 static const struct tegra_pmc_regs tegra234_pmc_regs = { 3756 .scratch0 = 0x2000, 3757 .dpd_req = 0, 3758 .dpd_status = 0, 3759 .dpd2_req = 0, 3760 .dpd2_status = 0, 3761 .rst_status = 0x70, 3762 .rst_source_shift = 0x2, 3763 .rst_source_mask = 0xfc, 3764 .rst_level_shift = 0x0, 3765 .rst_level_mask = 0x3, 3766 }; 3767 3768 static const char * const tegra234_reset_sources[] = { 3769 "SYS_RESET_N", 3770 "AOWDT", 3771 "BCCPLEXWDT", 3772 "BPMPWDT", 3773 "SCEWDT", 3774 "SPEWDT", 3775 "APEWDT", 3776 "LCCPLEXWDT", 3777 "SENSOR", 3778 "AOTAG", 3779 "VFSENSOR", 3780 "MAINSWRST", 3781 "SC7", 3782 "HSM", 3783 "CSITE", 3784 "RCEWDT", 3785 "PVA0WDT", 3786 "PVA1WDT", 3787 "L1A_ASYNC", 3788 "BPMPBOOT", 3789 "FUSECRC", 3790 }; 3791 3792 static const struct tegra_wake_event tegra234_wake_events[] = { 3793 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), 3794 TEGRA_WAKE_IRQ("rtc", 73, 10), 3795 }; 3796 3797 static const struct tegra_pmc_soc tegra234_pmc_soc = { 3798 .supports_core_domain = false, 3799 .num_powergates = 0, 3800 .powergates = NULL, 3801 .num_cpu_powergates = 0, 3802 .cpu_powergates = NULL, 3803 .has_tsense_reset = false, 3804 .has_gpu_clamps = false, 3805 .needs_mbist_war = false, 3806 .has_impl_33v_pwr = true, 3807 .maybe_tz_only = false, 3808 .num_io_pads = 0, 3809 .io_pads = NULL, 3810 .num_pin_descs = 0, 3811 .pin_descs = NULL, 3812 .regs = &tegra234_pmc_regs, 3813 .init = NULL, 3814 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3815 .irq_set_wake = tegra186_pmc_irq_set_wake, 3816 .irq_set_type = tegra186_pmc_irq_set_type, 3817 .reset_sources = tegra234_reset_sources, 3818 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 3819 .reset_levels = tegra186_reset_levels, 3820 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3821 .num_wake_events = ARRAY_SIZE(tegra234_wake_events), 3822 .wake_events = tegra234_wake_events, 3823 .pmc_clks_data = NULL, 3824 .num_pmc_clks = 0, 3825 .has_blink_output = false, 3826 }; 3827 3828 static const struct of_device_id tegra_pmc_match[] = { 3829 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 3830 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 3831 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 3832 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 3833 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 3834 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 3835 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 3836 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 3837 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 3838 { } 3839 }; 3840 3841 static void tegra_pmc_sync_state(struct device *dev) 3842 { 3843 int err; 3844 3845 /* 3846 * Newer device-trees have power domains, but we need to prepare all 3847 * device drivers with runtime PM and OPP support first, otherwise 3848 * state syncing is unsafe. 3849 */ 3850 if (!pmc->soc->supports_core_domain) 3851 return; 3852 3853 /* 3854 * Older device-trees don't have core PD, and thus, there are 3855 * no dependencies that will block the state syncing. We shouldn't 3856 * mark the domain as synced in this case. 3857 */ 3858 if (!pmc->core_domain_registered) 3859 return; 3860 3861 pmc->core_domain_state_synced = true; 3862 3863 /* this is a no-op if core regulator isn't used */ 3864 mutex_lock(&pmc->powergates_lock); 3865 err = dev_pm_opp_sync_regulators(dev); 3866 mutex_unlock(&pmc->powergates_lock); 3867 3868 if (err) 3869 dev_err(dev, "failed to sync regulators: %d\n", err); 3870 } 3871 3872 static struct platform_driver tegra_pmc_driver = { 3873 .driver = { 3874 .name = "tegra-pmc", 3875 .suppress_bind_attrs = true, 3876 .of_match_table = tegra_pmc_match, 3877 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3878 .pm = &tegra_pmc_pm_ops, 3879 #endif 3880 .sync_state = tegra_pmc_sync_state, 3881 }, 3882 .probe = tegra_pmc_probe, 3883 }; 3884 builtin_platform_driver(tegra_pmc_driver); 3885 3886 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 3887 { 3888 u32 value, saved; 3889 3890 saved = readl(pmc->base + pmc->soc->regs->scratch0); 3891 value = saved ^ 0xffffffff; 3892 3893 if (value == 0xffffffff) 3894 value = 0xdeadbeef; 3895 3896 /* write pattern and read it back */ 3897 writel(value, pmc->base + pmc->soc->regs->scratch0); 3898 value = readl(pmc->base + pmc->soc->regs->scratch0); 3899 3900 /* if we read all-zeroes, access is restricted to TZ only */ 3901 if (value == 0) { 3902 pr_info("access to PMC is restricted to TZ\n"); 3903 return true; 3904 } 3905 3906 /* restore original value */ 3907 writel(saved, pmc->base + pmc->soc->regs->scratch0); 3908 3909 return false; 3910 } 3911 3912 /* 3913 * Early initialization to allow access to registers in the very early boot 3914 * process. 3915 */ 3916 static int __init tegra_pmc_early_init(void) 3917 { 3918 const struct of_device_id *match; 3919 struct device_node *np; 3920 struct resource regs; 3921 unsigned int i; 3922 bool invert; 3923 3924 mutex_init(&pmc->powergates_lock); 3925 3926 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 3927 if (!np) { 3928 /* 3929 * Fall back to legacy initialization for 32-bit ARM only. All 3930 * 64-bit ARM device tree files for Tegra are required to have 3931 * a PMC node. 3932 * 3933 * This is for backwards-compatibility with old device trees 3934 * that didn't contain a PMC node. Note that in this case the 3935 * SoC data can't be matched and therefore powergating is 3936 * disabled. 3937 */ 3938 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 3939 pr_warn("DT node not found, powergating disabled\n"); 3940 3941 regs.start = 0x7000e400; 3942 regs.end = 0x7000e7ff; 3943 regs.flags = IORESOURCE_MEM; 3944 3945 pr_warn("Using memory region %pR\n", ®s); 3946 } else { 3947 /* 3948 * At this point we're not running on Tegra, so play 3949 * nice with multi-platform kernels. 3950 */ 3951 return 0; 3952 } 3953 } else { 3954 /* 3955 * Extract information from the device tree if we've found a 3956 * matching node. 3957 */ 3958 if (of_address_to_resource(np, 0, ®s) < 0) { 3959 pr_err("failed to get PMC registers\n"); 3960 of_node_put(np); 3961 return -ENXIO; 3962 } 3963 } 3964 3965 pmc->base = ioremap(regs.start, resource_size(®s)); 3966 if (!pmc->base) { 3967 pr_err("failed to map PMC registers\n"); 3968 of_node_put(np); 3969 return -ENXIO; 3970 } 3971 3972 if (np) { 3973 pmc->soc = match->data; 3974 3975 if (pmc->soc->maybe_tz_only) 3976 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 3977 3978 /* Create a bitmap of the available and valid partitions */ 3979 for (i = 0; i < pmc->soc->num_powergates; i++) 3980 if (pmc->soc->powergates[i]) 3981 set_bit(i, pmc->powergates_available); 3982 3983 /* 3984 * Invert the interrupt polarity if a PMC device tree node 3985 * exists and contains the nvidia,invert-interrupt property. 3986 */ 3987 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 3988 3989 pmc->soc->setup_irq_polarity(pmc, np, invert); 3990 3991 of_node_put(np); 3992 } 3993 3994 return 0; 3995 } 3996 early_initcall(tegra_pmc_early_init); 3997