1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/arm-smccc.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 20 #include <linux/debugfs.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/io.h> 27 #include <linux/iopoll.h> 28 #include <linux/irqdomain.h> 29 #include <linux/irq.h> 30 #include <linux/kernel.h> 31 #include <linux/of_address.h> 32 #include <linux/of_clk.h> 33 #include <linux/of.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_platform.h> 36 #include <linux/pinctrl/pinconf-generic.h> 37 #include <linux/pinctrl/pinconf.h> 38 #include <linux/pinctrl/pinctrl.h> 39 #include <linux/platform_device.h> 40 #include <linux/pm_domain.h> 41 #include <linux/reboot.h> 42 #include <linux/reset.h> 43 #include <linux/seq_file.h> 44 #include <linux/slab.h> 45 #include <linux/spinlock.h> 46 47 #include <soc/tegra/common.h> 48 #include <soc/tegra/fuse.h> 49 #include <soc/tegra/pmc.h> 50 51 #include <dt-bindings/interrupt-controller/arm-gic.h> 52 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 53 #include <dt-bindings/gpio/tegra186-gpio.h> 54 #include <dt-bindings/gpio/tegra194-gpio.h> 55 #include <dt-bindings/soc/tegra-pmc.h> 56 57 #define PMC_CNTRL 0x0 58 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 59 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 60 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 61 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 62 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 63 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 64 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 65 #define PMC_CNTRL_BLINK_EN 7 66 #define PMC_CNTRL_MAIN_RST BIT(4) 67 68 #define PMC_WAKE_MASK 0x0c 69 #define PMC_WAKE_LEVEL 0x10 70 #define PMC_WAKE_STATUS 0x14 71 #define PMC_SW_WAKE_STATUS 0x18 72 #define PMC_DPD_PADS_ORIDE 0x1c 73 #define PMC_DPD_PADS_ORIDE_BLINK 20 74 75 #define DPD_SAMPLE 0x020 76 #define DPD_SAMPLE_ENABLE BIT(0) 77 #define DPD_SAMPLE_DISABLE (0 << 0) 78 79 #define PWRGATE_TOGGLE 0x30 80 #define PWRGATE_TOGGLE_START BIT(8) 81 82 #define REMOVE_CLAMPING 0x34 83 84 #define PWRGATE_STATUS 0x38 85 86 #define PMC_BLINK_TIMER 0x40 87 #define PMC_IMPL_E_33V_PWR 0x40 88 89 #define PMC_PWR_DET 0x48 90 91 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 92 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 93 #define PMC_SCRATCH0_MODE_RCM BIT(1) 94 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 95 PMC_SCRATCH0_MODE_BOOTLOADER | \ 96 PMC_SCRATCH0_MODE_RCM) 97 98 #define PMC_CPUPWRGOOD_TIMER 0xc8 99 #define PMC_CPUPWROFF_TIMER 0xcc 100 #define PMC_COREPWRGOOD_TIMER 0x3c 101 #define PMC_COREPWROFF_TIMER 0xe0 102 103 #define PMC_PWR_DET_VALUE 0xe4 104 105 #define PMC_SCRATCH41 0x140 106 107 #define PMC_WAKE2_MASK 0x160 108 #define PMC_WAKE2_LEVEL 0x164 109 #define PMC_WAKE2_STATUS 0x168 110 #define PMC_SW_WAKE2_STATUS 0x16c 111 112 #define PMC_CLK_OUT_CNTRL 0x1a8 113 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 114 #define PMC_SENSOR_CTRL 0x1b0 115 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 116 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 117 118 #define PMC_RST_STATUS_POR 0 119 #define PMC_RST_STATUS_WATCHDOG 1 120 #define PMC_RST_STATUS_SENSOR 2 121 #define PMC_RST_STATUS_SW_MAIN 3 122 #define PMC_RST_STATUS_LP0 4 123 #define PMC_RST_STATUS_AOTAG 5 124 125 #define IO_DPD_REQ 0x1b8 126 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 127 #define IO_DPD_REQ_CODE_OFF (1U << 30) 128 #define IO_DPD_REQ_CODE_ON (2U << 30) 129 #define IO_DPD_REQ_CODE_MASK (3U << 30) 130 131 #define IO_DPD_STATUS 0x1bc 132 #define IO_DPD2_REQ 0x1c0 133 #define IO_DPD2_STATUS 0x1c4 134 #define SEL_DPD_TIM 0x1c8 135 136 #define PMC_SCRATCH54 0x258 137 #define PMC_SCRATCH54_DATA_SHIFT 8 138 #define PMC_SCRATCH54_ADDR_SHIFT 0 139 140 #define PMC_SCRATCH55 0x25c 141 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 142 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 143 #define PMC_SCRATCH55_PINMUX_SHIFT 24 144 #define PMC_SCRATCH55_16BITOP BIT(15) 145 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 146 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 147 148 #define GPU_RG_CNTRL 0x2d4 149 150 /* Tegra186 and later */ 151 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 152 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 153 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 154 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 155 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 156 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 157 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 158 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 159 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 160 161 #define WAKE_AOWAKE_CTRL 0x4f4 162 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 163 164 /* for secure PMC */ 165 #define TEGRA_SMC_PMC 0xc2fffe00 166 #define TEGRA_SMC_PMC_READ 0xaa 167 #define TEGRA_SMC_PMC_WRITE 0xbb 168 169 struct pmc_clk { 170 struct clk_hw hw; 171 unsigned long offs; 172 u32 mux_shift; 173 u32 force_en_shift; 174 }; 175 176 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 177 178 struct pmc_clk_gate { 179 struct clk_hw hw; 180 unsigned long offs; 181 u32 shift; 182 }; 183 184 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 185 186 struct pmc_clk_init_data { 187 char *name; 188 const char *const *parents; 189 int num_parents; 190 int clk_id; 191 u8 mux_shift; 192 u8 force_en_shift; 193 }; 194 195 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 196 "osc_div4", "extern1", 197 }; 198 199 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 200 "osc_div4", "extern2", 201 }; 202 203 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 204 "osc_div4", "extern3", 205 }; 206 207 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 208 { 209 .name = "pmc_clk_out_1", 210 .parents = clk_out1_parents, 211 .num_parents = ARRAY_SIZE(clk_out1_parents), 212 .clk_id = TEGRA_PMC_CLK_OUT_1, 213 .mux_shift = 6, 214 .force_en_shift = 2, 215 }, 216 { 217 .name = "pmc_clk_out_2", 218 .parents = clk_out2_parents, 219 .num_parents = ARRAY_SIZE(clk_out2_parents), 220 .clk_id = TEGRA_PMC_CLK_OUT_2, 221 .mux_shift = 14, 222 .force_en_shift = 10, 223 }, 224 { 225 .name = "pmc_clk_out_3", 226 .parents = clk_out3_parents, 227 .num_parents = ARRAY_SIZE(clk_out3_parents), 228 .clk_id = TEGRA_PMC_CLK_OUT_3, 229 .mux_shift = 22, 230 .force_en_shift = 18, 231 }, 232 }; 233 234 struct tegra_powergate { 235 struct generic_pm_domain genpd; 236 struct tegra_pmc *pmc; 237 unsigned int id; 238 struct clk **clks; 239 unsigned int num_clks; 240 struct reset_control *reset; 241 }; 242 243 struct tegra_io_pad_soc { 244 enum tegra_io_pad id; 245 unsigned int dpd; 246 unsigned int voltage; 247 const char *name; 248 }; 249 250 struct tegra_pmc_regs { 251 unsigned int scratch0; 252 unsigned int dpd_req; 253 unsigned int dpd_status; 254 unsigned int dpd2_req; 255 unsigned int dpd2_status; 256 unsigned int rst_status; 257 unsigned int rst_source_shift; 258 unsigned int rst_source_mask; 259 unsigned int rst_level_shift; 260 unsigned int rst_level_mask; 261 }; 262 263 struct tegra_wake_event { 264 const char *name; 265 unsigned int id; 266 unsigned int irq; 267 struct { 268 unsigned int instance; 269 unsigned int pin; 270 } gpio; 271 }; 272 273 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 274 { \ 275 .name = _name, \ 276 .id = _id, \ 277 .irq = _irq, \ 278 .gpio = { \ 279 .instance = UINT_MAX, \ 280 .pin = UINT_MAX, \ 281 }, \ 282 } 283 284 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 285 { \ 286 .name = _name, \ 287 .id = _id, \ 288 .irq = 0, \ 289 .gpio = { \ 290 .instance = _instance, \ 291 .pin = _pin, \ 292 }, \ 293 } 294 295 struct tegra_pmc_soc { 296 unsigned int num_powergates; 297 const char *const *powergates; 298 unsigned int num_cpu_powergates; 299 const u8 *cpu_powergates; 300 301 bool has_tsense_reset; 302 bool has_gpu_clamps; 303 bool needs_mbist_war; 304 bool has_impl_33v_pwr; 305 bool maybe_tz_only; 306 307 const struct tegra_io_pad_soc *io_pads; 308 unsigned int num_io_pads; 309 310 const struct pinctrl_pin_desc *pin_descs; 311 unsigned int num_pin_descs; 312 313 const struct tegra_pmc_regs *regs; 314 void (*init)(struct tegra_pmc *pmc); 315 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 316 struct device_node *np, 317 bool invert); 318 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 319 int (*irq_set_type)(struct irq_data *data, unsigned int type); 320 321 const char * const *reset_sources; 322 unsigned int num_reset_sources; 323 const char * const *reset_levels; 324 unsigned int num_reset_levels; 325 326 /* 327 * These describe events that can wake the system from sleep (i.e. 328 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 329 * are dealt with in the LIC. 330 */ 331 const struct tegra_wake_event *wake_events; 332 unsigned int num_wake_events; 333 334 const struct pmc_clk_init_data *pmc_clks_data; 335 unsigned int num_pmc_clks; 336 bool has_blink_output; 337 }; 338 339 static const char * const tegra186_reset_sources[] = { 340 "SYS_RESET", 341 "AOWDT", 342 "MCCPLEXWDT", 343 "BPMPWDT", 344 "SCEWDT", 345 "SPEWDT", 346 "APEWDT", 347 "BCCPLEXWDT", 348 "SENSOR", 349 "AOTAG", 350 "VFSENSOR", 351 "SWREST", 352 "SC7", 353 "HSM", 354 "CORESIGHT" 355 }; 356 357 static const char * const tegra186_reset_levels[] = { 358 "L0", "L1", "L2", "WARM" 359 }; 360 361 static const char * const tegra30_reset_sources[] = { 362 "POWER_ON_RESET", 363 "WATCHDOG", 364 "SENSOR", 365 "SW_MAIN", 366 "LP0" 367 }; 368 369 static const char * const tegra210_reset_sources[] = { 370 "POWER_ON_RESET", 371 "WATCHDOG", 372 "SENSOR", 373 "SW_MAIN", 374 "LP0", 375 "AOTAG" 376 }; 377 378 /** 379 * struct tegra_pmc - NVIDIA Tegra PMC 380 * @dev: pointer to PMC device structure 381 * @base: pointer to I/O remapped register region 382 * @wake: pointer to I/O remapped region for WAKE registers 383 * @aotag: pointer to I/O remapped region for AOTAG registers 384 * @scratch: pointer to I/O remapped region for scratch registers 385 * @clk: pointer to pclk clock 386 * @soc: pointer to SoC data structure 387 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 388 * @debugfs: pointer to debugfs entry 389 * @rate: currently configured rate of pclk 390 * @suspend_mode: lowest suspend mode available 391 * @cpu_good_time: CPU power good time (in microseconds) 392 * @cpu_off_time: CPU power off time (in microsecends) 393 * @core_osc_time: core power good OSC time (in microseconds) 394 * @core_pmu_time: core power good PMU time (in microseconds) 395 * @core_off_time: core power off time (in microseconds) 396 * @corereq_high: core power request is active-high 397 * @sysclkreq_high: system clock request is active-high 398 * @combined_req: combined power request for CPU & core 399 * @cpu_pwr_good_en: CPU power good signal is enabled 400 * @lp0_vec_phys: physical base address of the LP0 warm boot code 401 * @lp0_vec_size: size of the LP0 warm boot code 402 * @powergates_available: Bitmap of available power gates 403 * @powergates_lock: mutex for power gate register access 404 * @pctl_dev: pin controller exposed by the PMC 405 * @domain: IRQ domain provided by the PMC 406 * @irq: chip implementation for the IRQ domain 407 * @clk_nb: pclk clock changes handler 408 */ 409 struct tegra_pmc { 410 struct device *dev; 411 void __iomem *base; 412 void __iomem *wake; 413 void __iomem *aotag; 414 void __iomem *scratch; 415 struct clk *clk; 416 struct dentry *debugfs; 417 418 const struct tegra_pmc_soc *soc; 419 bool tz_only; 420 421 unsigned long rate; 422 423 enum tegra_suspend_mode suspend_mode; 424 u32 cpu_good_time; 425 u32 cpu_off_time; 426 u32 core_osc_time; 427 u32 core_pmu_time; 428 u32 core_off_time; 429 bool corereq_high; 430 bool sysclkreq_high; 431 bool combined_req; 432 bool cpu_pwr_good_en; 433 u32 lp0_vec_phys; 434 u32 lp0_vec_size; 435 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 436 437 struct mutex powergates_lock; 438 439 struct pinctrl_dev *pctl_dev; 440 441 struct irq_domain *domain; 442 struct irq_chip irq; 443 444 struct notifier_block clk_nb; 445 }; 446 447 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 448 .base = NULL, 449 .suspend_mode = TEGRA_SUSPEND_NONE, 450 }; 451 452 static inline struct tegra_powergate * 453 to_powergate(struct generic_pm_domain *domain) 454 { 455 return container_of(domain, struct tegra_powergate, genpd); 456 } 457 458 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 459 { 460 struct arm_smccc_res res; 461 462 if (pmc->tz_only) { 463 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 464 0, 0, 0, &res); 465 if (res.a0) { 466 if (pmc->dev) 467 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 468 __func__, res.a0); 469 else 470 pr_warn("%s(): SMC failed: %lu\n", __func__, 471 res.a0); 472 } 473 474 return res.a1; 475 } 476 477 return readl(pmc->base + offset); 478 } 479 480 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 481 unsigned long offset) 482 { 483 struct arm_smccc_res res; 484 485 if (pmc->tz_only) { 486 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 487 value, 0, 0, 0, 0, &res); 488 if (res.a0) { 489 if (pmc->dev) 490 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 491 __func__, res.a0); 492 else 493 pr_warn("%s(): SMC failed: %lu\n", __func__, 494 res.a0); 495 } 496 } else { 497 writel(value, pmc->base + offset); 498 } 499 } 500 501 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 502 { 503 if (pmc->tz_only) 504 return tegra_pmc_readl(pmc, offset); 505 506 return readl(pmc->scratch + offset); 507 } 508 509 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 510 unsigned long offset) 511 { 512 if (pmc->tz_only) 513 tegra_pmc_writel(pmc, value, offset); 514 else 515 writel(value, pmc->scratch + offset); 516 } 517 518 /* 519 * TODO Figure out a way to call this with the struct tegra_pmc * passed in. 520 * This currently doesn't work because readx_poll_timeout() can only operate 521 * on functions that take a single argument. 522 */ 523 static inline bool tegra_powergate_state(int id) 524 { 525 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 526 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 527 else 528 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 529 } 530 531 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 532 { 533 return (pmc->soc && pmc->soc->powergates[id]); 534 } 535 536 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 537 { 538 return test_bit(id, pmc->powergates_available); 539 } 540 541 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 542 { 543 unsigned int i; 544 545 if (!pmc || !pmc->soc || !name) 546 return -EINVAL; 547 548 for (i = 0; i < pmc->soc->num_powergates; i++) { 549 if (!tegra_powergate_is_valid(pmc, i)) 550 continue; 551 552 if (!strcmp(name, pmc->soc->powergates[i])) 553 return i; 554 } 555 556 return -ENODEV; 557 } 558 559 /** 560 * tegra_powergate_set() - set the state of a partition 561 * @pmc: power management controller 562 * @id: partition ID 563 * @new_state: new state of the partition 564 */ 565 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 566 bool new_state) 567 { 568 bool status; 569 int err; 570 571 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 572 return -EINVAL; 573 574 mutex_lock(&pmc->powergates_lock); 575 576 if (tegra_powergate_state(id) == new_state) { 577 mutex_unlock(&pmc->powergates_lock); 578 return 0; 579 } 580 581 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 582 583 err = readx_poll_timeout(tegra_powergate_state, id, status, 584 status == new_state, 10, 100000); 585 586 mutex_unlock(&pmc->powergates_lock); 587 588 return err; 589 } 590 591 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 592 unsigned int id) 593 { 594 u32 mask; 595 596 mutex_lock(&pmc->powergates_lock); 597 598 /* 599 * On Tegra124 and later, the clamps for the GPU are controlled by a 600 * separate register (with different semantics). 601 */ 602 if (id == TEGRA_POWERGATE_3D) { 603 if (pmc->soc->has_gpu_clamps) { 604 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 605 goto out; 606 } 607 } 608 609 /* 610 * Tegra 2 has a bug where PCIE and VDE clamping masks are 611 * swapped relatively to the partition ids 612 */ 613 if (id == TEGRA_POWERGATE_VDEC) 614 mask = (1 << TEGRA_POWERGATE_PCIE); 615 else if (id == TEGRA_POWERGATE_PCIE) 616 mask = (1 << TEGRA_POWERGATE_VDEC); 617 else 618 mask = (1 << id); 619 620 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 621 622 out: 623 mutex_unlock(&pmc->powergates_lock); 624 625 return 0; 626 } 627 628 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 629 { 630 unsigned int i; 631 632 for (i = 0; i < pg->num_clks; i++) 633 clk_disable_unprepare(pg->clks[i]); 634 } 635 636 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 637 { 638 unsigned int i; 639 int err; 640 641 for (i = 0; i < pg->num_clks; i++) { 642 err = clk_prepare_enable(pg->clks[i]); 643 if (err) 644 goto out; 645 } 646 647 return 0; 648 649 out: 650 while (i--) 651 clk_disable_unprepare(pg->clks[i]); 652 653 return err; 654 } 655 656 int __weak tegra210_clk_handle_mbist_war(unsigned int id) 657 { 658 return 0; 659 } 660 661 static int tegra_powergate_power_up(struct tegra_powergate *pg, 662 bool disable_clocks) 663 { 664 int err; 665 666 err = reset_control_assert(pg->reset); 667 if (err) 668 return err; 669 670 usleep_range(10, 20); 671 672 err = tegra_powergate_set(pg->pmc, pg->id, true); 673 if (err < 0) 674 return err; 675 676 usleep_range(10, 20); 677 678 err = tegra_powergate_enable_clocks(pg); 679 if (err) 680 goto disable_clks; 681 682 usleep_range(10, 20); 683 684 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 685 if (err) 686 goto disable_clks; 687 688 usleep_range(10, 20); 689 690 err = reset_control_deassert(pg->reset); 691 if (err) 692 goto powergate_off; 693 694 usleep_range(10, 20); 695 696 if (pg->pmc->soc->needs_mbist_war) 697 err = tegra210_clk_handle_mbist_war(pg->id); 698 if (err) 699 goto disable_clks; 700 701 if (disable_clocks) 702 tegra_powergate_disable_clocks(pg); 703 704 return 0; 705 706 disable_clks: 707 tegra_powergate_disable_clocks(pg); 708 usleep_range(10, 20); 709 710 powergate_off: 711 tegra_powergate_set(pg->pmc, pg->id, false); 712 713 return err; 714 } 715 716 static int tegra_powergate_power_down(struct tegra_powergate *pg) 717 { 718 int err; 719 720 err = tegra_powergate_enable_clocks(pg); 721 if (err) 722 return err; 723 724 usleep_range(10, 20); 725 726 err = reset_control_assert(pg->reset); 727 if (err) 728 goto disable_clks; 729 730 usleep_range(10, 20); 731 732 tegra_powergate_disable_clocks(pg); 733 734 usleep_range(10, 20); 735 736 err = tegra_powergate_set(pg->pmc, pg->id, false); 737 if (err) 738 goto assert_resets; 739 740 return 0; 741 742 assert_resets: 743 tegra_powergate_enable_clocks(pg); 744 usleep_range(10, 20); 745 reset_control_deassert(pg->reset); 746 usleep_range(10, 20); 747 748 disable_clks: 749 tegra_powergate_disable_clocks(pg); 750 751 return err; 752 } 753 754 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 755 { 756 struct tegra_powergate *pg = to_powergate(domain); 757 struct device *dev = pg->pmc->dev; 758 int err; 759 760 err = tegra_powergate_power_up(pg, true); 761 if (err) { 762 dev_err(dev, "failed to turn on PM domain %s: %d\n", 763 pg->genpd.name, err); 764 goto out; 765 } 766 767 reset_control_release(pg->reset); 768 769 out: 770 return err; 771 } 772 773 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 774 { 775 struct tegra_powergate *pg = to_powergate(domain); 776 struct device *dev = pg->pmc->dev; 777 int err; 778 779 err = reset_control_acquire(pg->reset); 780 if (err < 0) { 781 pr_err("failed to acquire resets: %d\n", err); 782 return err; 783 } 784 785 err = tegra_powergate_power_down(pg); 786 if (err) { 787 dev_err(dev, "failed to turn off PM domain %s: %d\n", 788 pg->genpd.name, err); 789 reset_control_release(pg->reset); 790 } 791 792 return err; 793 } 794 795 /** 796 * tegra_powergate_power_on() - power on partition 797 * @id: partition ID 798 */ 799 int tegra_powergate_power_on(unsigned int id) 800 { 801 if (!tegra_powergate_is_available(pmc, id)) 802 return -EINVAL; 803 804 return tegra_powergate_set(pmc, id, true); 805 } 806 EXPORT_SYMBOL(tegra_powergate_power_on); 807 808 /** 809 * tegra_powergate_power_off() - power off partition 810 * @id: partition ID 811 */ 812 int tegra_powergate_power_off(unsigned int id) 813 { 814 if (!tegra_powergate_is_available(pmc, id)) 815 return -EINVAL; 816 817 return tegra_powergate_set(pmc, id, false); 818 } 819 EXPORT_SYMBOL(tegra_powergate_power_off); 820 821 /** 822 * tegra_powergate_is_powered() - check if partition is powered 823 * @pmc: power management controller 824 * @id: partition ID 825 */ 826 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 827 { 828 if (!tegra_powergate_is_valid(pmc, id)) 829 return -EINVAL; 830 831 return tegra_powergate_state(id); 832 } 833 834 /** 835 * tegra_powergate_remove_clamping() - remove power clamps for partition 836 * @id: partition ID 837 */ 838 int tegra_powergate_remove_clamping(unsigned int id) 839 { 840 if (!tegra_powergate_is_available(pmc, id)) 841 return -EINVAL; 842 843 return __tegra_powergate_remove_clamping(pmc, id); 844 } 845 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 846 847 /** 848 * tegra_powergate_sequence_power_up() - power up partition 849 * @id: partition ID 850 * @clk: clock for partition 851 * @rst: reset for partition 852 * 853 * Must be called with clk disabled, and returns with clk enabled. 854 */ 855 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 856 struct reset_control *rst) 857 { 858 struct tegra_powergate *pg; 859 int err; 860 861 if (!tegra_powergate_is_available(pmc, id)) 862 return -EINVAL; 863 864 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 865 if (!pg) 866 return -ENOMEM; 867 868 pg->id = id; 869 pg->clks = &clk; 870 pg->num_clks = 1; 871 pg->reset = rst; 872 pg->pmc = pmc; 873 874 err = tegra_powergate_power_up(pg, false); 875 if (err) 876 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 877 err); 878 879 kfree(pg); 880 881 return err; 882 } 883 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 884 885 /** 886 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 887 * @pmc: power management controller 888 * @cpuid: CPU partition ID 889 * 890 * Returns the partition ID corresponding to the CPU partition ID or a 891 * negative error code on failure. 892 */ 893 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 894 unsigned int cpuid) 895 { 896 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 897 return pmc->soc->cpu_powergates[cpuid]; 898 899 return -EINVAL; 900 } 901 902 /** 903 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 904 * @cpuid: CPU partition ID 905 */ 906 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 907 { 908 int id; 909 910 id = tegra_get_cpu_powergate_id(pmc, cpuid); 911 if (id < 0) 912 return false; 913 914 return tegra_powergate_is_powered(pmc, id); 915 } 916 917 /** 918 * tegra_pmc_cpu_power_on() - power on CPU partition 919 * @cpuid: CPU partition ID 920 */ 921 int tegra_pmc_cpu_power_on(unsigned int cpuid) 922 { 923 int id; 924 925 id = tegra_get_cpu_powergate_id(pmc, cpuid); 926 if (id < 0) 927 return id; 928 929 return tegra_powergate_set(pmc, id, true); 930 } 931 932 /** 933 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 934 * @cpuid: CPU partition ID 935 */ 936 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 937 { 938 int id; 939 940 id = tegra_get_cpu_powergate_id(pmc, cpuid); 941 if (id < 0) 942 return id; 943 944 return tegra_powergate_remove_clamping(id); 945 } 946 947 static int tegra_pmc_restart_notify(struct notifier_block *this, 948 unsigned long action, void *data) 949 { 950 const char *cmd = data; 951 u32 value; 952 953 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 954 value &= ~PMC_SCRATCH0_MODE_MASK; 955 956 if (cmd) { 957 if (strcmp(cmd, "recovery") == 0) 958 value |= PMC_SCRATCH0_MODE_RECOVERY; 959 960 if (strcmp(cmd, "bootloader") == 0) 961 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 962 963 if (strcmp(cmd, "forced-recovery") == 0) 964 value |= PMC_SCRATCH0_MODE_RCM; 965 } 966 967 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 968 969 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 970 value = tegra_pmc_readl(pmc, PMC_CNTRL); 971 value |= PMC_CNTRL_MAIN_RST; 972 tegra_pmc_writel(pmc, value, PMC_CNTRL); 973 974 return NOTIFY_DONE; 975 } 976 977 static struct notifier_block tegra_pmc_restart_handler = { 978 .notifier_call = tegra_pmc_restart_notify, 979 .priority = 128, 980 }; 981 982 static int powergate_show(struct seq_file *s, void *data) 983 { 984 unsigned int i; 985 int status; 986 987 seq_printf(s, " powergate powered\n"); 988 seq_printf(s, "------------------\n"); 989 990 for (i = 0; i < pmc->soc->num_powergates; i++) { 991 status = tegra_powergate_is_powered(pmc, i); 992 if (status < 0) 993 continue; 994 995 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 996 status ? "yes" : "no"); 997 } 998 999 return 0; 1000 } 1001 1002 DEFINE_SHOW_ATTRIBUTE(powergate); 1003 1004 static int tegra_powergate_debugfs_init(void) 1005 { 1006 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 1007 &powergate_fops); 1008 if (!pmc->debugfs) 1009 return -ENOMEM; 1010 1011 return 0; 1012 } 1013 1014 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1015 struct device_node *np) 1016 { 1017 struct clk *clk; 1018 unsigned int i, count; 1019 int err; 1020 1021 count = of_clk_get_parent_count(np); 1022 if (count == 0) 1023 return -ENODEV; 1024 1025 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 1026 if (!pg->clks) 1027 return -ENOMEM; 1028 1029 for (i = 0; i < count; i++) { 1030 pg->clks[i] = of_clk_get(np, i); 1031 if (IS_ERR(pg->clks[i])) { 1032 err = PTR_ERR(pg->clks[i]); 1033 goto err; 1034 } 1035 } 1036 1037 pg->num_clks = count; 1038 1039 return 0; 1040 1041 err: 1042 while (i--) 1043 clk_put(pg->clks[i]); 1044 1045 kfree(pg->clks); 1046 1047 return err; 1048 } 1049 1050 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1051 struct device_node *np, bool off) 1052 { 1053 struct device *dev = pg->pmc->dev; 1054 int err; 1055 1056 pg->reset = of_reset_control_array_get_exclusive_released(np); 1057 if (IS_ERR(pg->reset)) { 1058 err = PTR_ERR(pg->reset); 1059 dev_err(dev, "failed to get device resets: %d\n", err); 1060 return err; 1061 } 1062 1063 err = reset_control_acquire(pg->reset); 1064 if (err < 0) { 1065 pr_err("failed to acquire resets: %d\n", err); 1066 goto out; 1067 } 1068 1069 if (off) { 1070 err = reset_control_assert(pg->reset); 1071 } else { 1072 err = reset_control_deassert(pg->reset); 1073 if (err < 0) 1074 goto out; 1075 1076 reset_control_release(pg->reset); 1077 } 1078 1079 out: 1080 if (err) { 1081 reset_control_release(pg->reset); 1082 reset_control_put(pg->reset); 1083 } 1084 1085 return err; 1086 } 1087 1088 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1089 { 1090 struct device *dev = pmc->dev; 1091 struct tegra_powergate *pg; 1092 int id, err = 0; 1093 bool off; 1094 1095 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1096 if (!pg) 1097 return -ENOMEM; 1098 1099 id = tegra_powergate_lookup(pmc, np->name); 1100 if (id < 0) { 1101 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1102 err = -ENODEV; 1103 goto free_mem; 1104 } 1105 1106 /* 1107 * Clear the bit for this powergate so it cannot be managed 1108 * directly via the legacy APIs for controlling powergates. 1109 */ 1110 clear_bit(id, pmc->powergates_available); 1111 1112 pg->id = id; 1113 pg->genpd.name = np->name; 1114 pg->genpd.power_off = tegra_genpd_power_off; 1115 pg->genpd.power_on = tegra_genpd_power_on; 1116 pg->pmc = pmc; 1117 1118 off = !tegra_powergate_is_powered(pmc, pg->id); 1119 1120 err = tegra_powergate_of_get_clks(pg, np); 1121 if (err < 0) { 1122 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1123 goto set_available; 1124 } 1125 1126 err = tegra_powergate_of_get_resets(pg, np, off); 1127 if (err < 0) { 1128 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1129 goto remove_clks; 1130 } 1131 1132 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1133 if (off) 1134 WARN_ON(tegra_powergate_power_up(pg, true)); 1135 1136 goto remove_resets; 1137 } 1138 1139 err = pm_genpd_init(&pg->genpd, NULL, off); 1140 if (err < 0) { 1141 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1142 err); 1143 goto remove_resets; 1144 } 1145 1146 err = of_genpd_add_provider_simple(np, &pg->genpd); 1147 if (err < 0) { 1148 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1149 np, err); 1150 goto remove_genpd; 1151 } 1152 1153 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1154 1155 return 0; 1156 1157 remove_genpd: 1158 pm_genpd_remove(&pg->genpd); 1159 1160 remove_resets: 1161 reset_control_put(pg->reset); 1162 1163 remove_clks: 1164 while (pg->num_clks--) 1165 clk_put(pg->clks[pg->num_clks]); 1166 1167 kfree(pg->clks); 1168 1169 set_available: 1170 set_bit(id, pmc->powergates_available); 1171 1172 free_mem: 1173 kfree(pg); 1174 1175 return err; 1176 } 1177 1178 static int tegra_powergate_init(struct tegra_pmc *pmc, 1179 struct device_node *parent) 1180 { 1181 struct device_node *np, *child; 1182 int err = 0; 1183 1184 np = of_get_child_by_name(parent, "powergates"); 1185 if (!np) 1186 return 0; 1187 1188 for_each_child_of_node(np, child) { 1189 err = tegra_powergate_add(pmc, child); 1190 if (err < 0) { 1191 of_node_put(child); 1192 break; 1193 } 1194 } 1195 1196 of_node_put(np); 1197 1198 return err; 1199 } 1200 1201 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1202 { 1203 struct tegra_powergate *pg = to_powergate(genpd); 1204 1205 reset_control_put(pg->reset); 1206 1207 while (pg->num_clks--) 1208 clk_put(pg->clks[pg->num_clks]); 1209 1210 kfree(pg->clks); 1211 1212 set_bit(pg->id, pmc->powergates_available); 1213 1214 kfree(pg); 1215 } 1216 1217 static void tegra_powergate_remove_all(struct device_node *parent) 1218 { 1219 struct generic_pm_domain *genpd; 1220 struct device_node *np, *child; 1221 1222 np = of_get_child_by_name(parent, "powergates"); 1223 if (!np) 1224 return; 1225 1226 for_each_child_of_node(np, child) { 1227 of_genpd_del_provider(child); 1228 1229 genpd = of_genpd_remove_last(child); 1230 if (IS_ERR(genpd)) 1231 continue; 1232 1233 tegra_powergate_remove(genpd); 1234 } 1235 1236 of_node_put(np); 1237 } 1238 1239 static const struct tegra_io_pad_soc * 1240 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1241 { 1242 unsigned int i; 1243 1244 for (i = 0; i < pmc->soc->num_io_pads; i++) 1245 if (pmc->soc->io_pads[i].id == id) 1246 return &pmc->soc->io_pads[i]; 1247 1248 return NULL; 1249 } 1250 1251 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, 1252 enum tegra_io_pad id, 1253 unsigned long *request, 1254 unsigned long *status, 1255 u32 *mask) 1256 { 1257 const struct tegra_io_pad_soc *pad; 1258 1259 pad = tegra_io_pad_find(pmc, id); 1260 if (!pad) { 1261 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1262 return -ENOENT; 1263 } 1264 1265 if (pad->dpd == UINT_MAX) 1266 return -ENOTSUPP; 1267 1268 *mask = BIT(pad->dpd % 32); 1269 1270 if (pad->dpd < 32) { 1271 *status = pmc->soc->regs->dpd_status; 1272 *request = pmc->soc->regs->dpd_req; 1273 } else { 1274 *status = pmc->soc->regs->dpd2_status; 1275 *request = pmc->soc->regs->dpd2_req; 1276 } 1277 1278 return 0; 1279 } 1280 1281 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, 1282 unsigned long *request, unsigned long *status, 1283 u32 *mask) 1284 { 1285 unsigned long rate, value; 1286 int err; 1287 1288 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); 1289 if (err) 1290 return err; 1291 1292 if (pmc->clk) { 1293 rate = pmc->rate; 1294 if (!rate) { 1295 dev_err(pmc->dev, "failed to get clock rate\n"); 1296 return -ENODEV; 1297 } 1298 1299 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1300 1301 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1302 value = DIV_ROUND_UP(1000000000, rate); 1303 value = DIV_ROUND_UP(200, value); 1304 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1305 } 1306 1307 return 0; 1308 } 1309 1310 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1311 u32 mask, u32 val, unsigned long timeout) 1312 { 1313 u32 value; 1314 1315 timeout = jiffies + msecs_to_jiffies(timeout); 1316 1317 while (time_after(timeout, jiffies)) { 1318 value = tegra_pmc_readl(pmc, offset); 1319 if ((value & mask) == val) 1320 return 0; 1321 1322 usleep_range(250, 1000); 1323 } 1324 1325 return -ETIMEDOUT; 1326 } 1327 1328 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1329 { 1330 if (pmc->clk) 1331 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1332 } 1333 1334 /** 1335 * tegra_io_pad_power_enable() - enable power to I/O pad 1336 * @id: Tegra I/O pad ID for which to enable power 1337 * 1338 * Returns: 0 on success or a negative error code on failure. 1339 */ 1340 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1341 { 1342 unsigned long request, status; 1343 u32 mask; 1344 int err; 1345 1346 mutex_lock(&pmc->powergates_lock); 1347 1348 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1349 if (err < 0) { 1350 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1351 goto unlock; 1352 } 1353 1354 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1355 1356 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1357 if (err < 0) { 1358 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1359 goto unlock; 1360 } 1361 1362 tegra_io_pad_unprepare(pmc); 1363 1364 unlock: 1365 mutex_unlock(&pmc->powergates_lock); 1366 return err; 1367 } 1368 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1369 1370 /** 1371 * tegra_io_pad_power_disable() - disable power to I/O pad 1372 * @id: Tegra I/O pad ID for which to disable power 1373 * 1374 * Returns: 0 on success or a negative error code on failure. 1375 */ 1376 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1377 { 1378 unsigned long request, status; 1379 u32 mask; 1380 int err; 1381 1382 mutex_lock(&pmc->powergates_lock); 1383 1384 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1385 if (err < 0) { 1386 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1387 goto unlock; 1388 } 1389 1390 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1391 1392 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1393 if (err < 0) { 1394 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1395 goto unlock; 1396 } 1397 1398 tegra_io_pad_unprepare(pmc); 1399 1400 unlock: 1401 mutex_unlock(&pmc->powergates_lock); 1402 return err; 1403 } 1404 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1405 1406 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1407 { 1408 unsigned long request, status; 1409 u32 mask, value; 1410 int err; 1411 1412 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, 1413 &mask); 1414 if (err) 1415 return err; 1416 1417 value = tegra_pmc_readl(pmc, status); 1418 1419 return !(value & mask); 1420 } 1421 1422 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1423 int voltage) 1424 { 1425 const struct tegra_io_pad_soc *pad; 1426 u32 value; 1427 1428 pad = tegra_io_pad_find(pmc, id); 1429 if (!pad) 1430 return -ENOENT; 1431 1432 if (pad->voltage == UINT_MAX) 1433 return -ENOTSUPP; 1434 1435 mutex_lock(&pmc->powergates_lock); 1436 1437 if (pmc->soc->has_impl_33v_pwr) { 1438 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1439 1440 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1441 value &= ~BIT(pad->voltage); 1442 else 1443 value |= BIT(pad->voltage); 1444 1445 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1446 } else { 1447 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1448 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1449 value |= BIT(pad->voltage); 1450 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1451 1452 /* update I/O voltage */ 1453 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1454 1455 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1456 value &= ~BIT(pad->voltage); 1457 else 1458 value |= BIT(pad->voltage); 1459 1460 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1461 } 1462 1463 mutex_unlock(&pmc->powergates_lock); 1464 1465 usleep_range(100, 250); 1466 1467 return 0; 1468 } 1469 1470 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1471 { 1472 const struct tegra_io_pad_soc *pad; 1473 u32 value; 1474 1475 pad = tegra_io_pad_find(pmc, id); 1476 if (!pad) 1477 return -ENOENT; 1478 1479 if (pad->voltage == UINT_MAX) 1480 return -ENOTSUPP; 1481 1482 if (pmc->soc->has_impl_33v_pwr) 1483 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1484 else 1485 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1486 1487 if ((value & BIT(pad->voltage)) == 0) 1488 return TEGRA_IO_PAD_VOLTAGE_1V8; 1489 1490 return TEGRA_IO_PAD_VOLTAGE_3V3; 1491 } 1492 1493 /** 1494 * tegra_io_rail_power_on() - enable power to I/O rail 1495 * @id: Tegra I/O pad ID for which to enable power 1496 * 1497 * See also: tegra_io_pad_power_enable() 1498 */ 1499 int tegra_io_rail_power_on(unsigned int id) 1500 { 1501 return tegra_io_pad_power_enable(id); 1502 } 1503 EXPORT_SYMBOL(tegra_io_rail_power_on); 1504 1505 /** 1506 * tegra_io_rail_power_off() - disable power to I/O rail 1507 * @id: Tegra I/O pad ID for which to disable power 1508 * 1509 * See also: tegra_io_pad_power_disable() 1510 */ 1511 int tegra_io_rail_power_off(unsigned int id) 1512 { 1513 return tegra_io_pad_power_disable(id); 1514 } 1515 EXPORT_SYMBOL(tegra_io_rail_power_off); 1516 1517 #ifdef CONFIG_PM_SLEEP 1518 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1519 { 1520 return pmc->suspend_mode; 1521 } 1522 1523 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1524 { 1525 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1526 return; 1527 1528 pmc->suspend_mode = mode; 1529 } 1530 1531 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1532 { 1533 unsigned long long rate = 0; 1534 u64 ticks; 1535 u32 value; 1536 1537 switch (mode) { 1538 case TEGRA_SUSPEND_LP1: 1539 rate = 32768; 1540 break; 1541 1542 case TEGRA_SUSPEND_LP2: 1543 rate = pmc->rate; 1544 break; 1545 1546 default: 1547 break; 1548 } 1549 1550 if (WARN_ON_ONCE(rate == 0)) 1551 rate = 100000000; 1552 1553 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1554 do_div(ticks, USEC_PER_SEC); 1555 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1556 1557 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1558 do_div(ticks, USEC_PER_SEC); 1559 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1560 1561 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1562 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1563 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1564 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1565 } 1566 #endif 1567 1568 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1569 { 1570 u32 value, values[2]; 1571 1572 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1573 } else { 1574 switch (value) { 1575 case 0: 1576 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1577 break; 1578 1579 case 1: 1580 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1581 break; 1582 1583 case 2: 1584 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1585 break; 1586 1587 default: 1588 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1589 break; 1590 } 1591 } 1592 1593 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1594 1595 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1596 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1597 1598 pmc->cpu_good_time = value; 1599 1600 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1601 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1602 1603 pmc->cpu_off_time = value; 1604 1605 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1606 values, ARRAY_SIZE(values))) 1607 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1608 1609 pmc->core_osc_time = values[0]; 1610 pmc->core_pmu_time = values[1]; 1611 1612 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1613 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1614 1615 pmc->core_off_time = value; 1616 1617 pmc->corereq_high = of_property_read_bool(np, 1618 "nvidia,core-power-req-active-high"); 1619 1620 pmc->sysclkreq_high = of_property_read_bool(np, 1621 "nvidia,sys-clock-req-active-high"); 1622 1623 pmc->combined_req = of_property_read_bool(np, 1624 "nvidia,combined-power-req"); 1625 1626 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1627 "nvidia,cpu-pwr-good-en"); 1628 1629 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1630 ARRAY_SIZE(values))) 1631 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1632 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1633 1634 pmc->lp0_vec_phys = values[0]; 1635 pmc->lp0_vec_size = values[1]; 1636 1637 return 0; 1638 } 1639 1640 static void tegra_pmc_init(struct tegra_pmc *pmc) 1641 { 1642 if (pmc->soc->init) 1643 pmc->soc->init(pmc); 1644 } 1645 1646 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1647 { 1648 static const char disabled[] = "emergency thermal reset disabled"; 1649 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1650 struct device *dev = pmc->dev; 1651 struct device_node *np; 1652 u32 value, checksum; 1653 1654 if (!pmc->soc->has_tsense_reset) 1655 return; 1656 1657 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1658 if (!np) { 1659 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1660 return; 1661 } 1662 1663 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1664 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1665 goto out; 1666 } 1667 1668 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1669 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1670 goto out; 1671 } 1672 1673 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1674 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1675 goto out; 1676 } 1677 1678 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1679 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1680 goto out; 1681 } 1682 1683 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1684 pinmux = 0; 1685 1686 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1687 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1688 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1689 1690 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1691 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1692 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 1693 1694 value = PMC_SCRATCH55_RESET_TEGRA; 1695 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1696 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1697 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1698 1699 /* 1700 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1701 * contain the checksum and are currently zero, so they are not added. 1702 */ 1703 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1704 + ((value >> 24) & 0xff); 1705 checksum &= 0xff; 1706 checksum = 0x100 - checksum; 1707 1708 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1709 1710 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 1711 1712 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1713 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1714 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1715 1716 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1717 1718 out: 1719 of_node_put(np); 1720 } 1721 1722 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 1723 { 1724 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1725 1726 return pmc->soc->num_io_pads; 1727 } 1728 1729 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 1730 unsigned int group) 1731 { 1732 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 1733 1734 return pmc->soc->io_pads[group].name; 1735 } 1736 1737 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 1738 unsigned int group, 1739 const unsigned int **pins, 1740 unsigned int *num_pins) 1741 { 1742 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1743 1744 *pins = &pmc->soc->io_pads[group].id; 1745 *num_pins = 1; 1746 1747 return 0; 1748 } 1749 1750 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 1751 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 1752 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 1753 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 1754 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1755 .dt_free_map = pinconf_generic_dt_free_map, 1756 }; 1757 1758 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 1759 unsigned int pin, unsigned long *config) 1760 { 1761 enum pin_config_param param = pinconf_to_config_param(*config); 1762 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1763 const struct tegra_io_pad_soc *pad; 1764 int ret; 1765 u32 arg; 1766 1767 pad = tegra_io_pad_find(pmc, pin); 1768 if (!pad) 1769 return -EINVAL; 1770 1771 switch (param) { 1772 case PIN_CONFIG_POWER_SOURCE: 1773 ret = tegra_io_pad_get_voltage(pmc, pad->id); 1774 if (ret < 0) 1775 return ret; 1776 1777 arg = ret; 1778 break; 1779 1780 case PIN_CONFIG_LOW_POWER_MODE: 1781 ret = tegra_io_pad_is_powered(pmc, pad->id); 1782 if (ret < 0) 1783 return ret; 1784 1785 arg = !ret; 1786 break; 1787 1788 default: 1789 return -EINVAL; 1790 } 1791 1792 *config = pinconf_to_config_packed(param, arg); 1793 1794 return 0; 1795 } 1796 1797 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 1798 unsigned int pin, unsigned long *configs, 1799 unsigned int num_configs) 1800 { 1801 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1802 const struct tegra_io_pad_soc *pad; 1803 enum pin_config_param param; 1804 unsigned int i; 1805 int err; 1806 u32 arg; 1807 1808 pad = tegra_io_pad_find(pmc, pin); 1809 if (!pad) 1810 return -EINVAL; 1811 1812 for (i = 0; i < num_configs; ++i) { 1813 param = pinconf_to_config_param(configs[i]); 1814 arg = pinconf_to_config_argument(configs[i]); 1815 1816 switch (param) { 1817 case PIN_CONFIG_LOW_POWER_MODE: 1818 if (arg) 1819 err = tegra_io_pad_power_disable(pad->id); 1820 else 1821 err = tegra_io_pad_power_enable(pad->id); 1822 if (err) 1823 return err; 1824 break; 1825 case PIN_CONFIG_POWER_SOURCE: 1826 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 1827 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 1828 return -EINVAL; 1829 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 1830 if (err) 1831 return err; 1832 break; 1833 default: 1834 return -EINVAL; 1835 } 1836 } 1837 1838 return 0; 1839 } 1840 1841 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 1842 .pin_config_get = tegra_io_pad_pinconf_get, 1843 .pin_config_set = tegra_io_pad_pinconf_set, 1844 .is_generic = true, 1845 }; 1846 1847 static struct pinctrl_desc tegra_pmc_pctl_desc = { 1848 .pctlops = &tegra_io_pad_pinctrl_ops, 1849 .confops = &tegra_io_pad_pinconf_ops, 1850 }; 1851 1852 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 1853 { 1854 int err; 1855 1856 if (!pmc->soc->num_pin_descs) 1857 return 0; 1858 1859 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 1860 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 1861 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 1862 1863 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 1864 pmc); 1865 if (IS_ERR(pmc->pctl_dev)) { 1866 err = PTR_ERR(pmc->pctl_dev); 1867 dev_err(pmc->dev, "failed to register pin controller: %d\n", 1868 err); 1869 return err; 1870 } 1871 1872 return 0; 1873 } 1874 1875 static ssize_t reset_reason_show(struct device *dev, 1876 struct device_attribute *attr, char *buf) 1877 { 1878 u32 value; 1879 1880 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 1881 value &= pmc->soc->regs->rst_source_mask; 1882 value >>= pmc->soc->regs->rst_source_shift; 1883 1884 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 1885 return sprintf(buf, "%s\n", "UNKNOWN"); 1886 1887 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 1888 } 1889 1890 static DEVICE_ATTR_RO(reset_reason); 1891 1892 static ssize_t reset_level_show(struct device *dev, 1893 struct device_attribute *attr, char *buf) 1894 { 1895 u32 value; 1896 1897 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 1898 value &= pmc->soc->regs->rst_level_mask; 1899 value >>= pmc->soc->regs->rst_level_shift; 1900 1901 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 1902 return sprintf(buf, "%s\n", "UNKNOWN"); 1903 1904 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 1905 } 1906 1907 static DEVICE_ATTR_RO(reset_level); 1908 1909 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 1910 { 1911 struct device *dev = pmc->dev; 1912 int err = 0; 1913 1914 if (pmc->soc->reset_sources) { 1915 err = device_create_file(dev, &dev_attr_reset_reason); 1916 if (err < 0) 1917 dev_warn(dev, 1918 "failed to create attr \"reset_reason\": %d\n", 1919 err); 1920 } 1921 1922 if (pmc->soc->reset_levels) { 1923 err = device_create_file(dev, &dev_attr_reset_level); 1924 if (err < 0) 1925 dev_warn(dev, 1926 "failed to create attr \"reset_level\": %d\n", 1927 err); 1928 } 1929 } 1930 1931 static int tegra_pmc_irq_translate(struct irq_domain *domain, 1932 struct irq_fwspec *fwspec, 1933 unsigned long *hwirq, 1934 unsigned int *type) 1935 { 1936 if (WARN_ON(fwspec->param_count < 2)) 1937 return -EINVAL; 1938 1939 *hwirq = fwspec->param[0]; 1940 *type = fwspec->param[1]; 1941 1942 return 0; 1943 } 1944 1945 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 1946 unsigned int num_irqs, void *data) 1947 { 1948 struct tegra_pmc *pmc = domain->host_data; 1949 const struct tegra_pmc_soc *soc = pmc->soc; 1950 struct irq_fwspec *fwspec = data; 1951 unsigned int i; 1952 int err = 0; 1953 1954 if (WARN_ON(num_irqs > 1)) 1955 return -EINVAL; 1956 1957 for (i = 0; i < soc->num_wake_events; i++) { 1958 const struct tegra_wake_event *event = &soc->wake_events[i]; 1959 1960 if (fwspec->param_count == 2) { 1961 struct irq_fwspec spec; 1962 1963 if (event->id != fwspec->param[0]) 1964 continue; 1965 1966 err = irq_domain_set_hwirq_and_chip(domain, virq, 1967 event->id, 1968 &pmc->irq, pmc); 1969 if (err < 0) 1970 break; 1971 1972 spec.fwnode = &pmc->dev->of_node->fwnode; 1973 spec.param_count = 3; 1974 spec.param[0] = GIC_SPI; 1975 spec.param[1] = event->irq; 1976 spec.param[2] = fwspec->param[1]; 1977 1978 err = irq_domain_alloc_irqs_parent(domain, virq, 1979 num_irqs, &spec); 1980 1981 break; 1982 } 1983 1984 if (fwspec->param_count == 3) { 1985 if (event->gpio.instance != fwspec->param[0] || 1986 event->gpio.pin != fwspec->param[1]) 1987 continue; 1988 1989 err = irq_domain_set_hwirq_and_chip(domain, virq, 1990 event->id, 1991 &pmc->irq, pmc); 1992 1993 /* 1994 * GPIOs don't have an equivalent interrupt in the 1995 * parent controller (GIC). However some code, such 1996 * as the one in irq_get_irqchip_state(), require a 1997 * valid IRQ chip to be set. Make sure that's the 1998 * case by passing NULL here, which will install a 1999 * dummy IRQ chip for the interrupt in the parent 2000 * domain. 2001 */ 2002 if (domain->parent) 2003 irq_domain_set_hwirq_and_chip(domain->parent, 2004 virq, 0, NULL, 2005 NULL); 2006 2007 break; 2008 } 2009 } 2010 2011 /* 2012 * For interrupts that don't have associated wake events, assign a 2013 * dummy hardware IRQ number. This is used in the ->irq_set_type() 2014 * and ->irq_set_wake() callbacks to return early for these IRQs. 2015 */ 2016 if (i == soc->num_wake_events) { 2017 err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX, 2018 &pmc->irq, pmc); 2019 2020 /* 2021 * Interrupts without a wake event don't have a corresponding 2022 * interrupt in the parent controller (GIC). Pass NULL for the 2023 * chip here, which causes a dummy IRQ chip to be installed 2024 * for the interrupt in the parent domain, to make this 2025 * explicit. 2026 */ 2027 if (domain->parent) 2028 irq_domain_set_hwirq_and_chip(domain->parent, virq, 0, 2029 NULL, NULL); 2030 } 2031 2032 return err; 2033 } 2034 2035 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2036 .translate = tegra_pmc_irq_translate, 2037 .alloc = tegra_pmc_irq_alloc, 2038 }; 2039 2040 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2041 { 2042 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2043 unsigned int offset, bit; 2044 u32 value; 2045 2046 if (data->hwirq == ULONG_MAX) 2047 return 0; 2048 2049 offset = data->hwirq / 32; 2050 bit = data->hwirq % 32; 2051 2052 /* clear wake status */ 2053 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2054 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2055 2056 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2057 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2058 2059 /* enable PMC wake */ 2060 if (data->hwirq >= 32) 2061 offset = PMC_WAKE2_MASK; 2062 else 2063 offset = PMC_WAKE_MASK; 2064 2065 value = tegra_pmc_readl(pmc, offset); 2066 2067 if (on) 2068 value |= BIT(bit); 2069 else 2070 value &= ~BIT(bit); 2071 2072 tegra_pmc_writel(pmc, value, offset); 2073 2074 return 0; 2075 } 2076 2077 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2078 { 2079 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2080 unsigned int offset, bit; 2081 u32 value; 2082 2083 if (data->hwirq == ULONG_MAX) 2084 return 0; 2085 2086 offset = data->hwirq / 32; 2087 bit = data->hwirq % 32; 2088 2089 if (data->hwirq >= 32) 2090 offset = PMC_WAKE2_LEVEL; 2091 else 2092 offset = PMC_WAKE_LEVEL; 2093 2094 value = tegra_pmc_readl(pmc, offset); 2095 2096 switch (type) { 2097 case IRQ_TYPE_EDGE_RISING: 2098 case IRQ_TYPE_LEVEL_HIGH: 2099 value |= BIT(bit); 2100 break; 2101 2102 case IRQ_TYPE_EDGE_FALLING: 2103 case IRQ_TYPE_LEVEL_LOW: 2104 value &= ~BIT(bit); 2105 break; 2106 2107 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2108 value ^= BIT(bit); 2109 break; 2110 2111 default: 2112 return -EINVAL; 2113 } 2114 2115 tegra_pmc_writel(pmc, value, offset); 2116 2117 return 0; 2118 } 2119 2120 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2121 { 2122 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2123 unsigned int offset, bit; 2124 u32 value; 2125 2126 /* nothing to do if there's no associated wake event */ 2127 if (WARN_ON(data->hwirq == ULONG_MAX)) 2128 return 0; 2129 2130 offset = data->hwirq / 32; 2131 bit = data->hwirq % 32; 2132 2133 /* clear wake status */ 2134 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 2135 2136 /* route wake to tier 2 */ 2137 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2138 2139 if (!on) 2140 value &= ~(1 << bit); 2141 else 2142 value |= 1 << bit; 2143 2144 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2145 2146 /* enable wakeup event */ 2147 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 2148 2149 return 0; 2150 } 2151 2152 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2153 { 2154 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2155 u32 value; 2156 2157 /* nothing to do if there's no associated wake event */ 2158 if (data->hwirq == ULONG_MAX) 2159 return 0; 2160 2161 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2162 2163 switch (type) { 2164 case IRQ_TYPE_EDGE_RISING: 2165 case IRQ_TYPE_LEVEL_HIGH: 2166 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2167 break; 2168 2169 case IRQ_TYPE_EDGE_FALLING: 2170 case IRQ_TYPE_LEVEL_LOW: 2171 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2172 break; 2173 2174 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2175 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2176 break; 2177 2178 default: 2179 return -EINVAL; 2180 } 2181 2182 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2183 2184 return 0; 2185 } 2186 2187 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2188 { 2189 struct irq_domain *parent = NULL; 2190 struct device_node *np; 2191 2192 np = of_irq_find_parent(pmc->dev->of_node); 2193 if (np) { 2194 parent = irq_find_host(np); 2195 of_node_put(np); 2196 } 2197 2198 if (!parent) 2199 return 0; 2200 2201 pmc->irq.name = dev_name(pmc->dev); 2202 pmc->irq.irq_mask = irq_chip_mask_parent; 2203 pmc->irq.irq_unmask = irq_chip_unmask_parent; 2204 pmc->irq.irq_eoi = irq_chip_eoi_parent; 2205 pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent; 2206 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2207 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2208 2209 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, 2210 &tegra_pmc_irq_domain_ops, pmc); 2211 if (!pmc->domain) { 2212 dev_err(pmc->dev, "failed to allocate domain\n"); 2213 return -ENOMEM; 2214 } 2215 2216 return 0; 2217 } 2218 2219 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2220 unsigned long action, void *ptr) 2221 { 2222 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2223 struct clk_notifier_data *data = ptr; 2224 2225 switch (action) { 2226 case PRE_RATE_CHANGE: 2227 mutex_lock(&pmc->powergates_lock); 2228 break; 2229 2230 case POST_RATE_CHANGE: 2231 pmc->rate = data->new_rate; 2232 /* fall through */ 2233 2234 case ABORT_RATE_CHANGE: 2235 mutex_unlock(&pmc->powergates_lock); 2236 break; 2237 2238 default: 2239 WARN_ON_ONCE(1); 2240 return notifier_from_errno(-EINVAL); 2241 } 2242 2243 return NOTIFY_OK; 2244 } 2245 2246 static void pmc_clk_fence_udelay(u32 offset) 2247 { 2248 tegra_pmc_readl(pmc, offset); 2249 /* pmc clk propagation delay 2 us */ 2250 udelay(2); 2251 } 2252 2253 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2254 { 2255 struct pmc_clk *clk = to_pmc_clk(hw); 2256 u32 val; 2257 2258 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; 2259 val &= PMC_CLK_OUT_MUX_MASK; 2260 2261 return val; 2262 } 2263 2264 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2265 { 2266 struct pmc_clk *clk = to_pmc_clk(hw); 2267 u32 val; 2268 2269 val = tegra_pmc_readl(pmc, clk->offs); 2270 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2271 val |= index << clk->mux_shift; 2272 tegra_pmc_writel(pmc, val, clk->offs); 2273 pmc_clk_fence_udelay(clk->offs); 2274 2275 return 0; 2276 } 2277 2278 static int pmc_clk_is_enabled(struct clk_hw *hw) 2279 { 2280 struct pmc_clk *clk = to_pmc_clk(hw); 2281 u32 val; 2282 2283 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); 2284 2285 return val ? 1 : 0; 2286 } 2287 2288 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state) 2289 { 2290 u32 val; 2291 2292 val = tegra_pmc_readl(pmc, offs); 2293 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2294 tegra_pmc_writel(pmc, val, offs); 2295 pmc_clk_fence_udelay(offs); 2296 } 2297 2298 static int pmc_clk_enable(struct clk_hw *hw) 2299 { 2300 struct pmc_clk *clk = to_pmc_clk(hw); 2301 2302 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); 2303 2304 return 0; 2305 } 2306 2307 static void pmc_clk_disable(struct clk_hw *hw) 2308 { 2309 struct pmc_clk *clk = to_pmc_clk(hw); 2310 2311 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); 2312 } 2313 2314 static const struct clk_ops pmc_clk_ops = { 2315 .get_parent = pmc_clk_mux_get_parent, 2316 .set_parent = pmc_clk_mux_set_parent, 2317 .determine_rate = __clk_mux_determine_rate, 2318 .is_enabled = pmc_clk_is_enabled, 2319 .enable = pmc_clk_enable, 2320 .disable = pmc_clk_disable, 2321 }; 2322 2323 static struct clk * 2324 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2325 const struct pmc_clk_init_data *data, 2326 unsigned long offset) 2327 { 2328 struct clk_init_data init; 2329 struct pmc_clk *pmc_clk; 2330 2331 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2332 if (!pmc_clk) 2333 return ERR_PTR(-ENOMEM); 2334 2335 init.name = data->name; 2336 init.ops = &pmc_clk_ops; 2337 init.parent_names = data->parents; 2338 init.num_parents = data->num_parents; 2339 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2340 CLK_SET_PARENT_GATE; 2341 2342 pmc_clk->hw.init = &init; 2343 pmc_clk->offs = offset; 2344 pmc_clk->mux_shift = data->mux_shift; 2345 pmc_clk->force_en_shift = data->force_en_shift; 2346 2347 return clk_register(NULL, &pmc_clk->hw); 2348 } 2349 2350 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2351 { 2352 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2353 2354 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; 2355 } 2356 2357 static int pmc_clk_gate_enable(struct clk_hw *hw) 2358 { 2359 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2360 2361 pmc_clk_set_state(gate->offs, gate->shift, 1); 2362 2363 return 0; 2364 } 2365 2366 static void pmc_clk_gate_disable(struct clk_hw *hw) 2367 { 2368 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2369 2370 pmc_clk_set_state(gate->offs, gate->shift, 0); 2371 } 2372 2373 static const struct clk_ops pmc_clk_gate_ops = { 2374 .is_enabled = pmc_clk_gate_is_enabled, 2375 .enable = pmc_clk_gate_enable, 2376 .disable = pmc_clk_gate_disable, 2377 }; 2378 2379 static struct clk * 2380 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2381 const char *parent_name, unsigned long offset, 2382 u32 shift) 2383 { 2384 struct clk_init_data init; 2385 struct pmc_clk_gate *gate; 2386 2387 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2388 if (!gate) 2389 return ERR_PTR(-ENOMEM); 2390 2391 init.name = name; 2392 init.ops = &pmc_clk_gate_ops; 2393 init.parent_names = &parent_name; 2394 init.num_parents = 1; 2395 init.flags = 0; 2396 2397 gate->hw.init = &init; 2398 gate->offs = offset; 2399 gate->shift = shift; 2400 2401 return clk_register(NULL, &gate->hw); 2402 } 2403 2404 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2405 struct device_node *np) 2406 { 2407 struct clk *clk; 2408 struct clk_onecell_data *clk_data; 2409 unsigned int num_clks; 2410 int i, err; 2411 2412 num_clks = pmc->soc->num_pmc_clks; 2413 if (pmc->soc->has_blink_output) 2414 num_clks += 1; 2415 2416 if (!num_clks) 2417 return; 2418 2419 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2420 if (!clk_data) 2421 return; 2422 2423 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2424 sizeof(*clk_data->clks), GFP_KERNEL); 2425 if (!clk_data->clks) 2426 return; 2427 2428 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2429 2430 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2431 clk_data->clks[i] = ERR_PTR(-ENOENT); 2432 2433 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2434 const struct pmc_clk_init_data *data; 2435 2436 data = pmc->soc->pmc_clks_data + i; 2437 2438 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2439 if (IS_ERR(clk)) { 2440 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2441 data->name, PTR_ERR_OR_ZERO(clk)); 2442 return; 2443 } 2444 2445 err = clk_register_clkdev(clk, data->name, NULL); 2446 if (err) { 2447 dev_warn(pmc->dev, 2448 "unable to register %s clock lookup: %d\n", 2449 data->name, err); 2450 return; 2451 } 2452 2453 clk_data->clks[data->clk_id] = clk; 2454 } 2455 2456 if (pmc->soc->has_blink_output) { 2457 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2458 clk = tegra_pmc_clk_gate_register(pmc, 2459 "pmc_blink_override", 2460 "clk_32k", 2461 PMC_DPD_PADS_ORIDE, 2462 PMC_DPD_PADS_ORIDE_BLINK); 2463 if (IS_ERR(clk)) { 2464 dev_warn(pmc->dev, 2465 "unable to register pmc_blink_override: %d\n", 2466 PTR_ERR_OR_ZERO(clk)); 2467 return; 2468 } 2469 2470 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 2471 "pmc_blink_override", 2472 PMC_CNTRL, 2473 PMC_CNTRL_BLINK_EN); 2474 if (IS_ERR(clk)) { 2475 dev_warn(pmc->dev, 2476 "unable to register pmc_blink: %d\n", 2477 PTR_ERR_OR_ZERO(clk)); 2478 return; 2479 } 2480 2481 err = clk_register_clkdev(clk, "pmc_blink", NULL); 2482 if (err) { 2483 dev_warn(pmc->dev, 2484 "unable to register pmc_blink lookup: %d\n", 2485 err); 2486 return; 2487 } 2488 2489 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 2490 } 2491 2492 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 2493 if (err) 2494 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 2495 err); 2496 } 2497 2498 static int tegra_pmc_probe(struct platform_device *pdev) 2499 { 2500 void __iomem *base; 2501 struct resource *res; 2502 int err; 2503 2504 /* 2505 * Early initialisation should have configured an initial 2506 * register mapping and setup the soc data pointer. If these 2507 * are not valid then something went badly wrong! 2508 */ 2509 if (WARN_ON(!pmc->base || !pmc->soc)) 2510 return -ENODEV; 2511 2512 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 2513 if (err < 0) 2514 return err; 2515 2516 /* take over the memory region from the early initialization */ 2517 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2518 base = devm_ioremap_resource(&pdev->dev, res); 2519 if (IS_ERR(base)) 2520 return PTR_ERR(base); 2521 2522 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 2523 if (res) { 2524 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 2525 if (IS_ERR(pmc->wake)) 2526 return PTR_ERR(pmc->wake); 2527 } else { 2528 pmc->wake = base; 2529 } 2530 2531 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 2532 if (res) { 2533 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 2534 if (IS_ERR(pmc->aotag)) 2535 return PTR_ERR(pmc->aotag); 2536 } else { 2537 pmc->aotag = base; 2538 } 2539 2540 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 2541 if (res) { 2542 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 2543 if (IS_ERR(pmc->scratch)) 2544 return PTR_ERR(pmc->scratch); 2545 } else { 2546 pmc->scratch = base; 2547 } 2548 2549 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 2550 if (IS_ERR(pmc->clk)) { 2551 err = PTR_ERR(pmc->clk); 2552 2553 if (err != -ENOENT) { 2554 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 2555 return err; 2556 } 2557 2558 pmc->clk = NULL; 2559 } 2560 2561 /* 2562 * PCLK clock rate can't be retrieved using CLK API because it 2563 * causes lockup if CPU enters LP2 idle state from some other 2564 * CLK notifier, hence we're caching the rate's value locally. 2565 */ 2566 if (pmc->clk) { 2567 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 2568 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); 2569 if (err) { 2570 dev_err(&pdev->dev, 2571 "failed to register clk notifier\n"); 2572 return err; 2573 } 2574 2575 pmc->rate = clk_get_rate(pmc->clk); 2576 } 2577 2578 pmc->dev = &pdev->dev; 2579 2580 tegra_pmc_init(pmc); 2581 2582 tegra_pmc_init_tsense_reset(pmc); 2583 2584 tegra_pmc_reset_sysfs_init(pmc); 2585 2586 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 2587 err = tegra_powergate_debugfs_init(); 2588 if (err < 0) 2589 goto cleanup_sysfs; 2590 } 2591 2592 err = register_restart_handler(&tegra_pmc_restart_handler); 2593 if (err) { 2594 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 2595 err); 2596 goto cleanup_debugfs; 2597 } 2598 2599 err = tegra_pmc_pinctrl_init(pmc); 2600 if (err) 2601 goto cleanup_restart_handler; 2602 2603 err = tegra_powergate_init(pmc, pdev->dev.of_node); 2604 if (err < 0) 2605 goto cleanup_powergates; 2606 2607 err = tegra_pmc_irq_init(pmc); 2608 if (err < 0) 2609 goto cleanup_powergates; 2610 2611 mutex_lock(&pmc->powergates_lock); 2612 iounmap(pmc->base); 2613 pmc->base = base; 2614 mutex_unlock(&pmc->powergates_lock); 2615 2616 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 2617 platform_set_drvdata(pdev, pmc); 2618 2619 return 0; 2620 2621 cleanup_powergates: 2622 tegra_powergate_remove_all(pdev->dev.of_node); 2623 cleanup_restart_handler: 2624 unregister_restart_handler(&tegra_pmc_restart_handler); 2625 cleanup_debugfs: 2626 debugfs_remove(pmc->debugfs); 2627 cleanup_sysfs: 2628 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 2629 device_remove_file(&pdev->dev, &dev_attr_reset_level); 2630 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); 2631 2632 return err; 2633 } 2634 2635 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 2636 static int tegra_pmc_suspend(struct device *dev) 2637 { 2638 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2639 2640 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 2641 2642 return 0; 2643 } 2644 2645 static int tegra_pmc_resume(struct device *dev) 2646 { 2647 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2648 2649 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 2650 2651 return 0; 2652 } 2653 2654 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 2655 2656 #endif 2657 2658 static const char * const tegra20_powergates[] = { 2659 [TEGRA_POWERGATE_CPU] = "cpu", 2660 [TEGRA_POWERGATE_3D] = "3d", 2661 [TEGRA_POWERGATE_VENC] = "venc", 2662 [TEGRA_POWERGATE_VDEC] = "vdec", 2663 [TEGRA_POWERGATE_PCIE] = "pcie", 2664 [TEGRA_POWERGATE_L2] = "l2", 2665 [TEGRA_POWERGATE_MPE] = "mpe", 2666 }; 2667 2668 static const struct tegra_pmc_regs tegra20_pmc_regs = { 2669 .scratch0 = 0x50, 2670 .dpd_req = 0x1b8, 2671 .dpd_status = 0x1bc, 2672 .dpd2_req = 0x1c0, 2673 .dpd2_status = 0x1c4, 2674 .rst_status = 0x1b4, 2675 .rst_source_shift = 0x0, 2676 .rst_source_mask = 0x7, 2677 .rst_level_shift = 0x0, 2678 .rst_level_mask = 0x0, 2679 }; 2680 2681 static void tegra20_pmc_init(struct tegra_pmc *pmc) 2682 { 2683 u32 value, osc, pmu, off; 2684 2685 /* Always enable CPU power request */ 2686 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2687 value |= PMC_CNTRL_CPU_PWRREQ_OE; 2688 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2689 2690 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2691 2692 if (pmc->sysclkreq_high) 2693 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 2694 else 2695 value |= PMC_CNTRL_SYSCLK_POLARITY; 2696 2697 if (pmc->corereq_high) 2698 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 2699 else 2700 value |= PMC_CNTRL_PWRREQ_POLARITY; 2701 2702 /* configure the output polarity while the request is tristated */ 2703 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2704 2705 /* now enable the request */ 2706 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2707 value |= PMC_CNTRL_SYSCLK_OE; 2708 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2709 2710 /* program core timings which are applicable only for suspend state */ 2711 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 2712 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 2713 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 2714 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 2715 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 2716 PMC_COREPWRGOOD_TIMER); 2717 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 2718 } 2719 } 2720 2721 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 2722 struct device_node *np, 2723 bool invert) 2724 { 2725 u32 value; 2726 2727 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2728 2729 if (invert) 2730 value |= PMC_CNTRL_INTR_POLARITY; 2731 else 2732 value &= ~PMC_CNTRL_INTR_POLARITY; 2733 2734 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2735 } 2736 2737 static const struct tegra_pmc_soc tegra20_pmc_soc = { 2738 .num_powergates = ARRAY_SIZE(tegra20_powergates), 2739 .powergates = tegra20_powergates, 2740 .num_cpu_powergates = 0, 2741 .cpu_powergates = NULL, 2742 .has_tsense_reset = false, 2743 .has_gpu_clamps = false, 2744 .needs_mbist_war = false, 2745 .has_impl_33v_pwr = false, 2746 .maybe_tz_only = false, 2747 .num_io_pads = 0, 2748 .io_pads = NULL, 2749 .num_pin_descs = 0, 2750 .pin_descs = NULL, 2751 .regs = &tegra20_pmc_regs, 2752 .init = tegra20_pmc_init, 2753 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2754 .reset_sources = NULL, 2755 .num_reset_sources = 0, 2756 .reset_levels = NULL, 2757 .num_reset_levels = 0, 2758 .pmc_clks_data = NULL, 2759 .num_pmc_clks = 0, 2760 .has_blink_output = true, 2761 }; 2762 2763 static const char * const tegra30_powergates[] = { 2764 [TEGRA_POWERGATE_CPU] = "cpu0", 2765 [TEGRA_POWERGATE_3D] = "3d0", 2766 [TEGRA_POWERGATE_VENC] = "venc", 2767 [TEGRA_POWERGATE_VDEC] = "vdec", 2768 [TEGRA_POWERGATE_PCIE] = "pcie", 2769 [TEGRA_POWERGATE_L2] = "l2", 2770 [TEGRA_POWERGATE_MPE] = "mpe", 2771 [TEGRA_POWERGATE_HEG] = "heg", 2772 [TEGRA_POWERGATE_SATA] = "sata", 2773 [TEGRA_POWERGATE_CPU1] = "cpu1", 2774 [TEGRA_POWERGATE_CPU2] = "cpu2", 2775 [TEGRA_POWERGATE_CPU3] = "cpu3", 2776 [TEGRA_POWERGATE_CELP] = "celp", 2777 [TEGRA_POWERGATE_3D1] = "3d1", 2778 }; 2779 2780 static const u8 tegra30_cpu_powergates[] = { 2781 TEGRA_POWERGATE_CPU, 2782 TEGRA_POWERGATE_CPU1, 2783 TEGRA_POWERGATE_CPU2, 2784 TEGRA_POWERGATE_CPU3, 2785 }; 2786 2787 static const struct tegra_pmc_soc tegra30_pmc_soc = { 2788 .num_powergates = ARRAY_SIZE(tegra30_powergates), 2789 .powergates = tegra30_powergates, 2790 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 2791 .cpu_powergates = tegra30_cpu_powergates, 2792 .has_tsense_reset = true, 2793 .has_gpu_clamps = false, 2794 .needs_mbist_war = false, 2795 .has_impl_33v_pwr = false, 2796 .maybe_tz_only = false, 2797 .num_io_pads = 0, 2798 .io_pads = NULL, 2799 .num_pin_descs = 0, 2800 .pin_descs = NULL, 2801 .regs = &tegra20_pmc_regs, 2802 .init = tegra20_pmc_init, 2803 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2804 .reset_sources = tegra30_reset_sources, 2805 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 2806 .reset_levels = NULL, 2807 .num_reset_levels = 0, 2808 .pmc_clks_data = tegra_pmc_clks_data, 2809 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 2810 .has_blink_output = true, 2811 }; 2812 2813 static const char * const tegra114_powergates[] = { 2814 [TEGRA_POWERGATE_CPU] = "crail", 2815 [TEGRA_POWERGATE_3D] = "3d", 2816 [TEGRA_POWERGATE_VENC] = "venc", 2817 [TEGRA_POWERGATE_VDEC] = "vdec", 2818 [TEGRA_POWERGATE_MPE] = "mpe", 2819 [TEGRA_POWERGATE_HEG] = "heg", 2820 [TEGRA_POWERGATE_CPU1] = "cpu1", 2821 [TEGRA_POWERGATE_CPU2] = "cpu2", 2822 [TEGRA_POWERGATE_CPU3] = "cpu3", 2823 [TEGRA_POWERGATE_CELP] = "celp", 2824 [TEGRA_POWERGATE_CPU0] = "cpu0", 2825 [TEGRA_POWERGATE_C0NC] = "c0nc", 2826 [TEGRA_POWERGATE_C1NC] = "c1nc", 2827 [TEGRA_POWERGATE_DIS] = "dis", 2828 [TEGRA_POWERGATE_DISB] = "disb", 2829 [TEGRA_POWERGATE_XUSBA] = "xusba", 2830 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2831 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2832 }; 2833 2834 static const u8 tegra114_cpu_powergates[] = { 2835 TEGRA_POWERGATE_CPU0, 2836 TEGRA_POWERGATE_CPU1, 2837 TEGRA_POWERGATE_CPU2, 2838 TEGRA_POWERGATE_CPU3, 2839 }; 2840 2841 static const struct tegra_pmc_soc tegra114_pmc_soc = { 2842 .num_powergates = ARRAY_SIZE(tegra114_powergates), 2843 .powergates = tegra114_powergates, 2844 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 2845 .cpu_powergates = tegra114_cpu_powergates, 2846 .has_tsense_reset = true, 2847 .has_gpu_clamps = false, 2848 .needs_mbist_war = false, 2849 .has_impl_33v_pwr = false, 2850 .maybe_tz_only = false, 2851 .num_io_pads = 0, 2852 .io_pads = NULL, 2853 .num_pin_descs = 0, 2854 .pin_descs = NULL, 2855 .regs = &tegra20_pmc_regs, 2856 .init = tegra20_pmc_init, 2857 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2858 .reset_sources = tegra30_reset_sources, 2859 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 2860 .reset_levels = NULL, 2861 .num_reset_levels = 0, 2862 .pmc_clks_data = tegra_pmc_clks_data, 2863 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 2864 .has_blink_output = true, 2865 }; 2866 2867 static const char * const tegra124_powergates[] = { 2868 [TEGRA_POWERGATE_CPU] = "crail", 2869 [TEGRA_POWERGATE_3D] = "3d", 2870 [TEGRA_POWERGATE_VENC] = "venc", 2871 [TEGRA_POWERGATE_PCIE] = "pcie", 2872 [TEGRA_POWERGATE_VDEC] = "vdec", 2873 [TEGRA_POWERGATE_MPE] = "mpe", 2874 [TEGRA_POWERGATE_HEG] = "heg", 2875 [TEGRA_POWERGATE_SATA] = "sata", 2876 [TEGRA_POWERGATE_CPU1] = "cpu1", 2877 [TEGRA_POWERGATE_CPU2] = "cpu2", 2878 [TEGRA_POWERGATE_CPU3] = "cpu3", 2879 [TEGRA_POWERGATE_CELP] = "celp", 2880 [TEGRA_POWERGATE_CPU0] = "cpu0", 2881 [TEGRA_POWERGATE_C0NC] = "c0nc", 2882 [TEGRA_POWERGATE_C1NC] = "c1nc", 2883 [TEGRA_POWERGATE_SOR] = "sor", 2884 [TEGRA_POWERGATE_DIS] = "dis", 2885 [TEGRA_POWERGATE_DISB] = "disb", 2886 [TEGRA_POWERGATE_XUSBA] = "xusba", 2887 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2888 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2889 [TEGRA_POWERGATE_VIC] = "vic", 2890 [TEGRA_POWERGATE_IRAM] = "iram", 2891 }; 2892 2893 static const u8 tegra124_cpu_powergates[] = { 2894 TEGRA_POWERGATE_CPU0, 2895 TEGRA_POWERGATE_CPU1, 2896 TEGRA_POWERGATE_CPU2, 2897 TEGRA_POWERGATE_CPU3, 2898 }; 2899 2900 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ 2901 ((struct tegra_io_pad_soc) { \ 2902 .id = (_id), \ 2903 .dpd = (_dpd), \ 2904 .voltage = (_voltage), \ 2905 .name = (_name), \ 2906 }) 2907 2908 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ 2909 ((struct pinctrl_pin_desc) { \ 2910 .number = (_id), \ 2911 .name = (_name) \ 2912 }) 2913 2914 #define TEGRA124_IO_PAD_TABLE(_pad) \ 2915 /* .id .dpd .voltage .name */ \ 2916 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 2917 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ 2918 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ 2919 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ 2920 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2921 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ 2922 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ 2923 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2924 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 2925 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 2926 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 2927 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 2928 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2929 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ 2930 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 2931 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2932 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ 2933 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 2934 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 2935 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2936 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 2937 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ 2938 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ 2939 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ 2940 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ 2941 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 2942 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2943 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2944 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2945 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") 2946 2947 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 2948 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) 2949 }; 2950 2951 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 2952 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2953 }; 2954 2955 static const struct tegra_pmc_soc tegra124_pmc_soc = { 2956 .num_powergates = ARRAY_SIZE(tegra124_powergates), 2957 .powergates = tegra124_powergates, 2958 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 2959 .cpu_powergates = tegra124_cpu_powergates, 2960 .has_tsense_reset = true, 2961 .has_gpu_clamps = true, 2962 .needs_mbist_war = false, 2963 .has_impl_33v_pwr = false, 2964 .maybe_tz_only = false, 2965 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 2966 .io_pads = tegra124_io_pads, 2967 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 2968 .pin_descs = tegra124_pin_descs, 2969 .regs = &tegra20_pmc_regs, 2970 .init = tegra20_pmc_init, 2971 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2972 .reset_sources = tegra30_reset_sources, 2973 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 2974 .reset_levels = NULL, 2975 .num_reset_levels = 0, 2976 .pmc_clks_data = tegra_pmc_clks_data, 2977 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 2978 .has_blink_output = true, 2979 }; 2980 2981 static const char * const tegra210_powergates[] = { 2982 [TEGRA_POWERGATE_CPU] = "crail", 2983 [TEGRA_POWERGATE_3D] = "3d", 2984 [TEGRA_POWERGATE_VENC] = "venc", 2985 [TEGRA_POWERGATE_PCIE] = "pcie", 2986 [TEGRA_POWERGATE_MPE] = "mpe", 2987 [TEGRA_POWERGATE_SATA] = "sata", 2988 [TEGRA_POWERGATE_CPU1] = "cpu1", 2989 [TEGRA_POWERGATE_CPU2] = "cpu2", 2990 [TEGRA_POWERGATE_CPU3] = "cpu3", 2991 [TEGRA_POWERGATE_CPU0] = "cpu0", 2992 [TEGRA_POWERGATE_C0NC] = "c0nc", 2993 [TEGRA_POWERGATE_SOR] = "sor", 2994 [TEGRA_POWERGATE_DIS] = "dis", 2995 [TEGRA_POWERGATE_DISB] = "disb", 2996 [TEGRA_POWERGATE_XUSBA] = "xusba", 2997 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2998 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2999 [TEGRA_POWERGATE_VIC] = "vic", 3000 [TEGRA_POWERGATE_IRAM] = "iram", 3001 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3002 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3003 [TEGRA_POWERGATE_AUD] = "aud", 3004 [TEGRA_POWERGATE_DFD] = "dfd", 3005 [TEGRA_POWERGATE_VE2] = "ve2", 3006 }; 3007 3008 static const u8 tegra210_cpu_powergates[] = { 3009 TEGRA_POWERGATE_CPU0, 3010 TEGRA_POWERGATE_CPU1, 3011 TEGRA_POWERGATE_CPU2, 3012 TEGRA_POWERGATE_CPU3, 3013 }; 3014 3015 #define TEGRA210_IO_PAD_TABLE(_pad) \ 3016 /* .id .dpd .voltage .name */ \ 3017 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ 3018 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ 3019 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ 3020 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3021 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3022 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ 3023 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ 3024 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ 3025 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ 3026 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ 3027 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ 3028 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ 3029 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ 3030 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3031 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 3032 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 3033 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 3034 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ 3035 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ 3036 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ 3037 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 3038 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3039 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 3040 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3041 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 3042 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 3043 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3044 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ 3045 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ 3046 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ 3047 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ 3048 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ 3049 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ 3050 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3051 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3052 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3053 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ 3054 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") 3055 3056 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3057 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) 3058 }; 3059 3060 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3061 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3062 }; 3063 3064 static const struct tegra_wake_event tegra210_wake_events[] = { 3065 TEGRA_WAKE_IRQ("rtc", 16, 2), 3066 TEGRA_WAKE_IRQ("pmu", 51, 86), 3067 }; 3068 3069 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3070 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3071 .powergates = tegra210_powergates, 3072 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3073 .cpu_powergates = tegra210_cpu_powergates, 3074 .has_tsense_reset = true, 3075 .has_gpu_clamps = true, 3076 .needs_mbist_war = true, 3077 .has_impl_33v_pwr = false, 3078 .maybe_tz_only = true, 3079 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3080 .io_pads = tegra210_io_pads, 3081 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3082 .pin_descs = tegra210_pin_descs, 3083 .regs = &tegra20_pmc_regs, 3084 .init = tegra20_pmc_init, 3085 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3086 .irq_set_wake = tegra210_pmc_irq_set_wake, 3087 .irq_set_type = tegra210_pmc_irq_set_type, 3088 .reset_sources = tegra210_reset_sources, 3089 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3090 .reset_levels = NULL, 3091 .num_reset_levels = 0, 3092 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3093 .wake_events = tegra210_wake_events, 3094 .pmc_clks_data = tegra_pmc_clks_data, 3095 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3096 .has_blink_output = true, 3097 }; 3098 3099 #define TEGRA186_IO_PAD_TABLE(_pad) \ 3100 /* .id .dpd .voltage .name */ \ 3101 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3102 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3103 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3104 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3105 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 3106 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 3107 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3108 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 3109 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3110 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3111 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3112 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ 3113 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3114 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3115 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3116 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 3117 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 3118 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 3119 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3120 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ 3121 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 3122 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 3123 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ 3124 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ 3125 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ 3126 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 3127 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 3128 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 3129 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 3130 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 3131 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 3132 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ 3133 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 3134 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 3135 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 3136 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 3137 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 3138 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 3139 3140 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3141 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) 3142 }; 3143 3144 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 3145 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3146 }; 3147 3148 static const struct tegra_pmc_regs tegra186_pmc_regs = { 3149 .scratch0 = 0x2000, 3150 .dpd_req = 0x74, 3151 .dpd_status = 0x78, 3152 .dpd2_req = 0x7c, 3153 .dpd2_status = 0x80, 3154 .rst_status = 0x70, 3155 .rst_source_shift = 0x2, 3156 .rst_source_mask = 0x3c, 3157 .rst_level_shift = 0x0, 3158 .rst_level_mask = 0x3, 3159 }; 3160 3161 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3162 struct device_node *np, 3163 bool invert) 3164 { 3165 struct resource regs; 3166 void __iomem *wake; 3167 u32 value; 3168 int index; 3169 3170 index = of_property_match_string(np, "reg-names", "wake"); 3171 if (index < 0) { 3172 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 3173 return; 3174 } 3175 3176 of_address_to_resource(np, index, ®s); 3177 3178 wake = ioremap(regs.start, resource_size(®s)); 3179 if (!wake) { 3180 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 3181 return; 3182 } 3183 3184 value = readl(wake + WAKE_AOWAKE_CTRL); 3185 3186 if (invert) 3187 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 3188 else 3189 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 3190 3191 writel(value, wake + WAKE_AOWAKE_CTRL); 3192 3193 iounmap(wake); 3194 } 3195 3196 static const struct tegra_wake_event tegra186_wake_events[] = { 3197 TEGRA_WAKE_IRQ("pmu", 24, 209), 3198 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 3199 TEGRA_WAKE_IRQ("rtc", 73, 10), 3200 }; 3201 3202 static const struct tegra_pmc_soc tegra186_pmc_soc = { 3203 .num_powergates = 0, 3204 .powergates = NULL, 3205 .num_cpu_powergates = 0, 3206 .cpu_powergates = NULL, 3207 .has_tsense_reset = false, 3208 .has_gpu_clamps = false, 3209 .needs_mbist_war = false, 3210 .has_impl_33v_pwr = true, 3211 .maybe_tz_only = false, 3212 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 3213 .io_pads = tegra186_io_pads, 3214 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 3215 .pin_descs = tegra186_pin_descs, 3216 .regs = &tegra186_pmc_regs, 3217 .init = NULL, 3218 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3219 .irq_set_wake = tegra186_pmc_irq_set_wake, 3220 .irq_set_type = tegra186_pmc_irq_set_type, 3221 .reset_sources = tegra186_reset_sources, 3222 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 3223 .reset_levels = tegra186_reset_levels, 3224 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3225 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 3226 .wake_events = tegra186_wake_events, 3227 .pmc_clks_data = NULL, 3228 .num_pmc_clks = 0, 3229 .has_blink_output = false, 3230 }; 3231 3232 #define TEGRA194_IO_PAD_TABLE(_pad) \ 3233 /* .id .dpd .voltage .name */ \ 3234 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3235 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3236 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3237 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 3238 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 3239 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3240 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 3241 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \ 3242 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \ 3243 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \ 3244 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \ 3245 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \ 3246 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3247 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \ 3248 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \ 3249 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3250 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \ 3251 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \ 3252 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \ 3253 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \ 3254 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \ 3255 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \ 3256 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \ 3257 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 3258 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \ 3259 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \ 3260 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 3261 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 3262 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3263 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \ 3264 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \ 3265 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \ 3266 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 3267 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \ 3268 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 3269 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 3270 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 3271 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 3272 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 3273 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 3274 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 3275 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \ 3276 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \ 3277 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 3278 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 3279 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 3280 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 3281 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 3282 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 3283 3284 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 3285 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD) 3286 }; 3287 3288 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 3289 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3290 }; 3291 3292 static const struct tegra_pmc_regs tegra194_pmc_regs = { 3293 .scratch0 = 0x2000, 3294 .dpd_req = 0x74, 3295 .dpd_status = 0x78, 3296 .dpd2_req = 0x7c, 3297 .dpd2_status = 0x80, 3298 .rst_status = 0x70, 3299 .rst_source_shift = 0x2, 3300 .rst_source_mask = 0x7c, 3301 .rst_level_shift = 0x0, 3302 .rst_level_mask = 0x3, 3303 }; 3304 3305 static const char * const tegra194_reset_sources[] = { 3306 "SYS_RESET_N", 3307 "AOWDT", 3308 "BCCPLEXWDT", 3309 "BPMPWDT", 3310 "SCEWDT", 3311 "SPEWDT", 3312 "APEWDT", 3313 "LCCPLEXWDT", 3314 "SENSOR", 3315 "AOTAG", 3316 "VFSENSOR", 3317 "MAINSWRST", 3318 "SC7", 3319 "HSM", 3320 "CSITE", 3321 "RCEWDT", 3322 "PVA0WDT", 3323 "PVA1WDT", 3324 "L1A_ASYNC", 3325 "BPMPBOOT", 3326 "FUSECRC", 3327 }; 3328 3329 static const struct tegra_wake_event tegra194_wake_events[] = { 3330 TEGRA_WAKE_IRQ("pmu", 24, 209), 3331 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 3332 TEGRA_WAKE_IRQ("rtc", 73, 10), 3333 }; 3334 3335 static const struct tegra_pmc_soc tegra194_pmc_soc = { 3336 .num_powergates = 0, 3337 .powergates = NULL, 3338 .num_cpu_powergates = 0, 3339 .cpu_powergates = NULL, 3340 .has_tsense_reset = false, 3341 .has_gpu_clamps = false, 3342 .needs_mbist_war = false, 3343 .has_impl_33v_pwr = true, 3344 .maybe_tz_only = false, 3345 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 3346 .io_pads = tegra194_io_pads, 3347 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 3348 .pin_descs = tegra194_pin_descs, 3349 .regs = &tegra194_pmc_regs, 3350 .init = NULL, 3351 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3352 .irq_set_wake = tegra186_pmc_irq_set_wake, 3353 .irq_set_type = tegra186_pmc_irq_set_type, 3354 .reset_sources = tegra194_reset_sources, 3355 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 3356 .reset_levels = tegra186_reset_levels, 3357 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3358 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 3359 .wake_events = tegra194_wake_events, 3360 .pmc_clks_data = NULL, 3361 .num_pmc_clks = 0, 3362 .has_blink_output = false, 3363 }; 3364 3365 static const struct of_device_id tegra_pmc_match[] = { 3366 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 3367 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 3368 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 3369 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 3370 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 3371 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 3372 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 3373 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 3374 { } 3375 }; 3376 3377 static struct platform_driver tegra_pmc_driver = { 3378 .driver = { 3379 .name = "tegra-pmc", 3380 .suppress_bind_attrs = true, 3381 .of_match_table = tegra_pmc_match, 3382 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3383 .pm = &tegra_pmc_pm_ops, 3384 #endif 3385 }, 3386 .probe = tegra_pmc_probe, 3387 }; 3388 builtin_platform_driver(tegra_pmc_driver); 3389 3390 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 3391 { 3392 u32 value, saved; 3393 3394 saved = readl(pmc->base + pmc->soc->regs->scratch0); 3395 value = saved ^ 0xffffffff; 3396 3397 if (value == 0xffffffff) 3398 value = 0xdeadbeef; 3399 3400 /* write pattern and read it back */ 3401 writel(value, pmc->base + pmc->soc->regs->scratch0); 3402 value = readl(pmc->base + pmc->soc->regs->scratch0); 3403 3404 /* if we read all-zeroes, access is restricted to TZ only */ 3405 if (value == 0) { 3406 pr_info("access to PMC is restricted to TZ\n"); 3407 return true; 3408 } 3409 3410 /* restore original value */ 3411 writel(saved, pmc->base + pmc->soc->regs->scratch0); 3412 3413 return false; 3414 } 3415 3416 /* 3417 * Early initialization to allow access to registers in the very early boot 3418 * process. 3419 */ 3420 static int __init tegra_pmc_early_init(void) 3421 { 3422 const struct of_device_id *match; 3423 struct device_node *np; 3424 struct resource regs; 3425 unsigned int i; 3426 bool invert; 3427 3428 mutex_init(&pmc->powergates_lock); 3429 3430 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 3431 if (!np) { 3432 /* 3433 * Fall back to legacy initialization for 32-bit ARM only. All 3434 * 64-bit ARM device tree files for Tegra are required to have 3435 * a PMC node. 3436 * 3437 * This is for backwards-compatibility with old device trees 3438 * that didn't contain a PMC node. Note that in this case the 3439 * SoC data can't be matched and therefore powergating is 3440 * disabled. 3441 */ 3442 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 3443 pr_warn("DT node not found, powergating disabled\n"); 3444 3445 regs.start = 0x7000e400; 3446 regs.end = 0x7000e7ff; 3447 regs.flags = IORESOURCE_MEM; 3448 3449 pr_warn("Using memory region %pR\n", ®s); 3450 } else { 3451 /* 3452 * At this point we're not running on Tegra, so play 3453 * nice with multi-platform kernels. 3454 */ 3455 return 0; 3456 } 3457 } else { 3458 /* 3459 * Extract information from the device tree if we've found a 3460 * matching node. 3461 */ 3462 if (of_address_to_resource(np, 0, ®s) < 0) { 3463 pr_err("failed to get PMC registers\n"); 3464 of_node_put(np); 3465 return -ENXIO; 3466 } 3467 } 3468 3469 pmc->base = ioremap(regs.start, resource_size(®s)); 3470 if (!pmc->base) { 3471 pr_err("failed to map PMC registers\n"); 3472 of_node_put(np); 3473 return -ENXIO; 3474 } 3475 3476 if (np) { 3477 pmc->soc = match->data; 3478 3479 if (pmc->soc->maybe_tz_only) 3480 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 3481 3482 /* Create a bitmap of the available and valid partitions */ 3483 for (i = 0; i < pmc->soc->num_powergates; i++) 3484 if (pmc->soc->powergates[i]) 3485 set_bit(i, pmc->powergates_available); 3486 3487 /* 3488 * Invert the interrupt polarity if a PMC device tree node 3489 * exists and contains the nvidia,invert-interrupt property. 3490 */ 3491 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 3492 3493 pmc->soc->setup_irq_polarity(pmc, np, invert); 3494 3495 of_node_put(np); 3496 } 3497 3498 return 0; 3499 } 3500 early_initcall(tegra_pmc_early_init); 3501