1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/arm-smccc.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 20 #include <linux/debugfs.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/iopoll.h> 29 #include <linux/irqdomain.h> 30 #include <linux/irq.h> 31 #include <linux/kernel.h> 32 #include <linux/of_address.h> 33 #include <linux/of_clk.h> 34 #include <linux/of.h> 35 #include <linux/of_irq.h> 36 #include <linux/of_platform.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/pinctrl/pinconf.h> 39 #include <linux/pinctrl/pinctrl.h> 40 #include <linux/platform_device.h> 41 #include <linux/pm_domain.h> 42 #include <linux/pm_opp.h> 43 #include <linux/power_supply.h> 44 #include <linux/reboot.h> 45 #include <linux/regmap.h> 46 #include <linux/reset.h> 47 #include <linux/seq_file.h> 48 #include <linux/slab.h> 49 #include <linux/spinlock.h> 50 #include <linux/string_choices.h> 51 #include <linux/syscore_ops.h> 52 53 #include <soc/tegra/common.h> 54 #include <soc/tegra/fuse.h> 55 #include <soc/tegra/pmc.h> 56 57 #include <dt-bindings/interrupt-controller/arm-gic.h> 58 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 59 #include <dt-bindings/gpio/tegra186-gpio.h> 60 #include <dt-bindings/gpio/tegra194-gpio.h> 61 #include <dt-bindings/gpio/tegra234-gpio.h> 62 #include <dt-bindings/soc/tegra-pmc.h> 63 64 #define PMC_CNTRL 0x0 65 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 66 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 67 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 68 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 69 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 70 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 71 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 72 #define PMC_CNTRL_BLINK_EN 7 73 #define PMC_CNTRL_MAIN_RST BIT(4) 74 75 #define PMC_WAKE_MASK 0x0c 76 #define PMC_WAKE_LEVEL 0x10 77 #define PMC_WAKE_STATUS 0x14 78 #define PMC_SW_WAKE_STATUS 0x18 79 #define PMC_DPD_PADS_ORIDE 0x1c 80 #define PMC_DPD_PADS_ORIDE_BLINK 20 81 82 #define DPD_SAMPLE 0x020 83 #define DPD_SAMPLE_ENABLE BIT(0) 84 #define DPD_SAMPLE_DISABLE (0 << 0) 85 86 #define PWRGATE_TOGGLE 0x30 87 #define PWRGATE_TOGGLE_START BIT(8) 88 89 #define REMOVE_CLAMPING 0x34 90 91 #define PWRGATE_STATUS 0x38 92 93 #define PMC_BLINK_TIMER 0x40 94 #define PMC_IMPL_E_33V_PWR 0x40 95 96 #define PMC_PWR_DET 0x48 97 98 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 99 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 100 #define PMC_SCRATCH0_MODE_RCM BIT(1) 101 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 102 PMC_SCRATCH0_MODE_BOOTLOADER | \ 103 PMC_SCRATCH0_MODE_RCM) 104 105 #define PMC_CPUPWRGOOD_TIMER 0xc8 106 #define PMC_CPUPWROFF_TIMER 0xcc 107 #define PMC_COREPWRGOOD_TIMER 0x3c 108 #define PMC_COREPWROFF_TIMER 0xe0 109 110 #define PMC_PWR_DET_VALUE 0xe4 111 112 #define PMC_USB_DEBOUNCE_DEL 0xec 113 #define PMC_USB_AO 0xf0 114 115 #define PMC_SCRATCH37 0x130 116 #define PMC_SCRATCH41 0x140 117 118 #define PMC_WAKE2_MASK 0x160 119 #define PMC_WAKE2_LEVEL 0x164 120 #define PMC_WAKE2_STATUS 0x168 121 #define PMC_SW_WAKE2_STATUS 0x16c 122 123 #define PMC_CLK_OUT_CNTRL 0x1a8 124 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 125 #define PMC_SENSOR_CTRL 0x1b0 126 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 127 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 128 129 #define PMC_RST_STATUS_POR 0 130 #define PMC_RST_STATUS_WATCHDOG 1 131 #define PMC_RST_STATUS_SENSOR 2 132 #define PMC_RST_STATUS_SW_MAIN 3 133 #define PMC_RST_STATUS_LP0 4 134 #define PMC_RST_STATUS_AOTAG 5 135 136 #define IO_DPD_REQ 0x1b8 137 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 138 #define IO_DPD_REQ_CODE_OFF (1U << 30) 139 #define IO_DPD_REQ_CODE_ON (2U << 30) 140 #define IO_DPD_REQ_CODE_MASK (3U << 30) 141 142 #define IO_DPD_STATUS 0x1bc 143 #define IO_DPD2_REQ 0x1c0 144 #define IO_DPD2_STATUS 0x1c4 145 #define SEL_DPD_TIM 0x1c8 146 147 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec 148 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0 149 150 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8 151 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc 152 #define PMC_UTMIP_UHSIC_FAKE 0x218 153 154 #define PMC_SCRATCH54 0x258 155 #define PMC_SCRATCH54_DATA_SHIFT 8 156 #define PMC_SCRATCH54_ADDR_SHIFT 0 157 158 #define PMC_SCRATCH55 0x25c 159 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 160 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 161 #define PMC_SCRATCH55_PINMUX_SHIFT 24 162 #define PMC_SCRATCH55_16BITOP BIT(15) 163 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 164 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 165 166 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c 167 168 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270 169 #define PMC_UTMIP_MASTER_CONFIG 0x274 170 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c 171 #define PMC_UTMIP_MASTER2_CONFIG 0x29c 172 173 #define GPU_RG_CNTRL 0x2d4 174 175 #define PMC_UTMIP_PAD_CFG0 0x4c0 176 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0 177 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0 178 /* Tegra186 and later */ 179 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 180 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 181 #define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1) 182 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 183 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 184 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 185 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 186 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 187 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 188 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 189 #define WAKE_AOWAKE_SW_STATUS_W_0 0x49c 190 #define WAKE_AOWAKE_SW_STATUS(x) (0x4a0 + ((x) << 2)) 191 #define WAKE_LATCH_SW 0x498 192 193 #define WAKE_AOWAKE_CTRL 0x4f4 194 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 195 196 #define SW_WAKE_ID 83 /* wake83 */ 197 198 /* for secure PMC */ 199 #define TEGRA_SMC_PMC 0xc2fffe00 200 #define TEGRA_SMC_PMC_READ 0xaa 201 #define TEGRA_SMC_PMC_WRITE 0xbb 202 203 struct pmc_clk { 204 struct clk_hw hw; 205 unsigned long offs; 206 u32 mux_shift; 207 u32 force_en_shift; 208 }; 209 210 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 211 212 struct pmc_clk_gate { 213 struct clk_hw hw; 214 unsigned long offs; 215 u32 shift; 216 }; 217 218 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 219 220 struct pmc_clk_init_data { 221 char *name; 222 const char *const *parents; 223 int num_parents; 224 int clk_id; 225 u8 mux_shift; 226 u8 force_en_shift; 227 }; 228 229 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 230 "osc_div4", "extern1", 231 }; 232 233 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 234 "osc_div4", "extern2", 235 }; 236 237 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 238 "osc_div4", "extern3", 239 }; 240 241 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 242 { 243 .name = "pmc_clk_out_1", 244 .parents = clk_out1_parents, 245 .num_parents = ARRAY_SIZE(clk_out1_parents), 246 .clk_id = TEGRA_PMC_CLK_OUT_1, 247 .mux_shift = 6, 248 .force_en_shift = 2, 249 }, 250 { 251 .name = "pmc_clk_out_2", 252 .parents = clk_out2_parents, 253 .num_parents = ARRAY_SIZE(clk_out2_parents), 254 .clk_id = TEGRA_PMC_CLK_OUT_2, 255 .mux_shift = 14, 256 .force_en_shift = 10, 257 }, 258 { 259 .name = "pmc_clk_out_3", 260 .parents = clk_out3_parents, 261 .num_parents = ARRAY_SIZE(clk_out3_parents), 262 .clk_id = TEGRA_PMC_CLK_OUT_3, 263 .mux_shift = 22, 264 .force_en_shift = 18, 265 }, 266 }; 267 268 struct tegra_powergate { 269 struct generic_pm_domain genpd; 270 struct tegra_pmc *pmc; 271 unsigned int id; 272 struct clk **clks; 273 unsigned int num_clks; 274 unsigned long *clk_rates; 275 struct reset_control *reset; 276 }; 277 278 struct tegra_io_pad_soc { 279 enum tegra_io_pad id; 280 unsigned int dpd; 281 unsigned int request; 282 unsigned int status; 283 unsigned int voltage; 284 const char *name; 285 }; 286 287 struct tegra_pmc_regs { 288 unsigned int scratch0; 289 unsigned int rst_status; 290 unsigned int rst_source_shift; 291 unsigned int rst_source_mask; 292 unsigned int rst_level_shift; 293 unsigned int rst_level_mask; 294 }; 295 296 struct tegra_wake_event { 297 const char *name; 298 unsigned int id; 299 unsigned int irq; 300 struct { 301 unsigned int instance; 302 unsigned int pin; 303 } gpio; 304 }; 305 306 #define TEGRA_WAKE_SIMPLE(_name, _id) \ 307 { \ 308 .name = _name, \ 309 .id = _id, \ 310 .irq = 0, \ 311 .gpio = { \ 312 .instance = UINT_MAX, \ 313 .pin = UINT_MAX, \ 314 }, \ 315 } 316 317 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 318 { \ 319 .name = _name, \ 320 .id = _id, \ 321 .irq = _irq, \ 322 .gpio = { \ 323 .instance = UINT_MAX, \ 324 .pin = UINT_MAX, \ 325 }, \ 326 } 327 328 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 329 { \ 330 .name = _name, \ 331 .id = _id, \ 332 .irq = 0, \ 333 .gpio = { \ 334 .instance = _instance, \ 335 .pin = _pin, \ 336 }, \ 337 } 338 339 struct tegra_pmc_soc { 340 unsigned int num_powergates; 341 const char *const *powergates; 342 unsigned int num_cpu_powergates; 343 const u8 *cpu_powergates; 344 345 bool has_tsense_reset; 346 bool has_gpu_clamps; 347 bool needs_mbist_war; 348 bool has_impl_33v_pwr; 349 bool maybe_tz_only; 350 351 const struct tegra_io_pad_soc *io_pads; 352 unsigned int num_io_pads; 353 354 const struct pinctrl_pin_desc *pin_descs; 355 unsigned int num_pin_descs; 356 357 const struct tegra_pmc_regs *regs; 358 void (*init)(struct tegra_pmc *pmc); 359 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 360 struct device_node *np, 361 bool invert); 362 void (*set_wake_filters)(struct tegra_pmc *pmc); 363 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 364 int (*irq_set_type)(struct irq_data *data, unsigned int type); 365 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, 366 bool new_state); 367 368 const char * const *reset_sources; 369 unsigned int num_reset_sources; 370 const char * const *reset_levels; 371 unsigned int num_reset_levels; 372 373 /* 374 * These describe events that can wake the system from sleep (i.e. 375 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 376 * are dealt with in the LIC. 377 */ 378 const struct tegra_wake_event *wake_events; 379 unsigned int num_wake_events; 380 unsigned int max_wake_events; 381 unsigned int max_wake_vectors; 382 383 const struct pmc_clk_init_data *pmc_clks_data; 384 unsigned int num_pmc_clks; 385 bool has_blink_output; 386 bool has_usb_sleepwalk; 387 bool supports_core_domain; 388 bool has_single_mmio_aperture; 389 }; 390 391 /** 392 * struct tegra_pmc - NVIDIA Tegra PMC 393 * @dev: pointer to PMC device structure 394 * @base: pointer to I/O remapped register region 395 * @wake: pointer to I/O remapped region for WAKE registers 396 * @aotag: pointer to I/O remapped region for AOTAG registers 397 * @scratch: pointer to I/O remapped region for scratch registers 398 * @clk: pointer to pclk clock 399 * @soc: pointer to SoC data structure 400 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 401 * @rate: currently configured rate of pclk 402 * @suspend_mode: lowest suspend mode available 403 * @cpu_good_time: CPU power good time (in microseconds) 404 * @cpu_off_time: CPU power off time (in microsecends) 405 * @core_osc_time: core power good OSC time (in microseconds) 406 * @core_pmu_time: core power good PMU time (in microseconds) 407 * @core_off_time: core power off time (in microseconds) 408 * @corereq_high: core power request is active-high 409 * @sysclkreq_high: system clock request is active-high 410 * @combined_req: combined power request for CPU & core 411 * @cpu_pwr_good_en: CPU power good signal is enabled 412 * @lp0_vec_phys: physical base address of the LP0 warm boot code 413 * @lp0_vec_size: size of the LP0 warm boot code 414 * @powergates_available: Bitmap of available power gates 415 * @powergates_lock: mutex for power gate register access 416 * @pctl_dev: pin controller exposed by the PMC 417 * @domain: IRQ domain provided by the PMC 418 * @irq: chip implementation for the IRQ domain 419 * @clk_nb: pclk clock changes handler 420 * @core_domain_state_synced: flag marking the core domain's state as synced 421 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes 422 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not 423 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask 424 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in 425 * cntrl register associated with each wake during system suspend. 426 */ 427 struct tegra_pmc { 428 struct device *dev; 429 void __iomem *base; 430 void __iomem *wake; 431 void __iomem *aotag; 432 void __iomem *scratch; 433 struct clk *clk; 434 435 const struct tegra_pmc_soc *soc; 436 bool tz_only; 437 438 unsigned long rate; 439 440 enum tegra_suspend_mode suspend_mode; 441 u32 cpu_good_time; 442 u32 cpu_off_time; 443 u32 core_osc_time; 444 u32 core_pmu_time; 445 u32 core_off_time; 446 bool corereq_high; 447 bool sysclkreq_high; 448 bool combined_req; 449 bool cpu_pwr_good_en; 450 u32 lp0_vec_phys; 451 u32 lp0_vec_size; 452 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 453 454 struct mutex powergates_lock; 455 456 struct pinctrl_dev *pctl_dev; 457 458 struct irq_domain *domain; 459 struct irq_chip irq; 460 461 struct notifier_block clk_nb; 462 463 bool core_domain_state_synced; 464 465 unsigned long *wake_type_level_map; 466 unsigned long *wake_type_dual_edge_map; 467 unsigned long *wake_sw_status_map; 468 unsigned long *wake_cntrl_level_map; 469 struct syscore_ops syscore; 470 }; 471 472 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 473 .base = NULL, 474 .suspend_mode = TEGRA_SUSPEND_NOT_READY, 475 }; 476 477 static inline struct tegra_powergate * 478 to_powergate(struct generic_pm_domain *domain) 479 { 480 return container_of(domain, struct tegra_powergate, genpd); 481 } 482 483 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 484 { 485 struct arm_smccc_res res; 486 487 if (pmc->tz_only) { 488 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 489 0, 0, 0, &res); 490 if (res.a0) { 491 if (pmc->dev) 492 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 493 __func__, res.a0); 494 else 495 pr_warn("%s(): SMC failed: %lu\n", __func__, 496 res.a0); 497 } 498 499 return res.a1; 500 } 501 502 return readl(pmc->base + offset); 503 } 504 505 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 506 unsigned long offset) 507 { 508 struct arm_smccc_res res; 509 510 if (pmc->tz_only) { 511 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 512 value, 0, 0, 0, 0, &res); 513 if (res.a0) { 514 if (pmc->dev) 515 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 516 __func__, res.a0); 517 else 518 pr_warn("%s(): SMC failed: %lu\n", __func__, 519 res.a0); 520 } 521 } else { 522 writel(value, pmc->base + offset); 523 } 524 } 525 526 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 527 { 528 if (pmc->tz_only) 529 return tegra_pmc_readl(pmc, offset); 530 531 return readl(pmc->scratch + offset); 532 } 533 534 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 535 unsigned long offset) 536 { 537 if (pmc->tz_only) 538 tegra_pmc_writel(pmc, value, offset); 539 else 540 writel(value, pmc->scratch + offset); 541 } 542 543 /* 544 * TODO Figure out a way to call this with the struct tegra_pmc * passed in. 545 * This currently doesn't work because readx_poll_timeout() can only operate 546 * on functions that take a single argument. 547 */ 548 static inline bool tegra_powergate_state(int id) 549 { 550 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 551 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 552 else 553 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 554 } 555 556 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 557 { 558 return (pmc->soc && pmc->soc->powergates[id]); 559 } 560 561 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 562 { 563 return test_bit(id, pmc->powergates_available); 564 } 565 566 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 567 { 568 unsigned int i; 569 570 if (!pmc || !pmc->soc || !name) 571 return -EINVAL; 572 573 for (i = 0; i < pmc->soc->num_powergates; i++) { 574 if (!tegra_powergate_is_valid(pmc, i)) 575 continue; 576 577 if (!strcmp(name, pmc->soc->powergates[i])) 578 return i; 579 } 580 581 return -ENODEV; 582 } 583 584 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, 585 bool new_state) 586 { 587 unsigned int retries = 100; 588 bool status; 589 int ret; 590 591 /* 592 * As per TRM documentation, the toggle command will be dropped by PMC 593 * if there is contention with a HW-initiated toggling (i.e. CPU core 594 * power-gated), the command should be retried in that case. 595 */ 596 do { 597 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 598 599 /* wait for PMC to execute the command */ 600 ret = readx_poll_timeout(tegra_powergate_state, id, status, 601 status == new_state, 1, 10); 602 } while (ret == -ETIMEDOUT && retries--); 603 604 return ret; 605 } 606 607 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) 608 { 609 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); 610 } 611 612 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, 613 bool new_state) 614 { 615 bool status; 616 int err; 617 618 /* wait while PMC power gating is contended */ 619 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 620 status == true, 1, 100); 621 if (err) 622 return err; 623 624 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 625 626 /* wait for PMC to accept the command */ 627 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 628 status == true, 1, 100); 629 if (err) 630 return err; 631 632 /* wait for PMC to execute the command */ 633 err = readx_poll_timeout(tegra_powergate_state, id, status, 634 status == new_state, 10, 100000); 635 if (err) 636 return err; 637 638 return 0; 639 } 640 641 /** 642 * tegra_powergate_set() - set the state of a partition 643 * @pmc: power management controller 644 * @id: partition ID 645 * @new_state: new state of the partition 646 */ 647 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 648 bool new_state) 649 { 650 int err; 651 652 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 653 return -EINVAL; 654 655 mutex_lock(&pmc->powergates_lock); 656 657 if (tegra_powergate_state(id) == new_state) { 658 mutex_unlock(&pmc->powergates_lock); 659 return 0; 660 } 661 662 err = pmc->soc->powergate_set(pmc, id, new_state); 663 664 mutex_unlock(&pmc->powergates_lock); 665 666 return err; 667 } 668 669 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 670 unsigned int id) 671 { 672 u32 mask; 673 674 mutex_lock(&pmc->powergates_lock); 675 676 /* 677 * On Tegra124 and later, the clamps for the GPU are controlled by a 678 * separate register (with different semantics). 679 */ 680 if (id == TEGRA_POWERGATE_3D) { 681 if (pmc->soc->has_gpu_clamps) { 682 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 683 goto out; 684 } 685 } 686 687 /* 688 * Tegra 2 has a bug where PCIE and VDE clamping masks are 689 * swapped relatively to the partition ids 690 */ 691 if (id == TEGRA_POWERGATE_VDEC) 692 mask = (1 << TEGRA_POWERGATE_PCIE); 693 else if (id == TEGRA_POWERGATE_PCIE) 694 mask = (1 << TEGRA_POWERGATE_VDEC); 695 else 696 mask = (1 << id); 697 698 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 699 700 out: 701 mutex_unlock(&pmc->powergates_lock); 702 703 return 0; 704 } 705 706 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) 707 { 708 unsigned long safe_rate = 100 * 1000 * 1000; 709 unsigned int i; 710 int err; 711 712 for (i = 0; i < pg->num_clks; i++) { 713 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); 714 715 if (!pg->clk_rates[i]) { 716 err = -EINVAL; 717 goto out; 718 } 719 720 if (pg->clk_rates[i] <= safe_rate) 721 continue; 722 723 /* 724 * We don't know whether voltage state is okay for the 725 * current clock rate, hence it's better to temporally 726 * switch clock to a safe rate which is suitable for 727 * all voltages, before enabling the clock. 728 */ 729 err = clk_set_rate(pg->clks[i], safe_rate); 730 if (err) 731 goto out; 732 } 733 734 return 0; 735 736 out: 737 while (i--) 738 clk_set_rate(pg->clks[i], pg->clk_rates[i]); 739 740 return err; 741 } 742 743 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) 744 { 745 unsigned int i; 746 int err; 747 748 for (i = 0; i < pg->num_clks; i++) { 749 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); 750 if (err) 751 return err; 752 } 753 754 return 0; 755 } 756 757 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 758 { 759 unsigned int i; 760 761 for (i = 0; i < pg->num_clks; i++) 762 clk_disable_unprepare(pg->clks[i]); 763 } 764 765 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 766 { 767 unsigned int i; 768 int err; 769 770 for (i = 0; i < pg->num_clks; i++) { 771 err = clk_prepare_enable(pg->clks[i]); 772 if (err) 773 goto out; 774 } 775 776 return 0; 777 778 out: 779 while (i--) 780 clk_disable_unprepare(pg->clks[i]); 781 782 return err; 783 } 784 785 static int tegra_powergate_power_up(struct tegra_powergate *pg, 786 bool disable_clocks) 787 { 788 int err; 789 790 err = reset_control_assert(pg->reset); 791 if (err) 792 return err; 793 794 usleep_range(10, 20); 795 796 err = tegra_powergate_set(pg->pmc, pg->id, true); 797 if (err < 0) 798 return err; 799 800 usleep_range(10, 20); 801 802 err = tegra_powergate_prepare_clocks(pg); 803 if (err) 804 goto powergate_off; 805 806 err = tegra_powergate_enable_clocks(pg); 807 if (err) 808 goto unprepare_clks; 809 810 usleep_range(10, 20); 811 812 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 813 if (err) 814 goto disable_clks; 815 816 usleep_range(10, 20); 817 818 err = reset_control_deassert(pg->reset); 819 if (err) 820 goto disable_clks; 821 822 usleep_range(10, 20); 823 824 if (pg->pmc->soc->needs_mbist_war) 825 err = tegra210_clk_handle_mbist_war(pg->id); 826 if (err) 827 goto disable_clks; 828 829 if (disable_clocks) 830 tegra_powergate_disable_clocks(pg); 831 832 err = tegra_powergate_unprepare_clocks(pg); 833 if (err) 834 return err; 835 836 return 0; 837 838 disable_clks: 839 tegra_powergate_disable_clocks(pg); 840 usleep_range(10, 20); 841 842 unprepare_clks: 843 tegra_powergate_unprepare_clocks(pg); 844 845 powergate_off: 846 tegra_powergate_set(pg->pmc, pg->id, false); 847 848 return err; 849 } 850 851 static int tegra_powergate_power_down(struct tegra_powergate *pg) 852 { 853 int err; 854 855 err = tegra_powergate_prepare_clocks(pg); 856 if (err) 857 return err; 858 859 err = tegra_powergate_enable_clocks(pg); 860 if (err) 861 goto unprepare_clks; 862 863 usleep_range(10, 20); 864 865 err = reset_control_assert(pg->reset); 866 if (err) 867 goto disable_clks; 868 869 usleep_range(10, 20); 870 871 tegra_powergate_disable_clocks(pg); 872 873 usleep_range(10, 20); 874 875 err = tegra_powergate_set(pg->pmc, pg->id, false); 876 if (err) 877 goto assert_resets; 878 879 err = tegra_powergate_unprepare_clocks(pg); 880 if (err) 881 return err; 882 883 return 0; 884 885 assert_resets: 886 tegra_powergate_enable_clocks(pg); 887 usleep_range(10, 20); 888 reset_control_deassert(pg->reset); 889 usleep_range(10, 20); 890 891 disable_clks: 892 tegra_powergate_disable_clocks(pg); 893 894 unprepare_clks: 895 tegra_powergate_unprepare_clocks(pg); 896 897 return err; 898 } 899 900 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 901 { 902 struct tegra_powergate *pg = to_powergate(domain); 903 struct device *dev = pg->pmc->dev; 904 int err; 905 906 err = tegra_powergate_power_up(pg, true); 907 if (err) { 908 dev_err(dev, "failed to turn on PM domain %s: %d\n", 909 pg->genpd.name, err); 910 goto out; 911 } 912 913 reset_control_release(pg->reset); 914 915 out: 916 return err; 917 } 918 919 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 920 { 921 struct tegra_powergate *pg = to_powergate(domain); 922 struct device *dev = pg->pmc->dev; 923 int err; 924 925 err = reset_control_acquire(pg->reset); 926 if (err < 0) { 927 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", 928 pg->genpd.name, err); 929 return err; 930 } 931 932 err = tegra_powergate_power_down(pg); 933 if (err) { 934 dev_err(dev, "failed to turn off PM domain %s: %d\n", 935 pg->genpd.name, err); 936 reset_control_release(pg->reset); 937 } 938 939 return err; 940 } 941 942 /** 943 * tegra_powergate_power_on() - power on partition 944 * @id: partition ID 945 */ 946 int tegra_powergate_power_on(unsigned int id) 947 { 948 if (!tegra_powergate_is_available(pmc, id)) 949 return -EINVAL; 950 951 return tegra_powergate_set(pmc, id, true); 952 } 953 EXPORT_SYMBOL(tegra_powergate_power_on); 954 955 /** 956 * tegra_powergate_power_off() - power off partition 957 * @id: partition ID 958 */ 959 int tegra_powergate_power_off(unsigned int id) 960 { 961 if (!tegra_powergate_is_available(pmc, id)) 962 return -EINVAL; 963 964 return tegra_powergate_set(pmc, id, false); 965 } 966 EXPORT_SYMBOL(tegra_powergate_power_off); 967 968 /** 969 * tegra_powergate_is_powered() - check if partition is powered 970 * @pmc: power management controller 971 * @id: partition ID 972 */ 973 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 974 { 975 if (!tegra_powergate_is_valid(pmc, id)) 976 return -EINVAL; 977 978 return tegra_powergate_state(id); 979 } 980 981 /** 982 * tegra_powergate_remove_clamping() - remove power clamps for partition 983 * @id: partition ID 984 */ 985 int tegra_powergate_remove_clamping(unsigned int id) 986 { 987 if (!tegra_powergate_is_available(pmc, id)) 988 return -EINVAL; 989 990 return __tegra_powergate_remove_clamping(pmc, id); 991 } 992 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 993 994 /** 995 * tegra_powergate_sequence_power_up() - power up partition 996 * @id: partition ID 997 * @clk: clock for partition 998 * @rst: reset for partition 999 * 1000 * Must be called with clk disabled, and returns with clk enabled. 1001 */ 1002 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 1003 struct reset_control *rst) 1004 { 1005 struct tegra_powergate *pg; 1006 int err; 1007 1008 if (!tegra_powergate_is_available(pmc, id)) 1009 return -EINVAL; 1010 1011 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1012 if (!pg) 1013 return -ENOMEM; 1014 1015 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); 1016 if (!pg->clk_rates) { 1017 kfree(pg->clks); 1018 return -ENOMEM; 1019 } 1020 1021 pg->id = id; 1022 pg->clks = &clk; 1023 pg->num_clks = 1; 1024 pg->reset = rst; 1025 pg->pmc = pmc; 1026 1027 err = tegra_powergate_power_up(pg, false); 1028 if (err) 1029 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 1030 err); 1031 1032 kfree(pg->clk_rates); 1033 kfree(pg); 1034 1035 return err; 1036 } 1037 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 1038 1039 /** 1040 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 1041 * @pmc: power management controller 1042 * @cpuid: CPU partition ID 1043 * 1044 * Returns the partition ID corresponding to the CPU partition ID or a 1045 * negative error code on failure. 1046 */ 1047 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 1048 unsigned int cpuid) 1049 { 1050 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 1051 return pmc->soc->cpu_powergates[cpuid]; 1052 1053 return -EINVAL; 1054 } 1055 1056 /** 1057 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 1058 * @cpuid: CPU partition ID 1059 */ 1060 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 1061 { 1062 int id; 1063 1064 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1065 if (id < 0) 1066 return false; 1067 1068 return tegra_powergate_is_powered(pmc, id); 1069 } 1070 1071 /** 1072 * tegra_pmc_cpu_power_on() - power on CPU partition 1073 * @cpuid: CPU partition ID 1074 */ 1075 int tegra_pmc_cpu_power_on(unsigned int cpuid) 1076 { 1077 int id; 1078 1079 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1080 if (id < 0) 1081 return id; 1082 1083 return tegra_powergate_set(pmc, id, true); 1084 } 1085 1086 /** 1087 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 1088 * @cpuid: CPU partition ID 1089 */ 1090 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 1091 { 1092 int id; 1093 1094 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1095 if (id < 0) 1096 return id; 1097 1098 return tegra_powergate_remove_clamping(id); 1099 } 1100 1101 static void tegra_pmc_program_reboot_reason(const char *cmd) 1102 { 1103 u32 value; 1104 1105 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 1106 value &= ~PMC_SCRATCH0_MODE_MASK; 1107 1108 if (cmd) { 1109 if (strcmp(cmd, "recovery") == 0) 1110 value |= PMC_SCRATCH0_MODE_RECOVERY; 1111 1112 if (strcmp(cmd, "bootloader") == 0) 1113 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 1114 1115 if (strcmp(cmd, "forced-recovery") == 0) 1116 value |= PMC_SCRATCH0_MODE_RCM; 1117 } 1118 1119 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 1120 } 1121 1122 static int tegra_pmc_reboot_notify(struct notifier_block *this, 1123 unsigned long action, void *data) 1124 { 1125 if (action == SYS_RESTART) 1126 tegra_pmc_program_reboot_reason(data); 1127 1128 return NOTIFY_DONE; 1129 } 1130 1131 static struct notifier_block tegra_pmc_reboot_notifier = { 1132 .notifier_call = tegra_pmc_reboot_notify, 1133 }; 1134 1135 static void tegra_pmc_restart(void) 1136 { 1137 u32 value; 1138 1139 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 1140 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1141 value |= PMC_CNTRL_MAIN_RST; 1142 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1143 } 1144 1145 static int tegra_pmc_restart_handler(struct sys_off_data *data) 1146 { 1147 tegra_pmc_restart(); 1148 1149 return NOTIFY_DONE; 1150 } 1151 1152 static int tegra_pmc_power_off_handler(struct sys_off_data *data) 1153 { 1154 /* 1155 * Reboot Nexus 7 into special bootloader mode if USB cable is 1156 * connected in order to display battery status and power off. 1157 */ 1158 if (of_machine_is_compatible("asus,grouper") && 1159 power_supply_is_system_supplied()) { 1160 const u32 go_to_charger_mode = 0xa5a55a5a; 1161 1162 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); 1163 tegra_pmc_restart(); 1164 } 1165 1166 return NOTIFY_DONE; 1167 } 1168 1169 static int powergate_show(struct seq_file *s, void *data) 1170 { 1171 unsigned int i; 1172 int status; 1173 1174 seq_printf(s, " powergate powered\n"); 1175 seq_printf(s, "------------------\n"); 1176 1177 for (i = 0; i < pmc->soc->num_powergates; i++) { 1178 status = tegra_powergate_is_powered(pmc, i); 1179 if (status < 0) 1180 continue; 1181 1182 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 1183 str_yes_no(status)); 1184 } 1185 1186 return 0; 1187 } 1188 1189 DEFINE_SHOW_ATTRIBUTE(powergate); 1190 1191 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1192 struct device_node *np) 1193 { 1194 struct clk *clk; 1195 unsigned int i, count; 1196 int err; 1197 1198 count = of_clk_get_parent_count(np); 1199 if (count == 0) 1200 return -ENODEV; 1201 1202 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 1203 if (!pg->clks) 1204 return -ENOMEM; 1205 1206 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); 1207 if (!pg->clk_rates) { 1208 kfree(pg->clks); 1209 return -ENOMEM; 1210 } 1211 1212 for (i = 0; i < count; i++) { 1213 pg->clks[i] = of_clk_get(np, i); 1214 if (IS_ERR(pg->clks[i])) { 1215 err = PTR_ERR(pg->clks[i]); 1216 goto err; 1217 } 1218 } 1219 1220 pg->num_clks = count; 1221 1222 return 0; 1223 1224 err: 1225 while (i--) 1226 clk_put(pg->clks[i]); 1227 1228 kfree(pg->clk_rates); 1229 kfree(pg->clks); 1230 1231 return err; 1232 } 1233 1234 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1235 struct device_node *np, bool off) 1236 { 1237 struct device *dev = pg->pmc->dev; 1238 int err; 1239 1240 pg->reset = of_reset_control_array_get_exclusive_released(np); 1241 if (IS_ERR(pg->reset)) { 1242 err = PTR_ERR(pg->reset); 1243 dev_err(dev, "failed to get device resets: %d\n", err); 1244 return err; 1245 } 1246 1247 err = reset_control_acquire(pg->reset); 1248 if (err < 0) { 1249 pr_err("failed to acquire resets: %d\n", err); 1250 goto out; 1251 } 1252 1253 if (off) { 1254 err = reset_control_assert(pg->reset); 1255 } else { 1256 err = reset_control_deassert(pg->reset); 1257 if (err < 0) 1258 goto out; 1259 1260 reset_control_release(pg->reset); 1261 } 1262 1263 out: 1264 if (err) { 1265 reset_control_release(pg->reset); 1266 reset_control_put(pg->reset); 1267 } 1268 1269 return err; 1270 } 1271 1272 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1273 { 1274 struct device *dev = pmc->dev; 1275 struct tegra_powergate *pg; 1276 int id, err = 0; 1277 bool off; 1278 1279 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1280 if (!pg) 1281 return -ENOMEM; 1282 1283 id = tegra_powergate_lookup(pmc, np->name); 1284 if (id < 0) { 1285 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1286 err = -ENODEV; 1287 goto free_mem; 1288 } 1289 1290 /* 1291 * Clear the bit for this powergate so it cannot be managed 1292 * directly via the legacy APIs for controlling powergates. 1293 */ 1294 clear_bit(id, pmc->powergates_available); 1295 1296 pg->id = id; 1297 pg->genpd.name = np->name; 1298 pg->genpd.flags = GENPD_FLAG_NO_SYNC_STATE; 1299 pg->genpd.power_off = tegra_genpd_power_off; 1300 pg->genpd.power_on = tegra_genpd_power_on; 1301 pg->pmc = pmc; 1302 1303 off = !tegra_powergate_is_powered(pmc, pg->id); 1304 1305 err = tegra_powergate_of_get_clks(pg, np); 1306 if (err < 0) { 1307 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1308 goto set_available; 1309 } 1310 1311 err = tegra_powergate_of_get_resets(pg, np, off); 1312 if (err < 0) { 1313 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1314 goto remove_clks; 1315 } 1316 1317 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1318 if (off) 1319 WARN_ON(tegra_powergate_power_up(pg, true)); 1320 1321 goto remove_resets; 1322 } 1323 1324 err = pm_genpd_init(&pg->genpd, NULL, off); 1325 if (err < 0) { 1326 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1327 err); 1328 goto remove_resets; 1329 } 1330 1331 err = of_genpd_add_provider_simple(np, &pg->genpd); 1332 if (err < 0) { 1333 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1334 np, err); 1335 goto remove_genpd; 1336 } 1337 1338 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1339 1340 return 0; 1341 1342 remove_genpd: 1343 pm_genpd_remove(&pg->genpd); 1344 1345 remove_resets: 1346 reset_control_put(pg->reset); 1347 1348 remove_clks: 1349 while (pg->num_clks--) 1350 clk_put(pg->clks[pg->num_clks]); 1351 1352 kfree(pg->clks); 1353 1354 set_available: 1355 set_bit(id, pmc->powergates_available); 1356 1357 free_mem: 1358 kfree(pg); 1359 1360 return err; 1361 } 1362 1363 bool tegra_pmc_core_domain_state_synced(void) 1364 { 1365 return pmc->core_domain_state_synced; 1366 } 1367 1368 static int 1369 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, 1370 unsigned int level) 1371 { 1372 struct dev_pm_opp *opp; 1373 int err; 1374 1375 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); 1376 if (IS_ERR(opp)) { 1377 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", 1378 level, opp); 1379 return PTR_ERR(opp); 1380 } 1381 1382 mutex_lock(&pmc->powergates_lock); 1383 err = dev_pm_opp_set_opp(pmc->dev, opp); 1384 mutex_unlock(&pmc->powergates_lock); 1385 1386 dev_pm_opp_put(opp); 1387 1388 if (err) { 1389 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", 1390 level, err); 1391 return err; 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) 1398 { 1399 struct generic_pm_domain *genpd; 1400 const char *rname[] = { "core", NULL}; 1401 int err; 1402 1403 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); 1404 if (!genpd) 1405 return -ENOMEM; 1406 1407 genpd->name = "core"; 1408 genpd->flags = GENPD_FLAG_NO_SYNC_STATE; 1409 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; 1410 1411 err = devm_pm_opp_set_regulators(pmc->dev, rname); 1412 if (err) 1413 return dev_err_probe(pmc->dev, err, 1414 "failed to set core OPP regulator\n"); 1415 1416 err = pm_genpd_init(genpd, NULL, false); 1417 if (err) { 1418 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); 1419 return err; 1420 } 1421 1422 err = of_genpd_add_provider_simple(np, genpd); 1423 if (err) { 1424 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); 1425 goto remove_genpd; 1426 } 1427 1428 return 0; 1429 1430 remove_genpd: 1431 pm_genpd_remove(genpd); 1432 1433 return err; 1434 } 1435 1436 static int tegra_powergate_init(struct tegra_pmc *pmc, 1437 struct device_node *parent) 1438 { 1439 struct of_phandle_args child_args, parent_args; 1440 struct device_node *np; 1441 int err = 0; 1442 1443 /* 1444 * Core power domain is the parent of powergate domains, hence it 1445 * should be registered first. 1446 */ 1447 np = of_get_child_by_name(parent, "core-domain"); 1448 if (np) { 1449 err = tegra_pmc_core_pd_add(pmc, np); 1450 of_node_put(np); 1451 if (err) 1452 return err; 1453 } 1454 1455 np = of_get_child_by_name(parent, "powergates"); 1456 if (!np) 1457 return 0; 1458 1459 for_each_child_of_node_scoped(np, child) { 1460 err = tegra_powergate_add(pmc, child); 1461 if (err < 0) 1462 break; 1463 1464 if (of_parse_phandle_with_args(child, "power-domains", 1465 "#power-domain-cells", 1466 0, &parent_args)) 1467 continue; 1468 1469 child_args.np = child; 1470 child_args.args_count = 0; 1471 1472 err = of_genpd_add_subdomain(&parent_args, &child_args); 1473 of_node_put(parent_args.np); 1474 if (err) 1475 break; 1476 } 1477 1478 of_node_put(np); 1479 1480 return err; 1481 } 1482 1483 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1484 { 1485 struct tegra_powergate *pg = to_powergate(genpd); 1486 1487 reset_control_put(pg->reset); 1488 1489 while (pg->num_clks--) 1490 clk_put(pg->clks[pg->num_clks]); 1491 1492 kfree(pg->clks); 1493 1494 set_bit(pg->id, pmc->powergates_available); 1495 1496 kfree(pg); 1497 } 1498 1499 static void tegra_powergate_remove_all(struct device_node *parent) 1500 { 1501 struct generic_pm_domain *genpd; 1502 struct device_node *np, *child; 1503 1504 np = of_get_child_by_name(parent, "powergates"); 1505 if (!np) 1506 return; 1507 1508 for_each_child_of_node(np, child) { 1509 of_genpd_del_provider(child); 1510 1511 genpd = of_genpd_remove_last(child); 1512 if (IS_ERR(genpd)) 1513 continue; 1514 1515 tegra_powergate_remove(genpd); 1516 } 1517 1518 of_node_put(np); 1519 1520 np = of_get_child_by_name(parent, "core-domain"); 1521 if (np) { 1522 of_genpd_del_provider(np); 1523 of_genpd_remove_last(np); 1524 } 1525 } 1526 1527 static const struct tegra_io_pad_soc * 1528 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1529 { 1530 unsigned int i; 1531 1532 for (i = 0; i < pmc->soc->num_io_pads; i++) 1533 if (pmc->soc->io_pads[i].id == id) 1534 return &pmc->soc->io_pads[i]; 1535 1536 return NULL; 1537 } 1538 1539 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, 1540 const struct tegra_io_pad_soc *pad, 1541 unsigned long *request, 1542 unsigned long *status, 1543 u32 *mask) 1544 { 1545 unsigned long rate, value; 1546 1547 if (pad->dpd == UINT_MAX) 1548 return -EINVAL; 1549 1550 *request = pad->request; 1551 *status = pad->status; 1552 *mask = BIT(pad->dpd); 1553 1554 if (pmc->clk) { 1555 rate = pmc->rate; 1556 if (!rate) { 1557 dev_err(pmc->dev, "failed to get clock rate\n"); 1558 return -ENODEV; 1559 } 1560 1561 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1562 1563 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1564 value = DIV_ROUND_UP(1000000000, rate); 1565 value = DIV_ROUND_UP(200, value); 1566 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1567 } 1568 1569 return 0; 1570 } 1571 1572 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1573 u32 mask, u32 val, unsigned long timeout) 1574 { 1575 u32 value; 1576 1577 timeout = jiffies + msecs_to_jiffies(timeout); 1578 1579 while (time_after(timeout, jiffies)) { 1580 value = tegra_pmc_readl(pmc, offset); 1581 if ((value & mask) == val) 1582 return 0; 1583 1584 usleep_range(250, 1000); 1585 } 1586 1587 return -ETIMEDOUT; 1588 } 1589 1590 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1591 { 1592 if (pmc->clk) 1593 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1594 } 1595 1596 /** 1597 * tegra_io_pad_power_enable() - enable power to I/O pad 1598 * @id: Tegra I/O pad ID for which to enable power 1599 * 1600 * Returns: 0 on success or a negative error code on failure. 1601 */ 1602 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1603 { 1604 const struct tegra_io_pad_soc *pad; 1605 unsigned long request, status; 1606 u32 mask; 1607 int err; 1608 1609 pad = tegra_io_pad_find(pmc, id); 1610 if (!pad) { 1611 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1612 return -ENOENT; 1613 } 1614 1615 mutex_lock(&pmc->powergates_lock); 1616 1617 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1618 if (err < 0) { 1619 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1620 goto unlock; 1621 } 1622 1623 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1624 1625 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1626 if (err < 0) { 1627 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1628 goto unlock; 1629 } 1630 1631 tegra_io_pad_unprepare(pmc); 1632 1633 unlock: 1634 mutex_unlock(&pmc->powergates_lock); 1635 return err; 1636 } 1637 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1638 1639 /** 1640 * tegra_io_pad_power_disable() - disable power to I/O pad 1641 * @id: Tegra I/O pad ID for which to disable power 1642 * 1643 * Returns: 0 on success or a negative error code on failure. 1644 */ 1645 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1646 { 1647 const struct tegra_io_pad_soc *pad; 1648 unsigned long request, status; 1649 u32 mask; 1650 int err; 1651 1652 pad = tegra_io_pad_find(pmc, id); 1653 if (!pad) { 1654 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1655 return -ENOENT; 1656 } 1657 1658 mutex_lock(&pmc->powergates_lock); 1659 1660 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1661 if (err < 0) { 1662 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1663 goto unlock; 1664 } 1665 1666 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1667 1668 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1669 if (err < 0) { 1670 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1671 goto unlock; 1672 } 1673 1674 tegra_io_pad_unprepare(pmc); 1675 1676 unlock: 1677 mutex_unlock(&pmc->powergates_lock); 1678 return err; 1679 } 1680 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1681 1682 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1683 { 1684 const struct tegra_io_pad_soc *pad; 1685 unsigned long status; 1686 u32 mask, value; 1687 1688 pad = tegra_io_pad_find(pmc, id); 1689 if (!pad) { 1690 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1691 return -ENOENT; 1692 } 1693 1694 if (pad->dpd == UINT_MAX) 1695 return -EINVAL; 1696 1697 status = pad->status; 1698 mask = BIT(pad->dpd); 1699 1700 value = tegra_pmc_readl(pmc, status); 1701 1702 return !(value & mask); 1703 } 1704 1705 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1706 int voltage) 1707 { 1708 const struct tegra_io_pad_soc *pad; 1709 u32 value; 1710 1711 pad = tegra_io_pad_find(pmc, id); 1712 if (!pad) 1713 return -ENOENT; 1714 1715 if (pad->voltage == UINT_MAX) 1716 return -ENOTSUPP; 1717 1718 mutex_lock(&pmc->powergates_lock); 1719 1720 if (pmc->soc->has_impl_33v_pwr) { 1721 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1722 1723 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1724 value &= ~BIT(pad->voltage); 1725 else 1726 value |= BIT(pad->voltage); 1727 1728 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1729 } else { 1730 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1731 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1732 value |= BIT(pad->voltage); 1733 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1734 1735 /* update I/O voltage */ 1736 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1737 1738 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1739 value &= ~BIT(pad->voltage); 1740 else 1741 value |= BIT(pad->voltage); 1742 1743 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1744 } 1745 1746 mutex_unlock(&pmc->powergates_lock); 1747 1748 usleep_range(100, 250); 1749 1750 return 0; 1751 } 1752 1753 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1754 { 1755 const struct tegra_io_pad_soc *pad; 1756 u32 value; 1757 1758 pad = tegra_io_pad_find(pmc, id); 1759 if (!pad) 1760 return -ENOENT; 1761 1762 if (pad->voltage == UINT_MAX) 1763 return -ENOTSUPP; 1764 1765 if (pmc->soc->has_impl_33v_pwr) 1766 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1767 else 1768 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1769 1770 if ((value & BIT(pad->voltage)) == 0) 1771 return TEGRA_IO_PAD_VOLTAGE_1V8; 1772 1773 return TEGRA_IO_PAD_VOLTAGE_3V3; 1774 } 1775 1776 #ifdef CONFIG_PM_SLEEP 1777 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1778 { 1779 return pmc->suspend_mode; 1780 } 1781 1782 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1783 { 1784 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1785 return; 1786 1787 pmc->suspend_mode = mode; 1788 } 1789 1790 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1791 { 1792 unsigned long long rate = 0; 1793 u64 ticks; 1794 u32 value; 1795 1796 switch (mode) { 1797 case TEGRA_SUSPEND_LP1: 1798 rate = 32768; 1799 break; 1800 1801 case TEGRA_SUSPEND_LP2: 1802 rate = pmc->rate; 1803 break; 1804 1805 default: 1806 break; 1807 } 1808 1809 if (WARN_ON_ONCE(rate == 0)) 1810 rate = 100000000; 1811 1812 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1813 do_div(ticks, USEC_PER_SEC); 1814 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1815 1816 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1817 do_div(ticks, USEC_PER_SEC); 1818 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1819 1820 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1821 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1822 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1823 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1824 } 1825 #endif 1826 1827 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1828 { 1829 u32 value, values[2]; 1830 1831 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1832 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1833 } else { 1834 switch (value) { 1835 case 0: 1836 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1837 break; 1838 1839 case 1: 1840 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1841 break; 1842 1843 case 2: 1844 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1845 break; 1846 1847 default: 1848 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1849 break; 1850 } 1851 } 1852 1853 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1854 1855 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1856 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1857 1858 pmc->cpu_good_time = value; 1859 1860 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1861 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1862 1863 pmc->cpu_off_time = value; 1864 1865 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1866 values, ARRAY_SIZE(values))) 1867 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1868 1869 pmc->core_osc_time = values[0]; 1870 pmc->core_pmu_time = values[1]; 1871 1872 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1873 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1874 1875 pmc->core_off_time = value; 1876 1877 pmc->corereq_high = of_property_read_bool(np, 1878 "nvidia,core-power-req-active-high"); 1879 1880 pmc->sysclkreq_high = of_property_read_bool(np, 1881 "nvidia,sys-clock-req-active-high"); 1882 1883 pmc->combined_req = of_property_read_bool(np, 1884 "nvidia,combined-power-req"); 1885 1886 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1887 "nvidia,cpu-pwr-good-en"); 1888 1889 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1890 ARRAY_SIZE(values))) 1891 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1892 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1893 1894 pmc->lp0_vec_phys = values[0]; 1895 pmc->lp0_vec_size = values[1]; 1896 1897 return 0; 1898 } 1899 1900 static int tegra_pmc_init(struct tegra_pmc *pmc) 1901 { 1902 if (pmc->soc->max_wake_events > 0) { 1903 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1904 if (!pmc->wake_type_level_map) 1905 return -ENOMEM; 1906 1907 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1908 if (!pmc->wake_type_dual_edge_map) 1909 return -ENOMEM; 1910 1911 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1912 if (!pmc->wake_sw_status_map) 1913 return -ENOMEM; 1914 1915 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1916 if (!pmc->wake_cntrl_level_map) 1917 return -ENOMEM; 1918 } 1919 1920 if (pmc->soc->init) 1921 pmc->soc->init(pmc); 1922 1923 return 0; 1924 } 1925 1926 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1927 { 1928 static const char disabled[] = "emergency thermal reset disabled"; 1929 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1930 struct device *dev = pmc->dev; 1931 struct device_node *np; 1932 u32 value, checksum; 1933 1934 if (!pmc->soc->has_tsense_reset) 1935 return; 1936 1937 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1938 if (!np) { 1939 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1940 return; 1941 } 1942 1943 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1944 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1945 goto out; 1946 } 1947 1948 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1949 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1950 goto out; 1951 } 1952 1953 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1954 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1955 goto out; 1956 } 1957 1958 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1959 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1960 goto out; 1961 } 1962 1963 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1964 pinmux = 0; 1965 1966 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1967 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1968 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1969 1970 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1971 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1972 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 1973 1974 value = PMC_SCRATCH55_RESET_TEGRA; 1975 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1976 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1977 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1978 1979 /* 1980 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1981 * contain the checksum and are currently zero, so they are not added. 1982 */ 1983 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1984 + ((value >> 24) & 0xff); 1985 checksum &= 0xff; 1986 checksum = 0x100 - checksum; 1987 1988 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1989 1990 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 1991 1992 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1993 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1994 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1995 1996 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1997 1998 out: 1999 of_node_put(np); 2000 } 2001 2002 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 2003 { 2004 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2005 2006 return pmc->soc->num_io_pads; 2007 } 2008 2009 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 2010 unsigned int group) 2011 { 2012 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 2013 2014 return pmc->soc->io_pads[group].name; 2015 } 2016 2017 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 2018 unsigned int group, 2019 const unsigned int **pins, 2020 unsigned int *num_pins) 2021 { 2022 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2023 2024 *pins = &pmc->soc->io_pads[group].id; 2025 *num_pins = 1; 2026 2027 return 0; 2028 } 2029 2030 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 2031 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 2032 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 2033 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 2034 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2035 .dt_free_map = pinconf_generic_dt_free_map, 2036 }; 2037 2038 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 2039 unsigned int pin, unsigned long *config) 2040 { 2041 enum pin_config_param param = pinconf_to_config_param(*config); 2042 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2043 const struct tegra_io_pad_soc *pad; 2044 int ret; 2045 u32 arg; 2046 2047 pad = tegra_io_pad_find(pmc, pin); 2048 if (!pad) 2049 return -EINVAL; 2050 2051 switch (param) { 2052 case PIN_CONFIG_POWER_SOURCE: 2053 ret = tegra_io_pad_get_voltage(pmc, pad->id); 2054 if (ret < 0) 2055 return ret; 2056 2057 arg = ret; 2058 break; 2059 2060 case PIN_CONFIG_MODE_LOW_POWER: 2061 ret = tegra_io_pad_is_powered(pmc, pad->id); 2062 if (ret < 0) 2063 return ret; 2064 2065 arg = !ret; 2066 break; 2067 2068 default: 2069 return -EINVAL; 2070 } 2071 2072 *config = pinconf_to_config_packed(param, arg); 2073 2074 return 0; 2075 } 2076 2077 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 2078 unsigned int pin, unsigned long *configs, 2079 unsigned int num_configs) 2080 { 2081 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2082 const struct tegra_io_pad_soc *pad; 2083 enum pin_config_param param; 2084 unsigned int i; 2085 int err; 2086 u32 arg; 2087 2088 pad = tegra_io_pad_find(pmc, pin); 2089 if (!pad) 2090 return -EINVAL; 2091 2092 for (i = 0; i < num_configs; ++i) { 2093 param = pinconf_to_config_param(configs[i]); 2094 arg = pinconf_to_config_argument(configs[i]); 2095 2096 switch (param) { 2097 case PIN_CONFIG_MODE_LOW_POWER: 2098 if (arg) 2099 err = tegra_io_pad_power_disable(pad->id); 2100 else 2101 err = tegra_io_pad_power_enable(pad->id); 2102 if (err) 2103 return err; 2104 break; 2105 case PIN_CONFIG_POWER_SOURCE: 2106 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 2107 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 2108 return -EINVAL; 2109 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 2110 if (err) 2111 return err; 2112 break; 2113 default: 2114 return -EINVAL; 2115 } 2116 } 2117 2118 return 0; 2119 } 2120 2121 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 2122 .pin_config_get = tegra_io_pad_pinconf_get, 2123 .pin_config_set = tegra_io_pad_pinconf_set, 2124 .is_generic = true, 2125 }; 2126 2127 static struct pinctrl_desc tegra_pmc_pctl_desc = { 2128 .pctlops = &tegra_io_pad_pinctrl_ops, 2129 .confops = &tegra_io_pad_pinconf_ops, 2130 }; 2131 2132 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 2133 { 2134 int err; 2135 2136 if (!pmc->soc->num_pin_descs) 2137 return 0; 2138 2139 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 2140 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 2141 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 2142 2143 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 2144 pmc); 2145 if (IS_ERR(pmc->pctl_dev)) { 2146 err = PTR_ERR(pmc->pctl_dev); 2147 dev_err(pmc->dev, "failed to register pin controller: %d\n", 2148 err); 2149 return err; 2150 } 2151 2152 return 0; 2153 } 2154 2155 static ssize_t reset_reason_show(struct device *dev, 2156 struct device_attribute *attr, char *buf) 2157 { 2158 u32 value; 2159 2160 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2161 value &= pmc->soc->regs->rst_source_mask; 2162 value >>= pmc->soc->regs->rst_source_shift; 2163 2164 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 2165 return sprintf(buf, "%s\n", "UNKNOWN"); 2166 2167 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 2168 } 2169 2170 static DEVICE_ATTR_RO(reset_reason); 2171 2172 static ssize_t reset_level_show(struct device *dev, 2173 struct device_attribute *attr, char *buf) 2174 { 2175 u32 value; 2176 2177 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2178 value &= pmc->soc->regs->rst_level_mask; 2179 value >>= pmc->soc->regs->rst_level_shift; 2180 2181 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 2182 return sprintf(buf, "%s\n", "UNKNOWN"); 2183 2184 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 2185 } 2186 2187 static DEVICE_ATTR_RO(reset_level); 2188 2189 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 2190 { 2191 struct device *dev = pmc->dev; 2192 int err = 0; 2193 2194 if (pmc->soc->reset_sources) { 2195 err = device_create_file(dev, &dev_attr_reset_reason); 2196 if (err < 0) 2197 dev_warn(dev, 2198 "failed to create attr \"reset_reason\": %d\n", 2199 err); 2200 } 2201 2202 if (pmc->soc->reset_levels) { 2203 err = device_create_file(dev, &dev_attr_reset_level); 2204 if (err < 0) 2205 dev_warn(dev, 2206 "failed to create attr \"reset_level\": %d\n", 2207 err); 2208 } 2209 } 2210 2211 static int tegra_pmc_irq_translate(struct irq_domain *domain, 2212 struct irq_fwspec *fwspec, 2213 unsigned long *hwirq, 2214 unsigned int *type) 2215 { 2216 if (WARN_ON(fwspec->param_count < 2)) 2217 return -EINVAL; 2218 2219 *hwirq = fwspec->param[0]; 2220 *type = fwspec->param[1]; 2221 2222 return 0; 2223 } 2224 2225 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 2226 unsigned int num_irqs, void *data) 2227 { 2228 struct tegra_pmc *pmc = domain->host_data; 2229 const struct tegra_pmc_soc *soc = pmc->soc; 2230 struct irq_fwspec *fwspec = data; 2231 unsigned int i; 2232 int err = 0; 2233 2234 if (WARN_ON(num_irqs > 1)) 2235 return -EINVAL; 2236 2237 for (i = 0; i < soc->num_wake_events; i++) { 2238 const struct tegra_wake_event *event = &soc->wake_events[i]; 2239 2240 /* IRQ and simple wake events */ 2241 if (fwspec->param_count == 2) { 2242 struct irq_fwspec spec; 2243 2244 if (event->id != fwspec->param[0]) 2245 continue; 2246 2247 err = irq_domain_set_hwirq_and_chip(domain, virq, 2248 event->id, 2249 &pmc->irq, pmc); 2250 if (err < 0) 2251 break; 2252 2253 /* simple hierarchies stop at the PMC level */ 2254 if (event->irq == 0) { 2255 err = irq_domain_disconnect_hierarchy(domain->parent, virq); 2256 break; 2257 } 2258 2259 spec.fwnode = &pmc->dev->of_node->fwnode; 2260 spec.param_count = 3; 2261 spec.param[0] = GIC_SPI; 2262 spec.param[1] = event->irq; 2263 spec.param[2] = fwspec->param[1]; 2264 2265 err = irq_domain_alloc_irqs_parent(domain, virq, 2266 num_irqs, &spec); 2267 2268 break; 2269 } 2270 2271 /* GPIO wake events */ 2272 if (fwspec->param_count == 3) { 2273 if (event->gpio.instance != fwspec->param[0] || 2274 event->gpio.pin != fwspec->param[1]) 2275 continue; 2276 2277 err = irq_domain_set_hwirq_and_chip(domain, virq, 2278 event->id, 2279 &pmc->irq, pmc); 2280 2281 /* GPIO hierarchies stop at the PMC level */ 2282 if (!err && domain->parent) 2283 err = irq_domain_disconnect_hierarchy(domain->parent, 2284 virq); 2285 break; 2286 } 2287 } 2288 2289 /* If there is no wake-up event, there is no PMC mapping */ 2290 if (i == soc->num_wake_events) 2291 err = irq_domain_disconnect_hierarchy(domain, virq); 2292 2293 return err; 2294 } 2295 2296 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2297 .translate = tegra_pmc_irq_translate, 2298 .alloc = tegra_pmc_irq_alloc, 2299 }; 2300 2301 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2302 { 2303 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2304 unsigned int offset, bit; 2305 u32 value; 2306 2307 offset = data->hwirq / 32; 2308 bit = data->hwirq % 32; 2309 2310 /* clear wake status */ 2311 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2312 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2313 2314 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2315 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2316 2317 /* enable PMC wake */ 2318 if (data->hwirq >= 32) 2319 offset = PMC_WAKE2_MASK; 2320 else 2321 offset = PMC_WAKE_MASK; 2322 2323 value = tegra_pmc_readl(pmc, offset); 2324 2325 if (on) 2326 value |= BIT(bit); 2327 else 2328 value &= ~BIT(bit); 2329 2330 tegra_pmc_writel(pmc, value, offset); 2331 2332 return 0; 2333 } 2334 2335 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2336 { 2337 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2338 unsigned int offset, bit; 2339 u32 value; 2340 2341 offset = data->hwirq / 32; 2342 bit = data->hwirq % 32; 2343 2344 if (data->hwirq >= 32) 2345 offset = PMC_WAKE2_LEVEL; 2346 else 2347 offset = PMC_WAKE_LEVEL; 2348 2349 value = tegra_pmc_readl(pmc, offset); 2350 2351 switch (type) { 2352 case IRQ_TYPE_EDGE_RISING: 2353 case IRQ_TYPE_LEVEL_HIGH: 2354 value |= BIT(bit); 2355 break; 2356 2357 case IRQ_TYPE_EDGE_FALLING: 2358 case IRQ_TYPE_LEVEL_LOW: 2359 value &= ~BIT(bit); 2360 break; 2361 2362 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2363 value ^= BIT(bit); 2364 break; 2365 2366 default: 2367 return -EINVAL; 2368 } 2369 2370 tegra_pmc_writel(pmc, value, offset); 2371 2372 return 0; 2373 } 2374 2375 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) 2376 { 2377 u32 value; 2378 2379 /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */ 2380 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2381 value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN; 2382 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2383 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); 2384 } 2385 2386 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2387 { 2388 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2389 unsigned int offset, bit; 2390 u32 value; 2391 2392 offset = data->hwirq / 32; 2393 bit = data->hwirq % 32; 2394 2395 /* clear wake status */ 2396 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 2397 2398 /* route wake to tier 2 */ 2399 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2400 2401 if (!on) 2402 value &= ~(1 << bit); 2403 else 2404 value |= 1 << bit; 2405 2406 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2407 2408 /* enable wakeup event */ 2409 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 2410 2411 return 0; 2412 } 2413 2414 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2415 { 2416 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2417 u32 value; 2418 2419 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2420 2421 switch (type) { 2422 case IRQ_TYPE_EDGE_RISING: 2423 case IRQ_TYPE_LEVEL_HIGH: 2424 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2425 set_bit(data->hwirq, pmc->wake_type_level_map); 2426 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2427 break; 2428 2429 case IRQ_TYPE_EDGE_FALLING: 2430 case IRQ_TYPE_LEVEL_LOW: 2431 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2432 clear_bit(data->hwirq, pmc->wake_type_level_map); 2433 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2434 break; 2435 2436 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2437 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2438 clear_bit(data->hwirq, pmc->wake_type_level_map); 2439 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2440 break; 2441 2442 default: 2443 return -EINVAL; 2444 } 2445 2446 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2447 2448 return 0; 2449 } 2450 2451 static void tegra_irq_mask_parent(struct irq_data *data) 2452 { 2453 if (data->parent_data) 2454 irq_chip_mask_parent(data); 2455 } 2456 2457 static void tegra_irq_unmask_parent(struct irq_data *data) 2458 { 2459 if (data->parent_data) 2460 irq_chip_unmask_parent(data); 2461 } 2462 2463 static void tegra_irq_eoi_parent(struct irq_data *data) 2464 { 2465 if (data->parent_data) 2466 irq_chip_eoi_parent(data); 2467 } 2468 2469 static int tegra_irq_set_affinity_parent(struct irq_data *data, 2470 const struct cpumask *dest, 2471 bool force) 2472 { 2473 if (data->parent_data) 2474 return irq_chip_set_affinity_parent(data, dest, force); 2475 2476 return -EINVAL; 2477 } 2478 2479 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2480 { 2481 struct irq_domain *parent = NULL; 2482 struct device_node *np; 2483 2484 np = of_irq_find_parent(pmc->dev->of_node); 2485 if (np) { 2486 parent = irq_find_host(np); 2487 of_node_put(np); 2488 } 2489 2490 if (!parent) 2491 return 0; 2492 2493 pmc->irq.name = dev_name(pmc->dev); 2494 pmc->irq.irq_mask = tegra_irq_mask_parent; 2495 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2496 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2497 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2498 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2499 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2500 2501 pmc->domain = irq_domain_create_hierarchy(parent, 0, 96, 2502 of_fwnode_handle(pmc->dev->of_node), 2503 &tegra_pmc_irq_domain_ops, pmc); 2504 if (!pmc->domain) { 2505 dev_err(pmc->dev, "failed to allocate domain\n"); 2506 return -ENOMEM; 2507 } 2508 2509 return 0; 2510 } 2511 2512 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2513 unsigned long action, void *ptr) 2514 { 2515 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2516 struct clk_notifier_data *data = ptr; 2517 2518 switch (action) { 2519 case PRE_RATE_CHANGE: 2520 mutex_lock(&pmc->powergates_lock); 2521 break; 2522 2523 case POST_RATE_CHANGE: 2524 pmc->rate = data->new_rate; 2525 fallthrough; 2526 2527 case ABORT_RATE_CHANGE: 2528 mutex_unlock(&pmc->powergates_lock); 2529 break; 2530 2531 default: 2532 WARN_ON_ONCE(1); 2533 return notifier_from_errno(-EINVAL); 2534 } 2535 2536 return NOTIFY_OK; 2537 } 2538 2539 static void pmc_clk_fence_udelay(u32 offset) 2540 { 2541 tegra_pmc_readl(pmc, offset); 2542 /* pmc clk propagation delay 2 us */ 2543 udelay(2); 2544 } 2545 2546 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2547 { 2548 struct pmc_clk *clk = to_pmc_clk(hw); 2549 u32 val; 2550 2551 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; 2552 val &= PMC_CLK_OUT_MUX_MASK; 2553 2554 return val; 2555 } 2556 2557 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2558 { 2559 struct pmc_clk *clk = to_pmc_clk(hw); 2560 u32 val; 2561 2562 val = tegra_pmc_readl(pmc, clk->offs); 2563 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2564 val |= index << clk->mux_shift; 2565 tegra_pmc_writel(pmc, val, clk->offs); 2566 pmc_clk_fence_udelay(clk->offs); 2567 2568 return 0; 2569 } 2570 2571 static int pmc_clk_is_enabled(struct clk_hw *hw) 2572 { 2573 struct pmc_clk *clk = to_pmc_clk(hw); 2574 u32 val; 2575 2576 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); 2577 2578 return val ? 1 : 0; 2579 } 2580 2581 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state) 2582 { 2583 u32 val; 2584 2585 val = tegra_pmc_readl(pmc, offs); 2586 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2587 tegra_pmc_writel(pmc, val, offs); 2588 pmc_clk_fence_udelay(offs); 2589 } 2590 2591 static int pmc_clk_enable(struct clk_hw *hw) 2592 { 2593 struct pmc_clk *clk = to_pmc_clk(hw); 2594 2595 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); 2596 2597 return 0; 2598 } 2599 2600 static void pmc_clk_disable(struct clk_hw *hw) 2601 { 2602 struct pmc_clk *clk = to_pmc_clk(hw); 2603 2604 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); 2605 } 2606 2607 static const struct clk_ops pmc_clk_ops = { 2608 .get_parent = pmc_clk_mux_get_parent, 2609 .set_parent = pmc_clk_mux_set_parent, 2610 .determine_rate = __clk_mux_determine_rate, 2611 .is_enabled = pmc_clk_is_enabled, 2612 .enable = pmc_clk_enable, 2613 .disable = pmc_clk_disable, 2614 }; 2615 2616 static struct clk * 2617 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2618 const struct pmc_clk_init_data *data, 2619 unsigned long offset) 2620 { 2621 struct clk_init_data init; 2622 struct pmc_clk *pmc_clk; 2623 2624 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2625 if (!pmc_clk) 2626 return ERR_PTR(-ENOMEM); 2627 2628 init.name = data->name; 2629 init.ops = &pmc_clk_ops; 2630 init.parent_names = data->parents; 2631 init.num_parents = data->num_parents; 2632 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2633 CLK_SET_PARENT_GATE; 2634 2635 pmc_clk->hw.init = &init; 2636 pmc_clk->offs = offset; 2637 pmc_clk->mux_shift = data->mux_shift; 2638 pmc_clk->force_en_shift = data->force_en_shift; 2639 2640 return clk_register(NULL, &pmc_clk->hw); 2641 } 2642 2643 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2644 { 2645 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2646 2647 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; 2648 } 2649 2650 static int pmc_clk_gate_enable(struct clk_hw *hw) 2651 { 2652 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2653 2654 pmc_clk_set_state(gate->offs, gate->shift, 1); 2655 2656 return 0; 2657 } 2658 2659 static void pmc_clk_gate_disable(struct clk_hw *hw) 2660 { 2661 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2662 2663 pmc_clk_set_state(gate->offs, gate->shift, 0); 2664 } 2665 2666 static const struct clk_ops pmc_clk_gate_ops = { 2667 .is_enabled = pmc_clk_gate_is_enabled, 2668 .enable = pmc_clk_gate_enable, 2669 .disable = pmc_clk_gate_disable, 2670 }; 2671 2672 static struct clk * 2673 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2674 const char *parent_name, unsigned long offset, 2675 u32 shift) 2676 { 2677 struct clk_init_data init; 2678 struct pmc_clk_gate *gate; 2679 2680 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2681 if (!gate) 2682 return ERR_PTR(-ENOMEM); 2683 2684 init.name = name; 2685 init.ops = &pmc_clk_gate_ops; 2686 init.parent_names = &parent_name; 2687 init.num_parents = 1; 2688 init.flags = 0; 2689 2690 gate->hw.init = &init; 2691 gate->offs = offset; 2692 gate->shift = shift; 2693 2694 return clk_register(NULL, &gate->hw); 2695 } 2696 2697 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2698 struct device_node *np) 2699 { 2700 struct clk *clk; 2701 struct clk_onecell_data *clk_data; 2702 unsigned int num_clks; 2703 int i, err; 2704 2705 num_clks = pmc->soc->num_pmc_clks; 2706 if (pmc->soc->has_blink_output) 2707 num_clks += 1; 2708 2709 if (!num_clks) 2710 return; 2711 2712 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2713 if (!clk_data) 2714 return; 2715 2716 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2717 sizeof(*clk_data->clks), GFP_KERNEL); 2718 if (!clk_data->clks) 2719 return; 2720 2721 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2722 2723 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2724 clk_data->clks[i] = ERR_PTR(-ENOENT); 2725 2726 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2727 const struct pmc_clk_init_data *data; 2728 2729 data = pmc->soc->pmc_clks_data + i; 2730 2731 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2732 if (IS_ERR(clk)) { 2733 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2734 data->name, PTR_ERR_OR_ZERO(clk)); 2735 return; 2736 } 2737 2738 err = clk_register_clkdev(clk, data->name, NULL); 2739 if (err) { 2740 dev_warn(pmc->dev, 2741 "unable to register %s clock lookup: %d\n", 2742 data->name, err); 2743 return; 2744 } 2745 2746 clk_data->clks[data->clk_id] = clk; 2747 } 2748 2749 if (pmc->soc->has_blink_output) { 2750 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2751 clk = tegra_pmc_clk_gate_register(pmc, 2752 "pmc_blink_override", 2753 "clk_32k", 2754 PMC_DPD_PADS_ORIDE, 2755 PMC_DPD_PADS_ORIDE_BLINK); 2756 if (IS_ERR(clk)) { 2757 dev_warn(pmc->dev, 2758 "unable to register pmc_blink_override: %d\n", 2759 PTR_ERR_OR_ZERO(clk)); 2760 return; 2761 } 2762 2763 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 2764 "pmc_blink_override", 2765 PMC_CNTRL, 2766 PMC_CNTRL_BLINK_EN); 2767 if (IS_ERR(clk)) { 2768 dev_warn(pmc->dev, 2769 "unable to register pmc_blink: %d\n", 2770 PTR_ERR_OR_ZERO(clk)); 2771 return; 2772 } 2773 2774 err = clk_register_clkdev(clk, "pmc_blink", NULL); 2775 if (err) { 2776 dev_warn(pmc->dev, 2777 "unable to register pmc_blink lookup: %d\n", 2778 err); 2779 return; 2780 } 2781 2782 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 2783 } 2784 2785 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 2786 if (err) 2787 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 2788 err); 2789 } 2790 2791 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = { 2792 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO), 2793 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE), 2794 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE), 2795 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP), 2796 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG), 2797 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG), 2798 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1), 2799 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3), 2800 }; 2801 2802 static const struct regmap_access_table pmc_usb_sleepwalk_table = { 2803 .yes_ranges = pmc_usb_sleepwalk_ranges, 2804 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges), 2805 }; 2806 2807 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) 2808 { 2809 struct tegra_pmc *pmc = context; 2810 2811 *value = tegra_pmc_readl(pmc, offset); 2812 return 0; 2813 } 2814 2815 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) 2816 { 2817 struct tegra_pmc *pmc = context; 2818 2819 tegra_pmc_writel(pmc, value, offset); 2820 return 0; 2821 } 2822 2823 static const struct regmap_config usb_sleepwalk_regmap_config = { 2824 .name = "usb_sleepwalk", 2825 .reg_bits = 32, 2826 .val_bits = 32, 2827 .reg_stride = 4, 2828 .fast_io = true, 2829 .rd_table = &pmc_usb_sleepwalk_table, 2830 .wr_table = &pmc_usb_sleepwalk_table, 2831 .reg_read = tegra_pmc_regmap_readl, 2832 .reg_write = tegra_pmc_regmap_writel, 2833 }; 2834 2835 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) 2836 { 2837 struct regmap *regmap; 2838 int err; 2839 2840 if (pmc->soc->has_usb_sleepwalk) { 2841 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); 2842 if (IS_ERR(regmap)) { 2843 err = PTR_ERR(regmap); 2844 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); 2845 return err; 2846 } 2847 } 2848 2849 return 0; 2850 } 2851 2852 static void tegra_pmc_reset_suspend_mode(void *data) 2853 { 2854 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; 2855 } 2856 2857 static int tegra_pmc_probe(struct platform_device *pdev) 2858 { 2859 void __iomem *base; 2860 struct resource *res; 2861 int err; 2862 2863 /* 2864 * Early initialisation should have configured an initial 2865 * register mapping and setup the soc data pointer. If these 2866 * are not valid then something went badly wrong! 2867 */ 2868 if (WARN_ON(!pmc->base || !pmc->soc)) 2869 return -ENODEV; 2870 2871 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 2872 if (err < 0) 2873 return err; 2874 2875 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, 2876 NULL); 2877 if (err) 2878 return err; 2879 2880 /* take over the memory region from the early initialization */ 2881 base = devm_platform_ioremap_resource(pdev, 0); 2882 if (IS_ERR(base)) 2883 return PTR_ERR(base); 2884 2885 if (pmc->soc->has_single_mmio_aperture) { 2886 pmc->wake = base; 2887 pmc->aotag = base; 2888 pmc->scratch = base; 2889 } else { 2890 pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake"); 2891 if (IS_ERR(pmc->wake)) 2892 return PTR_ERR(pmc->wake); 2893 2894 pmc->aotag = devm_platform_ioremap_resource_byname(pdev, "aotag"); 2895 if (IS_ERR(pmc->aotag)) 2896 return PTR_ERR(pmc->aotag); 2897 2898 /* "scratch" is an optional aperture */ 2899 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2900 "scratch"); 2901 if (res) { 2902 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 2903 if (IS_ERR(pmc->scratch)) 2904 return PTR_ERR(pmc->scratch); 2905 } else { 2906 pmc->scratch = NULL; 2907 } 2908 } 2909 2910 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); 2911 if (IS_ERR(pmc->clk)) 2912 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), 2913 "failed to get pclk\n"); 2914 2915 /* 2916 * PMC should be last resort for restarting since it soft-resets 2917 * CPU without resetting everything else. 2918 */ 2919 if (pmc->scratch) { 2920 err = devm_register_reboot_notifier(&pdev->dev, 2921 &tegra_pmc_reboot_notifier); 2922 if (err) { 2923 dev_err(&pdev->dev, 2924 "unable to register reboot notifier, %d\n", 2925 err); 2926 return err; 2927 } 2928 } 2929 2930 err = devm_register_sys_off_handler(&pdev->dev, 2931 SYS_OFF_MODE_RESTART, 2932 SYS_OFF_PRIO_LOW, 2933 tegra_pmc_restart_handler, NULL); 2934 if (err) { 2935 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 2936 err); 2937 return err; 2938 } 2939 2940 /* 2941 * PMC should be primary power-off method if it soft-resets CPU, 2942 * asking bootloader to shutdown hardware. 2943 */ 2944 err = devm_register_sys_off_handler(&pdev->dev, 2945 SYS_OFF_MODE_POWER_OFF, 2946 SYS_OFF_PRIO_FIRMWARE, 2947 tegra_pmc_power_off_handler, NULL); 2948 if (err) { 2949 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 2950 err); 2951 return err; 2952 } 2953 2954 /* 2955 * PCLK clock rate can't be retrieved using CLK API because it 2956 * causes lockup if CPU enters LP2 idle state from some other 2957 * CLK notifier, hence we're caching the rate's value locally. 2958 */ 2959 if (pmc->clk) { 2960 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 2961 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, 2962 &pmc->clk_nb); 2963 if (err) { 2964 dev_err(&pdev->dev, 2965 "failed to register clk notifier\n"); 2966 return err; 2967 } 2968 2969 pmc->rate = clk_get_rate(pmc->clk); 2970 } 2971 2972 pmc->dev = &pdev->dev; 2973 2974 err = tegra_pmc_init(pmc); 2975 if (err < 0) { 2976 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); 2977 return err; 2978 } 2979 2980 tegra_pmc_init_tsense_reset(pmc); 2981 2982 tegra_pmc_reset_sysfs_init(pmc); 2983 2984 err = tegra_pmc_pinctrl_init(pmc); 2985 if (err) 2986 goto cleanup_sysfs; 2987 2988 err = tegra_pmc_regmap_init(pmc); 2989 if (err < 0) 2990 goto cleanup_sysfs; 2991 2992 err = tegra_powergate_init(pmc, pdev->dev.of_node); 2993 if (err < 0) 2994 goto cleanup_powergates; 2995 2996 err = tegra_pmc_irq_init(pmc); 2997 if (err < 0) 2998 goto cleanup_powergates; 2999 3000 mutex_lock(&pmc->powergates_lock); 3001 iounmap(pmc->base); 3002 pmc->base = base; 3003 mutex_unlock(&pmc->powergates_lock); 3004 3005 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 3006 platform_set_drvdata(pdev, pmc); 3007 tegra_pm_init_suspend(); 3008 3009 /* Some wakes require specific filter configuration */ 3010 if (pmc->soc->set_wake_filters) 3011 pmc->soc->set_wake_filters(pmc); 3012 3013 debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops); 3014 3015 return 0; 3016 3017 cleanup_powergates: 3018 tegra_powergate_remove_all(pdev->dev.of_node); 3019 cleanup_sysfs: 3020 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 3021 device_remove_file(&pdev->dev, &dev_attr_reset_level); 3022 3023 return err; 3024 } 3025 3026 /* 3027 * Ensures that sufficient time is passed for a register write to 3028 * serialize into the 32KHz domain. 3029 */ 3030 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) 3031 { 3032 writel(value, pmc->wake + offset); 3033 udelay(130); 3034 } 3035 3036 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) 3037 { 3038 unsigned int offset = WAKE_AOWAKE_CNTRL(wake); 3039 u32 value; 3040 3041 value = readl(pmc->wake + offset); 3042 if (level) 3043 value |= WAKE_AOWAKE_CNTRL_LEVEL; 3044 else 3045 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 3046 3047 writel(value, pmc->wake + offset); 3048 } 3049 3050 static void wke_write_wake_levels(struct tegra_pmc *pmc) 3051 { 3052 unsigned int i; 3053 3054 for (i = 0; i < pmc->soc->max_wake_events; i++) 3055 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); 3056 } 3057 3058 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) 3059 { 3060 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0); 3061 } 3062 3063 static void wke_read_sw_wake_status(struct tegra_pmc *pmc) 3064 { 3065 unsigned long status; 3066 unsigned int wake, i; 3067 3068 for (i = 0; i < pmc->soc->max_wake_events; i++) 3069 wke_write_wake_level(pmc, i, 0); 3070 3071 wke_clear_sw_wake_status(pmc); 3072 3073 wke_32kwritel(pmc, 1, WAKE_LATCH_SW); 3074 3075 /* 3076 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to 3077 * obtain the current status of the input wake signals, change 3078 * the polarity of the wake level from 0->1 while latching to force 3079 * a positive edge if the sampled signal is '1'. 3080 */ 3081 for (i = 0; i < pmc->soc->max_wake_events; i++) 3082 wke_write_wake_level(pmc, i, 1); 3083 3084 /* 3085 * Wait for the update to be synced into the 32kHz domain, 3086 * and let enough time lapse, so that the wake signals have time to 3087 * be sampled. 3088 */ 3089 udelay(300); 3090 3091 wke_32kwritel(pmc, 0, WAKE_LATCH_SW); 3092 3093 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3094 3095 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3096 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); 3097 3098 for_each_set_bit(wake, &status, 32) 3099 set_bit(wake + (i * 32), pmc->wake_sw_status_map); 3100 } 3101 } 3102 3103 static void wke_clear_wake_status(struct tegra_pmc *pmc) 3104 { 3105 unsigned long status; 3106 unsigned int i, wake; 3107 u32 mask; 3108 3109 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3110 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); 3111 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; 3112 3113 for_each_set_bit(wake, &status, 32) 3114 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake)); 3115 } 3116 } 3117 3118 /* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */ 3119 static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index, 3120 unsigned long status) 3121 { 3122 unsigned int wake; 3123 3124 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status); 3125 3126 for_each_set_bit(wake, &status, 32) { 3127 irq_hw_number_t hwirq = wake + 32 * index; 3128 struct irq_desc *desc; 3129 unsigned int irq; 3130 3131 irq = irq_find_mapping(pmc->domain, hwirq); 3132 3133 desc = irq_to_desc(irq); 3134 if (!desc || !desc->action || !desc->action->name) { 3135 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq); 3136 continue; 3137 } 3138 3139 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name); 3140 generic_handle_irq(irq); 3141 } 3142 } 3143 3144 static void tegra186_pmc_wake_syscore_resume(void) 3145 { 3146 u32 status, mask; 3147 unsigned int i; 3148 3149 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3150 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); 3151 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; 3152 3153 tegra186_pmc_process_wake_events(pmc, i, status); 3154 } 3155 } 3156 3157 static int tegra186_pmc_wake_syscore_suspend(void) 3158 { 3159 wke_read_sw_wake_status(pmc); 3160 3161 /* flip the wakeup trigger for dual-edge triggered pads 3162 * which are currently asserting as wakeups 3163 */ 3164 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, 3165 pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3166 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, 3167 pmc->wake_type_level_map, pmc->soc->max_wake_events); 3168 3169 /* Clear PMC Wake Status registers while going to suspend */ 3170 wke_clear_wake_status(pmc); 3171 wke_write_wake_levels(pmc); 3172 3173 return 0; 3174 } 3175 3176 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3177 static int tegra_pmc_suspend(struct device *dev) 3178 { 3179 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3180 3181 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 3182 3183 return 0; 3184 } 3185 3186 static int tegra_pmc_resume(struct device *dev) 3187 { 3188 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3189 3190 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 3191 3192 return 0; 3193 } 3194 3195 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 3196 3197 #endif 3198 3199 static const char * const tegra20_powergates[] = { 3200 [TEGRA_POWERGATE_CPU] = "cpu", 3201 [TEGRA_POWERGATE_3D] = "td", 3202 [TEGRA_POWERGATE_VENC] = "venc", 3203 [TEGRA_POWERGATE_VDEC] = "vdec", 3204 [TEGRA_POWERGATE_PCIE] = "pcie", 3205 [TEGRA_POWERGATE_L2] = "l2", 3206 [TEGRA_POWERGATE_MPE] = "mpe", 3207 }; 3208 3209 static const struct tegra_pmc_regs tegra20_pmc_regs = { 3210 .scratch0 = 0x50, 3211 .rst_status = 0x1b4, 3212 .rst_source_shift = 0x0, 3213 .rst_source_mask = 0x7, 3214 .rst_level_shift = 0x0, 3215 .rst_level_mask = 0x0, 3216 }; 3217 3218 static void tegra20_pmc_init(struct tegra_pmc *pmc) 3219 { 3220 u32 value, osc, pmu, off; 3221 3222 /* Always enable CPU power request */ 3223 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3224 value |= PMC_CNTRL_CPU_PWRREQ_OE; 3225 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3226 3227 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3228 3229 if (pmc->sysclkreq_high) 3230 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 3231 else 3232 value |= PMC_CNTRL_SYSCLK_POLARITY; 3233 3234 if (pmc->corereq_high) 3235 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 3236 else 3237 value |= PMC_CNTRL_PWRREQ_POLARITY; 3238 3239 /* configure the output polarity while the request is tristated */ 3240 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3241 3242 /* now enable the request */ 3243 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3244 value |= PMC_CNTRL_SYSCLK_OE; 3245 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3246 3247 /* program core timings which are applicable only for suspend state */ 3248 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 3249 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 3250 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 3251 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 3252 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 3253 PMC_COREPWRGOOD_TIMER); 3254 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 3255 } 3256 } 3257 3258 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3259 struct device_node *np, 3260 bool invert) 3261 { 3262 u32 value; 3263 3264 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3265 3266 if (invert) 3267 value |= PMC_CNTRL_INTR_POLARITY; 3268 else 3269 value &= ~PMC_CNTRL_INTR_POLARITY; 3270 3271 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3272 } 3273 3274 static const struct tegra_pmc_soc tegra20_pmc_soc = { 3275 .supports_core_domain = true, 3276 .num_powergates = ARRAY_SIZE(tegra20_powergates), 3277 .powergates = tegra20_powergates, 3278 .num_cpu_powergates = 0, 3279 .cpu_powergates = NULL, 3280 .has_tsense_reset = false, 3281 .has_gpu_clamps = false, 3282 .needs_mbist_war = false, 3283 .has_impl_33v_pwr = false, 3284 .maybe_tz_only = false, 3285 .num_io_pads = 0, 3286 .io_pads = NULL, 3287 .num_pin_descs = 0, 3288 .pin_descs = NULL, 3289 .regs = &tegra20_pmc_regs, 3290 .init = tegra20_pmc_init, 3291 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3292 .powergate_set = tegra20_powergate_set, 3293 .reset_sources = NULL, 3294 .num_reset_sources = 0, 3295 .reset_levels = NULL, 3296 .num_reset_levels = 0, 3297 .pmc_clks_data = NULL, 3298 .num_pmc_clks = 0, 3299 .has_blink_output = true, 3300 .has_usb_sleepwalk = true, 3301 .has_single_mmio_aperture = true, 3302 }; 3303 3304 static const char * const tegra30_powergates[] = { 3305 [TEGRA_POWERGATE_CPU] = "cpu0", 3306 [TEGRA_POWERGATE_3D] = "td", 3307 [TEGRA_POWERGATE_VENC] = "venc", 3308 [TEGRA_POWERGATE_VDEC] = "vdec", 3309 [TEGRA_POWERGATE_PCIE] = "pcie", 3310 [TEGRA_POWERGATE_L2] = "l2", 3311 [TEGRA_POWERGATE_MPE] = "mpe", 3312 [TEGRA_POWERGATE_HEG] = "heg", 3313 [TEGRA_POWERGATE_SATA] = "sata", 3314 [TEGRA_POWERGATE_CPU1] = "cpu1", 3315 [TEGRA_POWERGATE_CPU2] = "cpu2", 3316 [TEGRA_POWERGATE_CPU3] = "cpu3", 3317 [TEGRA_POWERGATE_CELP] = "celp", 3318 [TEGRA_POWERGATE_3D1] = "td2", 3319 }; 3320 3321 static const u8 tegra30_cpu_powergates[] = { 3322 TEGRA_POWERGATE_CPU, 3323 TEGRA_POWERGATE_CPU1, 3324 TEGRA_POWERGATE_CPU2, 3325 TEGRA_POWERGATE_CPU3, 3326 }; 3327 3328 static const char * const tegra30_reset_sources[] = { 3329 "POWER_ON_RESET", 3330 "WATCHDOG", 3331 "SENSOR", 3332 "SW_MAIN", 3333 "LP0" 3334 }; 3335 3336 static const struct tegra_pmc_soc tegra30_pmc_soc = { 3337 .supports_core_domain = true, 3338 .num_powergates = ARRAY_SIZE(tegra30_powergates), 3339 .powergates = tegra30_powergates, 3340 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 3341 .cpu_powergates = tegra30_cpu_powergates, 3342 .has_tsense_reset = true, 3343 .has_gpu_clamps = false, 3344 .needs_mbist_war = false, 3345 .has_impl_33v_pwr = false, 3346 .maybe_tz_only = false, 3347 .num_io_pads = 0, 3348 .io_pads = NULL, 3349 .num_pin_descs = 0, 3350 .pin_descs = NULL, 3351 .regs = &tegra20_pmc_regs, 3352 .init = tegra20_pmc_init, 3353 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3354 .powergate_set = tegra20_powergate_set, 3355 .reset_sources = tegra30_reset_sources, 3356 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3357 .reset_levels = NULL, 3358 .num_reset_levels = 0, 3359 .pmc_clks_data = tegra_pmc_clks_data, 3360 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3361 .has_blink_output = true, 3362 .has_usb_sleepwalk = true, 3363 .has_single_mmio_aperture = true, 3364 }; 3365 3366 static const char * const tegra114_powergates[] = { 3367 [TEGRA_POWERGATE_CPU] = "crail", 3368 [TEGRA_POWERGATE_3D] = "td", 3369 [TEGRA_POWERGATE_VENC] = "venc", 3370 [TEGRA_POWERGATE_VDEC] = "vdec", 3371 [TEGRA_POWERGATE_MPE] = "mpe", 3372 [TEGRA_POWERGATE_HEG] = "heg", 3373 [TEGRA_POWERGATE_CPU1] = "cpu1", 3374 [TEGRA_POWERGATE_CPU2] = "cpu2", 3375 [TEGRA_POWERGATE_CPU3] = "cpu3", 3376 [TEGRA_POWERGATE_CELP] = "celp", 3377 [TEGRA_POWERGATE_CPU0] = "cpu0", 3378 [TEGRA_POWERGATE_C0NC] = "c0nc", 3379 [TEGRA_POWERGATE_C1NC] = "c1nc", 3380 [TEGRA_POWERGATE_DIS] = "dis", 3381 [TEGRA_POWERGATE_DISB] = "disb", 3382 [TEGRA_POWERGATE_XUSBA] = "xusba", 3383 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3384 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3385 }; 3386 3387 static const u8 tegra114_cpu_powergates[] = { 3388 TEGRA_POWERGATE_CPU0, 3389 TEGRA_POWERGATE_CPU1, 3390 TEGRA_POWERGATE_CPU2, 3391 TEGRA_POWERGATE_CPU3, 3392 }; 3393 3394 static const struct tegra_pmc_soc tegra114_pmc_soc = { 3395 .supports_core_domain = false, 3396 .num_powergates = ARRAY_SIZE(tegra114_powergates), 3397 .powergates = tegra114_powergates, 3398 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 3399 .cpu_powergates = tegra114_cpu_powergates, 3400 .has_tsense_reset = true, 3401 .has_gpu_clamps = false, 3402 .needs_mbist_war = false, 3403 .has_impl_33v_pwr = false, 3404 .maybe_tz_only = false, 3405 .num_io_pads = 0, 3406 .io_pads = NULL, 3407 .num_pin_descs = 0, 3408 .pin_descs = NULL, 3409 .regs = &tegra20_pmc_regs, 3410 .init = tegra20_pmc_init, 3411 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3412 .powergate_set = tegra114_powergate_set, 3413 .reset_sources = tegra30_reset_sources, 3414 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3415 .reset_levels = NULL, 3416 .num_reset_levels = 0, 3417 .pmc_clks_data = tegra_pmc_clks_data, 3418 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3419 .has_blink_output = true, 3420 .has_usb_sleepwalk = true, 3421 .has_single_mmio_aperture = true, 3422 }; 3423 3424 static const char * const tegra124_powergates[] = { 3425 [TEGRA_POWERGATE_CPU] = "crail", 3426 [TEGRA_POWERGATE_3D] = "3d", 3427 [TEGRA_POWERGATE_VENC] = "venc", 3428 [TEGRA_POWERGATE_PCIE] = "pcie", 3429 [TEGRA_POWERGATE_VDEC] = "vdec", 3430 [TEGRA_POWERGATE_MPE] = "mpe", 3431 [TEGRA_POWERGATE_HEG] = "heg", 3432 [TEGRA_POWERGATE_SATA] = "sata", 3433 [TEGRA_POWERGATE_CPU1] = "cpu1", 3434 [TEGRA_POWERGATE_CPU2] = "cpu2", 3435 [TEGRA_POWERGATE_CPU3] = "cpu3", 3436 [TEGRA_POWERGATE_CELP] = "celp", 3437 [TEGRA_POWERGATE_CPU0] = "cpu0", 3438 [TEGRA_POWERGATE_C0NC] = "c0nc", 3439 [TEGRA_POWERGATE_C1NC] = "c1nc", 3440 [TEGRA_POWERGATE_SOR] = "sor", 3441 [TEGRA_POWERGATE_DIS] = "dis", 3442 [TEGRA_POWERGATE_DISB] = "disb", 3443 [TEGRA_POWERGATE_XUSBA] = "xusba", 3444 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3445 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3446 [TEGRA_POWERGATE_VIC] = "vic", 3447 [TEGRA_POWERGATE_IRAM] = "iram", 3448 }; 3449 3450 static const u8 tegra124_cpu_powergates[] = { 3451 TEGRA_POWERGATE_CPU0, 3452 TEGRA_POWERGATE_CPU1, 3453 TEGRA_POWERGATE_CPU2, 3454 TEGRA_POWERGATE_CPU3, 3455 }; 3456 3457 #define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \ 3458 ((struct tegra_io_pad_soc) { \ 3459 .id = (_id), \ 3460 .dpd = (_dpd), \ 3461 .request = (_request), \ 3462 .status = (_status), \ 3463 .voltage = (_voltage), \ 3464 .name = (_name), \ 3465 }) 3466 3467 #define TEGRA_IO_PIN_DESC(_id, _name) \ 3468 ((struct pinctrl_pin_desc) { \ 3469 .number = (_id), \ 3470 .name = (_name), \ 3471 }) 3472 3473 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 3474 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"), 3475 TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"), 3476 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"), 3477 TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"), 3478 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), 3479 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), 3480 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), 3481 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), 3482 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), 3483 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), 3484 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), 3485 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), 3486 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), 3487 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"), 3488 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), 3489 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), 3490 TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"), 3491 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), 3492 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), 3493 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3494 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"), 3495 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"), 3496 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"), 3497 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"), 3498 TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"), 3499 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"), 3500 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), 3501 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), 3502 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), 3503 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"), 3504 }; 3505 3506 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 3507 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3508 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"), 3509 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3510 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"), 3511 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3512 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3513 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3514 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3515 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3516 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3517 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3518 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3519 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3520 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"), 3521 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3522 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3523 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"), 3524 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3525 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3526 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3527 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3528 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3529 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3530 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3531 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"), 3532 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3533 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3534 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3535 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3536 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"), 3537 }; 3538 3539 static const struct tegra_pmc_soc tegra124_pmc_soc = { 3540 .supports_core_domain = false, 3541 .num_powergates = ARRAY_SIZE(tegra124_powergates), 3542 .powergates = tegra124_powergates, 3543 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 3544 .cpu_powergates = tegra124_cpu_powergates, 3545 .has_tsense_reset = true, 3546 .has_gpu_clamps = true, 3547 .needs_mbist_war = false, 3548 .has_impl_33v_pwr = false, 3549 .maybe_tz_only = false, 3550 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 3551 .io_pads = tegra124_io_pads, 3552 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 3553 .pin_descs = tegra124_pin_descs, 3554 .regs = &tegra20_pmc_regs, 3555 .init = tegra20_pmc_init, 3556 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3557 .powergate_set = tegra114_powergate_set, 3558 .reset_sources = tegra30_reset_sources, 3559 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3560 .reset_levels = NULL, 3561 .num_reset_levels = 0, 3562 .pmc_clks_data = tegra_pmc_clks_data, 3563 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3564 .has_blink_output = true, 3565 .has_usb_sleepwalk = true, 3566 .has_single_mmio_aperture = true, 3567 }; 3568 3569 static const char * const tegra210_powergates[] = { 3570 [TEGRA_POWERGATE_CPU] = "crail", 3571 [TEGRA_POWERGATE_3D] = "3d", 3572 [TEGRA_POWERGATE_VENC] = "venc", 3573 [TEGRA_POWERGATE_PCIE] = "pcie", 3574 [TEGRA_POWERGATE_MPE] = "mpe", 3575 [TEGRA_POWERGATE_SATA] = "sata", 3576 [TEGRA_POWERGATE_CPU1] = "cpu1", 3577 [TEGRA_POWERGATE_CPU2] = "cpu2", 3578 [TEGRA_POWERGATE_CPU3] = "cpu3", 3579 [TEGRA_POWERGATE_CPU0] = "cpu0", 3580 [TEGRA_POWERGATE_C0NC] = "c0nc", 3581 [TEGRA_POWERGATE_SOR] = "sor", 3582 [TEGRA_POWERGATE_DIS] = "dis", 3583 [TEGRA_POWERGATE_DISB] = "disb", 3584 [TEGRA_POWERGATE_XUSBA] = "xusba", 3585 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3586 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3587 [TEGRA_POWERGATE_VIC] = "vic", 3588 [TEGRA_POWERGATE_IRAM] = "iram", 3589 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3590 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3591 [TEGRA_POWERGATE_AUD] = "aud", 3592 [TEGRA_POWERGATE_DFD] = "dfd", 3593 [TEGRA_POWERGATE_VE2] = "ve2", 3594 }; 3595 3596 static const u8 tegra210_cpu_powergates[] = { 3597 TEGRA_POWERGATE_CPU0, 3598 TEGRA_POWERGATE_CPU1, 3599 TEGRA_POWERGATE_CPU2, 3600 TEGRA_POWERGATE_CPU3, 3601 }; 3602 3603 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3604 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"), 3605 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"), 3606 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"), 3607 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), 3608 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), 3609 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"), 3610 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"), 3611 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), 3612 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"), 3613 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"), 3614 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"), 3615 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"), 3616 TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"), 3617 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), 3618 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), 3619 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), 3620 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), 3621 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"), 3622 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"), 3623 TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"), 3624 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), 3625 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), 3626 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), 3627 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), 3628 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), 3629 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), 3630 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3631 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"), 3632 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"), 3633 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"), 3634 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"), 3635 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"), 3636 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"), 3637 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), 3638 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), 3639 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), 3640 TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"), 3641 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"), 3642 }; 3643 3644 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3645 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3646 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3647 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3648 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3649 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3650 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3651 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3652 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3653 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3654 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3655 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"), 3656 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"), 3657 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"), 3658 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3659 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3660 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3661 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3662 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"), 3663 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"), 3664 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"), 3665 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3666 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3667 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3668 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3669 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3670 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3671 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3672 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3673 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3674 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3675 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3676 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"), 3677 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3678 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3679 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3680 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3681 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"), 3682 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3683 }; 3684 3685 static const char * const tegra210_reset_sources[] = { 3686 "POWER_ON_RESET", 3687 "WATCHDOG", 3688 "SENSOR", 3689 "SW_MAIN", 3690 "LP0", 3691 "AOTAG" 3692 }; 3693 3694 static const struct tegra_wake_event tegra210_wake_events[] = { 3695 TEGRA_WAKE_IRQ("rtc", 16, 2), 3696 TEGRA_WAKE_IRQ("pmu", 51, 86), 3697 }; 3698 3699 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3700 .supports_core_domain = false, 3701 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3702 .powergates = tegra210_powergates, 3703 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3704 .cpu_powergates = tegra210_cpu_powergates, 3705 .has_tsense_reset = true, 3706 .has_gpu_clamps = true, 3707 .needs_mbist_war = true, 3708 .has_impl_33v_pwr = false, 3709 .maybe_tz_only = true, 3710 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3711 .io_pads = tegra210_io_pads, 3712 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3713 .pin_descs = tegra210_pin_descs, 3714 .regs = &tegra20_pmc_regs, 3715 .init = tegra20_pmc_init, 3716 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3717 .powergate_set = tegra114_powergate_set, 3718 .irq_set_wake = tegra210_pmc_irq_set_wake, 3719 .irq_set_type = tegra210_pmc_irq_set_type, 3720 .reset_sources = tegra210_reset_sources, 3721 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3722 .reset_levels = NULL, 3723 .num_reset_levels = 0, 3724 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3725 .wake_events = tegra210_wake_events, 3726 .pmc_clks_data = tegra_pmc_clks_data, 3727 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3728 .has_blink_output = true, 3729 .has_usb_sleepwalk = true, 3730 .has_single_mmio_aperture = true, 3731 }; 3732 3733 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3734 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), 3735 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), 3736 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"), 3737 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), 3738 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), 3739 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), 3740 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3741 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), 3742 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"), 3743 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"), 3744 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"), 3745 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"), 3746 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), 3747 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), 3748 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"), 3749 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), 3750 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), 3751 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), 3752 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), 3753 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"), 3754 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), 3755 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), 3756 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"), 3757 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"), 3758 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"), 3759 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), 3760 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), 3761 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), 3762 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), 3763 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), 3764 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), 3765 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"), 3766 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), 3767 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), 3768 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), 3769 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), 3770 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), 3771 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 3772 }; 3773 3774 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 3775 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3776 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3777 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3778 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3779 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 3780 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 3781 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3782 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3783 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3784 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3785 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3786 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3787 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3788 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3789 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3790 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3791 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 3792 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 3793 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3794 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"), 3795 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3796 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3797 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3798 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3799 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3800 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3801 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3802 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3803 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3804 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3805 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 3806 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"), 3807 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 3808 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 3809 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 3810 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 3811 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3812 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 3813 }; 3814 3815 static const struct tegra_pmc_regs tegra186_pmc_regs = { 3816 .scratch0 = 0x2000, 3817 .rst_status = 0x70, 3818 .rst_source_shift = 0x2, 3819 .rst_source_mask = 0x3c, 3820 .rst_level_shift = 0x0, 3821 .rst_level_mask = 0x3, 3822 }; 3823 3824 static void tegra186_pmc_init(struct tegra_pmc *pmc) 3825 { 3826 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; 3827 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; 3828 3829 register_syscore_ops(&pmc->syscore); 3830 } 3831 3832 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3833 struct device_node *np, 3834 bool invert) 3835 { 3836 struct resource regs; 3837 void __iomem *wake; 3838 u32 value; 3839 int index; 3840 3841 index = of_property_match_string(np, "reg-names", "wake"); 3842 if (index < 0) { 3843 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 3844 return; 3845 } 3846 3847 of_address_to_resource(np, index, ®s); 3848 3849 wake = ioremap(regs.start, resource_size(®s)); 3850 if (!wake) { 3851 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 3852 return; 3853 } 3854 3855 value = readl(wake + WAKE_AOWAKE_CTRL); 3856 3857 if (invert) 3858 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 3859 else 3860 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 3861 3862 writel(value, wake + WAKE_AOWAKE_CTRL); 3863 3864 iounmap(wake); 3865 } 3866 3867 static const char * const tegra186_reset_sources[] = { 3868 "SYS_RESET", 3869 "AOWDT", 3870 "MCCPLEXWDT", 3871 "BPMPWDT", 3872 "SCEWDT", 3873 "SPEWDT", 3874 "APEWDT", 3875 "BCCPLEXWDT", 3876 "SENSOR", 3877 "AOTAG", 3878 "VFSENSOR", 3879 "SWREST", 3880 "SC7", 3881 "HSM", 3882 "CORESIGHT" 3883 }; 3884 3885 static const char * const tegra186_reset_levels[] = { 3886 "L0", "L1", "L2", "WARM" 3887 }; 3888 3889 static const struct tegra_wake_event tegra186_wake_events[] = { 3890 TEGRA_WAKE_IRQ("pmu", 24, 209), 3891 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 3892 TEGRA_WAKE_IRQ("rtc", 73, 10), 3893 }; 3894 3895 static const struct tegra_pmc_soc tegra186_pmc_soc = { 3896 .supports_core_domain = false, 3897 .num_powergates = 0, 3898 .powergates = NULL, 3899 .num_cpu_powergates = 0, 3900 .cpu_powergates = NULL, 3901 .has_tsense_reset = false, 3902 .has_gpu_clamps = false, 3903 .needs_mbist_war = false, 3904 .has_impl_33v_pwr = true, 3905 .maybe_tz_only = false, 3906 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 3907 .io_pads = tegra186_io_pads, 3908 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 3909 .pin_descs = tegra186_pin_descs, 3910 .regs = &tegra186_pmc_regs, 3911 .init = tegra186_pmc_init, 3912 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3913 .set_wake_filters = tegra186_pmc_set_wake_filters, 3914 .irq_set_wake = tegra186_pmc_irq_set_wake, 3915 .irq_set_type = tegra186_pmc_irq_set_type, 3916 .reset_sources = tegra186_reset_sources, 3917 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 3918 .reset_levels = tegra186_reset_levels, 3919 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3920 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 3921 .wake_events = tegra186_wake_events, 3922 .max_wake_events = 96, 3923 .max_wake_vectors = 3, 3924 .pmc_clks_data = NULL, 3925 .num_pmc_clks = 0, 3926 .has_blink_output = false, 3927 .has_usb_sleepwalk = false, 3928 .has_single_mmio_aperture = false, 3929 }; 3930 3931 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 3932 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), 3933 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), 3934 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), 3935 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), 3936 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), 3937 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3938 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), 3939 TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"), 3940 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"), 3941 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"), 3942 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"), 3943 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"), 3944 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), 3945 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"), 3946 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"), 3947 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), 3948 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"), 3949 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"), 3950 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"), 3951 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"), 3952 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"), 3953 TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"), 3954 TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"), 3955 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), 3956 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"), 3957 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"), 3958 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), 3959 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), 3960 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), 3961 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"), 3962 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"), 3963 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"), 3964 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), 3965 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"), 3966 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), 3967 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), 3968 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), 3969 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), 3970 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), 3971 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), 3972 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), 3973 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"), 3974 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"), 3975 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), 3976 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), 3977 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), 3978 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), 3979 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), 3980 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 3981 }; 3982 3983 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 3984 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3985 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3986 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3987 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 3988 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 3989 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3990 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3991 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"), 3992 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"), 3993 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"), 3994 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"), 3995 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"), 3996 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3997 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"), 3998 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"), 3999 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 4000 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"), 4001 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"), 4002 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"), 4003 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"), 4004 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"), 4005 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"), 4006 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"), 4007 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 4008 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"), 4009 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"), 4010 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4011 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 4012 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 4013 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"), 4014 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"), 4015 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"), 4016 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 4017 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"), 4018 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 4019 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4020 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4021 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4022 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4023 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 4024 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4025 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4026 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4027 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4028 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4029 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4030 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 4031 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4032 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4033 }; 4034 4035 static const struct tegra_pmc_regs tegra194_pmc_regs = { 4036 .scratch0 = 0x2000, 4037 .rst_status = 0x70, 4038 .rst_source_shift = 0x2, 4039 .rst_source_mask = 0x7c, 4040 .rst_level_shift = 0x0, 4041 .rst_level_mask = 0x3, 4042 }; 4043 4044 static const char * const tegra194_reset_sources[] = { 4045 "SYS_RESET_N", 4046 "AOWDT", 4047 "BCCPLEXWDT", 4048 "BPMPWDT", 4049 "SCEWDT", 4050 "SPEWDT", 4051 "APEWDT", 4052 "LCCPLEXWDT", 4053 "SENSOR", 4054 "AOTAG", 4055 "VFSENSOR", 4056 "MAINSWRST", 4057 "SC7", 4058 "HSM", 4059 "CSITE", 4060 "RCEWDT", 4061 "PVA0WDT", 4062 "PVA1WDT", 4063 "L1A_ASYNC", 4064 "BPMPBOOT", 4065 "FUSECRC", 4066 }; 4067 4068 static const struct tegra_wake_event tegra194_wake_events[] = { 4069 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA194_MAIN_GPIO(G, 4)), 4070 TEGRA_WAKE_IRQ("pmu", 24, 209), 4071 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 4072 TEGRA_WAKE_IRQ("rtc", 73, 10), 4073 TEGRA_WAKE_SIMPLE("usb3-port-0", 76), 4074 TEGRA_WAKE_SIMPLE("usb3-port-1", 77), 4075 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78), 4076 TEGRA_WAKE_SIMPLE("usb2-port-0", 79), 4077 TEGRA_WAKE_SIMPLE("usb2-port-1", 80), 4078 TEGRA_WAKE_SIMPLE("usb2-port-2", 81), 4079 TEGRA_WAKE_SIMPLE("usb2-port-3", 82), 4080 }; 4081 4082 static const struct tegra_pmc_soc tegra194_pmc_soc = { 4083 .supports_core_domain = false, 4084 .num_powergates = 0, 4085 .powergates = NULL, 4086 .num_cpu_powergates = 0, 4087 .cpu_powergates = NULL, 4088 .has_tsense_reset = false, 4089 .has_gpu_clamps = false, 4090 .needs_mbist_war = false, 4091 .has_impl_33v_pwr = true, 4092 .maybe_tz_only = false, 4093 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 4094 .io_pads = tegra194_io_pads, 4095 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 4096 .pin_descs = tegra194_pin_descs, 4097 .regs = &tegra194_pmc_regs, 4098 .init = tegra186_pmc_init, 4099 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4100 .set_wake_filters = tegra186_pmc_set_wake_filters, 4101 .irq_set_wake = tegra186_pmc_irq_set_wake, 4102 .irq_set_type = tegra186_pmc_irq_set_type, 4103 .reset_sources = tegra194_reset_sources, 4104 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 4105 .reset_levels = tegra186_reset_levels, 4106 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4107 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 4108 .wake_events = tegra194_wake_events, 4109 .max_wake_events = 96, 4110 .max_wake_vectors = 3, 4111 .pmc_clks_data = NULL, 4112 .num_pmc_clks = 0, 4113 .has_blink_output = false, 4114 .has_usb_sleepwalk = false, 4115 .has_single_mmio_aperture = false, 4116 }; 4117 4118 static const struct tegra_io_pad_soc tegra234_io_pads[] = { 4119 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"), 4120 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"), 4121 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"), 4122 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"), 4123 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"), 4124 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"), 4125 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"), 4126 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"), 4127 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"), 4128 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"), 4129 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"), 4130 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"), 4131 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 4132 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"), 4133 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"), 4134 }; 4135 4136 static const struct pinctrl_pin_desc tegra234_pin_descs[] = { 4137 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4138 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4139 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4140 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4141 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4142 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4143 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4144 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4145 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4146 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4147 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4148 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4149 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4150 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4151 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4152 }; 4153 4154 static const struct tegra_pmc_regs tegra234_pmc_regs = { 4155 .scratch0 = 0x2000, 4156 .rst_status = 0x70, 4157 .rst_source_shift = 0x2, 4158 .rst_source_mask = 0xfc, 4159 .rst_level_shift = 0x0, 4160 .rst_level_mask = 0x3, 4161 }; 4162 4163 static const char * const tegra234_reset_sources[] = { 4164 "SYS_RESET_N", /* 0x0 */ 4165 "AOWDT", 4166 "BCCPLEXWDT", 4167 "BPMPWDT", 4168 "SCEWDT", 4169 "SPEWDT", 4170 "APEWDT", 4171 "LCCPLEXWDT", 4172 "SENSOR", /* 0x8 */ 4173 NULL, 4174 NULL, 4175 "MAINSWRST", 4176 "SC7", 4177 "HSM", 4178 NULL, 4179 "RCEWDT", 4180 NULL, /* 0x10 */ 4181 NULL, 4182 NULL, 4183 "BPMPBOOT", 4184 "FUSECRC", 4185 "DCEWDT", 4186 "PSCWDT", 4187 "PSC", 4188 "CSITE_SW", /* 0x18 */ 4189 "POD", 4190 "SCPM", 4191 "VREFRO_POWERBAD", 4192 "VMON", 4193 "FMON", 4194 "FSI_R5WDT", 4195 "FSI_THERM", 4196 "FSI_R52C0WDT", /* 0x20 */ 4197 "FSI_R52C1WDT", 4198 "FSI_R52C2WDT", 4199 "FSI_R52C3WDT", 4200 "FSI_FMON", 4201 "FSI_VMON", /* 0x25 */ 4202 }; 4203 4204 static const struct tegra_wake_event tegra234_wake_events[] = { 4205 TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)), 4206 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA234_MAIN_GPIO(G, 4)), 4207 TEGRA_WAKE_IRQ("pmu", 24, 209), 4208 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), 4209 TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), 4210 TEGRA_WAKE_IRQ("rtc", 73, 10), 4211 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179), 4212 }; 4213 4214 static const struct tegra_pmc_soc tegra234_pmc_soc = { 4215 .supports_core_domain = false, 4216 .num_powergates = 0, 4217 .powergates = NULL, 4218 .num_cpu_powergates = 0, 4219 .cpu_powergates = NULL, 4220 .has_tsense_reset = false, 4221 .has_gpu_clamps = false, 4222 .needs_mbist_war = false, 4223 .has_impl_33v_pwr = true, 4224 .maybe_tz_only = false, 4225 .num_io_pads = ARRAY_SIZE(tegra234_io_pads), 4226 .io_pads = tegra234_io_pads, 4227 .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs), 4228 .pin_descs = tegra234_pin_descs, 4229 .regs = &tegra234_pmc_regs, 4230 .init = tegra186_pmc_init, 4231 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4232 .set_wake_filters = tegra186_pmc_set_wake_filters, 4233 .irq_set_wake = tegra186_pmc_irq_set_wake, 4234 .irq_set_type = tegra186_pmc_irq_set_type, 4235 .reset_sources = tegra234_reset_sources, 4236 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 4237 .reset_levels = tegra186_reset_levels, 4238 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4239 .num_wake_events = ARRAY_SIZE(tegra234_wake_events), 4240 .wake_events = tegra234_wake_events, 4241 .max_wake_events = 96, 4242 .max_wake_vectors = 3, 4243 .pmc_clks_data = NULL, 4244 .num_pmc_clks = 0, 4245 .has_blink_output = false, 4246 .has_single_mmio_aperture = false, 4247 }; 4248 4249 static const struct of_device_id tegra_pmc_match[] = { 4250 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 4251 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 4252 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 4253 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 4254 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 4255 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 4256 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 4257 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 4258 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 4259 { } 4260 }; 4261 4262 static void tegra_pmc_sync_state(struct device *dev) 4263 { 4264 struct device_node *np, *child; 4265 int err; 4266 4267 np = of_get_child_by_name(dev->of_node, "powergates"); 4268 if (!np) 4269 return; 4270 4271 for_each_child_of_node(np, child) 4272 of_genpd_sync_state(child); 4273 4274 of_node_put(np); 4275 4276 np = of_get_child_by_name(dev->of_node, "core-domain"); 4277 if (!np) 4278 return; 4279 4280 of_genpd_sync_state(np); 4281 of_node_put(np); 4282 4283 /* 4284 * Newer device-trees have power domains, but we need to prepare all 4285 * device drivers with runtime PM and OPP support first, otherwise 4286 * state syncing is unsafe. 4287 */ 4288 if (!pmc->soc->supports_core_domain) 4289 return; 4290 4291 /* 4292 * Older device-trees don't have core PD, and thus, there are 4293 * no dependencies that will block the state syncing. We shouldn't 4294 * mark the domain as synced in this case. 4295 */ 4296 pmc->core_domain_state_synced = true; 4297 4298 /* this is a no-op if core regulator isn't used */ 4299 mutex_lock(&pmc->powergates_lock); 4300 err = dev_pm_opp_sync_regulators(dev); 4301 mutex_unlock(&pmc->powergates_lock); 4302 4303 if (err) 4304 dev_err(dev, "failed to sync regulators: %d\n", err); 4305 } 4306 4307 static struct platform_driver tegra_pmc_driver = { 4308 .driver = { 4309 .name = "tegra-pmc", 4310 .suppress_bind_attrs = true, 4311 .of_match_table = tegra_pmc_match, 4312 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 4313 .pm = &tegra_pmc_pm_ops, 4314 #endif 4315 .sync_state = tegra_pmc_sync_state, 4316 }, 4317 .probe = tegra_pmc_probe, 4318 }; 4319 builtin_platform_driver(tegra_pmc_driver); 4320 4321 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 4322 { 4323 u32 value, saved; 4324 4325 saved = readl(pmc->base + pmc->soc->regs->scratch0); 4326 value = saved ^ 0xffffffff; 4327 4328 if (value == 0xffffffff) 4329 value = 0xdeadbeef; 4330 4331 /* write pattern and read it back */ 4332 writel(value, pmc->base + pmc->soc->regs->scratch0); 4333 value = readl(pmc->base + pmc->soc->regs->scratch0); 4334 4335 /* if we read all-zeroes, access is restricted to TZ only */ 4336 if (value == 0) { 4337 pr_info("access to PMC is restricted to TZ\n"); 4338 return true; 4339 } 4340 4341 /* restore original value */ 4342 writel(saved, pmc->base + pmc->soc->regs->scratch0); 4343 4344 return false; 4345 } 4346 4347 /* 4348 * Early initialization to allow access to registers in the very early boot 4349 * process. 4350 */ 4351 static int __init tegra_pmc_early_init(void) 4352 { 4353 const struct of_device_id *match; 4354 struct device_node *np; 4355 struct resource regs; 4356 unsigned int i; 4357 bool invert; 4358 4359 mutex_init(&pmc->powergates_lock); 4360 4361 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 4362 if (!np) { 4363 /* 4364 * Fall back to legacy initialization for 32-bit ARM only. All 4365 * 64-bit ARM device tree files for Tegra are required to have 4366 * a PMC node. 4367 * 4368 * This is for backwards-compatibility with old device trees 4369 * that didn't contain a PMC node. Note that in this case the 4370 * SoC data can't be matched and therefore powergating is 4371 * disabled. 4372 */ 4373 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4374 pr_warn("DT node not found, powergating disabled\n"); 4375 4376 regs.start = 0x7000e400; 4377 regs.end = 0x7000e7ff; 4378 regs.flags = IORESOURCE_MEM; 4379 4380 pr_warn("Using memory region %pR\n", ®s); 4381 } else { 4382 /* 4383 * At this point we're not running on Tegra, so play 4384 * nice with multi-platform kernels. 4385 */ 4386 return 0; 4387 } 4388 } else { 4389 /* 4390 * Extract information from the device tree if we've found a 4391 * matching node. 4392 */ 4393 if (of_address_to_resource(np, 0, ®s) < 0) { 4394 pr_err("failed to get PMC registers\n"); 4395 of_node_put(np); 4396 return -ENXIO; 4397 } 4398 } 4399 4400 pmc->base = ioremap(regs.start, resource_size(®s)); 4401 if (!pmc->base) { 4402 pr_err("failed to map PMC registers\n"); 4403 of_node_put(np); 4404 return -ENXIO; 4405 } 4406 4407 if (of_device_is_available(np)) { 4408 pmc->soc = match->data; 4409 4410 if (pmc->soc->maybe_tz_only) 4411 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 4412 4413 /* Create a bitmap of the available and valid partitions */ 4414 for (i = 0; i < pmc->soc->num_powergates; i++) 4415 if (pmc->soc->powergates[i]) 4416 set_bit(i, pmc->powergates_available); 4417 4418 /* 4419 * Invert the interrupt polarity if a PMC device tree node 4420 * exists and contains the nvidia,invert-interrupt property. 4421 */ 4422 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 4423 4424 pmc->soc->setup_irq_polarity(pmc, np, invert); 4425 4426 of_node_put(np); 4427 } 4428 4429 return 0; 4430 } 4431 early_initcall(tegra_pmc_early_init); 4432